H

13.
Building the Beta

6.004x Computation Structures
Part 2 Computer Architecture
Copyright 2015 MIT EECS
6.004 Computation Structures
L13: Building the Beta, Slide #1
CPU Design Tradeoffs
Maximum Performance: measured

by the numbers of instructions
executed per second
10 10
Minimum Cost : measured by the

size of the circuit.
Best Performance/Price: measured
by the ratio of MIPS to size. In
power-sensitive applications MIPS/
Watt is important too.
Processor Performance
Iron Law of performance:
Time
Instructions Cycles Time
=
Program
Program Instruction Cycle
Perf =
1
Time
Options to reduce execution time:

Executed instructions (work/instruction )
Cycles per instruction (CPI)
Cycle time (frequency )
Today: Simple, CPI=1 but low-frequency Beta

Later: Pipelining to increase frequency
Reminder: Beta ISA

6
11
1 0 XX X X
Rc
Ra
Rb
(UNUSED)
Operate class: Reg[Rc] Reg[Ra] op Reg[Rb]

16
1 1 XX XX
Rc
Ra
Literal C (signed)
Operate class: Reg[Rc] Reg[Ra] op SXT(C)

Opcodes, both formats:
ADD
SUB
CMPEQ CMPLE
AND
OR
SHL
SHR
0 1 XX XX
Rc
Ra
MUL*
CMPLT
XOR
SRA
DIV*
Instruction classes
distinguished by
OPCODE:
OP
OPC
MEM
Control Flow
*optional
XNOR
Literal C (signed)
LD: Reg[Rc] Mem[Reg[Ra]+SXT(C)]

ST: Mem[Reg[Ra]+SXT(C)] Reg[Rc]
LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)]
BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC PC+4+4*SXT(C)
BNE: Reg[Rc] PC+4; if Reg[Ra]0 then PC PC+4+4*SXT(C)
JMP: Reg[Rc] PC+4; PC Reg[Ra]
Approach: Incremental Featurism

Well implement datapaths for each instruction class
individually, and merge them (using MUXes, etc)
Steps:
1.
2.
3.
4.
Component Repertoire:
ALU instructions
Load & store instructions
Jump & branch instructions
Exceptions
Registers
Muxes
Black box ALU
ALU
RA1
WA
WE
WD
RA2
Register
File
(3-port)
A
D
WD
Instruction
Memory
A
RD
Data
Memory
R/W
RD1
RD2
Memories
Multi-Ported Register File

Write
Port
(independent Read addresses)
WA
clk
5
EN
CLK
EN
CLK
EN
CLK
Write Address
EN
CLK
WE
Write Enable
Write Data
RA2
RA1
CLK
WA
32
WD
RA1
RA2
Register
File
(3-port)
RD1
32
Read
Port 1
clk
32
(Independent Read Data)
Read
Port 2
EN
RD2
0
D
Q
2 combinational READ ports*,

1 clocked WRITE port
*internal logic ensures Reg[31] reads as 0
Q
Load-enabled register
Register File Timing

2 combinational READ ports, 1 clocked WRITE port
Read address
RA
Read data
RD
Reg[A]
new Reg[A]
tPD
tPD
CLK
Write enable
WE
Write address
WA
Write data
WD
new Reg[A]
ts th
What if (say) WA=RA1???

RD1 reads old value of Reg[RA1] until next clock edge!
ALU Instructions
32-bit (4-byte) ADD instruction:
31
26 25
21 20
16 15
11
10000000100000100001100000000000
Opcode
Rc
Means, to Beta,
Ra
Rb
(unused)
Reg[R4] Reg[R2] + Reg[R3]
Need hardware to:

FETCH (read) 32-bit instruction for the current cycle
DECODE instruction: ADD, SUB, XOR, etc
READ operands (Ra, Rb) from Register File
EXECUTE operation
WRITE-BACK result into Register File (Rc)
Instruction Fetch/Decode
Use a counter to FETCH the next instruction: PROGRAM
COUNTER (PC)
Reset
RESET
PC
00
A Instruction
32
+4
Memory
D
ID[31:0]
32
32
INSTRUCTION
WORD
FIELDS
OPCODE: ID[31:26]
Control Logic
CONTROL SIGNALS
Use PC as memory address

Add 4 to PC, load new value
at end of cycle
Fetch instruction from
memory
Use some instruction
fields directly (register
numbers, 16-bit
constant)
Use bits [31:26] to
generate control signals
ALU Op Datapath
31
26 25
Ra
11
Rb
(UNUSED)
00
+4
16 15
Rc
1 0 XX X X
PC
21 20
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
Rb: ID[15:11]
RA1
Rc: ID[25:21]
Register
File
WA
RD1
ID[31:26]
32
RA2
WD
RD2
WE
WERF
32
Control Logic
A
ALUFN
ALU
ALUFN
WERF!
WERF
32
ALU Op Datapath
Rc
1 0 XX X X
PC
Rb
(UNUSED)
00
+4
Ra
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
Rb: ID[15:11]
RA1
Rc: ID[25:21]
Register
File
WA
RD1
ID[31:26]
32
RA2
WD
RD2
WE
WERF
32
Control Logic
A
ALUFN
ALUFN
ALU
F(op)
WERF
32
ALU Operations (with constant)

31
26 25
1 1 XX XX
PC
21 20
Rc
16 15
Ra
Literal C (signed)
00
Instruction
Memory
D
+4
ID[31:0]
Ra: ID[20:16]
Sign-extension requires
no logic
RA1
Rc: ID[25:21]
WA
WA
RD1
Rb: ID[15:11]
Register
File
RA2
WD
RD2
WE
WERF
C: SXT(ID[15:0])
32
ID[31:26]
BSEL
Control Logic
31:16
15:0
A
BSEL
Just replicate
ID[15] sixteen
times to create
high-order bits!
ALUFN
ALU
ALUFN
WERF
ALU Operations (with constant)

1 1 XX XX
PC
Ra
Literal C (signed)
00
+4
Rc
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
RA1
Rc: ID[25:21]
WA
WA
RD1
Rb: ID[15:11]
Register
File
RA2
WD
RD2
WERF
WE
C: SXT(ID[15:0])
32
ID[31:26]
BSEL
Control Logic
BSEL
ALUFN
ALUFN
ALU
F(op)
WERF
Load Instruction
31
26 25
01 10 00
LD:
PC
21 20
Rc
16 15
Ra
Literal C (signed)
Reg[Rc] Mem[Reg[Ra]+SXT(C)]
00
+4
Instruction
Memory
This is just like

ADDC(Ra,C,)
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: D[15:11]
RA1
Register
File
WA
WA
RD1
RA2
WD
RD2
WE
WERF
C: SXT(ID[15:0])
ID[31:26]
1
BSEL
Control Logic
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
ALUFN
ALU
WD
R/W
OE
MWR
MOE
Data Memory
32
Adr
RD
32
0
WDSEL
Load Instruction
01 10 00
LD:
PC
Rc
Ra
Literal C (signed)
Reg[Rc] Mem[Reg[Ra]+SXT(C)]
00
+4
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: D[15:11]
RA1
Register
File
WA
WA
RD1
RA2
WD
RD2
WERF
WE
C: SXT(ID[15:0])
ID[31:26]
1
BSEL
Control Logic
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
ALUFN
ALU
WD
R/W
OE
A+B
Data Memory
Adr
32
MWR
MOE
0
1
RD
32
0
WDSEL
2
Store Instruction
31
26 25
01 10 01
ST:
PC
21 20
Rc
16 15
Ra
Literal C (signed)
Mem[Reg[Ra]+SXT(C)] Reg[Rc]
00
Instruction
Memory
D
+4
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
RA1
Rc: ID[25:21]
Register
File
WA
WA
RD1
RA2SEL
No WERF!
RA2
WD
RD2
WE
WERF
C: SXT(ID[15:0])
ID[31:26]
BSEL
Control Logic
32
RA2SEL
A
BSEL
WDSEL
ALUFN
MWR, MOE
ALUFN
ALU
WD
R/W
OE
MWR
MOE
Data Memory
Adr
RD
WERF
WDSEL
Store Instruction
01 10 01
ST:
PC
Rc
Ra
Literal C (signed)
Mem[Reg[Ra]+SXT(C)] Reg[Rc]
00
Instruction
Memory
D
+4
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
RA1
Rc: ID[25:21]
Register
File
WA
WA
RD1
RA2SEL
RA2
WD
RD2
WERF
WE
C: SXT(ID[15:0])
ID[31:26]
BSEL
Control Logic
1
32
RA2SEL
A
BSEL
WDSEL
ALUFN
MWR, MOE
ALUFN
ALU
WD
R/W
OE
Data Memory
A+B
Adr
MWR
MOE
1
0
RD
WERF
WDSEL
-L13: Building the Beta, Slide #17
JMP Instruction
31
01 10 11
JT
PCSEL
PC
26 25
21 20
Rc
16 15
Ra
Literal C (signed)
00
+4
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
Rc: ID[25:21]
RA1
Register
File
WA
WA
RD1
RA2SEL
RA2
WD
RD2
WE
WERF
JT
C: SXT(ID[15:0])
ID[31:26]
BSEL
Control Logic
PCSEL
RA2SEL
A
BSEL
WDSEL
ALUFN
MWR. MOE
ALU
ALUFN
WD
R/W
OE
MWR
MOE
Data Memory
Adr
RD
WERF
PC+4
32
0
WDSEL
JMP Instruction
01 10 11
JT
PCSEL
PC
Rc
Ra
Literal C (signed)
00
+4
Instruction
Memory
D
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
Rc: ID[25:21]
RA1
Register
File
WA
WA
RD1
RA2SEL
--
RA2
WD
RD2
WE
WERF
WD
R/W
OE
JT
C: SXT(ID[15:0])
ID[31:26]
BSEL
--
Control Logic
PCSEL
RA2SEL
A
BSEL
WDSEL
ALUFN
MWR. MOE
ALU
ALUFN
--
Data Memory
Adr
MWR
MOE
0
--
RD
WERF
PC+4
32
0
WDSEL
0
BEQ/BNE Instructions
31
01 11 00
JT
PCSEL
26 25
21 20
16 15
Rc
Ra
Literal C (signed)
BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC (PC+4)+4*SXT(C)
32
PC
01 11 01
00
Instruction
Memory
Literal C (signed)
ID[31:0]
Ra: ID[20:16]
(PC+4)+4*SXT(C)
Rb: ID[15:11]
Rc: ID[25:21]
0
RA1
Rc: ID[25:21]
Register
File
WA
WA
RD1
4*SXT(ID[15:0])
4* only
requires
adding 0b00
to low-order
bits no
HW needed!
Ra
BNE: Reg[Rc] PC+4; if Reg[Ra]0 then PC (PC+4)+4*SXT(C)
+4
Rc
RA2SEL
RA2
WD
RD2
WE
WERF
JT
C: SXT(ID[15:0])
ID[31:26]
BSEL
Control Logic
PCSEL
RA2SEL
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
ALU
ALUFN
WD
R/W
OE
MWR
MOE
Data Memory
Adr
RD
PC+4
0
WDSEL
BEQ/BNE Instructions
01 11 00
JT
PCSEL
0 or 1
Rc
Ra
Literal C (signed)
BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC (PC+4)+4*SXT(C)
32
PC
01 11 01
00
Instruction
Memory
Ra
Literal C (signed)
BNE: Reg[Rc] PC+4; if Reg[Ra]0 then PC (PC+4)+4*SXT(C)
+4
Rc
ID[31:0]
Ra: ID[20:16]
Rb: ID[15:11]
Rc: ID[25:21]
0
(PC+4)+4*SXT(C) +
RA1
Rc: ID[25:21]
RD1
4*SXT(ID[15:0])
Register
File
WA
WA
RA2SEL
--
RA2
WD
RD2
WERF
WE
JT
C: SXT(ID[15:0])
ID[31:26]
BSEL
--
Control Logic
PCSEL
RA2SEL
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
ALU
ALUFN
WD
R/W
OE
Data Memory
--
Adr
MWR
MOE
0
--
RD
PC+4
0
WDSEL
0
Load Relative Instruction

01 11 11
Rc
Ra
Literal C (signed)
LDR: Reg[Rc] Mem[PC + 4 + 4*SXT(C)]
Whats Load Relative good for anyway??? I thought

Code is PURE, i.e. READ-ONLY; and stored in a
PROGRAM region of memory;
Data is READ-WRITE, and stored either
On the STACK (local); or
In some GLOBAL VARIABLE region; or
In a global storage HEAP.
So why have an instruction designed to
load data thats near the instruction???
Addresses & other large constants
C: X = X * 123456;

BETA:
LD(X, r0)
LDR(c1, r1)
MUL(r0, r1, r0)
ST(r0, X)
...
c1: LONG(123456)
LDR Instruction
JT
PCSEL
01 11 11
IF
PC
Rc
Ra
Literal C (signed)
LDR:
00
Reg[Rc] Mem[PC + 4 + 4*SXT(C)]
Instruction
Memory
+4
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
RA1
Rc: ID[25:21]
Register
File
WA
WA
RD1
ID[31:26]
ASEL
RA2SEL
RA2
WD
RD2
WE
WERF
JT
C:SXT(ID[15:0])
(PC+4)+4*SXT(C)
BSEL
Control Logic
PCSEL
RA2SEL
ASEL
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
ALU
ALUFN
WD
R/W
OE
Data Memory
Adr
RD
MWR
MOE
Why not put

the ASEL
mux here?
PC+4
0
WDSEL
LDR Instruction
JT
PCSEL
01 11 11
IF
PC
Rc
Ra
Literal C (signed)
LDR:
00
Reg[Rc] Mem[PC + 4 + 4*SXT(C)]
Instruction
Memory
+4
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
Rb: ID[15:11]
0
RA1
Rc: ID[25:21]
Register
File
WA
WA
RD1
ID[31:26]
ASEL
Control Logic
PCSEL
RA2SEL
ASEL
BSEL
WDSEL
ALUFN
MWR, MOE
WERF
RA2SEL
--
RA2
WD
RD2
WERF
WE
JT
C:SXT(ID[15:0])
(PC+4)+4*SXT(C)
BSEL
--
1
A
ALU
ALUFN
WD
R/W
OE
Data Memory
Adr
MWR
MOE
0
1
RD
PC+4
0
WDSEL
2
Exceptions
What if something bad happens?
Execution of an illegal opcode
Reference to non-existent memory
Divide by zero
Or maybe just something unanticipated

User hits a key
A packet comes in via the network
Exceptions let us handle these cases in software:
Treat each case as an (implicit) procedure call

Procedure handles problem, returns to interrupted program
Transparent to interrupted program!
Important added capability: handlers for certain errors (illegal
opcodes), can extend ISA using software
Exception Processing
Plan:
Interrupt running program
Invoke exception handler (like a procedure call)
Return to continue execution
Exception and interrupt terms often used

interchangeably, with minor distinctions:
Exceptions usually refer to synchronous events, generated
by program (e.g., illegal instruction, divide-by-0, illegal
address)
Interrupts usually refer to asynchronous events,
generated by I/O devices (e.g., keystroke, packet received,
disk transfer complete)
Exception Implementation
Instead of executing instruction, fake a procedure call
Save current PC+4 (as branches do)
Load PC with exception vector: 0x4 for synchronous events,
0x8 for asynchronous events
We save PC+4 in register R30 (which we call XP)

and prohibit programs from using XP (why?)
Example: DIV unimplemented
LD(R31,A,R0)
LD(R31,B,R1)
DIV(R0,R1,R2)
ST(R2,C,R31)
IllOp:
PUSH(XP)
Forced by
Fetch inst. at Mem[Reg[XP]4]
hardware
check for DIV opcode, get reg numbers
perform operation in SW, fill result reg

POP(XP)
JMP(XP)
Exceptions
ILL
XAdr OP
PCSEL
JT
2
PC
Bad Opcode: Reg[XP] PC+4; PC IllOp

Other: Reg[XP] PC+4; PC Xadr
00
Instruction
Memory
D
+4
ID[31:0]
Ra: ID[20:16]
RA2SEL
WASEL
RA1
XP
Rc: ID[25:21]
RD1
RA2
WD
RD2
WE
WERF
JT
C: SXT(ID[15:0])
(PC+4)+4*SXT(C)
Register
File
WA
WA
IRQ
Rc: ID[25:21]
Rb: ID[15:11]
ID[31:26]
ASEL
BSEL
Control Logic
PCSEL
RA2SEL
ASEL
BSEL
WDSEL
ALUFN
MWR. MOE
WERF
WASEL
ALU
ALUFN
R/W
OE
MWR
MOE
Data Memory
Adr
RD
PC+4
0
WD
WDSEL
Exceptions
ILL
XAdr OP
PCSEL
3 or 4
JT
2
PC
Bad Opcode: Reg[XP] PC+4; PC IllOp

Other: Reg[XP] PC+4; PC Xadr
00
Instruction
Memory
D
+4
ID[31:0]
1
Ra: ID[20:16]
RA1
Rc: ID[25:21]
RD1
RA2SEL
Control Logic
PCSEL
RA2SEL
ASEL
BSEL
WDSEL
ALUFN
MWR. MOE
WERF
--
WD
RD2
WERF
WE
ID[31:26]
ASEL
WASEL
RA2
JT
C: SXT(ID[15:0])
(PC+4)+4*SXT(C)
Register
File
WA
WA
BSEL
--
-A
ALU
ALUFN
WD
R/W
OE
Data Memory
--
Adr
MWR
MOE
0
--
RD
PC+4
0
WASEL
XP
IRQ
Rc: ID[25:21]
Rb: ID[15:11]
WDSEL
0
Beta: Our Final Answer

ILL
XAdr OP
PCSEL
JT
Reset
RESET
PC
00
Instruction
Memory
D
+4
ID[31:0]
Ra: ID[20:16]
Rc: ID[25:21]
0
RA2SEL
WASEL
RA1
XP
RD1
Z
C: SXT(ID[15:0])
(PC+4)+4*SXT(C)
Register
File
WA
WA
Rc: ID[25:21] 0
IRQ
Rb: ID[15:11]
RA2
WD
RD2
WE
WERF
JT
ID[31:26]
ASEL
BSEL
Control Logic
ALUFN
ASEL
A
BSEL
MOE
ALU
ALUFN
WD
Data
Memory
MWR
PCSEL
Adr
RA2SEL
WE
MWR
OE
MOE
RD
WASEL
WDSEL
WERF
PC+4
0
WDSEL
ALUFN
ASEL
BSEL
MOE
MWR
PCSEL
RA2SEL
WASEL
WDSEL
WERF
ILLOP
BNE
BEQ
JMP
ST
LDR
LD
OPC
OP
IRQ
RESET
Control Logic
-- -- F(op) F(op) "+" "A" "+" --

--
--
--
-- -- 0
0
0 1 0 --
--
--
--
-- -- 0
1
1 -- 1 --
--
--
--
-- -- --
-- 1 1 0 --
--
--
--
0 0 0
0
0 0 1 0
0
0
0
-- 4 0
0
0 0 0 2 Z ? 1 : 0 Z ? 0 : 1 3
-- -- 0
-- -- -- 1 --
--
--
--
-- 1 0
0
0 0 -- 0
0
0
1
-- 0 1
1
2 2 -- 0
0
0
0
-- 1 1
1
1 1 0 1
1
1
1
Implementation choices:
64-location ROM indexed by opcode with external logic to
handle changes due to Z and IRQ inputs
Entirely combinational logic (faster, but much more work!)
Is that all
there is to
building a
processor???
No.
Youve gotta print
up all those little
Beta Inside
stickers.

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13.

Building the Beta

6.004 Computation Structures

L13: Building the Beta, Slide #1

CPU Design Tradeoffs

Maximum Performance: measured

Minimum Cost : measured by the

6.004 Computation Structures

L13: Building the Beta, Slide #2

Options to reduce execution time:

Today: Simple, CPI=1 but low-frequency Beta

6.004 Computation Structures

L13: Building the Beta, Slide #3

Reminder: Beta ISA

Operate class: Reg[Rc] Reg[Ra] op Reg[Rb]

Operate class: Reg[Rc] Reg[Ra] op SXT(C)

LD: Reg[Rc] Mem[Reg[Ra]+SXT(C)]

L13: Building the Beta, Slide #4

Approach: Incremental Featurism

Black box ALU

6.004 Computation Structures

Multi-Ported Register File

(Independent Read Data)

2 combinational READ ports*,

L13: Building the Beta, Slide #6

Register File Timing

What if (say) WA=RA1???

L13: Building the Beta, Slide #7

Reg[R4] Reg[R2] + Reg[R3]

Need hardware to:

L13: Building the Beta, Slide #8

6.004 Computation Structures

Use PC as memory address

L13: Building the Beta, Slide #9

Operate class: Reg[Rc] Reg[Ra] op Reg[Rb]

6.004 Computation Structures

L13: Building the Beta, Slide #10

Operate class: Reg[Rc] Reg[Ra] op Reg[Rb]

6.004 Computation Structures

L13: Building the Beta, Slide #11

ALU Operations (with constant)

Operate class: Reg[Rc] Reg[Ra] op SXT(C)

L13: Building the Beta, Slide #12

ALU Operations (with constant)

Operate class: Reg[Rc] Reg[Ra] op SXT(C)

6.004 Computation Structures

L13: Building the Beta, Slide #13

This is just like

6.004 Computation Structures

L13: Building the Beta, Slide #14

6.004 Computation Structures

6.004 Computation Structures

L13: Building the Beta, Slide #16

6.004 Computation Structures

-L13: Building the Beta, Slide #17

JMP: Reg[Rc] PC+4; PC Reg[Ra]

6.004 Computation Structures

L13: Building the Beta, Slide #18

JMP: Reg[Rc] PC+4; PC Reg[Ra]

6.004 Computation Structures

BEQ: Reg[Rc] PC+4; if Reg[Ra]=0 then PC (PC+4)+4*SXT(C)

BNE: Reg[Rc] PC+4; if Reg[Ra]0 then PC (PC+4)+4*SXT(C)

6.004 Computation Structures