Ipad 4 Schematic-1 PDF

www.mobile-files.
com
www.witesomtesla.com
MLB
R8296
R5991
R8297
C5991
820-3249-TOP
R5990
C1021
J3700
C3787
C3764
R3750
C3757
J5950
R6111_RF
R6112_RF
R6107_RF
R5932
R5933
R5962
R5961
C3756
C3754
C3753
C3752
C3751
C3713
C3746
C3767
C3744
C3743
C3742
U3740
C3747
C8143
C8103
R0730
U5902
R1200
R1201
R1202
R2242
C2232
C2206
C2202
C2230
R2290
C2203
C2247
C2245
R2280
L2212
C2251
C2242
C2243
C2244
C2246
C2248
R8269
R8262
R2281
C2249
R8240
R8235
R8231
C5551
C3609
R2282
L2222
L5570
C5640
R5640
C5582
C5583
C5552
C5584
C5553
U5620
C5630
U5630
R5631
R5630
C5550
C5580
C5562
C0605
U5640
L5530
R5641
C5572
L5510
R0932
C5670
L5580
L5560
C5570
C5573
L5500
U5650
U5660
C5671
C5561
C5571
C5661
C5581
CA150
C11F0
R0842
CA197
C3612
C0637
C0982
C0981
C1163
R2283
C2250
C0821
C0842
C1178
C1177
C1175
R8257
C3109
C3111
C1608
R3107
C1143
C1119
C1108
R0930
C0612
CA192
R0931
R0933
C0613
C0633
C0634
R0613
C2280
R2284
L2232
C5560
R0610
C2281
R2285
U3100
C1168
C0608
C0930
R6108_RF
R0708
R0716
R0710
R0709
R0700
R0701
R0702
R1206
R1205
R1204
C1429
C1428
C1416
C1329
C1328
C1317
C1142
C1194
C1109
C1125
C1121
C0955
CA152
R0920
C0950
R1260
C1110
C1148 C1147
C2282
R2286
L2202
C5563
C0933
C11A1
C1181
C11B1
C1199
DZ5760
R3740
R3070
R9021
C5766
R9031
C11A0
C2283
R2287
R8282
C11B0
R3601
U3003
C2284
R2241
CA153
C0980
C2285
L2242
C8157
C2271
C2286
R2240
C8139
C2221
C2287
L5550
U5600
R0705
R0706
U5610
J6000
C2270
R8261
C2253
C2220
L2201
R8270
C2233
C2241
C0907
C0820
C3690
R8239
C1167
C3604
R8265
C0961
CA194
C1176
C3006
R8232
R9001
C7526
R8227
C8130
C7522
C2239
C8236
C7523
U2200
R8280
C7524
FL7500
L5520
U6104_RF
C7527
C7525
U3101
L2210
C6108_RF
R0831
C2240
RF
C1602
L5540
1_
C1606
L2200
C6
11
R1691
C5660
RF
C1691
C3613
0_
R1690
C1690
R3120
19
R6114_RF
R6105_RF
C1605
FL0910
FL5740
J6190_RF
C3611
C0904
C1171
R0843
C6
C6102_RF
C6101_RF
C8235
C8234
R6113_RF
C6103_RF
C0935
C0908
C0843
RF
C3710
C3745
L8109
U6102_RF
C0960
C1172
R1207
2_
C6109
L6111_RF
C8256
CA198
C1145
19
C3763
C6110_RF
C8110
R1421
C1450
C0903
C1185
C1174
C6
C3766
FL3741
C3761
C3720
C3755
C3768
C3760
C6104_RF
C1609
C1415
C1410
R1405
C0635
C1159
C1160
C1169
C6191_RF
C3750
R3743
U5670
R0719
C3783
C3749
FL3740
C3740
U5903
C1601
C1418
C1417
C0636
C11C0
R0900
R0940
C11D0
C11D1
C0621
C0609
C1158
C11C1
C1157
C1161
C1180
C11E1
R0942
C0631
C1173
C1184
C11E0
C0630
R9011
R9010
R0941
R0911
C0811
C0909
C1149
C0632
CA187
C1154
C1182
C1183
C0614
CA199
C1150
C1460
C1190
R1406
C1162
C1164
C1151
C1170
C1118
C1155
C1156
C1152
C1130
C1133
C0957
C0931
C1139
R8218
C1138
C1153
C0812
C3780
R3744
R1654
C0607
C1135
C0810
FL3751
R3745
R5935
C1604
C0606
C1122
CA188
C3711
C3721
C1607
C1117
C1131
C1106
CA193
R0950
CA195
R0604
C1123
C1134
C1116
U1400
C1114
C1128
C0953
R0921
C0929
C1126
C8109
C5936
C3712
C3722
C3723
R3753
R3742
L8225
C8233
C1600
C1124
C1132
C1140
C0928
C0934
C1107
C1141
FL0911
C0956
C1120
C1137
C1129
CA189
C0623
C0952
C0932
C1113
C1136
L6190_RF
C1115
J6191_RF
C0910
R1210
CA151
C0951
U6101_RF
R1211
C0927
Q9010
Q8201
L6192_RF
L6191_RF
CA190
CA196
C1198
CA191
C1166
Q8203
C6107_RF
C5733
C5731
C1352
C0924
C1165
C8156
L5730
C1191
C1361
R1352
CA186
R1321
C8188
Q8200
C8158
R8293
R1351
C1316
C1310
C1332
R1320
C8159
R8291
C8291
D5990
C1315
D8228
C8232
C8105
R8290
Q8202
C8160
C8187
C8189
C8140
C8167
C8141
C5732
C8137
C8207
C8282
R8203
C8204
C5710
DZ5710
C8215
C8146
C8135
C8153
C8190
C8136
C8191
R8100
C5741
FL5710
DZ5740
C5730
C8145
C8281
C8151
C5711
C8214
R8172
C8212
C8132
C3770
C5740
C8238
C8133
C8221
C8201
C8172
C8223
C8170
C8174
C8173
C8171
C3771
C8217
C8138
C8290
R8292
R8173
C8239
C8134
C8266
C1452
C1111
C8168
C8251
C8210
C8161
C8209
C8169
C8162
Q8104
C8192
C3773
C8267
C8193
C8206
L3750
C3759
R1655
C8196
C8220
C3772
L8104
R8196
R8219
D8230
R1452
C1195
R8170
C1461
R1306
C1196
C5990
FL5990
C3748
C3786
FL3750
MLB
R1451
R1305
C1350
C1193
Q9020
R9020
C8112
C5722
R5790
C5721
U1300
R9030
C5960
R5960
C1360
Q9030
R8116
Q8123
R8130
DZ8120
C5783
C5900
C5750
L5757
C8111
C0651
DZ5901
DZ5900
DZ5902
DZ5903
L5930
C8102
C8123
R0703
R0704
Y0602
C8104
R0650
R0711
R0651
R0713
R0720
R0714
L5701
L5700
L5931
L8110
J3011
DZ5990
C5765
FL5750
L8103
L8102
820-3249-BOT
DZ5750
R0721
R3741
L3740
R9000
R5934
C5920
C8142
R1220
R0717
C0650
R8216
C8122
R1203
C3070
DZ5792
C8121
C8155
C8120
CA185
C5910
C8263
C3741
C1179
J3010
L8255
C8144
R1209
DZ5791
C8148
R0652
R1208
J5401
C8262
C8147
R0718
J6051
J5400
R9002
C8124
L8101
L8100
C3784
R3755
R3754
R3752
R0621
U3750
R0622
C3758
R3751
R6109_RF
R0608
R0620
R0715
R3071
L8229
C8108
C8119
R0643
C0640
R0640
R0832
U3007
C1102
R0642
C1103
D8258
C8226
C1610
C1620
C8152
C8149
Y8138
C3005
C3007
C1630
U8100
C1331
C8118
C1318
C1054
C1095
R1054
C8107
R1355
C1326
C1363
C1333
C1313
C1412
C1419
C1434
C1413
C1435
C1426
C1402
C3112
C1456
R1455
R1095
R3180
R3171
C3105
U3010
U3009
C3041
C3050
R3025
U3060
C3602
C3615
C3009
R2205
R3030
R8281
C8101
C3781
C3606
C1020
C3788
C1624
C8165
C8264
C3104
C1634
C8131
L8105
C8265
C3102
C1614
LED9000
C8164
C8237
C1325
R1021
C8292
R3181
R3155
R3033
R3101
C3103
C8166
C8163
R8222
C3031
L8112
C8117
C8100
U0600
C1101
C3030
R3031
J5900
C8126
C8125
L8106
C8154
C1303
C1414
C5941
C1309
R5930
R5931
C5943
C5944
C1057
R1053
R3066
C1305
U5900
C5934
C5933
C1321
R1354
C1100
C1319
C1430
L8111
L8107
C8195
C1302
R1353
C1362
C1354
C1403
C1404
C3053
C3605
L3620
R3614
C1301
C1323
C1322
C5930
C5932
C1320
C5935
C5940
C5942
C1330
C5931
R5929
D8100
C1304
C1306
C1308
R1056
C1056
R1356
U1600
D3000
C1104
C3101
C3607
C3620
C3608
C3632
C3631
R3631
R3620
R1055
C1058
R1022
R1096
C3603
C3614
R1420
C1105
C3601
C3630
R1084
C1314
C1096
U3600
C1409
R3032
C3618
C3617
L3000
4R7
R3160
C3616
R3630
R1454
U3000
R3190
C1085
C1084
C1411
C3108
R1083
C1405
C1407
C1307
C1334
C1401
C1421
C3106
C3000
R3612
C3002
C3001
R1456
C3110
C3192
C3107
R3611
R3613
R3610
R3640
C3191
R3173
R3012
C1463
C3060
R0760
C3691
J6050
C1454
R3009
R3060
C3610
R1453
C1422
C3008
J2200
C1462
C1431
C1432
J7500
C1420
C1423
C1335
C1324
C1356
C1022
R1020
C1327
R10234
C1312
C1425
C1311
C1424
C1023
C1408
C1197
C1613
C1427
C1633
C8194
C1623
C1612
C1433
C1622
C1192
C1632
C1625
C1144
C1635
C1406
C1615
C1650
C8113
C1651
C1631
C8114
C1652
C1621
C1611
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ECN
DESCRIPTION OF REVISION
0001554595
CK
APPD
DATE
iPad 4th Gen
PRODUCTION RELEASED
2012-07-26
LAST_MODIFIED=Thu Jul 26 10:29:36 2012

D
PDF CSA CONTENTS
SYNC MASTER
DATE
(SYSTEM DRI)
TABLE_TABLEOFCONTENTS_HEAD
Table of Contents
N/A
N/A
BLOCK DIAGRAM: SYSTEM
N/A
N/A
BOM TABLES
N/A
N/A
AP: MAIN
N/A
N/A
AP: I/Os
N/A
N/A
AP: NAND
N/A
N/A
AP: TV,DP,MIPI
N/A
N/A
10
AP: DDR
N/A
N/A
11
AP: POWER
N/A
N/A
12
AP: MISC & ALIASES
N/A
N/A
TABLE_TABLEOFCONTENTS_HEAD
(AMANDA)
TABLE_TABLEOFCONTENTS_ITEM
2
(AMANDA)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
10
33
(AMANDA)
32
(TERRY)
SYNC MASTER
DATE
(SYSTEM DRI)
83
PMU: ADRIANA PAGE 3
MADHAVI
12/06/2011
(MADHAVI)
90
DEBUG/MISC.
MLB
11/09/2011
(AMANDA)
93
TEST/HOLES/FIDUCUALS
N/A
N/A
(AMANDA)
121
POWER ALIASES
N/A
N/A
(MADHAVI)
150
CONSTRAINTS: MLB RULES
MIKE
11/30/2011
(AMANDA)
151
CONSTRAINTS: LOW SPEED BUS
MIKE
11/30/2011
(AMANDA)
152
CONSTRAINTS: DISPLAY/AUDIO
MIKE
11/30/2011
(AMANDA)
153
CONSTRAINTS: DDR/FMI
MIKE
11/30/2011
(AMANDA)
154
CONSTRAINTS: POWER / GND
MIKE
11/30/2011
(AMANDA)
31
(TERRY)
PDF CSA CONTENTS
(AMANDA)
34
35
36
37
38
39
11
13
DDR 0 AND 1
N/A
N/A
14
DDR 2 AND 3
N/A
N/A
16
NAND
N/A
N/A
(TERRY)
12
(TERRY)
13
(AMANDA)
14
(AMANDA)
21
ALIASES
N/A
N/A
22
VIDEO: EDP CONNECTOR
N/A
N/A
30
GRAPE: GROUNDHOG,CONN,BOOST
N/A
N/A
31
GRAPE: Z1, Z2
N/A
N/A
36
AUDIO: L81 CODEC
N/A
N/A
37
AUDIO: SPEAKER AMP
N/A
N/A
54
SENSOR FLEX CONN
N/A
N/A
55
SENSOR CONN FILTERS 1
N/A
N/A
56
N/A
N/A
57
E75 DOCK SUPPORT
N/A
N/A
58
IO FLEX CONN
N/A
N/A
59
TRISTAR
N/A
N/A
60
CONNECTOR: CELLULAR
N/A
N/A
61
WIFI/BT
N/A
N/A
75
POWER: BATTERY CONNECTOR
MADHAVI
12/06/2011
(MADHAVI)
81
PMU: ADRIANA PAGE 1
MADHAVI
12/06/2011
(MADHAVI)
82
PMU: ADRIANA PAGE 2
MADHAVI
12/06/2011
15
(JOE)
16
(AMANDA)
17
(AMANDA)
18
(TERRY)
19
(TERRY)
20
(MARK)
21
(MARK)
22
(MARK)
23
(JOE)
24
(JOE)
25
(JOE)
26
(AMANDA)
27
(MATT)
28
29
30
(MADHAVI)
DRAWING TITLE
X140 MLB
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
DRAWING
THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
MLB
DRAWING
051-9385
REVISION
A.0.0
BRANCH
PAGE
1 OF 154
SHEET
1 OF 39
SIZE
Z2
SPI3
CSA 31
ISP_I2C1
MIPI1C
FF CAMERA
ISP_I2C0
MIPI0C
REAR CAMERA
VGA FLEX
VA5 FLEX
HSIC1_1
GROUNDHOG
CSA 30
Z1
UART3
CSA 31
UART4
I2S2
LPDDR2
DISPLAY/
TOUCH PANEL
BT_I2S
CSA 61
BALI
CSA 13-14
EDP
CELLULAR/
GPS
HSIC1
HSIC3
IPC
WIFI/BT ANT
WIFI/BT
UART1
PRIMARY CELLULAR ANT

DIVERSITY CELLULAR ANT
USART
USART
BACKLIGHT
NOT ON
WIFI-ONLY CONFIG
C
GPS ANT
SIM CARD
CSA 60
UART5
HALL EFF 1
BUTTON FLEX
PMU
ADRIANA
BATTERY
USB11
USB2.0
UART2
UART6
CSA 75
HALL EFF 2
HOME BUTTON
DWI
I2C0
CSA 81,82
TRISTAR
I2S1
AUDIO CODEC
I2C1
PROX SENSOR
COMPASS
SENSOR BOARD
SENSOR BOARD
L81
I2C2
GYRO
ACCELEROMETER
CSA 59
FMI0 FMI1
SPI1
SPI
I2S0
ASP
I2S3
I2S4
XSP
MBUS
AMP
SPEAKER
AMP
NC
HP
ALS
CSA 36
SENSOR BOARD
SENSOR BOARD
VGA FLEX
SYNC_MASTER=N/A
SYNC_DATE=N/A
PAGE TITLE
NAND FLASH
MIC1
BLOCK DIAGRAM: SYSTEM
MIC2
DRAWING NUMBER
Apple Inc.
R

CSA 16
051-9385
REVISION
A.0.0
BRANCH
PAGE
2 OF 154
SHEET
2 OF 39
SIZE
SCH AND BOARD P/N
Page Notes
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
051-9385
SCH,MLB,X140
SCH1
CRITICAL
820-3249
PCBF,MLB,X140
PCB1
CRITICAL
Power aliases required by this page:
TABLE_5_ITEM
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
SOC
BOM OPTIONS
COMMON
ALTERNATE
16GB_PROD: 16GB CONFIG
32GB_PROD: 32GB CONFIG
64GB_PROD: 64 GB CONFIG
DEV: DEV BOARD ONLY
MLB: MLB BOARD ONLY
MLB_A: WIFI ONLY CONFIG
MLB_B: CELLULAR CONFIG
MLB_C: CELLULAR CONFIG
MLB_D: LEGACY CELLULAR CONFIG
MLB_E: LEGACY CELLULAR CONFIG
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
U0600
CRITICAL
CRITICAL
U8100
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
343S0598
IC,SOC,H5G,FCBGA1089,0.5MM
PMU
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
TABLE_5_ITEM
343S0622
IC,PMU,ADRIANA,D2018A1,FCBGA
SDRAM
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
TABLE_5_ITEM
333S0636
LPDDR2,533MHZ,512MB,SAMSUNG,35NM
U1300,U1400
CRITICAL
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
BASIC
COMMON,ALTERNATE
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
333S0637
333S0636
U1300,U1400 LPDDR2,533MHZ,HYNIX,38NM
333S0638
333S0636
U1400,U1400 LPDDR2,533MHZ,ELPIDA,38NM
TABLE_BOMGROUP_ITEM
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
TABLE_ALT_ITEM
NAND
16GB FLASH CONFIGURATIONS
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
U1600
CRITICAL
16GB_PROD
CRITICAL
BOM OPTION
U1600
CRITICAL
32GB_PROD
TABLE_5_ITEM
335S0878
TOSHIBA PPN1.5 16GB

MECHANICAL PARTS
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
TABLE_5_ITEM
335S0879
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
PD_FENCE_NAND
CRITICAL
PD_FENCE_LARGE
CRITICAL
PD_FENCE_AMP
CRITICAL
TOSHIBA PPN1.5 32GB
BOM OPTION
TABLE_5_ITEM
NAND
806-4195
FENCE,NAND,TOP,MLB,X140
SOC/PMU
806-3493
FENCE,LARGE,TOP,MLB,X140
AUDIO
806-3956
FENCE,AMP,MLB,X140
GRAPE
806-4196
FENCE,1,BTM,MLB,X140
PD_FENCE_BTM1
CRITICAL
MEMORY
806-3492
FENCE,2,BTM,MLB,X140
PD_FENCE_BTM2
CRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM

TABLE_5_HEAD
PART#
BARCODE LABEL/EEEE CODES
QTY
DESCRIPTION
CRITICAL
BOM OPTION
U1600
CRITICAL
64GB_PROD
CRITICAL
BOM OPTION
U1600
CRITICAL
128GB_PROD
TABLE_5_ITEM
335S0880
TOSHIBA PPN1.5 64GB
TABLE_5_HEAD
CRITICAL
BOM OPTION
825-7838
PART#
QTY
1
EEEE FOR 639-3736 (MLB A 16G)
DESCRIPTION
EEEE_F1WD
CRITICAL
EEEE_MLB_A_16G
825-7838
EEEE_F1WH
CRITICAL
EEEE_MLB_A_32G
825-7838
EEEE_F1W8
CRITICAL
EEEE_MLB_A_64G
825-7838
EEEE_F80Q
CRITICAL
EEEE_MLB_A_128G
825-7838
EEEE FOR 639-3263 (MLB B 16G)
EEEE_DWKG
CRITICAL
EEEE_MLB_B_16G
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
PART#
TABLE_5_ITEM
825-7838
EEEE_F1W7
CRITICAL
EEEE_MLB_B_32G
825-7838
EEEE_F1WC
CRITICAL
EEEE_MLB_B_64G
825-7838
EEEE_F80P
CRITICAL
EEEE_MLB_B_128G
825-7838
EEEE FOR 639-3741 (MLB C 16G)
EEEE_F1WG
CRITICAL
EEEE_MLB_C_16G
825-7838
EEEE_F1WF
CRITICAL
EEEE_MLB_C_32G
825-7838
EEEE_F1W9
CRITICAL
EEEE_MLB_C_64G
825-7838
EEEE_F80R
CRITICAL
EEEE_MLB_C_128G
DESCRIPTION
TABLE_5_ITEM
335S0912
TABLE_5_ITEM
QTY
1
TOSHIBA PPN1.5 128GB
TABLE_5_ITEM
SYNC_MASTER=N/A
TABLE_5_ITEM
PAGE TITLE
SYNC_DATE=N/A
BOM TABLES
TABLE_5_ITEM
DRAWING NUMBER
TABLE_5_ITEM
Apple Inc.
TABLE_5_ITEM

051-9385
REVISION
A.0.0
BRANCH
PAGE
4 OF 154
SHEET
3 OF 39
SIZE
39
0%
1/32W
MF
01005
C0605
0.1UF
20%
2 4V
X5R
01005
34
0.00 2
1
C0606
0.1UF
8.2PF
20%
2 4V
X5R
01005
PP1V8_PL0_F
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
C0607
MAX_NECK_LENGTH=3MM
+/-0.5PF
16V
2 NP0-C0G-CERM
01005
=PP1V0_HSIC_H5
1
C0630
0.01UF
34
C0631
0.01UF
10%
6.3V
2 X5R
01005
10%
2 6.3V
X5R
01005
C0637
C0621
8.2PF
10%
01005
10%
2 6.3V
X5R
01005
C0612
0.01UF
+/-0.5PF
8.2PF
C0608
16V
2 6.3V
2 NP0-C0G-CERM
X5R
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
01005
C0632
0.1UF
20%
2 6.3V
X5R-CERM
01005
C0633
0.1UF
C0634
0.1UF
20%
2 6.3V
X5R-CERM
01005
C0635
0.01UF
20%
2 6.3V
X5R-CERM
01005
10%
2 6.3V
X5R
01005
C0636
8.2PF
8.2PF
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
34
=PP3V3_USB_H5
34
CHANGE TO USB 3.3V TO AVOID

ISSUE FOUND IN H5P:
FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5%
C0614
1UF
+/-0.5PF
10%
6.3V
2 16V
NP0-C0G-CERM 2 CERM
01005
402
BCM4330
WLAN
34 10 7 5 4
BI
36 14
BI
NOSTUFF
=PP1V8_H5
R0608
1
2
5%
MF
1/32W 01005
=PP1V8_H5
36 26
BI
36 26
BI
10
100K 2
1
5%
1/32W 01005
R0621
1
36
100K 2
36
5%
1/32W 01005
36 25
36 25
R0622
10
5%
1/32W 01005
PP0600
SM
R0640
P4MM
PP
7.5K
10
5%
1/32W
MF
2 01005
IN
U0600
BALI-H5G
USB 1.1 BASEBAND/TRISTAR

NEEDED IF WE GO TO 9600
AN17 HSIC3_DATA
AM17 HSIC3_STB
TRISTAR
H17 JTAG_SEL
JTAG_AP_SEL
NC_JTAG_AP_TRTCK
NO_TEST=TRUE
JTAG_AP_TRST_L
TP_JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TMS
JTAG_AP_TCK
J16
K16
H16
F16
F17
J17
XI0 J33
XO0 K33
OMIT_TABLE
C0613
8.2PF
0.1UF
+/-0.5PF
20%
01005
01005
MLB
USB_ANALOGTEST R25
JTAG_TRTCK
JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
USB_VBUS P28
USB_ID P27
USB_BRICKID P31
MLB OPTION USED FOR FF
R0652
AP_WDOG
0.00 2
1
36
36
XTAL_AP_24M_I
XTAL_AP_24M_O
USB_AP_P
USB_AP_N
AP_WDOG_RESET_IN
OUT
0%
1/32W
MF
01005
25
C
1
R0650
USB11_DP E32 USB11_AP_BBMUX_P BI

USB11_DM D32 USB11_AP_BBMUX_N BI
USB_DP M33
USB_DM N33
6 7 9 34
4V
2 16V
NP0-C0G-CERM2 X5R
WDOG C18
BGA
SYM 1 OF 12
AP_TESTMODE
IN
D18 TESTMODE
USB_REXT T30
L31 FUSE1_FSRC
10
=PP1V8_H5
1
39 30 26 25
8MA
C0623
25 36
25 36
BI
25 36
BI
25 36
CRITICAL
1.00M
1%
1/32W
MF
2 01005
Y0602
SM-2
R0651
22
5%
1/32W
MF
01005
24.000MHZ-16PF-60PPM
36
AP_24M_O
CRITICAL
1
2 4
C0650
USB_AP_VBUS0
NC_USB_ID
NC_USB_BRICKID
NO_TEST=TRUE
CRITICAL
C0651
22PF
5%
2 16V
CERM
01005
NC_USB_ANALOGTEST
NO_TEST=TRUE
22PF
PPVBUS_USB
5%
16V
CERM
01005
29
NO_TEST=TRUE
100K 2
1
34 10 7 5 4
IN
2.7MA
PER PIN
R31 HSIC2_DATA
NC_HSIC2_DATA
NO_TEST=TRUE
T31 HSIC2_STB
NC_HSIC2_STB
NO_TEST=TRUE
HSIC3_BB_DATA
HSIC3_BB_STB
R0620
39 36 10
R33 HSIC1_DATA
T33 HSIC1_STB
HSIC1_WLAN_DATA
HSIC1_WLAN_STB
MDM9615
BB
100K
34 10 7 5 4
36 14
11.9MA
PER PIN
5.4MA USB_DVDD R30

30MA USB_VDD330 P26
USB_ASW_VDD18 N26
<1MA
=PP1V8_VDDIO18_H5
1
0.01UF
=PP1V2_HSIC_H5
1
=PP1V0_USB_H5
C0609
10
N32
NEW TO BALI CPU0_SWITCH
CPU_VDD CONTROL CPU1_SWITCH N24
AP_TST_STPCLK
TP_AP_TST_CLKOUT
A19 TST_STPCLK
C19 TST_CLKOUT
OUT
AP_FAST_SCAN_CLK
N27 FAST_SCAN_CLK
IN
AP_HOLD_RESET
G16 HOLD_RESET
OUT
USB_BRICKID_DM_MON P29
R0610
USB_REXT0
CPU0_SWITCH
CPU1_SWITCH
68.1K
OUT
30
OUT
30
NC_USB_BRICKID_DM_MON
NO_TEST=TRUE
1%
1/20W
MF
2 201
R0613
43.2
1%
1/20W
MF
2 201
G17 RESET*
RST_AP_L
1
C0640
1000PF
10%
2 16V
X7R-CERM
0201
R06421
100K
1%
1/32W
MF
01005 2
AP_DDR1_CKEIN_1V2
1
A18
L6
F9
AG10
AD5
CFSB
DDR0_CKEIN
DDR1_CKEIN
DDR2_CKEIN
DDR3_CKEIN
R0643
221K
1%
1/32W
MF
01005 2
P32 USB_ASW_VSS18
VSS
R29 USB_VSSA0
VSS
=PP1V8_PLL_H5
VDD_ANA_PLL U18
OMIT_TABLE
R0604
34
HSIC2_DVDD102 T28
HSIC3_DVDD103 AF18
BGA
SYM 11 OF 12
T25 HSIC2_DVSS
AG19 HSIC3_DVSS
BALI-H5G
M28
N3
N9
N11
N13
N15
N17
N19
N21
N23
P1
P8
P10
P12
P14
P16
P18
P20
P22
P30
P33
R2
R6
R9
R11
R13
R15
R17
R19
R21
R23
R32
T5
T6
T8
T10
T12
T14
T16
T22
T24
T32
U1
U2
U4
U9
U11
U13
U15
U17
U21
U23
U33
V8
V10
V12
V14
V16
V19
V21
V23
V30
W3
W9
W11
W13
W15
W17
W20
W22
W24
Y1
Y10
Y12
Y14
Y16
Y18
Y19
Y21
Y23
Y25
Y28
Y32
AA2
AA9
AA11
AA13
AA15
AA17
AA20
AA22
AA24
HSIC_VSS121
HSIC_VSS122
HSIC_VSS123
U0600
R28
T29
AG18
A1
A2
C33
F1
A11
A14
A17
A32
A33
B1
B2
B4
B9
B12
B15
B32
B33
C7
C10
C13
C16
A3
D3
D5
D8
D11
D14
D17
U19
E10
E22
E24
E25
F2
F5
F22
F24
F25
F30
A31
G3
G18
G21
G22
G26
V18
H4
H9
H10
H11
H12
H13
H14
H21
H22
H28
H33
J2
J9
J11
J13
J15
J21
T18
K3
K8
K10
K12
K14
K22
K26
K30
L1
L4
L9
L11
L13
L15
L17
L19
L21
L33
M2
M3
M8
M10
M12
M14
M16
M18
M20
M22
HSIC_VDD121 R27
HSIC_VDD122 R26
HSIC_VDD123 AF19
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: MAIN
DRAWING NUMBER
Apple Inc.
R

051-9385
REVISION
A.0.0
BRANCH
PAGE
6 OF 154
SHEET
4 OF 39
SIZE
R0700
33.2
36 18
OUT
I2S0_CODEC_ASP_MCK_R 1
L81 CODEC ASP

1.8V
19
OUT
1%
1/32W
MF
01005
R0730
33.2
I2S1_SPKAMP_MCK_R
1%
1/32W
MF
01005
36
36 18
OUT
36 18
OUT
36 18
IN
36 18
OUT
L19 AMPLIFIERS
1.8V
BT
1.8V
19
OUT
19
OUT
19
IN
19
OUT
36 14
OUT
36 14
OUT
36 14
IN
36 14
OUT
36 18
36 18
L81 CODEC XSP

1.8V
OUT
OUT
36 18
IN
36 18
OUT
I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_DOUT
I2S1_SPKAMP_MCK
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_DIN
I2S1_SPKAMP_DOUT
NC_I2S2_MCK
I2S2_BT_BCLK
I2S2_BT_LRCK
I2S2_BT_DIN
I2S2_BT_DOUT
NO_TEST=TRUE
NC_I2S3_MCK
I2S3_CODEC_XSP_BCLK
I2S3_CODEC_XSP_LRCK
I2S3_CODEC_XSP_DIN
I2S3_CODEC_XSP_DOUT
NC_I2S4_MCK
NC_I2S4_BCLK
NC_I2S4_LRCK
NC_I2S4_DIN
NC_I2S4_DOUT
NOT USED
NC_AP_GPIO216
10
USED FOR DEBUG

AND SW UPDATE
OS CURRENTLY SUPPORTS
USB1.1 FOR DEBUG.
TO BB
1.8V IO
10
IN
10
IN
36 18
IN
36 18
OUT
36 18
OUT
36 18
OUT
26
IN
26
OUT
26
36 26
IN
IN
OUT
R0720
100K
5%
1/20W
MF
201 2
36 16
IN
36 16
OUT
36 16
OUT
36 16
OUT
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
M27
M29
N31
M32
M26
H30
L24
L23
M24
N30
J29
L29
L28
L26
L25
L32
E29
K32
J25
M30
F31
H25
K28
K31
J32
AB29
Y29
AA28
AA32
SPI1_CODEC_MISO
SPI1_CODEC_MOSI
SPI1_CODEC_SCLK
SPI1_CODEC_CS_L
U0600
BALI-H5G
BGA
SYM 3 OF 12
OMIT_TABLE
I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT
I2C0_SCL Y33
I2C0_SDA U29
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SCL W27
I2C1_SDA W29
I2C1_SCL_1V8
I2C1_SDA_1V8
I2C2_SCL H20
I2C2_SDA B19
I2C2_SCL_3V0
I2C2_SDA_3V0
BI
OUT
5 19 25 30 36
5 19 25 30 36
BI
OUT
5 22 36
5 22 36
BI
OUT
5 22 36
5 22 36
TO:
TRISTAR 0011010X
ADRIANA PMU 0111100X
L19 LEFT 1000000X
L19 RIGHT 1000001X
OMIT_TABLE
U0600
BALI-H5G
TO SENSOR BOARD:
AD7149 PROX 0101100X
AKM8975B COMPASS 0001110X
TO SENSOR BOARD:
CT809 ALS 0111001X
LIS331DLH ACCEL 0011001X
AP3GDL8 GYRO 1101000X
NC_SWI_AP
SWI_DATA AB27 NO_TEST=TRUE
DWI_CLK T26
DWI_DI W32
DWI_DO W28
I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT
DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO
OUT
30 36
IN
30 36
OUT
30 36
D19
G20
E19
F19
IN
30 20 5
IN
36 26
IN
20
IN
22
IN
14
OUT
26
IN
26
OUT
39 26
OUT
26 5
OUT
26
IN
22
IN
36 26
I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT
I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT
IN
26
IN
10
IN
30 25
IN
10
IN
26
OUT
22
IN
22
IN
IN
36 14
IN
10
IN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
IN
OUT
10
IN
10
IN
30 20 5
IN
16 5
IN
14
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
OUT
30
32 5
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
IN
OUT
20
30 5
AB28 SPI2_MISO
BB_JTAG_TRST_RF_L
AB33 SPI2_MOSI
BB_JTAG_TDI_RF
AC29 SPI2_SCLK
BB_JTAG_TDO_RF
GPIO_BB_HSIC_HOST_RDY W33 SPI2_SSIN
SPI3_GRAPE_MISO
SPI3_GRAPE_MOSI
SPI3_GRAPE_SCLK
SPI3_GRAPE_CS_L
30 23 5
36 14 5
K29 SPDIF
Y31
V28
V32
V29
GPIO_BOARD_ID_2
GPIO_BOARD_ID_1
GPIO_BOARD_ID_0
TP_SPI0_SSIN
I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT
IN
19 5
OUT
19 5
OUT
19
IN
15
OUT
19
IN
19
IN
18
IN
16
OUT
16
OUT
GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BB_HSIC_DEV_RDY
GPIO_BTN_VOL_UP_L
GPIO_ALS_IRQ_L
GPIO_BT_WAKE
GPIO_AP_MODEM_WAKE
BB_JTAG_TMS_RF
GPIO_BB_RST_L
GPIO_BB_RADIO_ON_L
GPIO_BB_RESET_DET_L
GPIO_ACCEL_IRQ2_L
GPIO_BB_HSIC_RESUME
GPIO_WLAN_HSIC_HOST_RDY
GPIO_BTN_VOL_DOWN_L
GPIO_BB_GSM_TXBURST
GPIO_BOARD_ID_3
PMU_GPIO_TS_INT
GPIO_BOOT_CONFIG_0
GPIO_BB_GPS_SYNC
GPIO_PROX_IRQ_L
GPIO_GYRO_IRQ1
GPIO_PMU_KEEPACT
GPIO_PMU_IRQ_L
GPIO_WLAN_HSIC_DEV_RDY
GPIO_BOOT_CONFIG_1
GPIO_FORCE_DFU
GPIO_DFU_STATUS
GPIO_BOOT_CONFIG_2
GPIO_BOOT_CONFIG_3
GPIO_BTN_SRL_L
GPIO_GRAPE_IRQ_L
GPIO_WL_HSIC_RESUME
GPIO_SPKAMP_RST_L
GPIO_SPKAMP_KEEPALIVE
GPIO_SPKAMP_RIGHT_IRQ_L
PM_LCDVDD_PWREN
GPIO_SPKAMP_LEFT_IRQ_L
SPK_ID
GPIO_CODEC_IRQ_L
AK20
AJ19
AK22
AK19
AK21
AK24
AJ21
AK18
AL26
AH25
AJ18
AJ23
AK23
AJ20
AJ22
AJ24
AL25
AM26
AK25
AN26
F26
E26
J31
F29
E30
H31
J30
H32
G27
E27
F32
J28
G31
G32
G28
G33
J26
G30
G29
F27
GPIO_GRAPE_FW_DNLD_EN_L
GPIO_GRAPE_RST_L
H19
J19
BGA
SYM 2 OF 12
EHCI_PORT_PWR0
EHCI_PORT_PWR1
EHCI_PORT_PWR2
EHCI_PORT_PWR3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
AK28
AJ25
AK26
AK27
TMR32_PWM0 V33
TMR32_PWM1 W31
TMR32_PWM2 V27
UART0_RXD K18
UART0_TXD K19
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
AM27
AM28
AN27
AN28
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
Y30
AC27
AC33
AD33
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
AB32
AC30
AC32
AD32
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
Y27
AA29
AB31
AC31
UART5_RXD J18
UART5_TXD K17
UART6_CTSN
UART6_RTSN
UART6_RXD
UART6_TXD
AC28
W30
AA30
AA31
GPIO_BRD_REV0
GPIO_BRD_REV1
GPIO_BRD_REV2
NC_EHCI_PORT_PWR3_AP
NO_TEST=TRUE
GPIO_GYRO_IRQ2
GPIO_ACCEL_IRQ1_L
NC_TMR32_PWM2_AP
NO_TEST=TRUE
10
IN
10
IN
22
IN
22
NC_UART0_RXD
NC_UART0_TXD
NO_TEST=TRUE
UART1_BB_CTS_L
UART1_BB_RTS_L
UART1_BB_RXD
UART1_BB_TXD
BB_JTAG_TCK_RF
NC_UART2_RTSN
UART2_TS_ACC_RXD
UART2_TS_ACC_TXD
IN
26 36
26 36
OUT
IN
25 26 36
OUT
25 26 36
OUT
26
TO BB UART
MDM9600
NO_TEST=TRUE
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
IN
25 36
OUT
25 36
IN
14 36
OUT
14 36
IN
14 36
OUT
14 36
IN
14 36
OUT
14 36
TO TRISTAR
1.8V
TO BT UART
BCM4330
NO_TEST=TRUE
NC_UART4_CTS_L
NC_UART4_RTC_L
UART4_WLAN_RXD
UART4_WLAN_TXD
NO_TEST=TRUE
UART5_BATTERY_TRXD
NC_UART5_TXD
35
WIFI DEBUG
28 30
OUT
NO_TEST=TRUE
NC_UART6_CTSN
NC_UART6_RTSN
UART6_AP_RXD
UART6_AP_TXD
NO_TEST=TRUE
NO_TEST=TRUE
IN
25 36
OUT
25 36
TO TRISTAR
1.8V
=PP1V8_H5
1
R0716
100K
GPIO_VSEL25_I2C2 E31
GPIO_VSEL25_SPI3 H29
GRAPE
3.0V
10
IN
NO_TEST=TRUE
GPIO_SVSEL18_FMI H27
GPIO_SVSEL25_FMI G25
GPIO_3V0
GPIO_3V1
IN
5%
1/20W
MF
2 201
4 5 7 10 34
R0717
100K
5%
1/20W
MF
2 201
GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3
VSEL18_FMI AND VSEL25_FMI LOW => FMI CHANNEL AT 1.8V
VSEL25_I2C2 HIGH => I2C2 3.0V
VSEL25_SPI3 HIGH => SPI3 3.0V
B
34 10 7 5 4
=PP1V8_H5
1
NOSTUFF
R0760
100K
5%
1/20W
MF
2 201
16 5
GPIO_GRAPE_IRQ_L
BUTTON PULLUPS
I2C PULL-UPS
R0708
34 32 5
30 23 5
220K 2
=PP1V8_S2R_MISC 1
GPIO_PMU_KEEPACT
GPIO_FORCE_DFU
GPIO_DFU_STATUS
GPIO_BB_RADIO_ON_L
GPIO_SPKAMP_RST_L
5%
1/20W
MF
201
GPIO_BTN_HOME_L
R0709
=PP1V8_ALWAYS
34
30 20 5
GPIO_BTN_ONOFF_L
220K 2
5%
1/20W
MF
201
R0710
34 32 5
30 20 5
220K 2
=PP1V8_S2R_MISC 1
GPIO_BTN_SRL_L
5%
1/20W
MF
201
R0711
100K
5%
1/20W
MF
2 201
R0713
100K
5%
1/20W
MF
2 201
NOSTUFF
R0714
100K
5%
1/20W
MF
2 201
NOSTUFF
R0715
100K
5%
1/20W
MF
2 201
R0718
100K
5%
1/20W
MF
2 201
R0719
100K
5%
1/20W
MF
2 201
NEED TO CHARACTERIZE RISE TIME

AND SIZE THESE RESISTORS
5 30
5 32
21 20
5
5 26
34 10 7 5 4
5 14 36
R0701
5 19
2.2K
5%
1/32W
MF
2 01005
5 19
R0721
100K
5%
1/20W
MF
2 201
PP3V0_SENSOR_FLT
=PP1V8_H5
36 30 25 19 5
I2C0_SDA_1V8
36 30 25 19 5
I2C0_SCL_1V8
36 22 5
I2C1_SDA_1V8
36 22 5
I2C1_SCL_1V8
36 22 5
I2C2_SDA_3V0
36 22 5
I2C2_SCL_3V0
R0702
2.2K
5%
1/32W
MF
2 01005
R0703
1.00K
5%
1/32W
MF
2 01005
R0704
1.00K
5%
1/32W
MF
2 01005
R0705
1.00K
5%
1/32W
MF
2 01005
R0706
1.00K
5%
1/32W
MF
2 01005
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: I/Os
DRAWING NUMBER
Apple Inc.
R

051-9385
REVISION
A.0.0
BRANCH
PAGE
7 OF 154
SHEET
5 OF 39
SIZE
34 9 6
AB8
AB10
AB12
AB14
AB16
AB18
AB19
AB21
AB23
AB25
AB30
AC1
AC3
AC9
AC11
AC13
AC15
AC17
AC20
AC22
AC24
AD8
AD10
AD12
AD14
AD16
AD18
AD19
AD21
AD23
AD25
AE4
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE17
AE22
AE30
AE32
A6
AF3
AF16
AG2
AG16
AG17
AG25
U0600
BALI-H5G
BGA
SYM 12 OF 12
OMIT_TABLE
VSS
VSS
AH5
AH10
AH15
AH16
AH17
AH30
AH32
P24
AJ17
AJ27
AK2
AK8
AK14
AK17
AH1
AL3
AL7
AL10
AL13
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL1
AL29
AM1
AM2
AM6
AM9
AM12
AM15
AM32
AM33
AN1
AN2
AL33
T20
AN11
AN14
AN32
AN33
AN3
AN31
AN6
C1
=PP1V8_NAND_H5
1
R0832
100K
38 13 6
FMI1_CE0_L
38 13 6
FMI0_CE0_L
R0831
100K
5%
1/32W
MF
2 01005
5%
1/32W
MF
2 01005
C
38 13 6
OUT
38 13
BI
38 13
BI
38 13
BI
38 13
BI
38 13
BI
38 13
BI
38 13
BI
38 13
BI
FMI0_CE0_L
NC_FMI0_CE1_L
NC_FMI0_CE2_L
NC_FMI0_CE3_L
NC_FMI0_CE4_L
NC_FMI0_CE5_L
NC_FMI0_CE6_L
NC_FMI0_CE7_L
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
38 13
OUT
38 13
OUT
38 13
OUT
38 13
OUT
38 13
OUT
34 9 6
AN29
AM30
AL28
AL27
AJ32
AJ31
AM31
AL30
FMI0_CEN0
FMI0_CEN1
FMI0_CEN2
FMI0_CEN3
FMI0_CEN4
FMI0_CEN5
FMI0_CEN6
FMI0_CEN7
AM29
AK33
AJ30
AK31
AH28
AJ29
AN30
AH27
FMI0_IO0
FMI0_IO1
FMI0_IO2
FMI0_IO3
FMI0_IO4
FMI0_IO5
FMI0_IO6
FMI0_IO7
CKPLUS_WAIVE=PDIFPR_BADTERM
AK29
NC_FMI0_RE
NO_TEST=TRUE
AJ28
FMI0_ALE
AH29
FMI0_CLE
AK32
FMI0_WE_L
AK30
FMI0_RE_L
AL31
FMI0_DQS
NC_FMI0_DQSN NO_TEST=TRUE AL32
AG27
U0600
BALI-H5G
BGA
SYM 4 OF 12
OMIT_TABLE
FMI0_WENN
FMI0_ALE
FMI0_CLE
FMI0_WEN
FMI0_REN
FMI0_DQS
FMI0_DQSN
FMI0_DQVREF
=PP1V8_NAND_H5
AF26
AB26
PVDDP_GRP1
PVDDP_GRP2
FMI_DQVREF_H5
AG28
FMI0_VREF
FMI1_CEN0
FMI1_CEN1
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN5
FMI1_CEN6
FMI1_CEN7
AF29
AF30
AE29
AD30
AF27
AE27
AF28
AE28
FMI1_IO0
FMI1_IO1
FMI1_IO2
FMI1_IO3
FMI1_IO4
FMI1_IO5
FMI1_IO6
FMI1_IO7
AE33
AH33
AG33
AG30
AD31
AE31
AG29
AD29
FMI1_WENN
FMI1_ALE
FMI1_CLE
FMI1_WEN
FMI1_REN
FMI1_DQS
FMI1_DQSN
FMI1_DQVREF
FMI1_CE0_L
NC_FMI1_CE1_L
NC_FMI1_CE2_L
NC_FMI1_CE3_L
NC_FMI1_CE4_L
NC_FMI1_CE5_L
NC_FMI1_CE6_L
NC_FMI1_CE7_L
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
OUT
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
CKPLUS_WAIVE=PDIFPR_BADTERM
AG31 NO_TEST=TRUE NC_FMI1_RE
AJ33
FMI1_ALE
AH31
FMI1_CLE
AG32
FMI1_WE_L
AF31
FMI1_RE_L
AF32
FMI1_DQS
AF33 NO_TEST=TRUE NC_FMI1_DQSN
AD27
6 13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
OUT
13 38
OUT
13 38
OUT
13 38
OUT
13 38
OUT
13 38
=PP1V8_NAND_H5
1
=PP1V8_VDDIO18_H5
PVDDP_GRP3 P25
PVDDP_GRP4 G19
PVDDP_GRP5 K24
FMI1_VREF AD28
R0842
51.1K
1%
1/32W
MF
2 01005
34 9 7 6 4
C0820
0.1UF
20%
2 4V
X5R
01005
0.1UF
FMI_DQVREF_H5
R0843
=PP1V8_NAND_H5
C0842
20%
2 4V
X5R
01005
1%
1/32W
MF
2 01005
34 9 6
51.1K
4 6 7 9 34
6 9 34
C0843
0.1UF
20%
2 4V
X5R
01005
=PP1V8_VDDIO18_H5
C0821
0.1UF
C0810
0.1UF
20%
2 4V
X5R
01005
20%
4V
2 X5R
01005
C0811
0.1UF
20%
4V
2 X5R
01005
C0812
0.1UF
20%
4V
2 X5R
01005
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: NAND
DRAWING NUMBER
Apple Inc.
R

051-9385
REVISION
A.0.0
BRANCH
PAGE
8 OF 154
SHEET
6 OF 39
SIZE
4
34
=PP1V0_DP_PAD_DVDD_H5
1
C0910
8.2PF
+/-0.1PF%
25V
2 CER
0201
=PP1V8_DP_H5
R0911
=PP1V8_EDP_H5
34
5%
1/20W
MF
201
C0931
56PF
5%
2 6.3V
NP0-C0G
01005
C0928
8.2PF
C0929
8.2PF
C0930
56PF
C0932
0.22UF
+/-0.5PF
+/-0.5PF
5%
2 16V
2 16V
2 6.3V
NP0-C0G-CERM
NP0-C0G-CERM
NP0-C0G
01005
01005
01005
20%
2 6.3V
X5R
402
39
PP1V8_EDP_AVDD_AUX
C0933
0.22UF
C0927
0.1UF
56PF
20%
2 4V
X5R
01005
C0934
0.22UF
34
C0924
5%
2 6.3V
NP0-C0G
01005
20%
2 6.3V
X5R
402
20%
2 6.3V
X5R
402
=PP1V8_VDDIO18_H5
1
0.01UF
10%
2 6.3V
X5R
01005
=PP1V0_EDP_PAD_DVDD_H5
34
C0909
0.1UF
10%
2 6.3V
X5R
201
=PP1V8_VDDIO18_H5 4
VOLTAGE=1.8V
C0955
0.1UF
10%
2 6.3V
X5R
201
R0950
39
6.34K
1%
1/20W
MF
2 201
10%
6.3V
2 X5R
201
NC_DAC_AP_OUT2
K23 DAC_COMP
OMIT_TABLE
DAC_OUT1 F33
NO_TEST=TRUE
NC_DAC_AP_OUT1
DP_HPD B18
NO_TEST=TRUE
NC_DP_HPD
NC_DP_AUX_P
NC_DP_AUX_N
1UF
C0981
0.01UF
10%
2 6.3V
CERM
402
10%
2 6.3V
X5R
01005
C0982
56PF
5%
2 6.3V
NP0-C0G
01005
IN
VOLTAGE=0.4V
PP0V4_MIPI0D
MAX_NECK_LENGTH=3MM
C0960
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
37 15
OUT
2.2NF
10%
2 10V
X5R-CERM
0201
=PP1V0_MIPI_H5
C0908
0.1UF
C0903
0.1UF
10%
2 6.3V
X5R
201
8.2PF
IN
37 21
IN
37 21
IN
37 21
IN
IN
37 21
IN
MIPI0C_CAM_RF_DATA_P<0>
MIPI0C_CAM_RF_DATA_N<0>
AM22 MIPI0C_DPDATA0
AN22 MIPI0C_DNDATA0
AM21 MIPI0C_DPDATA1
AN21 MIPI0C_DNDATA1
NC_MIPI0C_CAM_RF_DATA_P<2>
NC_MIPI0C_CAM_RF_DATA_N<2>
NO_TEST=TRUE
NC_MIPI0C_CAM_RF_DATA_P<3>
NC_MIPI0C_CAM_RF_DATA_N<3>
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
BGA
SYM 5 OF 12
OMIT_TABLE
AM19 MIPI0C_DPDATA2
AN19 MIPI0C_DNDATA2
R0930
1.00K
5%
1/32W
MF
2 01005
ISP0_FLASH
ISP0_PRE_FLASH
ISP0_SCL
ISP0_SDA
M25
M31
AA27
U28
ISP1_FLASH
ISP1_PRE_FLASH
ISP1_SCL
ISP1_SDA
N25 SOCHOT1_L
L30 SOCHOT0_L
AA33
U30
R0931
1.00K
5%
1/32W
MF
2 01005
NO_TEST=TRUE
EDP_DATA_P<0> A30 EDP_PAD_TX0P

EDP_DATA_N<0> A29 EDP_PAD_TX0N
DP_PAD_TX0P D24
DP_PAD_TX0N D23
NO_TEST=TRUE
EDP_DATA_P<1> D28 EDP_PAD_TX1P

EDP_DATA_N<1> D27 EDP_PAD_TX1N
DP_PAD_TX1P B24
DP_PAD_TX1N B23
NO_TEST=TRUE
EDP_DATA_P<2> B28 EDP_PAD_TX2P

EDP_DATA_N<2> B27 EDP_PAD_TX2N
DP_PAD_TX2P C22
DP_PAD_TX2N C21
NO_TEST=TRUE
EDP_DATA_P<3> C26 EDP_PAD_TX3P

EDP_DATA_N<3> C25 EDP_PAD_TX3N
DP_PAD_TX3P A22
DP_PAD_TX3N A21
NO_TEST=TRUE
NO_TEST=TRUE
NC_DP_DATA_P<0>
NC_DP_DATA_N<0>
NO_TEST=TRUE
NC_DP_DATA_P<1>
NC_DP_DATA_N<1>
NO_TEST=TRUE
NC_DP_DATA_P<2>
NC_DP_DATA_N<2>
NO_TEST=TRUE
NC_DP_DATA_P<3>
NC_DP_DATA_N<3>
NO_TEST=TRUE
E28 EDP_PAD_R_BIAS
R0921
4.99K
F28 EDP_PAD_DC_TP
1%
1/32W
MF
2 01005
4 5 7 10 34
R0932
R0933
1.00K
1.00K
5%
1/32W
MF
2 01005
TP_EDP_AP_ANALOG_TEST
5%
1/32W
MF
2 01005
NO_TEST=TRUE
ISP0_CAM_RF_RST_L
OUT
NC_ISP0_CAM_RF_FLASH
ISP0_CAM_RF_I2C_SCL OUT
ISP0_CAM_RF_I2C_SDA BI
DP_PAD_R_BIAS E23
DP_R_BIAS
NOTE: 0.6V ANALOG REF
DP_PAD_DC_TP F23 TP_DP_AP_ANALOG_TEST
R0920
4.99K
1%
1/32W
MF
2 01005
0.01UF
10%
6.3V
2 X5R
01005
22
22 36
22 36
7 32
7
FRONT FACING CAM
ISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDA
ISP1_CAM_FF_CLK_R
MIPI1C_DPDATA1 AM25
MIPI1C_DNDATA1 AN25
0%
1/32W
R0940
ISP1_CAM_FF_CLK
ISP1_CAM_FF_SHUTDOWN_L
MF
01005
MIPI1C_CAM_FF_DATA_P<0>
MIPI1C_CAM_FF_DATA_N<0>
NO_TEST=TRUE
NO_TEST=TRUE
22 36
BI
22 36
OUT
22 36
OUT
22
OUT
22 36
OUT
22
SHUTDOWN IS ACTIVE HIGH
SHUTDOWN IS ACTIVE LOW
=PP1V8_H5
IN
21 37
IN
21 37
MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_N
NOSTUFF
R0942
IN
21 37
IN
21 37
SOCHOT1_L PULL-UP ON CSA 90

32 7
SOCHOT1_L
SOCHOT0_L
4 5 7 10 34
R0941
100K
NC_MIPI1C_CAM_FF_DATA_P<1>
NC_MIPI1C_CAM_FF_DATA_N<1>
AG20
AG21
AG22
AG23
AG24
MIPI1C_DPCLK AM24
MIPI1C_DNCLK AN24
0.00 2
1
OUT
100K
5%
1/32W
MF
2 01005
5%
1/32W
MF
2 01005
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: TV,DP,MIPI
DRAWING NUMBER
Apple Inc.
NOSTUFF
C0950
REAR FACING CAM
U31
36
SENSOR1_CLK
SENSOR1_RST T27
MIPI0C_DPCLK
MIPI0C_DNCLK
C0957
10%
2 6.3V
X5R
01005
DP_PAD_AUXP A26
DP_PAD_AUXN A25
AP_EDP_R_BIAS
NOSTUFF
1
0.01UF
=PP1V8_H5
MIPI1C_DPDATA0 AM23
MIPI1C_DNDATA0 AN23
0.00 2 R0900
1
0%
MF
ISP0_CAM_RF_CLK
36 V31 ISP0_CAM_RF_CLK_R
SENSOR0_CLK
01005
1/32W
ISP0_CAM_RF_SHUTDOWN
SENSOR0_RST U32
AM18 MIPI0C_DPDATA3
AN18 MIPI0C_DNDATA3
AM20
AN20
MIPI0C_CAM_RF_CLK_P
MIPI0C_CAM_RF_CLK_N
U0600
BALI-H5G
MIPI_VSS
37 21
U27 MIPI_VSYNC
2MA
PER PIN
10%
2 10V
X5R-CERM
0201
EDP_AUX_P
EDP_AUX_N
C30 EDP_PAD_AUXP
C29 EDP_PAD_AUXN
NOTE: 0.6V ANALOG REF
C0961
2.2NF
40MA MIPI_VDD10
37 21
NO_TEST=TRUE
MAX_NECK_LENGTH=3MM
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
B
NC_MIPI_VSYNC_H5
VOLTAGE=0.4V
PP0V4_MIPI1D
C0904
AF20
AF21
AF22
AF23
AF24
10%
2 6.3V
X5R
201
E18 EDP_HPD
B25
B26
A27
A28
1UF
10%
2 6.3V
CERM
402
MIPI0D_VREG_0P4V AH20
MIPI1D_VREG_0P4V AH23
C0935
MIPI0D_VDD18 AH19
MIPI1D_VDD18 AH24
3.3MA
MIPI0D_VDD10_PLL AH21
3.3MA
MIPI1D_VDD10_PLL AH22
34
EDP_HPD
G24 DAC_AVSS18A
C0980
15MA DAC_AVDD18A H24
NO_TEST=TRUE
G23 DAC_AVSS18D
0201-1
1
C0907
0.1UF
PP1V0_MIPI_PLL_F
15MA DAC_AVDD18D H23
NC_DAC_AP_OUT3
DAC_OUT2 E33
B22 DP_PAD_AVSS_AUX
39
A20
B20
E20
E21
NO_TEST=TRUE
BGA
SYM 6 OF 12
DP_PAD_AVSS3
DP_PAD_AVSS1
DP_PAD_AVSS2
DP_PAD_AVSS0
MAX_NECK_LENGTH=3MM
D25
D26
C27
C28
DAC_OUT3 D33
J24 DAC_IREF
C20
F20
D20
F21
=PP1V0_MIPI_PLL_H5 1
0.01UF
J23 DAC_VREF
BALI-H5G
6 7 9 34
C0952
10%
2 6.3V
X5R
01005
20%
2 4V
X5R
01005
DAC_AP_IREF
37 15
34
U0600
65MA
PER PIN
B21 DP_PAD_AVSSP0
80-OHM-0.2A-0.4-OHM
34
=PP1V8_MIPI_H5
VOLTAGE=1.0V
FL0910
DAC_AP_VREF
DAC_AP_COMP
65MA
PER PIN
16MA DP_PAD_AVDD_AUX D22
10%
2 6.3V
X5R
201
NOSTUFF
DP_PAD_AVDD3
DP_PAD_AVDD2
DP_PAD_AVDD1
DP_PAD_AVDD0
0.1UF
NOSTUFF
10MA DP_PAD_AVDDP0 D21
NOSTUFF
C0956
22MA DP_PAD_AVDDX C23
1
TABLE_ALT_ITEM
A23 DP_PAD_AVSSX
RDAR://PROBLEM/11104943
15MA DP_PAD_DVDD C24
FL0910
A24 DP_PAD_DVSS
16MA EDP_PAD_AVDD_AUX D30
155S0359
B30 EDP_PAD_AVSS_AUX
155S0725
B29 EDP_PAD_AVSSP0
COMMENTS:
C32 EDP_PAD_AVSSX
REF DES
D31 EDP_PAD_DVSS
BOM OPTION
EDP_PAD_AVSS3
EDP_PAD_AVSS2
EDP_PAD_AVSS1
EDP_PAD_AVSS0
ALTERNATE FOR
PART NUMBER
EDP_PAD_AVDD3
EDP_PAD_AVDD2
EDP_PAD_AVDD1
EDP_PAD_AVDD0
TABLE_ALT_HEAD
PART NUMBER
EDP_PAD_AVDDP0 D29
DAC_AP_COMP_FTR
10MA
2
0201
EDP_PAD_AVDDX B31
22MA
15MA EDP_PAD_DVDD C31
FL0911
240-OHM-0.2A-0.8-OHM
=PP1V8_VDDIO18_H5
C0951
0.1UF
MAX_NECK_LENGTH=3MM
NOSTUFF
34 9 7 6 4
4 6 7 9 34
C0953
051-9385
REVISION
A.0.0
BRANCH
PAGE
9 OF 154
SHEET
7 OF 39
SIZE
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
OUT
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
BI
38 11
OUT
38 11
OUT
38 11
OUT
38 11
34 8
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<2>
DDR1_CA<3>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>
DDR0_DM<0>
DDR0_DM<1>
DDR0_DM<2>
DDR0_DM<3>
E12
E9
C14
D6
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR1_DM0
DDR1_DM1
DDR1_DM2
DDR1_DM3
L5
N5
G4
R5
DDR1_DM<0>
DDR1_DM<1>
DDR1_DM<2>
DDR1_DM<3>
DDR0_DQS_P<0>
DDR0_DQS_N<0>
DDR0_DQS_P<1>
DDR0_DQS_N<1>
DDR0_DQS_P<2>
DDR0_DQS_N<2>
DDR0_DQS_P<3>
DDR0_DQS_N<3>
A13
A12
A7
A8
A16
A15
A4
A5
DDR0_PDQS0
DDR0_NDQS0
DDR0_PDQS1
DDR0_NDQS1
DDR0_PDQS2
DDR0_NDQS2
DDR0_PDQS3
DDR0_NDQS3
DDR1_PDQS0
DDR1_NDQS0
DDR1_PDQS1
DDR1_NDQS1
DDR1_PDQS2
DDR1_NDQS2
DDR1_PDQS3
DDR1_NDQS3
G1
H1
N1
M1
D1
E1
T1
R1
DDR1_DQS_P<0>
DDR1_DQS_N<0>
DDR1_DQS_P<1>
DDR1_DQS_N<1>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
DDR0_CK
DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_RREF
DDR0_CSN0
DDR0_CSN1
DDR0_VREF_DQ
DDR0_VDD_CKE
4.7K
PPVREF_DDR1_DQ_H5
=PP1V2_S2R_H5
20%
6.3V
X5R
0201
10%
2 6.3V
X5R
01005
C1054
0.01UF
10%
6.3V
2 X5R
01005
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
OUT
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
BI
11 38
38 12
BI
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
OUT
11 38
38 12
OUT
8
8 34
34 8
R1056
4.7K
1%
1/32W
MF
2 01005
DDR3_CA<0>
DDR3_CA<1>
DDR3_CA<2>
DDR3_CA<3>
DDR3_CA<4>
DDR3_CA<5>
DDR3_CA<6>
DDR3_CA<7>
DDR3_CA<8>
DDR3_CA<9>
DDR2_DM<0>
DDR2_DM<1>
DDR2_DM<2>
DDR2_DM<3>
AD4
AG4
AB6
AK4
DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
AK11
AG14
AJ8
AG15
DDR3_DM<0>
DDR3_DM<1>
DDR3_DM<2>
DDR3_DM<3>
DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
DDR2_DQS_P<3>
DDR2_DQS_N<3>
AA1
AB1
AG1
AF1
V1
W1
AK1
AJ1
DDR2_PDQS0
DDR2_NDQS0
DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2
DDR2_NDQS2
DDR2_PDQS3
DDR2_NDQS3
DDR3_PDQS0
DDR3_NDQS0
DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2
DDR3_NDQS2
DDR3_PDQS3
DDR3_NDQS3
AN7
AN8
AN13
AN12
AN4
AN5
AN16
AN15
DDR3_DQS_P<0>
DDR3_DQS_N<0>
DDR3_DQS_P<1>
DDR3_DQS_N<1>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
DDR3_DQS_P<3>
DDR3_DQS_N<3>
AH14
DDR2_CK_P
AH13
DDR2_CK_N
AN10
DDR2_CKE<0>
NC_DDR2_CKE<1> NO_TEST=TRUEAN9
AH9
H5G_DDR2_ZQ
AG9
DDR2_CSN<0>
NO_TEST=TRUE
AG8
NC_DDR2_CSN<1>
PPVREF_DDR2_DQ_H5
=PP1V2_S2R_H5
1
C1056
0.01UF
10%
6.3V
2 X5R
01005
R1084
4.7K
1%
1/32W
MF
2 01005
C1022
20%
6.3V
X5R
0201
C1084
0.01UF
10%
2 6.3V
X5R
01005
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
12 38
12 38
12 38
12 38
R10234
C1023
240
1%
1/20W
MF
2 201
20%
6.3V
X5R
0201
C1095
10%
2 6.3V
X5R
01005
SYNC_MASTER=N/A
PAGE TITLE
PPVREF_DDR3_DQ_H5
VOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
12 38
BI
0.01UF
1%
1/32W
MF
2 01005
10%
2 6.3V
X5R
01005
12 38
BI
=PP1V2_VDDIOD_H5
4.7K
0.01UF
BI
0.22UF
R1095
C1085
AH4
DDR3_CK_P
OUT
AJ4
DDR3_CK_N
OUT
AD1
DDR3_CKE<0>
OUT
AE1 NO_TEST=TRUE NC_DDR3_CKE<1>
AB5
H5G_DDR3_ZQ
AC6
DDR3_CSN<0>
OUT
AC5 NO_TEST=TRUE NC_DDR3_CSN<1>
AJ11
PPVREF_DDR3_DQ_H5 8
AE8
=PP1V2_S2R_H5 8 34
0.22UF
PPVREF_DDR2_DQ_H5
1
DDR3_CK
DDR3_CKB
DDR3_CKE0
DDR3_CKE1
DDR3_RREF
DDR3_CSN0
DDR3_CSN1
DDR3_VREF_DQ
DDR3_VDD_CKE
1
1
VOLTAGE=0.6V
DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_RREF
DDR2_CSN0
DDR2_CSN1
AB4 DDR2_VREF_DQ
Y8 DDR2_VDD_CKE
34 9 8
4.7K
10%
2 6.3V
X5R
01005
OMIT_TABLE
W5
W6
Y5
Y6
AA6
AD6
AE5
AE6
AF6
AF5
=PP1V2_VDDIOD_H5
R1083
0.01UF
BGA
SYM 8 OF 12
DDR3_DQ<0>
DDR3_DQ<1>
DDR3_DQ<2>
DDR3_DQ<3>
DDR3_DQ<4>
DDR3_DQ<5>
DDR3_DQ<6>
DDR3_DQ<7>
DDR3_DQ<8>
DDR3_DQ<9>
DDR3_DQ<10>
DDR3_DQ<11>
DDR3_DQ<12>
DDR3_DQ<13>
DDR3_DQ<14>
DDR3_DQ<15>
DDR3_DQ<16>
DDR3_DQ<17>
DDR3_DQ<18>
DDR3_DQ<19>
DDR3_DQ<20>
DDR3_DQ<21>
DDR3_DQ<22>
DDR3_DQ<23>
DDR3_DQ<24>
DDR3_DQ<25>
DDR3_DQ<26>
DDR3_DQ<27>
DDR3_DQ<28>
DDR3_DQ<29>
DDR3_DQ<30>
DDR3_DQ<31>
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9
1%
1/20W
MF
2 201
1%
1/32W
MF
2 01005
BALI-H5G
AL8
AL9
AK9
AJ9
AM10
AJ10
AK10
AL11
AM11
AL12
AK12
AJ12
AM13
AK13
AJ13
AJ14
AM5
AL6
AK6
AJ6
AM7
AK7
AJ7
AM8
AM14
AL14
AJ15
AK15
AL15
AJ16
AK16
AM16
DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA4
DDR2_CA5
DDR2_CA6
DDR2_CA7
DDR2_CA8
DDR2_CA9
240
1%
1/20W
MF
2 201
20%
6.3V
X5R
0201
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
U0600
AH6
AG6
AH7
AG7
AH8
AH11
AG11
AG12
AH12
AG13
R1022
240
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>
R1021
AB2
AB3
AC2
AC4
AD2
AD3
AE2
AE3
AF2
AF4
AG5
AH2
AJ2
AG3
AH3
AJ3
W2
W4
Y2
Y3
Y4
AA3
AA4
AA5
AK3
AL2
AM3
AM4
AL4
AL5
AK5
AJ5
DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>
11 38
C1021
PPVREF_DDR1_DQ_H5
BI
C1058
VOLTAGE=0.6V
BI
38 12
34 9 8
1%
1/32W
MF
2 01005
0.01UF
38 12
11 38
4.7K
C1057
11 38
BI
=PP1V2_VDDIOD_H5
R1055
PPVREF_DDR0_DQ_H5
NO_TEST=TRUE
DDR1_CK_P
DDR1_CK_N
DDR1_CKE<0>
NC_DDR1_CKE<1>
H5G_DDR1_ZQ
DDR1_CSN<0>
NC_DDR1_CSN<1>
BI
0.22UF
R1053
NO_TEST=TRUE
34 9 8
1%
1/32W
MF
01005
F11
F12
A10
A9
E11
F10
E13
L3
H8
C1020
=PP1V2_VDDIOD_H5
4.7K
DDR1_CK
DDR1_CKB
DDR1_CKE0
DDR1_CKE1
DDR1_RREF
DDR1_CSN0
DDR1_CSN1
DDR1_VREF_DQ
DDR1_VDD_CKE
0.22UF
1%
1/20W
MF
2 201
R1054
DDR1_DQ<0>
DDR1_DQ<1>
DDR1_DQ<2>
DDR1_DQ<3>
DDR1_DQ<4>
DDR1_DQ<5>
DDR1_DQ<6>
DDR1_DQ<7>
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<13>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<16>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQ<22>
DDR1_DQ<23>
DDR1_DQ<24>
DDR1_DQ<25>
DDR1_DQ<26>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQ<29>
DDR1_DQ<30>
DDR1_DQ<31>
E15
F15
F14
E14
F13
E8
F8
F7
E7
F6
240
OMIT_TABLE
H2
H3
J3
J4
K2
L2
K4
K5
N2
P2
P3
R3
T2
R4
T3
T4
C2
D2
E2
E4
E3
F3
F4
G2
U3
V2
V3
U5
V4
V5
U6
V6
DDR1_CA0
DDR1_CA1
DDR1_CA2
DDR1_CA3
DDR1_CA4
DDR1_CA5
DDR1_CA6
DDR1_CA7
DDR1_CA8
DDR1_CA9
R1020
1%
1/32W
MF
2 01005
BGA
SYM 7 OF 12
DDR1_DQ0
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ30
DDR1_DQ31
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CA6
DDR0_CA7
DDR0_CA8
DDR0_CA9
U0600
BALI-H5G
G5
G6
H5
H6
J5
M5
M6
N6
P5
P6
P4
N4
J1
NO_TEST=TRUE K1
M4
K6
NO_TEST=TRUE J6
PPVREF_DDR0_DQ_H5 D10
H15
=PP1V2_S2R_H5
OUT
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4>
DDR0_CA<5>
DDR0_CA<6>
DDR0_CA<7>
DDR0_CA<8>
DDR0_CA<9>
DDR0_CK_P
DDR0_CK_N
DDR0_CKE<0>
NC_DDR0_CKE<1>
H5G_DDR0_ZQ
DDR0_CSN<0>
NC_DDR0_CSN<1>
34 9 8
B14
B13
D13
C12
D12
B11
C11
B10
C9
D9
B8
C8
B7
B6
C6
D7
B17
C17
B16
E17
D16
E16
C15
D15
E6
B5
C5
E5
C4
D4
B3
C3
DDR0_DQ<0>
DDR0_DQ<1>
DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4>
DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<7>
DDR0_DQ<8>
DDR0_DQ<9>
DDR0_DQ<10>
DDR0_DQ<11>
DDR0_DQ<12>
DDR0_DQ<13>
DDR0_DQ<14>
DDR0_DQ<15>
DDR0_DQ<16>
DDR0_DQ<17>
DDR0_DQ<18>
DDR0_DQ<19>
DDR0_DQ<20>
DDR0_DQ<21>
DDR0_DQ<22>
DDR0_DQ<23>
DDR0_DQ<24>
DDR0_DQ<25>
DDR0_DQ<26>
DDR0_DQ<27>
DDR0_DQ<28>
DDR0_DQ<29>
DDR0_DQ<30>
DDR0_DQ<31>
R1096
4.7K
1%
1/32W
MF
2 01005
C1096
0.01UF
10%
2 6.3V
X5R
01005
SYNC_DATE=N/A
AP: DDR
DRAWING NUMBER
VOLTAGE=0.6V
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
10 OF 154
SHEET
8 OF 39
6
34
C1147
4.3UF
20%
4V
X5R-CERM 2
0610
C1148
4.3UF
C1149
C1150
1UF
20%
4V
X5R-CERM 2
0610
C1151 1
1UF
0.47UF
C1152 1
C1153 1
20%
4V
CERM-X5R-1 2
201
20%
6.3V
X5R-CERM 2
01005
0.47UF
20%
20%
6.3V 2
4V
X5R
CERM-X5R-1 2
0201
201
20%
6.3V 2
X5R
0201
C1155
4.3UF
=PPVDD_SOC_H5
U0600
BALI-H5G
BGA
SYM 10 OF 12
OMIT_TABLE
9500MA MAX
VDD
VDD
U10
U12
U14
U16
U22
U24
V9
V11
V13
V15
V17
V25
W8
W10
W12
W14
W16
T19
W26
Y9
Y11
Y13
Y15
Y17
Y26
AA8
AA10
AA12
AA14
AA16
AA18
AA26
AB9
AB11
AB13
AB15
AB17
AC8
AC10
AC12
AC14
AC16
AC18
AD9
AD11
AD13
AD15
AD17
AE16
AE18
AF17
U20
R18
R24
C1161
1UF
34
C1159 1
C1160 1
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
10UF
20%
6.3V 2
X5R
603
10UF
20%
6.3V 2
X5R
603
C1102 1
C1103 1
20%
6.3V 2
X5R
603
20%
6.3V 2
X5R
603
10UF
10UF
1UF
C1165 1
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V
X5R-CERM 2
01005
1UF
V20
V22
V24
Y20
Y22
Y24
1UF
1UF
1UF
C1166 1
0.1UF
1UF
C11C0 1
0.1UF
AA21
AB20
AB22
AC19
AC21
AD20
AE19
AE21
C11C1 1
8.2PF
8.2PF
20%
+/-0.5PF
+/-0.5PF
6.3V
16V
16V
X5R-CERM 2NP0-C0G-CERM 2NP0-C0G-CERM 2
01005
01005
01005
=PPVDD_CPU1_H5
C1167
4.3UF
C1173
C1174
1UF
1UF
20%
6.3V 2
X5R
0201
C1168 1
C1169 1
C1170 1
C1171 1
C1172 1
20%
4V
X5R-CERM 2
0610
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
4.3UF
20%
4V
X5R-CERM 2
0610
34
C1158 1
20%
6.3V 2
X5R
0201
C1164 1
1UF
20%
6.3V 2
X5R
0201
1UF
C1175 1
C1176 1
C1177 1
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V
X5R-CERM 2
01005
1UF
20%
6.3V 2
X5R
0201
1UF
1UF
1UF
C1178 1
0.1UF
1UF
C11D0 1
0.1UF
C11D1 1
8.2PF
8.2PF
20%
+/-0.5PF
+/-0.5PF
6.3V
16V
16V
01005
01005
01005
C1179 1
10UF
20%
6.3V 2
X5R
603
C1180
C1181
4.3UF
34 9
4.3UF
20%
4V
X5R-CERM 2
0610
C1182 1
C1183 1
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
1UF
1UF
20%
4V
X5R-CERM 2
0610
CA186 1
10UF
CA189
0.22UF
CA191
0.22UF
20%
6.3V
2 X5R
0201
VDD_CPUB
1.1A@1.1V
VDD_CPU0
2.5A@1.1V
AA23
AB24
AC23
AC25
AD22
AD24
AE23
AE25
2.5A@1.1V
VDD_CPU1
AA19
AA25
W19
W21
W23
W25
550MA@1.1V
VDD_SRAM
VDDIOD
1000MA@1.2V
FAST SCAN CLK

GPIO_3V0
USB11
SPI3
CA192
20%
2 6.3V
X5R
0201
=PP1V2_VDDIOD_H5
G7
G8
G9
G10
G11
G12
G13
G14
G15
H7
J7
K7
L7
M7
N7
P7
R7
T7
U7
V7
W7
Y7
AA7
AB7
AC7
AD7
AE7
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
C1193 1
C1190 1
C1191 1
20%
6.3V 2
X5R
0201
20%
4V
X5R-CERM 2
0610
20%
4V
X5R-CERM 2
0610
1UF
4.3UF
C1194 1
1UF
20%
6.3V 2
X5R
0201
C1195
VDDIOD2 FMI0-3 (1.8V)

45MA
AC26
AD26
AE26
VDDIOD3 FMI1-3 (1.8V)

45MA
45MA
VDDIO18_GRP2
C1192
10UF
20%
6.3V 2
X5R
603
C1196 1
0.47UF
0.47UF
20%
20%
4V
4V
CERM-X5R-1 2 CERM-X5R-1 2
201
201
C1143 1
C1197 1
C1142 1
0.22UF
0.22UF
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
C1144 1
0.22UF
0.22UF
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
C
=PP1V8_VDDIO18_H5
I2C2
AG26
AH26
AJ26
4.3UF
8 34
12MA
VDDIO18_GRP1 H18
1
H26
J27
K27
L27
C1198
C1199
0.22UF
0.22UF
20%
2 6.3V
X5R
0201
20%
2 6.3V
X5R
0201
4 6 7 9 34
C1145
56PF
5%
2 6.3V
NP0-C0G
01005
18MA
VDDIO18_GRP3 N29
5MA
AE20 VDD_ANA0 TEMP SENSOR
ANALOG
AE24 VDD_ANA1
5MA
W18 VDD_ANA_TMPSADC0
P13 VDD_ANA_TMPSADC1
0.22UF
20%
6.3V
2 X5R
0201
OMIT_TABLE
35MA
VDDIO18_GRP4
U25
U26
V26
10MA
VDDIO18_GRP5 AF25
12MA
VDDIO18_GRP6 AH18
=PP1V8_NAND_H5
1
CA193
10UF
CA194
4.3UF
20%
2 6.3V
CERM-X5R
0402-1
20%
6.3V 2
X5R
603
20%
6.3V 2
X5R
0201
CA190
BGA
SYM 9 OF 12
J20 VDDIOD0
2MA
K20 VDDIOD1
2MA
0.22UF
20%
6.3V 2
X5R
0201
0.22UF
10UF
8.2PF
=PP3V0_VDDIO30_H5
20%
2 6.3V
X5R
0201
C1104
C11E1 1
8.2PF
CA188 1
0.22UF
20%
6.3V 2
X5R
0201
C11E0 1
20%
+/-0.5PF
+/-0.5PF
4V
16V
16V
CERM-X5R-1 2NP0-C0G-CERM 2NP0-C0G-CERM 2
201
01005
01005
CA187 1
0.22UF
20%
6.3V 2
X5R
603
34 6
C1185 1
0.47UF
20%
4V
CERM-X5R-1 2
201
=PP3V0_VDDIO30_H5
CA185 1
34 9
C1184 1
0.47UF
BALI-H5G
52MA
N28 VDDIO30_GRP1
F18 VDDIO30_GRP2
K25 VDDIO30_GRP3
=PPVDD_SRAM_H5
34 9 7 6 4
C1101
U0600
8.2PF
C1157 1
CA195
C1105
1UF
CA196
10UF
10%
2 6.3V
CERM
402
20%
2 4V
X5R-CERM
0610
20%
2 6.3V
CERM-X5R
0402-1
CA197
10UF
20%
2 6.3V
CERM-X5R
0402-1
CA198
1UF
CRITICAL
CA199
0.47UF
10%
2 6.3V
CERM
402
20%
2 4V
X7S
0204
C11F0
8.2PF
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
=PP1V8_VDDIO18_H5
CA150
0.22UF
C11B1 1
8.2PF
20%
+/-0.5PF
+/-0.5PF
6.3V
16V
16V
01005
01005
01005
20%
4V
X5R-CERM 2
0610
C1163 1
=PPVDD_SOC_H5
C1100
C11B0 1
0.1UF
C1156 1
C1162
1
34 9
C1154 1
0.1UF
4.3UF
20%
4V
X5R-CERM 2
0610
J8
J10
J12
J14
J22
K9
K11
K13
K15
K21
L8
L10
L12
L14
L16
L18
L20
L22
M9
M11
M13
M15
M17
M19
M21
M23
N8
N10
N12
N14
N16
N18
N20
N22
P9
P11
P15
P17
P19
P21
P23
R8
R10
R12
R14
R16
R20
R22
T9
T11
T13
T15
T17
T21
T23
U8
=PPVDD_CPU0_H5
34
34 9
=PPVDD_CPUB_H5
CA151
0.22UF
20%
2 6.3V
X5R
0201
CA152
20%
6.3V
2 X5R
0201
CA153
0.22UF
20%
6.3V
2 X5R
0201
0.22UF
20%
6.3V
2 X5R
0201
10UF
20%
6.3V 2
X5R
603
TABLE_ALT_HEAD
C1106
4.3UF
20%
4V
X5R-CERM 2
0610
C1119 1
0.47UF
20%
4V
CERM-X5R-1 2
201
C1107
4.3UF
20%
4V
X5R-CERM 2
0610
C1120
0.47UF
20%
4V
CERM-X5R-1 2
201
C1108
4.3UF
20%
4V
X5R-CERM 2
0610
C1121
0.47UF
20%
4V
CERM-X5R-1 2
201
C1109
C1110 1
C1111 1
20%
4V
X5R-CERM 2
0610
20%
4V
X5R-CERM 2
0610
20%
4V
X5R-CERM 2
0610
4.3UF
C1122 1
0.47UF
20%
4V
CERM-X5R-1 2
201
4.3UF
C1123 1
0.47UF
20%
4V
CERM-X5R-1 2
201
4.3UF
C1113
1UF
10%
2 6.3V
CERM
402
C1124 1
C1125
0.47UF
0.47UF
20%
4V
CERM-X5R-1 2
201
20%
4V
CERM-X5R-1 2
201
C1114
1UF
C1115
1UF
1UF
10%
6.3V
2 CERM
402
10%
2 6.3V
CERM
402
C1116
10%
2 6.3V
CERM
402
C1117
1UF
10%
2 6.3V
CERM
402
C1118
1UF
PART NUMBER
ALTERNATE FOR
PART NUMBER
138S0702
138S0657
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
10%
2 6.3V
CERM
402
QTY 21 RDAR://PROBLEM/8837828
C1106,C1107,C1108,C1109,C1110,C1111,C1147,C1148,C1155,C1156,C1167,C1168,C1180,C1181,C1190,C1191,C1315,C1321,C1415,C1421,CA194
C1126 1
0.47UF
20%
4V
CERM-X5R-1 2
201
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: POWER
DRAWING NUMBER
Apple Inc.
C1128 1
0.22UF
20%
6.3V 2
X5R
0201
C1129 1
0.22UF
20%
6.3V 2
X5R
0201
C1130 1
0.22UF
20%
6.3V 2
X5R
0201
C1131 1
0.22UF
20%
6.3V 2
X5R
0201
C1132 1
0.22UF
20%
6.3V 2
X5R
0201
C1133 1
0.22UF
20%
6.3V 2
X5R
0201
C1134 1
0.22UF
20%
6.3V 2
X5R
0201
C1135
0.22UF
20%
6.3V 2
X5R
0201
C1136
0.1UF
20%
6.3V
X5R-CERM 2
01005
C1137
0.1UF
20%
6.3V
X5R-CERM 2
01005
C1138
0.1UF
20%
6.3V
X5R-CERM 2
01005
C1139
0.1UF
20%
6.3V
X5R-CERM 2
01005
C1140
0.1UF
20%
6.3V
X5R-CERM 2
01005
C1141
0.1UF
20%
6.3V
X5R-CERM 2
01005
C11A0
8.2PF
C11A1
8.2PF
+/-0.5PF
+/-0.5PF
16V
16V
NP0-C0G-CERM 2NP0-C0G-CERM 2
01005
01005

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
11 OF 154
SHEET
9 OF 39
BOOT CONFIG ID
STUFF FOR FORM FACTOR BOARD

34 10 7 5 4
=PP1V8_H5
1
R1201
10K
BOOT_CONFIG[3]
OUT
GPIO_BOOT_CONFIG_3
BOOT_CONFIG[2]
OUT
GPIO_BOOT_CONFIG_2
BOOT_CONFIG[1]
OUT
GPIO_BOOT_CONFIG_1
BOOT_CONFIG[0]
OUT
GPIO_BOOT_CONFIG_0
NOSTUFF
R1200
10K
5%
1/32W
MF
2 01005
5%
1/32W
MF
2 01005
JTAG
NOSTUFF
R1202
R1203
10K
10K
5%
1/32W
MF
2 01005
5%
1/32W
MF
2 01005
R1210
1
100
JTAG_AP_SEL
OUT
5%
1/32W
MF
01005
R1211
1
BOOT_CONFIG[3-0]
CURRENT SETTING ---> 1100
1101
1110
FMI0/1 2/2 CS
FMI0/1 4/4 CS
FMI0/1 4/4 CS WITH TEST
1.
2.
3.
100
JTAG_AP_TRST_L
OUT
4 36 39
5%
1/32W
MF
01005
S/W READ FLOW

SET GPIO AS INPUT
DISABLE PU AND ENABLE PD
READ
FOR REFERENCE
BOOT_CONFIG[3:0]
0000
SPI0
0001
SPI1
0010
SPI0 W/TEST
0011
SPI1 W/TEST
0100
FMI0 2CS
0101
FMI0 4CS
0110
FMI0 4CS W/TEST
0111
RESERVED
1000
FMI1 2 CS
1001
FMI1 4 CS
1010
FMI1 4CS W/TEST
1100
FMI0/1 2/2 CS
1101
FMI0/1 4/4 CS
1110
FMI0/1 4/4 CS W/TEST
1111
RESERVED
C
R1260
100K 2
1
BOARD ID
34 10 7 5 4
=PP1V8_H5
MLB_D&MLB_E
R1220
MLB_C&MLB_E
MLB_B&MLB_D
R1204
10K
R1205
10K
5%
1/32W
MF
2 01005
OUT
10K
5%
1/32W
MF
2 01005
5%
1/32W
MF
2 01005
AP_TST_STPCLK
OUT
AP_FAST_SCAN_CLK
OUT
AP_HOLD_RESET
OUT
NOSTUFF
XW1200
DEV
R1206
SHORT-01005
2
1
10K
5%
1/32W
MF
2 01005
NOSTUFF
XW1201
SHORT-01005
2
1
BOARD_ID[3]
BOARD_ID[2]
OUT
GPIO_BOARD_ID_3
OUT
GPIO_BOARD_ID_2
BOARD_ID[1]
OUT
GPIO_BOARD_ID_1
BOARD_ID[0]
OUT
GPIO_BOARD_ID_0
NOSTUFF
XW1202
SHORT-01005
2
1
S/W READ FLOW
BOARD_ID[3-0]
AP_TESTMODE
5%
1/32W
MF
01005
0000
0001
0010
0011
0100
0101
1010
1011
1110
1111
X140
X140
X140
X140
X140
X140
X140
X140
X140
X140
AP WLAN (MLB A)
DEV WLAN
AP BB_41 (MLB B)
DEV BB_41
AP BB_42 (MLB C)
DEV BB_42
AP BB_26A (MLB D)
DEV BB_26A
AP BB_26 (MLB E)
DEV BB_26
1.
2.
3.
SET GPIO AS INPUT

DISABLE PU AND ENABLE PD
READ
B
25
IN
USB_BRICKID
MAKE_BASE=TRUE
PMU_USB_BRICKID
OUT
30
BOARD REVISION
5
OUT
OUT
OUT
GPIO_BRD_REV2
GPIO_BRD_REV1
GPIO_BRD_REV0
1
NOSTUFF
R1207
10K
5%
1/32W
MF
2 01005
NOSTUFF
R1208
10K
5%
1/32W
MF
2 01005
R1209
10K
5%
1/32W
MF
2 01005
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AP: MISC & ALIASES

DRAWING NUMBER
BRD_REV[2-0]
000
001
010
CURRENT SETTING ---> 011
PROTO
PROTO 2
EVT
DVT
S/W READ FLOW

1.
2.
3.
Apple Inc.
SET GPIO AS INPUT

ENABLE PU AND DISABLE PD
READ

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
12 OF 154
SHEET
10 OF 39
38 8
38 8
38 8
38 8
=PP1V2_S2R_DDR
38 8
38 8
R1305
C1360
10K
38 8
0.01UF
1%
1/32W
MF
2 01005
38 8
10%
6.3V
2 X5R
01005
DDR1_CK_P
DDR1_CK_N
DDR1_CKE<0>
38 8
38 8
PPVREF_DDR0_CA
1
R1306
10K
1%
1/32W
MF
2 01005
C1350
0.01UF
10%
6.3V
2 X5R
01005
38 8
11 38 39
DDR1_CSN<0>
38 8
38 8
38 8
=PP1V2_S2R_DDR
38 8
10K
1%
1/32W
MF
2 01005
38 8
C1361
38 8
0.01UF
10%
2 6.3V
X5R
01005
38 8
38 8
38 8
PPVREF_DDR1_CA
R1352
10K
1%
1/32W
MF
2 01005
C1352
0.01UF
10%
2 6.3V
X5R
01005
38 8
11 38 39
VOLTAGE=0.6V
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
34 12 11
=PP1V2_VDDQ_DDR
38 8
38 8
R1353
4.7K
38 8
C1362
38 8
0.01UF
1%
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
38 8
PPVREF_DDR0_DQ
1
R1354
4.7K
1%
1/32W
MF
2 01005
C1354
0.01UF
10%
6.3V
2 X5R
01005
11 38 39
VOLTAGE=0.6V
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
34 12 11
=PP1V2_VDDQ_DDR
38 8
38 8
R1355
4.7K
C1363
38 8
0.01UF
1%
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
PPVREF_DDR1_DQ
1
R1356
4.7K
1%
1/32W
MF
2 01005
C1356
0.01UF
10%
6.3V
2 X5R
01005
XXXMB
BGA
SYM 1 OF 2
OMIT_TABLE
U12 CK_1
U11 CKB_1
V13 CKE_1
G16
G17
H17
H18
J16
N16
N17
P17
P18
R16
DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4>
DDR0_CA<5>
DDR0_CA<6>
DDR0_CA<7>
DDR0_CA<8>
DDR0_CA<9>
CK_2 K17
CKB_2 L17
CKE_2 J18
DDR0_CK_P
DDR0_CK_N
DDR0_CKE<0>
U13 CSB_1
CSB_2 J17
DDR0_CSN<0>
DDR1_DM<1>
DDR1_DM<0>
DDR1_DM<3>
DDR1_DM<2>
C12
B10
B16
D7
DM0_2 K3
DM1_2 M2
DM2_2 G4
DM3_2 T2
DM0_1
DM1_1
DM2_1
DM3_1
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<13>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<0>
DDR1_DQ<1>
DDR1_DQ<2>
DDR1_DQ<3>
DDR1_DQ<4>
DDR1_DQ<5>
DDR1_DQ<6>
DDR1_DQ<7>
DDR1_DQ<24>
DDR1_DQ<25>
DDR1_DQ<26>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQ<29>
DDR1_DQ<30>
DDR1_DQ<31>
DDR1_DQ<16>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQ<22>
DDR1_DQ<23>
C15
D15
B14
C14
D14
E14
B13
C13
C9
D9
B8
C8
D8
E8
B7
C7
B18
C18
D18
E18
B17
D17
E17
E16
B6
B5
C5
D5
B4
C4
B3
C3
DQ0_1
DQ1_1
DQ2_1
DQ3_1
DQ4_1
DQ5_1
DQ6_1
DQ7_1
DQ8_1
DQ9_1
DQ10_1
DQ11_1
DQ12_1
DQ13_1
DQ14_1
DQ15_1
DQ16_1
DQ17_1
DQ18_1
DQ19_1
DQ20_1
DQ21_1
DQ22_1
DQ23_1
DQ24_1
DQ25_1
DQ26_1
DQ27_1
DQ28_1
DQ29_1
DQ30_1
DQ31_1
DDR1_DQS_P<1>
DDR1_DQS_N<1>
D13 DQS0_1
D12 DQSB0_1
DQS0_2 J4
DQSB0_2 K4
DDR0_DQS_P<1>
DDR0_DQS_N<1>
DDR1_DQS_P<0>
DDR1_DQS_N<0>
D10 DQS1_1
C10 DQSB1_1
DQS1_2 M4
DQSB1_2 M3
DDR0_DQS_P<0>
DDR0_DQS_N<0>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
C16 DQS2_1
D16 DQSB2_1
DQS2_2 F4
DQSB2_2 F3
DDR0_DQS_P<3>
DDR0_DQS_N<3>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
D6 DQS3_1
C6 DQSB3_1
DQS3_2 T3
DQSB3_2 T4
DDR0_DQS_P<2>
DDR0_DQS_N<2>
U10 VREFCA_1
D11 VREFDQ_1
VREFCA_2 M17
VREFDQ_2 L4
DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2
DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2
DDR0_DM<1>
DDR0_DM<0>
DDR0_DM<3>
DDR0_DM<2>
G3
G2
H5
H4
H3
H2
J3
J2
N4
N3
P5
P4
P3
P2
R4
R3
B2
C2
D3
D2
E4
E3
E2
F2
T5
U5
U4
U2
V5
V4
V3
V2
DDR0_DQ<8>
DDR0_DQ<9>
DDR0_DQ<10>
DDR0_DQ<11>
DDR0_DQ<12>
DDR0_DQ<13>
DDR0_DQ<14>
DDR0_DQ<15>
DDR0_DQ<0>
DDR0_DQ<1>
DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4>
DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<7>
DDR0_DQ<24>
DDR0_DQ<25>
DDR0_DQ<26>
DDR0_DQ<27>
DDR0_DQ<28>
DDR0_DQ<29>
DDR0_DQ<30>
DDR0_DQ<31>
DDR0_DQ<16>
DDR0_DQ<17>
DDR0_DQ<18>
DDR0_DQ<19>
DDR0_DQ<20>
DDR0_DQ<21>
DDR0_DQ<22>
DDR0_DQ<23>
8 38
8 38
8 38
8 38
8 38
8 38
34 12
8 38
=PP1V8_S2R_DDR
8 38
C1301
8 38
10UF
C1302
8 38
8 38
C1303
1UF
C1304
1UF
10%
6.3V
CERM 2
402
20%
6.3V
X5R 2
603
C1305
0.01UF
10%
6.3V
CERM 2
402
0.01UF
10%
6.3V
X5R 2
01005
10%
6.3V
X5R 2
01005
8 38
C1306
0.22UF
8 38
C1308 1
C1307 1
C1309
0.22UF
0.22UF
20%
6.3V
X5R 2
0201
56PF
5%
6.3V
NP0-C0G 2
01005
20%
6.3V
X5R 2
0201
20%
6.3V
X5R 2
0201
8 38
PPVREF_DDR1_CA
PPVREF_DDR1_DQ
39 38 11
39 38 11
38
DDR1_ZQ
U7 ZQ_1
ZQ_2 R17
PPVREF_DDR0_CA
PPVREF_DDR0_DQ
8 38
=PP1V2_S2R_DDR
34 12 11
8 38
C1310
C1311
0.22UF
8 38
8 38
C1312
0.22UF
20%
6.3V
X5R 2
0201
8 38
0.22UF
20%
6.3V
X5R 2
0201
20%
6.3V
X5R 2
0201
C1313 1
0.22UF
20%
6.3V
X5R 2
0201
8 38
8 38
8 38
8 38
8 38
C1314
10UF
8 38
20%
6.3V
X5R 2
603
8 38
8 38
C1315
C1316
4.3UF
C1317 1
1UF
20%
4V
X5R-CERM 2
0610
1UF
10%
6.3V
CERM 2
402
10%
6.3V
CERM 2
402
C1318
0.01UF
C1319
56PF
5%
6.3V
NP0-C0G 2
01005
10%
10V
X5R-CERM 2
0201
8 38
8 38
8 38
8 38
34 12 11
=PP1V2_VDDQ_DDR
8 38
8 38
8 38
8 38
8 38
C1323
C1320
56PF
C1321
10UF
5%
6.3V
NP0-C0G 2
01005
C1324 1
4.3UF
20%
6.3V 2
X5R
603
C1325
0.22UF
20%
4V
X5R-CERM 2
0610
0.22UF
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
C1326
0.22UF
20%
6.3V 2
X5R
0201
C1322
0.01UF
10%
6.3V 2
X5R
01005
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
34 12 11
=PP1V2_S2R_DDR
C1327
8 38
10UF
8 38
20%
6.3V
X5R 2
603
8 38
C1328
1UF
10%
6.3V
CERM 2
402
C1329
1UF
10%
6.3V
CERM 2
402
C1330
0.01UF
10%
6.3V
X5R 2
01005
C1331
0.01UF
10%
6.3V
X5R 2
01005
8 38
11 38 39
C1332
11 38 39
20%
6.3V
X5R 2
0201
DDR0_ZQ
VDD1_0
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
E11
E19
L5
M18
U17
T18
V10
V16
V18
W5
W16
W19
W18
V19
A3
T19
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
H1
M1
W3
E1
U1
B12
D4
U3
A14
C17
C19
A10
A17
J5
K2
A8
N2
R5
A13
E10
E15
P1
VDDQ27
VDDQ32
VDDQ31
VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33
F18
H16
K16
L16
P16
T11
T12
T14
V7
T8
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10
U1300
H4G-DRAM
XXXMB
BGA
SYM 2 OF 2
OMIT_TABLE
VSS0
VSS55
VSS2
VSS3
VSS4
VSS49
VSS6
VSS7
A16
A19
A4
A6
B15
C1
B9
C11
VSS9
VSS10
VSS1
VSS12
VSS13
VSS51
D1
D19
A1
VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5
VSS47
VSS32
VSS33
VSS34
VSS35
VSS36
A18
R18
R2
T1
T17
U16
VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
W2
U6
V11
V12
V15
T6
V9
W1
W4
E12
E13
G5
8 38
0.22UF
38
A2
B1
B11
F17
L2
M16
T10
U18
V17
V6
W17
U19
8 38
11 38 39
VOLTAGE=0.6V
8 38
38 8
R1351
H4G-DRAM
CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2
VOLTAGE=0.6V
38 8
34 12 11
U1300
DDR_2
CA0_1
CA1_1
CA2_1
CA3_1
CA4_1
CA5_1
CA6_1
CA7_1
CA8_1
CA9_1
DDR_1
34 12 11
T15
U15
U14
V14
T13
T9
U9
U8
V8
T7
VSS
38 8
VDD1
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<2>
DDR1_CA<3>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>
38 8
VDD2
VDDQ
C1333 1
0.22UF
20%
6.3V
X5R 2
0201
C1334 1
0.22UF
20%
6.3V
X5R 2
0201
C1335
VDDCA
56PF
5%
6.3V
NP0-C0G 2
01005
R1320
R1321
240
240
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
DDR 0 AND 1
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
13 OF 154
SHEET
11 OF 39
38 8
DDR3_CK_P
DDR3_CK_N
DDR3_CKE<0>
U12 CK_1
U11 CKB_1
V13 CKE_1
CK_2 K17
CKB_2 L17
CKE_2 J18
DDR2_CK_P
DDR2_CK_N
DDR2_CKE<0>
38 8
DDR3_CSN<0>
U13 CSB_1
CSB_2 J17
DDR2_CSN<0>
38 8
=PP1V2_S2R_DDR
38 8
38 8
R1405
10K
38 8
0.01UF
1%
1/32W
MF
2 01005
C1460
38 8
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
PPVREF_DDR2_CA
1
R1406
10K
1%
1/32W
MF
2 01005
C1450
0.01UF
10%
6.3V
2 X5R
01005
12 38 39
38 8
VOLTAGE=0.6V
38 8
CA0_1
CA1_1
CA2_1
CA3_1
CA4_1
CA5_1
CA6_1
CA7_1
CA8_1
CA9_1
U1400
H4G-DRAM
XXXMB
BGA
SYM 1 OF 2
OMIT_TABLE
CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2
G16
G17
H17
H18
J16
N16
N17
P17
P18
R16
DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>
8 38
34 11
=PP1V8_S2R_DDR
8 38
C1401
8 38
C1402
10UF
8 38
8 38
C1403
1UF
20%
6.3V
X5R 2
603
8 38
1UF
38 8
38 8
R1451
10K
C1461
38 8
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
PPVREF_DDR3_CA
1
R1452
10K
1%
1/32W
MF
2 01005
C1452
0.01UF
10%
6.3V
2 X5R
01005
38 8
12 38 39
38 8
VOLTAGE=0.6V
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
34 12 11
38 8
=PP1V2_VDDQ_DDR
38 8
R1453
4.7K
38 8
C1462
38 8
0.01UF
1%
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
38 8
PPVREF_DDR2_DQ
1
R1454
4.7K
1%
1/32W
MF
2 01005
C1454
0.01UF
10%
6.3V
2 X5R
01005
38 8
12 38 39
VOLTAGE=0.6V
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
38 8
34 12
38 8
11 =PP1V2_VDDQ_DDR
38 8
R1455
4.7K
C1463
38 8
0.01UF
1%
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
38 8
38 8
38 8
PPVREF_DDR3_DQ
1
R1456
4.7K
1%
1/32W
MF
2 01005
DDR3_DQ<8>
DDR3_DQ<9>
DDR3_DQ<10>
DDR3_DQ<11>
DDR3_DQ<12>
DDR3_DQ<13>
DDR3_DQ<14>
DDR3_DQ<15>
DDR3_DQ<0>
DDR3_DQ<1>
DDR3_DQ<2>
DDR3_DQ<3>
DDR3_DQ<4>
DDR3_DQ<5>
DDR3_DQ<6>
DDR3_DQ<7>
DDR3_DQ<24>
DDR3_DQ<25>
DDR3_DQ<26>
DDR3_DQ<27>
DDR3_DQ<28>
DDR3_DQ<29>
DDR3_DQ<30>
DDR3_DQ<31>
DDR3_DQ<16>
DDR3_DQ<17>
DDR3_DQ<18>
DDR3_DQ<19>
DDR3_DQ<20>
DDR3_DQ<21>
DDR3_DQ<22>
DDR3_DQ<23>
C15
D15
B14
C14
D14
E14
B13
C13
C9
D9
B8
C8
D8
E8
B7
C7
B18
C18
D18
E18
B17
D17
E17
E16
B6
B5
C5
D5
B4
C4
B3
C3
DQ0_1
DQ1_1
DQ2_1
DQ3_1
DQ4_1
DQ5_1
DQ6_1
DQ7_1
DQ8_1
DQ9_1
DQ10_1
DQ11_1
DQ12_1
DQ13_1
DQ14_1
DQ15_1
DQ16_1
DQ17_1
DQ18_1
DQ19_1
DQ20_1
DQ21_1
DQ22_1
DQ23_1
DQ24_1
DQ25_1
DQ26_1
DQ27_1
DQ28_1
DQ29_1
DQ30_1
DQ31_1
DDR3_DQS_P<1>
DDR3_DQS_N<1>
D13 DQS0_1
D12 DQSB0_1
DQS0_2 J4
DQSB0_2 K4
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR3_DQS_P<0>
DDR3_DQS_N<0>
D10 DQS1_1
C10 DQSB1_1
DQS1_2 M4
DQSB1_2 M3
DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR3_DQS_P<3>
DDR3_DQS_N<3>
C16 DQS2_1
D16 DQSB2_1
DQS2_2 F4
DQSB2_2 F3
DDR2_DQS_P<3>
DDR2_DQS_N<3>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
D6 DQS3_1
C6 DQSB3_1
DQS3_2 T3
DQSB3_2 T4
DDR2_DQS_P<2>
DDR2_DQS_N<2>
U10 VREFCA_1
D11 VREFDQ_1
VREFCA_2 M17
VREFDQ_2 L4
0.01UF
1%
1/32W
MF
2 01005
C1456
0.01UF
10%
6.3V
2 X5R
01005
DDR_2
=PP1V2_S2R_DDR
DDR_1
34 12 11
DM0_1
DM1_1
DM2_1
DM3_1
DM0_2
DM1_2
DM2_2
DM3_2
K3
M2
G4
T2
DDR2_DM<1>
DDR2_DM<0>
DDR2_DM<3>
DDR2_DM<2>
DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2
DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2
G3
G2
H5
H4
H3
H2
J3
J2
N4
N3
P5
P4
P3
P2
R4
R3
B2
C2
D3
D2
E4
E3
E2
F2
T5
U5
U4
U2
V5
V4
V3
V2
DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>
38 8
38 8
PPVREF_DDR3_CA
PPVREF_DDR3_DQ
39 38 12
39 38 12
38
DDR3_ZQ
U7 ZQ_1
ZQ_2 R17
PPVREF_DDR2_CA
PPVREF_DDR2_DQ
38
0.01UF
10%
6.3V
X5R 2
01005
10%
6.3V
X5R 2
01005
8 38
8 38
C1406
0.22UF
8 38
C1408 1
C1407 1
56PF
20%
6.3V 2
X5R
0201
20%
6.3V
X5R 2
0201
8 38
C1409
0.22UF
0.22UF
20%
6.3V 2
X5R
0201
8 38
5%
6.3V
NP0-C0G 2
01005
=PP1V2_S2R_DDR
8 38
C1411
8 38
C1412
0.22UF
20%
6.3V
X5R 2
0201
8 38
C1413 1
0.22UF
0.22UF
20%
6.3V
X5R 2
0201
20%
6.3V 2
X5R
0201
20%
6.3V
X5R 2
0201
8 38
8 38
C1414
10UF
8 38
20%
6.3V
X5R 2
603
8 38
8 38
C1415
4.3UF
C1416
1UF
20%
4V
X5R-CERM 2
0610
C1418
C1417 1
C1419
0.01UF
1UF
10%
6.3V
CERM 2
402
56PF
10%
10V
X5R-CERM 2
0201
10%
6.3V
CERM 2
402
5%
6.3V
NP0-C0G 2
01005
8 38
A2
B1
B11
F17
L2
M16
T10
U18
V17
V6
W17
U19
VDD1_0
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
E11
E19
L5
M18
U17
T18
V10
V16
V18
W5
W16
W19
W18
V19
A3
T19
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
H1
M1
W3
E1
U1
B12
D4
U3
A14
C17
C19
A10
A17
J5
K2
A8
N2
R5
A13
E10
E15
P1
VDDQ27
VDDQ32
VDDQ31
VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33
F18
H16
K16
L16
P16
T11
T12
T14
V7
T8
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10
8 38
8 38
8 38
8 38
34 12 11
=PP1V2_VDDQ_DDR
8 38
8 38
8 38
8 38
8 38
C1423 1
56PF
5%
6.3V
NP0-C0G 2
01005
C1420
C1421
10UF
C1424 1
4.3UF
0.22UF
20%
6.3V
X5R 2
0201
20%
4V
X5R-CERM 2
0610
20%
6.3V
X5R 2
603
C1425
0.22UF
20%
6.3V
X5R 2
0201
C1426
0.22UF
20%
6.3V
X5R 2
0201
C1422
0.01UF
10%
6.3V
X5R 2
01005
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
8 38
34 12 11
=PP1V2_S2R_DDR
8 38
C1427
8 38
10UF
8 38
20%
6.3V 2
X5R
603
8 38
C1428
1UF
10%
6.3V 2
CERM
402
C1429
C1430
1UF
0.01UF
10%
6.3V 2
CERM
402
10%
6.3V 2
X5R
01005
C1431
0.01UF
10%
6.3V 2
X5R
01005
8 38
8 38
8 38
C1432
0.22UF
20%
6.3V 2
X5R
0201
8 38
8 38
12 38 39
VOLTAGE=0.6V
8 38
0.22UF
C12
B10
B16
D7
C1405
0.01UF
10%
6.3V
CERM 2
402
10%
6.3V
CERM 2
402
C1410
DDR3_DM<1>
DDR3_DM<0>
DDR3_DM<3>
DDR3_DM<2>
C1404
8 38
34 12 11
38 8
C1434 1
C1433 1
0.22UF
0.22UF
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
C1435
U1400
H4G-DRAM
XXXMB
BGA
SYM 2 OF 2
OMIT_TABLE
VSS
T15
U15
U14
V14
T13
T9
U9
U8
V8
T7
38 8
VDD1
DDR3_CA<0>
DDR3_CA<1>
DDR3_CA<2>
DDR3_CA<3>
DDR3_CA<4>
DDR3_CA<5>
DDR3_CA<6>
DDR3_CA<7>
DDR3_CA<8>
DDR3_CA<9>
38 8
34 12 11
VDD2
VDDQ
VSS0
VSS55
VSS2
VSS3
VSS4
VSS49
VSS6
VSS7
A16
A19
A4
A6
B15
C1
B9
C11
VSS9
VSS10
VSS1
VSS12
VSS13
VSS51
D1
D19
A1
VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5
VSS47
VSS32
VSS33
VSS34
VSS35
VSS36
A18
R18
R2
T1
T17
U16
VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
W2
U6
V11
V12
V15
T6
V9
W1
W4
E12
E13
G5
VDDCA
56PF
5%
6.3V
NP0-C0G 2
01005
8 38
8 38
12 38 39
12 38 39
DDR2_ZQ
1
R1421
R1420
240
240
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
DDR 2 AND 3
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
14 OF 154
SHEET
12 OF 39
7
34
3
=PP1V8_NAND
=PP3V3_NAND
C1600
10UF
C1601
10UF
C1602
10UF
C1610
10UF
C1611
10UF
C1612
10UF
C1613
10UF
C1614
10UF
10UF
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
0.22UF
20%
6.3V
2 X5R
0201
C1607
27PF
5%
2 25V
NP0-C0G
0201
C1605
0.22UF
20%
2 6.3V
X5R
0201
C1608
27PF
5%
25V
2 NP0-C0G
0201
C1606
0.22UF
C1620
0.22UF
20%
2 6.3V
X5R
0201
20%
2 6.3V
X5R
0201
C1609
27PF
C1630
27PF
5%
2 25V
NP0-C0G
0201
5%
25V
2 NP0-C0G
0201
C1621
0.22UF
20%
2 6.3V
X5R
0201
C1631
27PF
5%
2 25V
NP0-C0G
0201
C1622
0.22UF
20%
6.3V
2 X5R
0201
C1632
27PF
5%
2 25V
NP0-C0G
0201
C1623
0.22UF
20%
2 6.3V
X5R
0201
C1633
27PF
5%
25V
2 NP0-C0G
0201
C1624
0.22UF
20%
2 6.3V
X5R
0201
C1634
27PF
5%
2 25V
NP0-C0G
0201
13 34
C1615
20%
2 6.3V
CERM-X5R
0402-1
C1604
C1625
0.22UF
20%
6.3V
2 X5R
0201
C1635
27PF
5%
2 25V
NP0-C0G
0201
PPVDDI_NAND_U1600
27PF
C1651
1UF
20%
2 6.3V
X5R
0201
C1650
1UF
20%
6.3V
2 X5R
0201
VOLTAGE=1.2V
MAX_NECK_LENGTH=3MM
B6
F2
M6
OB8
5%
25V
2 NP0-C0G
0201
VDDI
38 13 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 13 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
38 6
BI
FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
G3
H2
J3
K2
L5
K6
J5
H6
IO0-0
IO1-0
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
IO7-0
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
G1
J1
L1
N3
N5
L7
J7
G7
IO0-1
IO1-1
IO2-1
IO3-1
IO4-1
IO5-1
IO6-1
IO7-1
N1
N7
OC8
OD8
OE0
OF8
G0
OA8
C1652
VCC
VCCQ
OMIT_TABLE
U1600
LGA-12X17
XXNM-XGBX8-MLC-PPN1.5-ODP
=PP1V8_NAND
CE0*
CLE0
ALE0
WE0*
A5
A3
C1
E3
RE0 B4
RE0* C7
DQS0 H4
DQS0* F4
FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L
DQS1 M4
DQS1* K4
IN
6 13 38
IN
6 13 38
IN
6 13 38
FMI0_RE_L
IN
6 13 38
FMI0_DQS
IN
6 13 38
13 34
R1655
5%
1/32W
MF
2 01005
NC
NAND_SLOT0_RDYBSY_L
C5
C3
D2
E1
RE1 D4
RE1* D6
6 38
100K
NC
R/B0* E5
CE1*
CLE1
ALE1
WE1*
IN
FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_WE_L
NC
IN
6 38
IN
6 13 38
IN
6 13 38
IN
6 13 38
FMI1_RE_L
IN
6 13 38
FMI1_DQS
IN
6 13 38
=PP1V8_NAND
R1690
OA0 TCKC
OB0 TMSC
C1690
0.1UF
1%
1/32W
MF
2 01005
DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
20%
2 4V
X5R
01005
1
1
1
1
38 13 6
FMI0_WE_L
1 TPTP1605
38 13 6
FMI0_DQS
1 TPTP1613
FMI1_AD<0>
FMI1_ALE
FMI1_CLE
FMI1_RE_L
1
1
1
1
38 13 6
FMI1_WE_L
1 TPTP1611
38 13 6
FMI1_DQS
1 TPTP1615
38 13 6
38 13 6
FMI_ZQ_U1600
38 13 6
VSSQ
R1654
243
R1691
1%
1/20W
MF
2 201
51.1K
1%
1/32W
MF
2 01005
C1691
0.1UF
20%
2 4V
X5R
01005
38 13 6
38 13 6
38 13 6
38 13 6
TP1600
TP1601
TPTP1602
TPTP1603
FMI0_AD<0>
FMI0_ALE
FMI0_CLE
FMI0_RE_L
38 13 6
FMI_DQVREF_NAND
ZQ A1
VSS
B2
F6
L3
TP_FMI_TMSC_U1600
51.1K
NC
A7
M2
OC0
OD0
OE8
OF0
G8
TP_FMI_TCKC_U1600
TEST POINTS
1
R/B1* E7
VREF G5
13 34
TP
TP
TP1606
TP1607
TPTP1608
TPTP1609
TP
TP
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
NAND
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
16 OF 154
SHEET
13 OF 39
WIFI ALIASES
36 4
36 4
36 5
36 5
30
30
30
30
5
36 5
36 5
36 5
36 5
36 30
36 5
36 5
36 5
36 5
36 5
36 5
5
34
HSIC1_WLAN_DATA
HSIC1_WLAN_STB
PMU_GPIO_WLAN_REG_ON
PMU_GPIO_WLAN_HOST_WAKE
PMU_GPIO_BT_REG_ON
PMU_GPIO_BT_HOST_WAKE
GPIO_BT_WAKE
UART3_BT_RXD
UART3_BT_TXD
UART3_BT_CTS_L
UART3_BT_RTS_L
PMU_GPIO_CLK_32K_WLAN
I2S2_BT_BCLK
I2S2_BT_DOUT
I2S2_BT_DIN
I2S2_BT_LRCK
UART4_WLAN_RXD
UART4_WLAN_TXD
GPIO_WL_HSIC_RESUME
VDDIO_WLAN_BT_1V8
MAKE_BASE=TRUE
50_HSIC_WLAN_DATA
50_HSIC_WLAN_STROBE
AP_HSIC3_RDY
DEV_HSIC3_RDY
WLAN_REG_ON
HOST_WAKE_WLAN
BT_REG_ON
HOST_WAKE_BT
BT_WAKE
BT_UART_TXD
BT_UART_RXD
BT_UART_RTS_L
BT_UART_CTS_L
CLK32K_AP
BT_PCM_CLK
BT_PCM_IN
BT_PCM_OUT
BT_PCM_SYNC
WLAN_UART_TXD
WLAN_UART_RXD
WLAN_HSIC3_RESUME
MAKE_BASE=TRUE
PP_WL_BT_VDDIO_AP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
ALIASES
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
21 OF 154
SHEET
14 OF 39
6
34
39 34 30 29 25
=PP3V3_LCD
PPVCC_MAIN
1
C2240
0.1UF
10%
2 6.3V
X5R
201
C2239
PM_LCDVDD_PWREN
IN
R2205
100K
5%
1/20W
MF
2 201
C2241
3900PF
10%
50V
2 X7R
0402
ON
TDFN
CRITICAL
PART NUMBER
ALTERNATE FOR
PART NUMBER
155S0667
155S0583
155S0625
155S0559
1.00M
CONN_EDP_DATA_EMI_N<0>
REF DES
COMMENTS:
L2242,L5500,L5510,L5520,L5530,L5540,L5930,L5931
TABLE_ALT_ITEM
RDAR://PROBLEM/8616060,
RADAR://PROBLEM/9015335
L2202,L2212,L2222,L2232
CRITICAL
L2201
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
39 15
FERR-120-OHM-1.5A
PP3V3_S0_LCD_FERR
GND
8
C2203
0.1UF
10%
2 6.3V
X5R
201
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
1
1
C2202
1UF
10%
2 6.3V
CERM
402
2
0402A
NOSTUFF
R2290
47K
C2230
C2232
8.2PF
82PF
5%
1/20W
MF
2 201
5%
2 25V
NP0-C0G-CERM
0201
C2206
1000PF
+/-0.1PF%
2 25V
CER
0201
10%
2 16V
X7R-CERM
0201
R2280
1
BOM OPTION
TABLE_ALT_ITEM
10%
6.3V
2 X5R
201
U2200
LCD_RAMP 7 CAP
TABLE_ALT_HEAD
0.1UF
VDD
EDP CONNECTOR
SLG5AP302
39 15
15 37
VOLTAGE=3.3V
PP3V3_S0_LCD_FERR
39
PP3V3_LCDVDD_SW_F
01005
C2280
1.2PF
1
+/-0.1PF
16V
NP0-C0G
01005
37 7
R2281
1.00M
CONN_EDP_DATA_EMI_P<0>
15 37
37 7
IN
IN
EDP_AUX_N
EDP_AUX_P
01005
201 6.3V
20.1UF
37 EDP_AUX_EMI_N
10% X5R
C22511
0.1UF
2
37 EDP_AUX_EMI_P
201 6.3V
10% X5R
C22501
CONN_EDP_AUX_EMI_P
R2282
37 7
15 37
IN
EDP_DATA_N<0>
01005
C2282
37 7
1.2PF
IN
EDP_DATA_P<0>
C22421
201 6.3V
20.1UF
10% X5R
C22431
0.1UF
2
201 6.3V
10% X5R
37
37
EDP_DATA_EMI_N<0>
EDP_DATA_EMI_P<0>
NC
2 CRITICAL 3
1
37 7
IN
R2283
37 7
15 37
IN
EDP_DATA_N<1>
EDP_DATA_P<1>
01005
201 6.3V
20.1UF
10% X5R
C22451
0.1UF
2
201 6.3V
10% X5R
C22441
37
37
EDP_DATA_EMI_N<1>
EDP_DATA_EMI_P<1>
15 37
NC
NC
NC
15 37
39 15
15 37
L2222
NOSTUFF
+/-0.1PF
16V
NP0-C0G
01005
37 7
IN
37 7
IN
EDP_DATA_N<2>
EDP_DATA_P<2>
R2284
1.00M2
1
4
SYM_VER-2
TCM0806-4SM
12-OHM-100MA-8.5GHZ
1.2PF
NC
2 CRITICAL 3
C2283
CONN_EDP_AUX_EMI_P
37 15
15 37
L2212
+/-0.1PF
16V
NP0-C0G
01005
201 6.3V
20.1UF
10% X5R
C22471
0.1UF
2
201 6.3V
10% X5R
C22461
37
EDP_DATA_EMI_N<2>
2 CRITICAL 3
15 37
37
EDP_DATA_EMI_P<2>
15 37
37 30
IN
37 30
IN
37 30
IN
37 30
IN
37 30
IN
37 30
IN
SYM_VER-2
TCM0806-4SM
12-OHM-100MA-8.5GHZ
J2200_43_GND
NC
L2232
15 37
J2200_29_GND
LED_IO_5_B
LED_IO_3_B
LED_IO_1_B
LED_IO_6_A
LED_IO_4_A
LED_IO_2_A
39 15
EDP_HPD
J2200
502250-8051-B
54
52
NOSTUFF
CRITICAL
15 37
SYM_VER-2
TCM0806-4SM
12-OHM-100MA-8.5GHZ
1.00M2
1
518S0827
15 37
1%
1/32W
MF
2 01005
+/-0.1PF
16V
NP0-C0G
01005
CONN_EDP_AUX_EMI_N
SYM_VER-2
NOSTUFF
L2242
90-OHM-50MA
2 TCM0605-1 3
100K
1.00M
CRITICAL
R2241
1.2PF
1%
1/32W
MF
01005
C2281
1
R2240
100K
NOSTUFF
OUT
7 37
R2242
F-RT-SM
100K
1%
1/32W
MF
2 01005
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
CONN_EDP_AUX_EMI_N
LED_IO_6_B
LED_IO_4_B
LED_IO_2_B
J2200_36_GND
LED_IO_5_A
LED_IO_3_A
LED_IO_1_A
IN
30 37
IN
30 37
IN
30 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 37
15 39
IN
30 37
IN
30 37
IN
30 37
NC
NC
01005
C2284
1.2PF
1
37 7
IN
37 7
IN
EDP_DATA_N<3>
NOSTUFF
+/-0.1PF
16V
NP0-C0G
01005
EDP_DATA_P<3>
C22481
201 6.3V
20.1UF
10% X5R
37
EDP_DATA_EMI_N<3>
C22491
201 6.3V
0.1UF
2
10% X5R
37
EDP_DATA_EMI_P<3>
1.00M2
1
4
SYM_VER-2
TCM0806-4SM
12-OHM-100MA-8.5GHZ
53
55
15 37
15 37
L2202
R2285
1
2 CRITICAL 3
15 37
01005
C2285
1.2PF
1
CRITICAL
NOSTUFF
1.00M2
1.2PF
NOSTUFF
+/-0.1PF
16V
NP0-C0G
01005
34
1
VOLTAGE=20.4V
0402
=PPLED_REG_B
39
PPLED_BACK_REG_B
C2253
100PF
5%
2 50V
CERM
0402
J2200_36_GND
C2270
820PF
10%
50V
2 CERM
0402
C2271
8.2PF
+/-0.25PF
2 50V
CERM
402-1
15 39
SYNC_MASTER=N/A
L2200
FERR-240-OHM-25%-300MA
J2200_43_GND
15 39
5%
1/20W
MF
201
15 37
C2287
34
=PPLED_REG_A
VOLTAGE=20.4V
0402
1.2PF
2
NOSTUFF
39
VIDEO: EDP CONNECTOR

DRAWING NUMBER
C2233
100PF
5%
2 50V
CERM
0402
C2220
820PF
10%
50V
2 CERM
0402
C2221
Apple Inc.
8.2PF
+/-0.25PF
2 50V
CERM
402-1

SYNC_DATE=N/A
PAGE TITLE
PPLED_BACK_REG_A
+/-0.1PF
16V
NP0-C0G
01005
CRITICAL
01005
R2297
R2287
1.00M2
15 39
5%
1/20W
MF
201
J2200_29_GND
R2296
C2286
15 37
01005
FERR-240-OHM-25%-300MA
5%
1/20W
MF
201
R2286
1
L2210
R2295
+/-0.1PF
16V
NP0-C0G
01005
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
22 OF 154
SHEET
15 OF 39
6
PP18V_GRAPE
=PP3V0_GRAPE_MARIO1
C3005
0.1UF
QTY
DESCRIPTION
CRITICAL
BOM OPTION
C3007
0.1UF
10%
25V
X5R
402
TABLE_5_HEAD
PART#
0.1UF
10%
25V
X5R
402
C3053
10%
25V
X5R
402
1
=PP3V0_GRAPE
34
C3006
0.1UF
R3025
10K
5%
1/20W
MF
2 201
TABLE_5_ITEM
CRITICAL
VDDH
CONNECTORS TO GRAPE FLEX
U3003
16
AG_SHLD_TST_FLEX
17
AG_SHLD_TST
17
17
5%
1/20W
MF
201
17
17
17
NOSTUFF
17
R3071
C3070
17
0.1UF
5%
1/20W
MF
2 201
17
10%
25V
2 X5R
402
17
17
17
17
17
17
P/N 518S0828
17
17
MATES WITH LEFTMOST GRAPE FLEX TAIL
17
17
CRITICAL
B1
C1
E1
F2
H1
J1
J2
J3
MUX_IN<0>
MUX_IN<1>
MUX_IN<2>
MUX_IN<3>
MUX_IN<4>
MUX_IN<5>
MUX_IN<6>
MUX_IN<7>
MUX_IN<8>
MUX_IN<9>
MUX_IN<10>
MUX_IN<11>
MUX_IN<12>
MUX_IN<13>
MUX_IN<14>
MUX_IN<15>
MUX_IN<16>
MUX_IN<17>
MUX_IN<18>
MUX_IN<19>
17
R3070
17
K4
H5
I5
J8
J9
K8
J10
I10
H10
F11
C11
E10
A11
NC
B4
NC
A5
NC
A2
J3010
502250-8037-B
41
39
F-RT-SM
NC
16
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
MT_PANEL_OUT<36>
MT_PANEL_OUT<38>
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
MT_PANEL_IN<29>
MT_PANEL_IN<27>
MT_PANEL_IN<25>
MT_PANEL_IN<23>
MT_PANEL_IN<21>
MT_PANEL_IN<19>
MT_PANEL_IN<17>
MT_PANEL_IN<15>
MT_PANEL_IN<13>
MT_PANEL_IN<11>
MT_PANEL_IN<9>
MT_PANEL_IN<7>
MT_PANEL_IN<5>
MT_PANEL_IN<3>
MT_PANEL_IN<1>
AG_SHLD_TST_FLEX
17
MT_PANEL_OUT<37>
MT_PANEL_OUT<39>
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
17
16
16
17
17
MT_PANEL_IN<28>
MT_PANEL_IN<26>
MT_PANEL_IN<24>
MT_PANEL_IN<22>
MT_PANEL_IN<20>
MT_PANEL_IN<18>
MT_PANEL_IN<16>
MT_PANEL_IN<14>
MT_PANEL_IN<12>
MT_PANEL_IN<10>
MT_PANEL_IN<8>
MT_PANEL_IN<6>
MT_PANEL_IN<4>
MT_PANEL_IN<2>
MT_PANEL_IN<0>
17
C7
A7
B7
B8
A8
C8
Z1_BON_L<0>
Z1_BON_L<1>
Z1_BON_L<2>
Z1_BON_L<3>
Z1_BON_L<4>
Z1_BON_L<5>
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
38
40
VSTM0
VSTM1
VSTM2
VSTM3
VSTM4
VSTM5
VSTM6
VSTM7
VSTM8
VSTM9
VSTM10
VSTM11
VSTM12
VSTM13
VSTM14
VSTM15
VSTM16
VSTM17
VSTM18
VSTM19
VSTM20
VSTM21
VSTM22
VSTM23
VSTM24
VSTM25
VSTM26
VSTM27
VSTM28
VSTM29
VSTM30
VSTM31
VSTM32
VSTM33
VSTM34
VSTM35
VSTM36
VSTM37
VSTM38
VSTM39
VSTM40
VSTM41
VSTM42
VSTM43
VSTM44
VSTM46
VSTM45
VSTM47
CRITICAL
OMIT
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
A1
B2
C2
D1
D2
E2
F1
G1
G2
I1
H2
I2
K1
K2
I3
K3
J4
I4
K6
H6
K5
J5
I7
K9
I8
K10
I6
J7
K11
I9
J11
I11
H11
G11
G10
F10
C10
D10
E11
D11
B11
NC
B10
NC
C4
NC
A4
36 16 5
MT_PANEL_OUT<0>
MT_PANEL_OUT<1>
MT_PANEL_OUT<2>
MT_PANEL_OUT<3>
MT_PANEL_OUT<4>
MT_PANEL_OUT<5>
MT_PANEL_OUT<6>
MT_PANEL_OUT<7>
MT_PANEL_OUT<8>
MT_PANEL_OUT<9>
MT_PANEL_OUT<10>
MT_PANEL_OUT<11>
MT_PANEL_OUT<12>
MT_PANEL_OUT<13>
MT_PANEL_OUT<14>
MT_PANEL_OUT<15>
MT_PANEL_OUT<16>
MT_PANEL_OUT<17>
MT_PANEL_OUT<18>
MT_PANEL_OUT<19>
MT_PANEL_OUT<20>
MT_PANEL_OUT<21>
MT_PANEL_OUT<22>
MT_PANEL_OUT<23>
MT_PANEL_OUT<24>
MT_PANEL_OUT<25>
MT_PANEL_OUT<26>
MT_PANEL_OUT<27>
MT_PANEL_OUT<28>
MT_PANEL_OUT<29>
MT_PANEL_OUT<30>
MT_PANEL_OUT<31>
MT_PANEL_OUT<32>
MT_PANEL_OUT<33>
MT_PANEL_OUT<34>
MT_PANEL_OUT<35>
MT_PANEL_OUT<36>
MT_PANEL_OUT<37>
MT_PANEL_OUT<38>
MT_PANEL_OUT<39>
16
36 16 5
SPI3_GRAPE_SCLK
SPI3_GRAPE_CS_L
MAKE_BASE=TRUE
SPI3_GRAPE_MOSI
GPIO_GRAPE_RST_L
MAKE_BASE=TRUE
A_AD_R0 A10
A_AD_R1 B9
A_AD_R2 A9
TO Z2
17
16
16
36 16 5
16
5
GRAPE_MOSI
RST_GRAPE_Z1_L
RST_GRAPE_Z2_L
MAKE_BASE=TRUE
16
17
17
17
16
16
16
16
16
36 16 5
16
SPI3_GRAPE_MISO
GRAPE_MISO
MAKE_BASE=TRUE
17
16
16
16
34 17 16
=PP3V0_GRAPE
=PP3V0_GRAPE
16 17 34
16
R3030
16
R3031
10K
16
10K
5%
1/20W
MF
2 201
16
16
C3030
0.1UF
10%
6.3V
2 X5R
201
5%
1/20W
MF
2 201
C3031 1R3032 1R3033

0.1UF
10%
2 6.3V
X5R
201
3.3K
10K
5%
1/20W
MF
2 201
VCCA VCCB
16
5%
1/20W
MF
2 201
U3007
16
36 16 5
IN
36 16 5
IN
16
16
PQFP1
SPI3_GRAPE_SCLK
SPI3_GRAPE_CS_L
16
6 1A1 CRITICAL
8 2A1
4 1DIR
1 1OE*
16
16
SPI3_GRAPE_MOSI
16
36 16 5
16
IN
7 1A2
9 2A2
16
5 2DIR
16 2OE*
DIR_U3007
16
16
GPIO_GRAPE_FW_DNLD_EN_L
IN
16
1B1 15
2B1 13
Z1_SCLK
Z2_H_CS_L
OUT
17
OUT
16 17
TO Z1/Z2
1B2 14
2B2 12
Z1_MISO
Z1_CS_OE
C
OUT
17
OUT
16 17
APN:311S0485
(A -> B)
16
GND
16
16
16
16
16
34
=PP1V8_MISC
=PP3V0_GRAPE
1
16 17 34
C3060
0.1UF
10%
6.3V
2 X5R
201
Z1_B_ADR<0>
Z1_B_ADR<1>
Z1_B_ADR<2>
A1
A2
VCCA
17
VCCB
U3060
17
17
OUT
GPIO_GRAPE_IRQ_L
SN74LVC1T45YZPR
BGA
C1
B2
DIR
GND
MATES WITH RIGHTMOST GRAPE FLEX TAIL
17
16
NC
NC
NC
NC
NC
B5
A3
C5
B3
GRAPE_SCLK
GRAPE_CS_L
MAKE_BASE=TRUE
16
GPIO_GRAPE_IRQ_3V0_L
C2
IN
17
GND
G8
G7
G6
G5
F7
F6
E7
E6
E5
E3
D7
C9
BGA
C6
D3
D4
D5
D6
D8
D9
E4
E8
F4
F5
F8 NC
F9
G3
G4
G9
H3
H4
H7
H8
H9
J6
K7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
17
GROUNDHOG
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
MUX8
MUX9
MUX10
MUX11
MUX12
MUX13
MUX14
MUX15
MUX16
MUX17
MUX18
MUX19
MUX20
MUX21
MUX22
MUX23
VCC_DIG
11
U3003
IC,ASIC,GROUNDHOG B0,120B BGA
SN74AVCH4T245RSV
10
343S0525
16 17 34
10%
6.3V
2 X5R
201
A6
16
F3
E9
B6
B1
CRITICAL
J3011
NOSTUFF
502250-8037-B
R3060
1
BOOST CONVERTOR
16
16
16
16
16
16
16
16
16
16
16
16
16
16
MT_PANEL_OUT<0>
MT_PANEL_OUT<2>
MT_PANEL_OUT<4>
MT_PANEL_OUT<6>
MT_PANEL_OUT<8>
MT_PANEL_OUT<10>
MT_PANEL_OUT<12>
MT_PANEL_OUT<14>
MT_PANEL_OUT<16>
MT_PANEL_OUT<18>
MT_PANEL_OUT<20>
MT_PANEL_OUT<22>
MT_PANEL_OUT<24>
MT_PANEL_OUT<26>
MT_PANEL_OUT<28>
MT_PANEL_OUT<30>
MT_PANEL_OUT<32>
MT_PANEL_OUT<34>
16
16
16
VR_BOOST_L 1
16
34 17 16
VR_BOOST_SW
2
VLF
C3009
=PP3V0_GRAPE
0.1UF
16
16
16
CRITICAL
1
16
U3000
TPS61045
16
NC
16
16
16
16
R3066
PP18V_R_GRAPE
0.1
1%
1/20W
MF
201
C3008 1
R30091
5%
25V
NPO-C0G 2
0201
1%
1/16W
MF-LF
402 2
1M
PP18V_GRAPE
=PP3V0_GRAPE
16
VOLTAGE=18V
DO
QFN-1
1UF
17 16
2.2UF
4 VR_BOOST_FBK
CTRL
PM_BOOST_EN
THRML
PAD
9
SW
C3002
470PF
10%
16V
2 X5R-X7R-CERM
0201
IN
=PP3V0_GRAPE
1
C3050
Y 4
71.5K
Z1_CS_L
U3009
SN74LVC1G125DRYR-M
OUT
OUT
SPI3_GRAPE_MISO
LLP
4
17
Z1_MOSI
2
NC 5
OE*
17
17 16
IN
Z1_CS_OE
NC
1%
1/20W
MF
2 201
SYNC_MASTER=N/A
SYNC_DATE=N/A
PAGE TITLE
GRAPE: GROUNDHOG,CONN,BOOST
AGND_U3000
DRAWING NUMBER
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
Apple Inc.
TABLE_ALT_ITEM
311S0523
311S0485
U3007
311S0524
311S0533
U3009
311S0525
311S0532
U3010
R
TABLE_ALT_ITEM
SM
TABLE_ALT_ITEM
IN
NC
NC
10%
6.3V
2 X5R
201
CRITICAL
36 16 5
Z2_H_CS_L 2 A
16 17 34
C3041
0.1UF
0.1UF
10%
2 6.3V
X5R
201
SN74LVC1G126DRYR-M
LLP
R3012
16 17 34
1 OE
17
XW3000
IN
Z1_CS_OE
GND
1
C3001
10%
2 6.3V
X5R
603
CRITICAL
U3010
C3000
10%
2 25V
X5R
603-1
17 16
FB
VCC
VIN
16
16
SOD-323
A
K
33PF
10%
25V
X5R
402
16
LOAD CURRENT ~ 153UA
VOLTAGE=18V
D3000
B0520WSXG
16
39
38
40
CRITICAL
L3000
4.7UH-700MA-280MOHM
16
16
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND
16
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
PGND
16
MT_PANEL_OUT<1>
MT_PANEL_OUT<3>
MT_PANEL_OUT<5>
MT_PANEL_OUT<7>
MT_PANEL_OUT<9>
MT_PANEL_OUT<11>
MT_PANEL_OUT<13>
MT_PANEL_OUT<15>
MT_PANEL_OUT<17>
MT_PANEL_OUT<19>
MT_PANEL_OUT<21>
MT_PANEL_OUT<23>
MT_PANEL_OUT<25>
MT_PANEL_OUT<27>
MT_PANEL_OUT<29>
MT_PANEL_OUT<31>
MT_PANEL_OUT<33>
MT_PANEL_OUT<35>
CRITICAL
16
5%
1/20W
MF
201
MIN_NECK_MIDTH SHOULD BE 0.4MM
F-RT-SM
41
39

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
30 OF 154
SHEET
16 OF 39
ZEPHYR 1+ ASIC
C3102
0.1UF
4.7
5%
1/20W
MF
201
17
Z1_1V8_OUT
10%
6.3V
2 X5R
201
VOLTAGE=3.0V
4.7UF
=PP3V0_GRAPE
0.1UF
10%
6.3V
2 X5R
201
VDDANA AND VDDCORE

ARE EACH GENERATED WITHIN
Z2 AND BYPASSED OUTSIDE
R3155
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
NC
0.1UF
10%
6.3V
2 X5R
201
B6
C10
C5
C9
VDDIO
V18
SCLK
CS*
MISO
MOSI
CRITICAL
U3100
BCM5973
BGA
A11
B10
B9
B8
Z1_GO
Z1_DONE
PCLK A12
Z1_PCLK
STMOUT A10
STMIN A13
16 17
IN
16
IN
16 17
OUT
16 17
A2
A1
A3
A4
B4
B3
Z1_BON_L<0>
Z1_BON_L<1>
Z1_BON_L<2>
Z1_BON_L<3>
Z1_BON_L<4>
Z1_BON_L<5>
VOLTAGE=1.8V
10%
6.3V
2 X5R
201
VDDANA VDDCORE
CFG1
17
16
MODE
DEPENDENT 1
DEPENDENT 2
AUTONOMOUS
16
CFG0
SLAVE
K48 USES DEPENDENT 2 MODE

16
16
IN1_0
IN1_1
B8 IN2_0
NC
C8 IN2_1
NC
NC
NC
16
B7
C7
16
16
U3101
R3181
100
5%
1/32W
MF
2 01005
34 17 16
FBGA
IN3_0
IN3_1
IN8_0
IN8_1
C2 IN9_0
NC
A2 IN9_1
NC
1
R3173
0
5%
1/20W
MF
2 201
B2
IN10_0
NC
C1 IN10_1
NC
B1
IN11_0
NC
A1 IN11_1
NC
NC
BOOT_CFG0_R
BOOT_CFG1_R
R3171
0
5%
1/20W
MF
2 201
NC
NC
NC
E6
ARMTAPMD*
F6
D3
BOOT_CFG0
BOOT_CFG1
G5
F5
FLOO
LFOO
G7
EXTFLLIN
C3192
10UF
20%
2 6.3V
CERM-X5R
0402-1
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
J2
J3
H4
J6
G3
F3
F4
H6
GPIO_GRAPE_IRQ_3V0_L
PM_BOOST_EN
Z1_GO
17
Z1_DONE
17
GRAPE_CS_L
IN 16
GRAPE_MOSI
IN 16
GRAPE_MISO
OUT 16
GRAPE_SCLK
IN 16
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
G6
E8
E9
F7
TP_U3101_TCK
TP_U3101_TDI
TP_U3101_TDO
TP_U3101_TMS
H_CS*
H_SCLK
H_SDI
H_SDO
H1
J1
H3
J4
Z2_H_CS_L
Z1_SCLK
Z1_MISO
Z1_MOSI
A_CS*
A_SCLK
A_SDI
A_SDO
F1
G1
F2
G4
Z2_A_CS_L
TP_Z2_A_SCLK
TP_Z2_A_SDI
TP_Z2_A_SDO
TM0
TM1
E7
D4
TP_U3101_TM0
U3101_TM1
CLKIN
CLKOUT
E5
E4
RESET*
D5
BCM5974CKFBGH
A6
NC
NC
=PP3V0_GRAPE
10UF
20%
2 6.3V
CERM-X5R
0402-1
Z1_CS_OE_R
NC_BON_L1 NO_TEST=TRUE
AG_SHLD_TST 16
NC_BON_L3 NO_TEST=TRUE
IN4_0
NC
B6 IN4_1
NC
A3
B3
J8
H9
J9
H7
J7
H5
A4
16
0.1UF
C3191
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
CRITICAL
IN7_0
NC
B4 IN7_1
NC
U3100_TM
C3106
10%
6.3V
2 X5R
201
F9
F8
G9
B5 IN6_0
NC
A5 IN6_1
NC
16
D
R3190
B_ADR0
B_ADR1
B_ADR2
C6 IN5_0
NC
C5 IN5_1
NC
16
RESET* A7 RST_GRAPE_Z1_L
NC
NC
A7
A8
4.7UF
20%
6.3V
2 X5R-CERM1
402
Z2_3V3_1V8_IN
1
34
C3107
1.00 2
Z1_1V8_OUT
17
VOLTAGE=1.8V
1%
1/20W
MF
201
MIN_NECK_MIDTH SHOULD BE 0.4MM
VDDIO VDDLDO
A9
IN0_0
NC
B9 IN0_1
NC
17
C3108
0.1UF
10%
6.3V
2 X5R
201
17
Z1_B_ADR<0>
Z1_B_ADR<1>
Z1_B_ADR<2>
TM A9
IN
C3110
0.1UF
20%
4V
2 X5R
402
Z1_STMIN
B_ADR0 A5
B_ADR1 B5
B_ADR2 A6
BON_L0
BON_L1
BON_L2
BON_L3
BON_L4
BON_L5
2.2UF
Z1_SCLK
Z1_CS_L
Z1_MISO
Z1_MOSI
GO A8
DONE B7
INTERNAL PU
R3120
Z1_PCLK
NC_BON_L5
Z2 - PRODUCT STRAP OPTIONS
17
5%
1/20W
MF
201
Z1_CS_OE
IN
16
NO_TEST=TRUE
16
IN
16 17
IN
16 17
OUT
16 17
BON_L3
OUT
16
OUT
16
K48
FLOAT
FLOAT
FLOAT
K94
FLOAT
LOW
FLOAT
DEFAULT
B1
B2
B12
B13
C2
C3
C6
C7
C8
C11
C12
D3
D11
F7
H7
L3
L4
L5
L6
L7
L8
L9
L10
L11
GNDANA
J2
CRITICAL ERROR
J2
R3160
100K
5%
1/20W
MF
2 201
16 17 34
R3107
100K
5%
1/20W
MF
2 201
PMU_GPIO_CLK_32K_GRAPE
MAKE_BASE=TRUE
IN
30 36
R3180
100
RST_GRAPE_Z2_L
IN
5%
1/32W
MF
2 01005
16
GND
SYNC_MASTER=N/A
PAGE TITLE
GNDDIG GNDIO
DRAWING NUMBER

SYNC_DATE=N/A
GRAPE: Z1, Z2
Apple Inc.
MODE
HOST_REFCLK
NC
BON_L4
LOW
ALL OTHER STRAPS
=PP3V0_GRAPE
IN
BON_L5
C3
C4
D6
D7
D8
C9
D9
G2
D1
H8
16
VDDANA
VDDDIG
5%
1/20W
MF
2 201
C3112
C3105
VOLTAGE=1.8V
D2
16
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IN32
IN33
IN34
IN35
IN36
IN37
IN38
IN39
IN40
IN41
IN42
IN43
IN44
IN45
IN46
IN47
IN48
IN49
IN50
IN51
IN52
IN53
IN54
IN55
IN56
IN57
IN58
IN59
IN60
IN61
IN62
IN63
0.1UF
10%
6.3V
2 X5R
201
C4
16
C3109
B11
16
VOLTAGE=1.8V
Z2_VDDANA
G6
G7
G8
K4
K10
16
H2
G2
D7
C1
F1
J1
D2
D1
K7
H1
E1
E2
J2
G1
F2
J7
K2
N4
M5
N5
M6
N3
M3
L1
K1
L2
N6
M2
M4
M1
N2
N1
N13
N12
M10
M13
N8
M12
K13
L13
L12
M11
N11
M8
N9
M9
N10
K12
J13
F12
G13
NC
J12
NC
E12
NC
E13
NC
H13
NC
N7
NC
D13
NC
D12
NC
H12
NC
F13
NC
C13
NC
E7
NC
M7
NC
G12
20%
2 6.3V
CERM-X5R
0402-1
16 17 34
100K
MT_PANEL_IN<0>
MT_PANEL_IN<1>
MT_PANEL_IN<2>
MT_PANEL_IN<3>
MT_PANEL_IN<4>
MT_PANEL_IN<5>
MT_PANEL_IN<6>
MT_PANEL_IN<7>
MT_PANEL_IN<8>
MT_PANEL_IN<9>
MT_PANEL_IN<10>
MT_PANEL_IN<11>
MT_PANEL_IN<12>
MT_PANEL_IN<13>
MT_PANEL_IN<14>
MT_PANEL_IN<15>
MT_PANEL_IN<16>
MT_PANEL_IN<17>
MT_PANEL_IN<18>
MT_PANEL_IN<19>
MT_PANEL_IN<20>
MT_PANEL_IN<21>
MT_PANEL_IN<22>
MT_PANEL_IN<23>
MT_PANEL_IN<24>
MT_PANEL_IN<25>
MT_PANEL_IN<26>
MT_PANEL_IN<27>
MT_PANEL_IN<28>
MT_PANEL_IN<29>
MUX_IN<0>
MUX_IN<1>
MUX_IN<2>
MUX_IN<3>
MUX_IN<4>
MUX_IN<5>
MUX_IN<6>
MUX_IN<7>
MUX_IN<8>
MUX_IN<9>
MUX_IN<10>
MUX_IN<11>
MUX_IN<12>
MUX_IN<13>
MUX_IN<14>
MUX_IN<15>
MUX_IN<16>
MUX_IN<17>
MUX_IN<18>
MUX_IN<19>
C3111
10UF
2.2UF
C3104 1 C3103
20%
6.3V
2 X5R-CERM1
402
C3101
20%
2 4V
X5R
402
MT_3V3_INT
=PP3V0_GRAPE_Z2
Z2_VDDCORE
1
E2
E3
R3101
ARM9 MCU (Z2 BASED)
=PP3V0_GRAPE_Z1
G8
H2
J5
34
E1
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
31 OF 154
SHEET
17 OF 39
6
34 19
=PP1V8_AUDIO
1
C3602
0.1UF
C3604
0.1UF
20%
2 4V
X5R
01005
MIKEY BUS FILTER
C3609
20%
2 10V
X5R-CERM
0402
1
1.0UF
R3699
CRITICAL
C3699
4.7UF
VOLTAGE=1.7V
PP1V7_VA_VCP_R
1%
1/20W
MF
201
20%
6.3V
2 X5R-CERM1
402
20%
2 6.3V
X5R
0201-MUR
1.00 2
C3698
1.0UF
GND_AUDIO_CODEC
10%
2 16V
X5R-CERM
0201
C3601
20%
2 6.3V
X5R-CERM1
402
R3630
1.00 1
1%
1/20W
MF
201
C3614
0.1UF
CRITICAL
4.7UF
20%
2 6.3V
X5R
0201-MUR
37 18
37 18
CRITICAL
1
1%
1/20W
MF
2 201
L81_FLYN
20%
6.3V
X5R-CERM1
402
R3601
2.21K2
1%
1/20W
MF
201
NC_MIC1_BIAS
18 AIN1P
18 AIN1N
18 MIC1_BIAS_FILT
L81_MIC2_BIAS_IN
L81_MIC2_BIAS
H10
J10
K10
NO_TEST=TRUE
H2
E3
E4
H3
VP0 E8
VP1 E9
CRITICAL
FLYP
FLYC
FLYN
U3600
CS42L81-CWZR-A1
WLCSP
SYM 1 OF 2
MIC1_BIAS
AIN1+
AIN1MIC1_BIAS_FILT
C3612
4.7UF
2
L82_MIC2_BIAS_FILT
37 L81_AIN2_P
37 L81_AIN2_N
L81_MIC2_BIAS_FILT_IN
20%
6.3V
X5R-CERM1
402
XW3602
SHORT-8L-0.25MM-SM
2
1
37 HP_MIC_P
CODEC_HP_HS4_REF
NOSTUFF
SHORT-8L-0.25MM-SM
2
1
37 HP_MIC_N
CODEC_HP_HS3_REF
NOSTUFF
DP
DN
HPOUTA
HPOUTB
HS3
HS4
HS3_REF
HS4_REF
HPDETECT
C3616
0.01UF
1
10V 10%
0201
X5R-CERM
XW3603
18
18
18
C3617
NC_MIC3_BIAS
AIN3P
AIN3N
MIC3_BIAS_FILT
H4
NO_TEST=TRUE
C3
C2
G3
MIC3_BIAS
AIN3+
AIN3MIC3_BIAS_FILT
NC_MIC4_BIAS
AIN4P
AIN4N
MIC4_BIAS_FILT
NO_TEST=TRUE
F4
D2
E2
F2
MIC4_BIAS
AIN4+
AIN4MIC4_BIAS_FILT
10V 10%
0201
X5R-CERM
18
18
18
NOSTUFF
CRITICAL
C3618
C10
L81_SPEAKER_VQ
SPEAKER_VQ
2.2UF
10%
6.3V 2
X5R
402
GND_AUDIO_CODEC
L81_MBUS_P
L81_MBUS_N
CODEC_HP_LEFT
CODEC_HP_RIGHT
CODEC_HP_HS3
CODEC_HP_HS4
FILT+
FILT-
E1
F1
C3690
0.01UF
10%
2 6.3V
X5R
01005
CODEC_MIC_BIAS_FILT
MAKE_BASE=TRUE
GND_AUDIO_CODEC
3.3K 2
5%
1/32W
MF
01005
18 39
20%
6.3V
X5R-CERM1
402
SIGNAL_MODEL=EMPTY
C3632
L3620
CODEC_HP_DET_R
NOSTUFF
1
0201
CONN_HP_HEADSET_DET
C3620
4700PF
HP_LEFT_FILT
18 37
18 37
TO HEADPHONE JACK
HP_RIGHT_FILT
C3691
34 18
10%
2 6.3V
X5R
01005
NOSTUFF
R3640
1.00K
5%
1/32W
MF
2 01005
30
IN
OUT
22
IN
22
IN
22
IN
22
IN
22
18
MAKE_BASE=TRUE
L81_FILT
1
HP_HS4_FILT
C3610
CODEC_HP_HS3_REF
18
CODEC_HP_HS4_REF
18
MAKE_BASE=TRUE
HP_HS3_REF_FILT
GND_AUDIO_CODEC18
MAKE_BASE=TRUE
HP_HS4_REF_FILT
39
L81_MBUS_REF
OUT
18 25
2
DIGITAL MIC
22
IN
22
IN
DMIC1_FF_SD
DMIC1_FF_SCLK
R3612 1
1/32W 5%
R3613 1
1/32W 5%
2 22
L81_DMIC1_FF_SD
MF 01005
2 22
L81_DMIC1_FF_SCLK
MF 01005
NC_DMIC2_SCLK
=PP1V8_AUDIO
22
MAKE_BASE=TRUE
18
18
OUT
MAKE_BASE=TRUE
18
18
PLACE L3600 TO 3605 CLOSE

TO THE HP CONNECTOR
18
18
20
MAKE_BASE=TRUE
SHORT-8L-0.25MM-SM
1
2
18
IN
10%
2 10V
X7R
201
18
MIC1_BIAS_FILT
MIC3_BIAS_FILT
MIC4_BIAS_FILT
CODEC_HP_DET
18
0.01UF
4.7UF
18
4.7UF
5%
1/20W
MF
201
C3608
CODEC_HP_DET
R3614
MAKE_BASE=TRUE
25 37
240-OHM-0.2A-0.8-OHM
R3620
CRITICAL
20%
2 6.3V
X5R-CERM1
402
BI
NOSTUFF
XW3600
18 39
25 37
100PF
29 39
NC_CODEC_LINE_OUT_L
LINEOUTA K6 NO_TEST=TRUE
NC_CODEC_LINE_OUT_R
LINEOUTB J6 NO_TEST=TRUE
LINEOUT_REF H6
AIN1P
AIN1N
AIN3P
AIN3N
AIN4P
AIN4N
NOSTUFF
CODEC_AIN
HP_HS3_FILT
0.01UF
1
100PF
5%
2 25V
NP0-CERM
0201
BI
5%
2 25V
NP0-CERM
0201
20%
6.3V
X5R-CERM1
402
0.15MM
0.30MM
0.15MM
0.30MM
J4
K4
J8
K8
J1
K1
K7
J7
H8
MIKEY_TS_P
MIKEY_TS_N
5%
1/20W
MF
201
E10
A10
K2
J2
G2
18
MIC2_BIAS_IN
MIC2_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
AIN2+
AIN2M
C3631
4.7UF
L81_NVCP
GNDP
GNDD
GNDHS
GNDHS
GNDA
18
J3
G4
K3
F3
C1
D1
CRITICAL
LDO10
NOSTUFF
C3607
1
L81_PVCP
D10
NC_RIGHT_CH_OUT_P
AOUT2+
NO_TEST=TRUE
NC_RIGHT_CH_OUT_N
AOUT2- D9 NO_TEST=TRUE
C3611 1
20%
6.3V 2
X5R
0201-MUR
CRITICAL
NC_LEFT_CH_OUT_P
AOUT1+ F10
NO_TEST=TRUE
NC_LEFT_CH_OUT_N
AOUT1_M F9 NO_TEST=TRUE
CRITICAL
1.0UF
10%
16V
2 X5R-CERM
0201
+VCP_FILT H9
J9
GNDCP
K9
-VCP_FILT
VOLTAGE=4.7V
C3613
0.1UF
VPROG_MB H1
VL A8
A9
VD
G1
4.7UF
VPROG_CP G10
C3606
VCP0 G8
VCP1 G9
CRITICAL
VA
L81_FLYC
12
NOSTUFF
R3696
5%
2 25V
NP0-CERM
0201
5%
1/20W
MF
201
PP_VPROG_MB_R
L81_FLYP
20%
6.3V
X5R-CERM1
402
C3630
R3631
255K
C3605
2
L81_MBUS_P
L81_MBUS_N
R3697
PP_VPROG_CP_R
12
5%
1/20W
MF
201
VOLTAGE=4.7V
4.7UF
SIGNAL_MODEL=EMPTY
100PF
PLACE R3630 & R3631 CLOSE TO U3600
R3698
C3603
4.7UF
10%
16V
X5R-CERM 2
0201
=PP1V7_VA_VCP
CRITICAL
0.1UF
C3615
20%
4V
2 X5R
01005
39 18
=PPVCC_MAIN_AUDIO
34 18
34 19
36 5
IN
36 5
IN
36 5
IN
36 5
IN
36 5
IN
36 5
IN
36 5
IN
36 5
IN
36 5
IN
25 18
IN
36 5
OUT
36 5
OUT
IN
36 5
36 5
OUT
OUT
30
OUT
I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN
I2S3_CODEC_XSP_BCLK
I2S3_CODEC_XSP_LRCK
I2S3_CODEC_XSP_DOUT
I2S3_CODEC_XSP_DIN
L81_MBUS_REF
SPI1_CODEC_CS_L
SPI1_CODEC_SCLK
SPI1_CODEC_MOSI
SPI1_CODEC_MISO
R3610
1/32W 5%
R3611
1/32W 5%
2 22
I2S3_CODEC_XSP_SDOUT
MF 01005
CRITICAL
U3600
A3
B3
A2
A1
ASP_SCLK
ASP_LRCK
ASP_SDIN
ASP_SDOUT
B4
B5
A5
A4
K5
C5
A6
B8
A7
XSP_SCLK
XSP_LRCK_FSYNC
XSP_SDIN_DAC2_MUTE
XSP_SDOUT
MBUS_REF
CS*
CCLK
CDIN
CDOUT
B9
B10
C9
DMIC1_SD
DMIC1_SCLK
B7 DMIC2_SD CS42L81-CWZR-A1
NO_TEST=TRUE
B6 DMIC2_SCLK
WLCSP
SYM 2 OF 2
C8 MCLK
2 22 36 I2S0_CODEC_ASP_SDOUT
MF 01005
GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_CODEC_RST_L
B1
B2
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
C6
D3
D5
D6
D7
D8
E5
E6
E7
F5
F6
F7
F8
G5
G6
G7
H5
H7
J5
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
AUDIO: L81 CODEC

DRAWING NUMBER
TSTI0 C4
TSTI1 C7
TSTI2 D4
INT*
WAKE*
RESET*
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
18 OF 39
PAGE
36 OF 154
SHEET
LEFT SPEAKER AMP
TABLE_5_HEAD
PART#
=PP1V7_VA_VCP
CRITICAL
4.7UF
C3742
4.7UF
CRITICAL
C3743
4.7UF
L19_L_VBOOST
CRITICAL CRITICAL
C3744
0.1UF
20%
20%
20%
10%
10V
10V
16V
2 10V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
0402
0402
0402
0201
C3745 1 C3710 1 C3711

22UF
20%
10V
2 X5R-CERM
2
0603-1
22UF
20%
10V
2
X5R-CERM
0603-1
27PF
C3712
5%
16V
2 NP0-C0G
01005
27PF
0.1UF
10%
16V
X5R-CERM
0201
5%
2 16V
NP0-C0G
01005
VBST
CRITICAL
2
36 30 25 19 5
I2C0_SDA_1V8
D5
36 30 25 19 5
I2C0_SCL_1V8
D6
GPIO_SPKAMP_LEFT_IRQ_L
A7
GPIO_SPKAMP_RST_L
A6
19 5
19 5
SW
SDA
ISENSE- F1
ISENSE+ E1
INT*
RESET*
OUT+ D2
OUT- C2
D7 ALIVE
C7 ADO
I2S1_SPKAMP_MCK_R
E7
19 5
I2S1_SPKAMP_BCLK
E6
19 5
I2S1_SPKAMP_LRCK
F6
19 5
I2S1_SPKAMP_DOUT
F7
I2S1_SPKAMP_DIN
E5
19 5
19 5
L19_L_FILT
L19_L_LDO_FILT
37
37
R3742,R3743,R3752,R3753
113S0022
RES,MF,1/10W,0OHM,5,0603,SMD,LF
FL3740,FL3741,FL3750,FL3751
37
37
2
X5R-CERM1
402
R3745 SPKR_L_VSENSE_N
C3748
1
20%
6.3V
1
10%
10V
1 OMIT_TABLE
10
R3740
LRCK/FSYNC
0.100
1
2
MIN_LINE_WIDTH=0.5 1%
MM
MIN_NECK_WIDTH=0.2
MM
1/4W
1
MF
R3741
0805
44.2K
1%
1/20W
MF
2 201
NOSTUFF
OMIT_TABLE
C3768
R3743
SCLK
B5
B6
C6
E4
F3
F4
R3744
1
2
X5R-CERM
0201
5%
1/20W
MF
2 201 CRITICAL
GNDA
100PF
5%
25V
NP0-CERM 2
0201
NOSTUFF
R3742
100PF
5%
OMIT_TABLE
1/20W
CRITICAL
MF
FL3741
2 201
MIN_LINE_WIDTH=0.5220-OHM-2.0A
MM
1
2
37 SPKR_L_FLR
SPKR_L_CONN_P
0603
C3740
NOSTUFF
18PF
+/-0.1PF%
2 25V
CER
0201
C3761
8.2PF
5%
25V
2 NP0-C0G-CERM
0201
10K
SPKR_L_VSENSE_P
19 37
5%
1/20W
MF
201
5%
25V
NP0-CERM 2
0201
10
19 37
5%
1/20W
MF
201
C3760
SPKR_L_P
37 SPKR_L_N
SDOUT
C3767
0.01UF
37
SDIN
NOSTUFF
2
X5R-CERM1
402
SPKR_L_SES_N
SPKR_L_SES_P
10K
4.7UF
SPKR_L_VSENSE_N_FILT
SPKR_L_VSENSE_P_FILT
IREF+ B7 L19_L_IREF
A3
B3
B4
C3
C4
D3
D4
RES,MF,1/20W,0.0OHM,5,0201,SMD
0.1UF
MCLK
GNDP
4.7UF
VSENSE- E3
VSENSE+ E2
SCL
117S0002
18 19 34
1
20%
6.3V
FILT+ F2
LDO_FILT C5
WLCSP
VER1
BOM OPTION
C3747
CS35L19B-CWZR
A2
B2
CRITICAL
10%
6.3V
2 X5R
201
VA
VP
C3746
U3740
L19_L_SWITCH
TFA302610A-SM
CRITICAL
L3740
2.2UH-20%-3.3A-0.115OHM
1
C3713
F5
A4
A5
C3741
A1
B1
C1
D1
CRITICAL
DESCRIPTION
TABLE_5_ITEM
=PPVCC_MAIN_AUDIO
1
QTY
TABLE_5_ITEM
I2C ADDRESS: 1000000X
34
18
19
19 37
SPEAKER CONNECTOR
NOSTUFF
C3763
3.9PF
+/-0.1PF
2 25V
NP0-C0G-CERM
0201
OMIT_TABLE
CRITICAL
FL3740
220-OHM-2.0A
1
37 19
SPKR_L_CONN_N
0603
1
C3749
8.2PF
NOSTUFF
C3766
3.9PF
+/-0.1PF%
+/-0.1PF
25V
2 25V
CER
2 NP0-C0G-CERM
0201
0201
NOSTUFF
C3764
18PF
=PPVCC_MAIN_AUDIO
=PP1V7_VA_VCP 18
C3752
C3753
C3754
4.7UF
4.7UF
0.1UF
20%
20%
20%
10%
10V
16V
2 10V
X5R-CERM 2 10V
X5R-CERM 2 X5R-CERM 2 X5R-CERM
0402
0402
0402
0201
C3755 1 C3720
22UF
20%
2 10V
2
X5R-CERM
0603-1
22UF
20%
10V
X5R-CERM2
0603-1
C3721
0.1UF
C3722
VBST
CRITICAL
A2
B2
WLCSP
VER1
SW
36 30 25 19 5
I2C0_SDA_1V8
36 30 25 19 5
I2C0_SCL_1V8
D6 SCL
GPIO_SPKAMP_RIGHT_IRQ_L
A7 INT*
GPIO_SPKAMP_RST_L
A6 RESET*
19 5
19 5
I2S1_SPKAMP_BCLK
E6 SCLK
19 5
I2S1_SPKAMP_LRCK
F6 LRCK/FSYNC
19 5
I2S1_SPKAMP_DOUT
F7 SDIN
19 5
I2S1_SPKAMP_DIN
E5 SDOUT
FILT+ F2
LDO_FILT C5
ISENSE- F1
ISENSE+ E1
OUT+ D2
OUT- C2
10%
2 6.3V
X5R
201
37 19
SPKR_R_VSENSE_P
37 19
SPKR_R_CONN_N
37 19
L19_R_FILT
L19_R_LDO_FILT
SIGNAL_MODEL=EMPTY
8
NOSTUFF
CRITICAL
SIGNAL_MODEL=EMPTY
37
37
37
37
R3755
1
NOSTUFF
2
X5R-CERM1
402
100PF
5%
25V
NP0-CERM 2
0201
C3780
1
10%
10V
37
2
X5R-CERM
0201
1OMIT_TABLE
OMIT_TABLE
C3788 1
R3752
100PF
5%
OMIT_TABLE
1/20W
CRITICAL
MF
FL3751
2 201
MIN_LINE_WIDTH=0.5220-OHM-2.0A
MM
2
37 SPKR_R_FLR 1
SPKR_R_CONN_P
0603
1
C3750
NOSTUFF
18PF
+/-0.1PF%
2 25V
CER
0201
C3781
8.2PF
5%
25V
2 NP0-C0G-CERM
0201
C3784
18PF
SPKR_R_VSENSE_N
C3773 1
100PF
5%
16V
NP0-C0G 2
01005
19 37
10K
SPKR_R_VSENSE_P
19 37
19 37
C3783
3.9PF
+/-0.1PF
2 25V
NP0-C0G-CERM
0201
SYNC_MASTER=N/A
PAGE TITLE
SPKR_R_CONN_N
0603
1
C3759
8.2PF
5%
2 25V
NP0-C0G-CERM
0201
5%
16V
NP0-C0G 2
01005
NOSTUFF
CRITICAL
NOSTUFF
FL3750
NOSTUFF
5%
25V
NP0-CERM 2
0201
10
220-OHM-2.0A
100PF
5%
1/20W
MF
201
NOSTUFF
R3753
1
2
MIN_LINE_WIDTH=0.5 1%
MM
1
MIN_NECK_WIDTH=0.2
MM
1/4W
R3751
MF
0805
44.2K
1%
1/20W
MF
2 201
R3754
0.01UF
37
10K
C3772
5%
2 16V
NP0-C0G
01005
5%
1/20W
MF
201
C3787 1
NOSTUFF
SPKR_R_SES_N
SPKR_R_SES_P
0.100
GNDA
5%
2 16V
NP0-C0G
01005
100PF
4.7UF
1
20%
6.3V
SPKR_R_VSENSE_N_FILT
SPKR_R_VSENSE_P_FILT
SPKR_R_P
SPKR_R_N
NOSTUFF
CRITICAL
C3770
C3771
C3758
R3750
XW3777
SPKR_R_VSENSE_N
OMIT_TABLE
CRITICAL
XW3776
1
2
X5R-CERM1
402
1
2
3
4
5
6
SIGNAL_MODEL=EMPTY
NOSTUFF
CRITICAL
5%
1/20W
MF
2 201 CRITICAL
B5
B6
C6
E4
F3
F4
A3
B3
B4
C3
C4
D3
D4
SPKR_R_CONN_P
C3757
10
GNDP
OUT
37 19
SM
19 34
M-RT-SM
7
PLACE XWS CLOSE TO CONNECTOR
IREF+ B7 L19_R_IREF
E7 MCLK
SM
SIGNAL_MODEL=EMPTY
XW3775
SPKR_L_VSENSE_N
SPK_ID
0.1UF
1
20%
6.3V
D7 ALIVE
I2S1_SPKAMP_MCK_R
19 5
SPKR_L_CONN_N
100PF
VA
VSENSE- E3
VSENSE+ E2
C7 ADO
PP1V7_VA_VCP
37 19
78171-6006
4.7UF
CS35L19B-CWZR
D5 SDA
39 34 29
L19_R_SWITCH
SPKR_L_VSENSE_P
C3756
U3750
2.2UH-20%-3.3A-0.115OHM
19 5
VP
CRITICAL
L3750
1
2
TFA302610A-SM
5%
2 16V
NP0-C0G
01005
27PF
10%
5%
16V
16V
X5R-CERM 2 NP0-C0G
01005
0201
C3723
27PF
F5
4.7UF
A4
A5
C3751
L19_R_VBOOST
CRITICAL CRITICAL
A1
B1
C1
D1
CRITICAL CRITICAL CRITICAL

1
37 19
37 19
J3700
XW3774
SM
I2C ADDRESS: 1000001X
34
18
19
CRITICAL
SPKR_L_CONN_P
SM
19 37
5%
2 25V
NP0-C0G-CERM
0201
RIGHT SPEAKER AMP
APN 518S0672
19 37
DRAWING NUMBER
NOSTUFF
Apple Inc.
C3786
3.9PF
+/-0.1PF%
+/-0.1PF
2 25V
CER
2 25V
NP0-C0G-CERM
0201
0201

SYNC_DATE=N/A
AUDIO: SPEAKER AMP
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
37 OF 154
SHEET
19 OF 39
APN: 518S0828
CRITICAL
J5400
502250-8037-B
40
38
22
36 22
36 22
22
36 22
22
CONN_ISP0_CAM_RF_SHUTDOWN
CONN_I2C2_SCL_3V0
CONN_I2C1_SCL_1V8
CONN_DMIC1_FF_SD
CONN_ISP0_CAM_RF_I2C_SCL
CONN_HALL_IRQ
NC
NC
NC
37 21
37 21
MIPI0C_CAM_RF_DATA_F_P<0>
MIPI0C_CAM_RF_DATA_F_N<1>
F-RT-SM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_I2C2_SDA_3V0
CONN_ALS_IRQ_L
CONN_I2C1_SDA_1V8
CONN_DMIC1_FF_SCLK
CONN_ISP0_CAM_RF_I2C_SDA
NC
NC
NC
22
22 36
22
22 36
22
22 36
PP3V0_S2R_HALL_FLT
21
CONN_ISP0_CAM_RF_RST_L
22
PP3V0_SENSOR_FLT
PP1V8_SENSOR_FLT
PP2V8_CAM_FLT
CONN_ISP0_CAM_RF_CLK
5 21
21
21
22 36
21 37
21 37
39
41
APN: 518S0828
CRITICAL
J5401
502250-8037-B
40
38
NC
37 21
MIPI0C_CAM_RF_CLK_F_N
36 22
CONN_ISP1_CAM_FF_I2C_SCL
37 21
37 21
22
30 5
5
22
18
22
22
22
NC
MIPI1C_CAM_FF_CLK_F_N
MIPI1C_CAM_FF_DATA_F_N<0>
CONN_PROX_IRQ_L
GPIO_BTN_ONOFF_L
GPIO_BTN_VOL_DOWN_L
NC
CONN_ACCEL_IRQ1_L
CONN_HP_HEADSET_DET
CONN_HP_RIGHT_FILT1
CONN_HP_HS3_REF_MIC2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
F-RT-SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
NC
NC
MIPI0C_CAM_RF_CLK_F_P
CONN_ISP1_CAM_FF_CLK
CONN_ISP1_CAM_FF_I2C_SDA
MIPI1C_CAM_FF_CLK_F_P
MIPI1C_CAM_FF_DATA_F_P<0>
CONN_GYRO_IRQ2
GPIO_BTN_SRL_L
GPIO_BTN_VOL_UP_L
NC
CONN_ACCEL_IRQ2_L
CONN_GYRO_IRQ1
CONN_HP_LEFT_FILT1
CONN_HP_HS3_FILT1
CONN_HP_HS4_FILT1
21 37
22 36
22 36
21 37
21 37
22
5 30
5
22
22
22
22
22
39
41
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
SENSOR FLEX CONN

DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
54 OF 154
SHEET
20 OF 39
NOSTUFF
R5500
0
5%
1/20W
MF
201
CRITICAL
L5500
L5550
90-OHM-50MA
TCM0605-1
240-OHM-0.2A-0.8-OHM
SYM_VER-1
37 7
BI
=PP3V0_S2R_HALL
34 23
BI
20 37
PP3V0_S2R_HALL_FLT
2
0201
1
37 7
BI
BI
20 37
8.2PF
L5560
240-OHM-25%-400MA
NOSTUFF
=PP1V8_SENSOR
34
R5510
1
2 X7R-CERM
1000PF
20
5%
1/20W
MF
201
+/-0.1PF%
25V
2 CER
0201
10%
10V
402
1UF
5%
25V
0201
10%
16V
0201
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
C5553
C5552
C5551
2 NP0-C0G-CERM
2 X5R
R5501
0
82PF
NOSTUFF
C5550
PP1V8_SENSOR_FLT
2
0402
DCR 0.31
C5560
82PF
5%
5%
1/20W
MF
201
C5561
1UF
10%
C5562
10%
+/-0.1PF%
2 25V
CER
0201
1000PF
2 16V
X7R-CERM
2 25V
2 10V
NP0-C0G-CERM
X5R
0201
402
0201
20
VOLTAGE=1.8V
C5563
8.2PF
CRITICAL
L5510
L5570
90-OHM-50MA
TCM0605-1
240-OHM-25%-400MA
SYM_VER-1
37 7
BI
BI
20 37
34
=PP2V8_CAM
37 7
BI
BI
20 37
5%
0201
1UF
10%
C5572
10%
+/-0.1PF%
25V
2 CER
0201
1000PF
2 16V
X7R-CERM
402
0201
20
VOLTAGE=2.8V
C5573
8.2PF
L5580
240-OHM-25%-400MA
34
NOSTUFF
=PP3V0_SENSOR
PP3V0_SENSOR_FLT
2
0402
R5520
0
C5571
5%
1/20W
MF
201
2 25V
2 10V
X5R
NP0-C0G-CERM
R5511
1
C5570
82PF
NOSTUFF
PP2V8_CAM_FLT
2
0402
DCR 0.31
DCR 0.31
1
C5580
82PF
5%
1/20W
MF
201
5%
25V
2 NP0-C0G-CERM 2
0201
C5581
10%
10V
X5R
402
10%
6.3V
2 X5R
201
1UF
C5582
0.1UF
C5583
1000PF
10%
16V
2 X7R-CERM
0201
C5584
5 20
VOLTAGE=3.0V
8.2PF MAX_NECK_LENGTH=3 MM
+/-0.1PF%
25V
2 CER
0201
CRITICAL
L5520
90-OHM-50MA
TCM0605-1
SYM_VER-1
37 7
IN
MIPI0C_CAM_RF_CLK_N
37 7
IN
MIPI0C_CAM_RF_CLK_P
OUT
20 37
OUT
20 37
NOSTUFF
R5521
0
5%
1/20W
MF
201
NOSTUFF
R5530
5%
1/20W
MF
201
CRITICAL
L5530
90-OHM-50MA
TCM0605-1
SYM_VER-1
37 7
IN
MIPI1C_CAM_FF_CLK_P
37 7
IN
MIPI1C_CAM_FF_CLK_N
OUT
20 37
OUT
20 37
NOSTUFF
R5531
0
5%
1/20W
MF
201
NOSTUFF
R5540
0
5%
1/20W
MF
201
CRITICAL
SYNC_MASTER=N/A
L5540
SYM_VER-1
37 7
37 7
BI
BI
BI
BI
DRAWING NUMBER
20 37
Apple Inc.
R
20 37
NOSTUFF
R5541
0

5%
1/20W
MF
201
SYNC_DATE=N/A
PAGE TITLE
90-OHM-50MA
TCM0605-1
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
55 OF 154
SHEET
21 OF 39
1
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
155S0643
155S0373
REF DES
COMMENTS:
U5600,U5610,U5620,U5630,U5640,U5650,U5660,U5670
TABLE_ALT_ITEM
RADAR:8376668
U5600
800MHZ-100MA-27PF
0603
7
36 5
5
36 5
ISP1_CAM_FF_SHUTDOWN_L
I2C2_SDA_3V0
GPIO_ALS_IRQ_L
I2C1_SDA_1V8
IN
BI
OUT
BI
1
2
3
4
IN1
IN2
OUT1 5
OUT2 6
IN3
OUT3 7
IN4
OUT4 8
CONN_ISP1_CAM_FF_SHUTDOWN_L
CONN_I2C2_SDA_3V0
CONN_ALS_IRQ_L
CONN_I2C1_SDA_1V8
OUT
20
20 36
BI
IN
20
BI
20 36
IN
20
9
10
GND
U5610
800MHZ-100MA-27PF
0603
18
IN
36 5
IN
36 5
IN
IN
DMIC1_FF_SD
I2C1_SCL_1V8
I2C2_SCL_3V0
ISP0_CAM_RF_SHUTDOWN
1
2
3
4
IN1
OUT1 5
IN2
IN3
OUT2 6
OUT3 7
IN4
OUT4 8
CONN_DMIC1_FF_SD
CONN_I2C1_SCL_1V8
CONN_I2C2_SCL_3V0
CONN_ISP0_CAM_RF_SHUTDOWN
OUT
20 36
OUT
20 36
OUT
20
9
10
GND
CRITICAL
U5660
800MHZ-100MA-27PF
0603-1
20
IN
20
IN
20
OUT
CONN_HP_HS4_FILT1
CONN_HP_HS3_FILT1
CONN_HP_LEFT_FILT1
NC
1 IN1
2 IN2
3 IN3
4 IN4
OUT1 5
OUT2 6
OUT3 7
OUT4 8
HP_HS4_FILT
HP_HS3_FILT
HP_LEFT_FILT
OUT
18
OUT
18
IN
18
NC
9
10
GND
U5620
800MHZ-100MA-27PF
0603
IN
36 7
BI
IN
36 7
IN
DMIC1_FF_SCLK
ISP0_CAM_RF_I2C_SDA
ISP0_CAM_RF_RST_L
ISP0_CAM_RF_I2C_SCL
1
2
3
4
IN1
IN2
OUT1 5
OUT2 6
IN3
IN4
OUT3 7
OUT4 8
CONN_DMIC1_FF_SCLK
CONN_ISP0_CAM_RF_RST_L
OUT
BI
GND
9
10
DO NOT STUFF WITHOUT

AUDIO TEM APPROVAL
AND RECHARACTERIZATION
20
20
OUT
20 36
NOSTUFF
C5620
CRITICAL
27PF
U5670
5%
25V
2 NP0-C0G
0201
800MHZ-100MA-27PF
0603-1
U5630
R5630
IN
ISP0_CAM_RF_CLK
22
36
ISP0_CAM_RF_C
1
C5630
1000PF
20
IN
20
OUT
CONN_HP_RIGHT_FILT1
36
ISP0_CAM_RF_FILT
30
10%
16V
0201
PMU_GPIO_HALL_IRQ
OUT
NC
NC
1
2
3
4
IN1
OUT1 5
IN2
IN3
OUT2 6
OUT3 7
OUT4 8
IN4
1 IN1
2 IN2
3 IN3
NC
HP_HS4_REF_FILT
HP_HS3_REF_FILT
HP_RIGHT_FILT
OUT1 5
OUT2 6
OUT3 7
4 IN4
OUT4 8
OUT
18
OUT
18
IN
18
NC
GND
0603
5%
1/16W
MF-LF
402
NOSTUFF
22 OHM
PLACE IT NEAR U0600
22
IN
800MHZ-100MA-27PF
R5631
5%
1/16W
MF-LF
402
20
NC
NC
CONN_HALL_IRQ
OUT
IN
20 36
20
GND
2 X7R-CERM
9
10
36 7
20 36
OUT
9
10
18
U5640
800MHZ-100MA-27PF
0603
36 7
36 7
IN
ISP1_CAM_FF_CLK1
22
5%
1/16W
MF-LF
402
22 OHM
PLACE IT NEAR U0600
R5641
36
ISP1_CAM_FF_C
1
NOSTUFF
C5640
1000PF
22
5
36 7
IN
OUT
BI
36
ISP1_CAM_FF_I2C_SCL
GPIO_PROX_IRQ_L
ISP1_CAM_FF_I2C_SDA
ISP1_CAM_FF_FILT
1
2
3
4
IN1
OUT1 5
IN2
IN3
OUT2 6
OUT3 7
IN4
OUT4 8
5%
1/16W
MF-LF
402
CONN_PROX_IRQ_L
OUT
IN
20 36
20
BI
OUT
20 36
20 36
GND
9
10
R5640
10%
16V
0201
2 X7R-CERM
U5650
800MHZ-100MA-27PF
0603
OUT
OUT
OUT
OUT
GPIO_GYRO_IRQ1
GPIO_ACCEL_IRQ2_L
GPIO_GYRO_IRQ2
GPIO_ACCEL_IRQ1_L
1 IN1
2 IN2
3 IN3
OUT1 5
OUT2 6
OUT3 7
4 IN4
OUT4 8
CONN_GYRO_IRQ1
CONN_ACCEL_IRQ2_L
CONN_GYRO_IRQ2
CONN_ACCEL_IRQ1_L
IN
20
IN
20
IN
20
IN
20
GND
9
SYNC_MASTER=N/A
10
SYNC_DATE=N/A
PAGE TITLE

DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
56 OF 154
SHEET
22 OF 39
L5700
FERR-22-OHM-1A-0.065-OHM
E75_ACC_POUT_ID1
2
0201
0.055 OHM DCR
CONN_E75_ACC_POUT_ID1
C
25
DZ5791
14.2V-6PF
TABLE_ALT_HEAD
24
VOLTAGE=3.3V
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
377S0116
377S0108
DZ5760
155S0320
155S0513
L5700,L5701RDAR://PROBLEM/9625601
155S0657
155S0537
FL5710,FL5750
155S0741
155S0397
L5757
TABLE_ALT_ITEM
TABLE_ALT_ITEM
0201-1
TABLE_ALT_ITEM
TABLE_ALT_ITEM
L5701
FERR-22-OHM-1A-0.065-OHM
1
0201
0.055 OHM DCR
C
25
E75_ACC_POUT_ID2
DZ5792
14.2V-6PF
0201-1
24
VOLTAGE=3.3V
FL5710
120-OHM-200MA
24
IN
DISCRETE_BTN_HOME_L
GPIO_BTN_HOME_L
0201
OUT
5 30
C5710
DZ5710
0201
+/-0.1PF%
2 25V
CER
0201
6.8V-100PF
8.2PF
C5711
8.2PF
+/-0.1PF%
2 25V
CER
0201
L5757
FERR-70-OHM-4A
39 34
PPVBUS_USB_EMI
2
0603
C5721
27PF
5%
2 25V
NP0-C0G
0201
C5722
8.2PF
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
R5790
CONN_E75_PPVBUS_USB
2
5%
1/20W
MF
2 201
0402
5%
25V
2 NP0-C0G
0201
27V-100PF
100K
C5750
DZ5760
27PF
C5783
0.01UF
10%
2 50V
X7R
402
24
VOLTAGE=6.0V
NOSTUFF
FL5740
120-OHM-200MA
24
IN
CONN_HALL2_IRQ
PMU_GPIO_HALL2_IRQ
0201
2
C5740
NOSTUFF
6.8V-100PF
5%
1/20W
MF
2 201
DZ5740
0201
OUT
30
R5741
5%
1/20W
MF
2 201
USED TO BE C5740 27PF CAP

WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING
USED TO BE C5741 27PF CAP

WHEN HALL2 WAS USED
NOSTUFF
L5730
240-OHM-0.2A-0.8-OHM
34 21
=PP3V0_S2R_HALL 1
PP3V0_S2R_HALL2_FLT
2
0201
1
NOSTUFF
C5730
82PF
NOSTUFF
C5731
1UF
5%
10%
2 25V
2 10V
NP0-C0G-CERM
X5R
0201
402
NOSTUFF
C5732
1000PF
10%
2 16V
X7R-CERM
0201
24
VOLTAGE=3.0V
C5733
5%
1/20W
MF
2 201
USED TO BE C5733 8.2PF CAP

WHEN HALL2 WAS USED
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
E75 DOCK SUPPORT

DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
57 OF 154
SHEET
23 OF 39
IO FLEX CONNECTOR
PN 516S0542 (PLUG - MALE)
CRITICAL
J5900
CPB6450-0101F
M-ST-SM
51
53
C
25
24 23
CONN_E75_ACC_DET_L
OUT
36 25
BI
36 25
BI
36 25
BI
36 25
BI
CONN_E75_DPAIR2_P
CONN_E75_DPAIR2_N
CONN_E75_DPAIR1_N
CONN_E75_DPAIR1_P
CONN_E75_PPVBUS_USB
1
C5900
8.2PF
+/-0.5PF
16V
2 NP0-C0G-CERM
01005
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
C
1
23
C5910
8.2PF
1
+/-0.5PF
16V
2 NP0-C0G-CERM
01005
23
C5920
8.2PF
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
NC
NC
CONN_E75_PPVBUS_USB
23 24
518S0692
CRITICAL
J5950
FF18-6A-R11AD-B-3H
F-RT-SM
23
PP3V0_S2R_HALL2_FLT
NC
23
OUT
23
OUT
CONN_HALL2_IRQ
DISCRETE_BTN_HOME_L
NC
1
2
3
4
5
6
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
IO FLEX CONN
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
58 OF 154
SHEET
24 OF 39
C5930
1.0UF
20%
6.3V
2 X5R
0201-MUR
C5935
0.1UF
10%
2 6.3V
X5R
201
=PP3V3_ACC
36 25
TO BB USB
36 25
10
ACCESSORY USB
36 4
BI
36 4
BI
36 5
ACCESSORY UART
36 5
36 5
AP DEBUG UART
8.2PF
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
36 26 5
MLB_A
R5970
100K
R5971
100K
CRITICAL
U5900
IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36
L5930
90-OHM-50MA
29
TCM0605-1
SYM_VER-1
C5934
1UF
10%
2 25V
X5R
0402
CONN_E75_DPAIR1_P
BI
24 36
CONN_E75_DPAIR1_N
BI
24 36
WCSP
USB_TS_BBMUX_P
USB_TS_BBMUX_N
A1
B1
USB_BRICKID
C2
USB_AP_P
USB_AP_N
A3
B3
UART2_TS_ACC_TXD
UART2_TS_ACC_RXD
E2
E1
UART6_AP_TXD
UART6_AP_RXD
F2
F1
UART1_TX
UART1_RX
SWITCH_EN E4
HOST_RESET B6
D2
D1
UART2_TX
UART2_RX
SDA
SCL
INT
BYPASS
A5
B5
C5943
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
MIKEY_TS_P
MIKEY_TS_N
JTAG_AP_TCK_TS_R
JTAG_AP_TMS_TS_R
CRITICAL
8.2PF
DIG_DP
P_IN F6
OMIT_TABLE
DIG_DN
ACC1 C5
ACC2 E5
USB1_DP
USB1_DN
DP1 A2
DN1 B2
BRICK_ID
DP2 A4
USB0_DP
DN2 B4
USB0_DN
CON_DET_L E3
UART0_TX
UART0_RX
OVP_SW_EN* D6
JTAG_CLK
JTAG_DIO
E75_ACC_POUT_ID1
E75_ACC_POUT_ID2
5%
1/20W
MF
2 201
23
23
36
TS_E75_DPAIR2_P
TS_E75_DPAIR2_N
30
PMU_E75_ACC_DET_L
D3
D4
C6
E6
L5931
RST_AP_L
TS_HOST_RESET
OUT
IN
90-OHM-50MA
29
TCM0605-1
SYM_VER-1
4 26 30 39
CONN_E75_DPAIR2_P
BI
24 36
CONN_E75_DPAIR2_N
BI
24 36
25
5 19 30 36
5 19 30 36
5 30
C5944
8.2PF
TSSLP-2-1
1
CRITICAL
OUT
DZ5901
ESD0P2RF-02LS
OVP_SW_EN_L
I2C0_SDA_1V8
I2C0_SCL_1V8
PMU_GPIO_TS_INT
BYPASS_U5900
CRITICAL
DZ5900
TSSLP-2-1
TS_E75_DPAIR1_P
36 TS_E75_DPAIR1_N
36
CRITICAL
ESD0P2RF-02LS
36
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
F5
C1
A6
5%
1/20W
MF
2 201
MLB_A
BOM OPTION
0.1UF
C3
C4
UART1_BB_RXD
UART1_BB_TXD
BB DEBUG UART
(TS OFF TO H5G UART1)
CRITICAL
34
PPVBUS_PROT
DVSS
DVSS
DVSS
36 26 5
36 5
C5932
U5900
37 18
DESCRIPTION
TABLE_5_ITEM
THS7383IYKAR
37 18
QTY
343S0614
10%
6.3V
2 X5R
201
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
ACC_PWR D5
10%
2 6.3V
X5R
201
C5942
8.2PF
C5941
VDD_1V8 F3
0.1UF
VDD_3V0 F4
C5931
TABLE_5_HEAD
PART#
8.2PF
=PP1V8_S2R_USBMUX
1
C5940
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
1
34 25
TRISTAR
=PP3V0_S2R_TRISTAR
34
2
1
CRITICAL
CRITICAL
DZ5902
DZ5903
ESD0P2RF-02LS
C5933
20%
6.3V
2 X5R
0201-MUR
ESD0P2RF-02LS
TSSLP-2-1
1.0UF
TSSLP-2-1
R5930
JTAG_AP_TCK
36 4
0.00 2
PPVCC_MAIN
0%
1/32W
MF
01005
TABLE_ALT_HEAD
R5991
R5931
1
JTAG_AP_TMS
36 4
100K
0.00 2
5%
1/32W
MF
2 01005
PLACE NEAR U5900
0%
1/32W
MF
01005
R5929
18
OUT
L81_MBUS_REF
C5991
8.2PF
10K
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
155S0773
155S0453
FL5990
TABLE_ALT_ITEM
+/-0.5PF
16V
2 NP0-C0G-CERM
01005
FL5990
120-OHM-210MA
R5990
1
PMU_E75_ACC_DET_R_L
2
01005
5%
1/32W
MF
01005
SM-201
MLB_D&MLB_E
A
0.1UF
10%
2 6.3V
X5R
201
CONN_E75_ACC_DET_L
CRITICAL
IN
24
DZ5990
ESD0P2RF-02LS
+/-0.5PF
16V
2 NP0-C0G-CERM
01005
D5990
C5960
C5990
8.2PF
K CRITICAL
=PP3V2_S2R_USBMUX
0.00 2
0%
1/32W
MF
01005
TRISTAR BASEBAND USB MUX

(NEEDED FOR MDM9600 BB)
34
15 29 30 34 39
TSSLP-2-1
1
DSF01S30SC
MLB_D&MLB_E
R5961
10K
5%
1/20W
MF
2 201
34 25
=PP1V8_S2R_USBMUX
VCC
36 4
36 4
BI
BI
36 25
36 25
USB11_AP_BBMUX_P
USB11_AP_BBMUX_N
5 M+
4 M-
USB_TS_BBMUX_P
USB_TS_BBMUX_N
7 D+
6 D-
TS_BBMUX_EN_L
MLB_D&MLB_E
U5902
1
Y+ 1
Y- 2
USB_BBMUX_BB_P
USB_BBMUX_BB_N
PI3USB102ZLE
25 26 36
BI
25 26 36
0.1UF
MLB_D&MLB_E
R5934
R5962
SEL 10
OE*
PMU_GPIO_BBUSBTODOCK_EN_R
R5960
10K
5%
1/20W
MF
2 201
0.00 2
1
PMU_GPIO_BBUSBTODOCK_EN
0%
1/32W
MF
01005
MLB_D&MLB_E
DEFAULT =>
SEL
Y+
Y-
M+
M-
D+
D-
IN
25
30
IN
TS_HOST_RESET
0.00 2
IN
AP_WDOG_RESET_IN
TS_HOST_RESET_R
0%
1/32W
MF
01005
SOT891
4
PMU_RESET_IN_R
U5903
NOTE: ISOLATE SELECT SIGNAL FROM

PMU ON MLB_B AND MLB_C SO THE MUX
IS PERMANENTLY POINTED TO THE DOCK
PMU_RESET_IN
OUT
30
220K 1
R5933
USB_TS_BBMUX_P
220K 1
MF 5%
1/32W
01005
SYNC_MASTER=N/A
PAGE TITLE
R5965
USB_BBMUX_BB_P
DRAWING NUMBER
Apple Inc.
R
MLB_B&MLB_C
R5966
USB_TS_BBMUX_N
SYNC_DATE=N/A
TRISTAR
25 26 36
5%
1/20W
MF
201
USB_BBMUX_BB_N

25 26 36
5%
1/20W
MF
201
MF 5%
1/32W
01005
MLB_B&MLB_C
36 25
22
5%
1/32W
MF
01005
NC
R5935
1
R5932
BASEBAND USB MUX BYPASS

36 25
74LVC1G32
C5936
10%
2 6.3V
X5R
201
TQFN
GND
1
BI
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
59 OF 154
SHEET
25 OF 39
CELLULAR/GPS HOTBAR PADS

OMIT
998-3732
J6000
HOT-BAR-PADS
DEBUG
HB-SM
BB_JTAG_TMS_RF
34
=BATT_POS_F_3G
C
27
39 30 25 4
5
30
5
39 5
5
36 5
IN
IN
OUT
IN
OUT
IN
36 5
OUT
OUT
IN
IN
OUT
30
OUT
30
IN
36 25
BI
36 25
BI
36 25 5
OUT
36 25 5
IN
36 5
IN
OUT
OUT
36 5
IN
BI
WLAN_TX_BLANK
RST_AP_L
GPIO_BB_RADIO_ON_L
PMU_GPIO_BB_PMU_RST_L
GPIO_BB_GSM_TXBURST
GPIO_BB_RST_L
GPIO_BB_RESET_DET_L
GPIO_BB_HSIC_HOST_RDY
GPIO_BB_HSIC_RESUME
BB_JTAG_TDO_RF
BB_JTAG_TDI_RF
BB_JTAG_TRST_RF_L
GPIO_BB_GPS_SYNC
PMU_GPIO_BB_HOST_WAKE
BB_VBUS_DET
USB_BBMUX_BB_P
USB_BBMUX_BB_N
UART1_BB_RXD
UART1_BB_TXD
UART1_BB_CTS_L
UART1_BB_RTS_L
OUT
GPIO_AP_MODEM_WAKE
36 26 4
BI
HSIC3_BB_STB
36 26 4
BI
HSIC3_BB_DATA
IN
BB_JTAG_TCK_RF
36 5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NOSTUFF
J6050
MM4829-2702
F-ST-SM
36 26 4
HSIC3_BB_STB
4
3
2
IN
NOSTUFF
J6051
MM4829-2702
F-ST-SM
36 26 4
HSIC3_BB_DATA
1
4
3
2
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A
CONNECTOR: CELLULAR
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
60 OF 154
SHEET
26 OF 39
WLAN/BT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN
CONDUCTED TEST PORT
TABLE_5_HEAD
DESCRIPTION
CRITICAL
BOM OPTION
ANTENNA CONNECTOR
TABLE_5_ITEM
339S0171
WIFI MODULE - MURATA
CRITICAL
U6101_RF
CRITICAL
CRITICAL
MM4829-2702
C6193_RF
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
J6190_RF
COMMENTS:
F-ST-SM
TABLE_ALT_ITEM
339S0175
339S0171
U6101_RF
311S0548
311S0398
U6102_RF
CRITICAL
WIFI MODULE - USI
WIFI_50S
50_OHM
RF_ANT_MATCH1
WIFI_50S
50_OHM
2
3
4
+/-0.1PF
50V
NP0-CERM
0402
CRITICAL
CRITICAL
C6191_RF
WIFI_50S
50_OHM
IN
GND
SM
5.6NH+/-0.3NH
WIFI_50S
50_OHM
SHORT-0402
1
2
GND
NOSTUFF
L6191_RF
NOSTUFF
5.6NH-3%-0.35A
0201
5.6NH-3%-0.35A
0201
L6192_RF
39
C6101_RF
10UF
20%
2 6.3V
CERM-X5R
0402-1
BATT_VCC_WLAN
HI 1
LO 3
0402
XW6102_RF
5 COM
RF_CAL_MATCH
+/-0.25PF%
25V
NP0-C0G
0201
DPX205850DT-9038A1SJ
8.2PF
RF_CAL
1
OUT
+/-0.05PF
2 50V
NP0-CERM
0402
L6190_RF
=BATT_VCC
U6104_RF
0.2PF
NOSTUFF
34
CRITICAL
F-ST-SM
C6192_RF
3.9PF
RF_ANT
TABLE_ALT_ITEM
J6191_RF
MM8030-2600RK0
6
4
2
QTY
4
3
PART#
C6102_RF
27PF
5%
2 16V
NP0-C0G
01005
R6108_RF
39
PP_WLAN_VDDIO_1V8
VOLTAGE=1.8V
C6103_RF
0.01UF
NOSTUFF
R6105_RF
R6107_RF
32K INTERFACE TO AP
5%
1/32W
MF
2 01005
XW6101_RF
CLK32K_AP
14
VDDIO_1P8V
SHORT-01005
1
2
WLAN_CLK32K
32
GPIO_6
CRITICAL
14
L6111_RF
IN
WLAN_REG_ON
IN
BT_REG_ON
31
JTAG_SEL
2.5UH-30%-0.7A-0.24OHM
1
6
29
WLAN_BUCK_OUT
27 14
27PF
14 27
VOLTAGE=1.8V
10K
CLK32K_AP
GPIO_6
VIN_1P2LDO
BT_REG_ON
14
JTAG_SEL
WLAN_SR_VLX1
28
SR_VLX
50_HSIC_WLAN_DATA
50_HSIC_WLAN_STROBE
24
25
WLAN_HSIC_DATA
WLAN_HSIC_STROBE
2G_ANT
5G_ANT
8.2PF
42
52
38
38
HOST_WAKE_BT 34
50_WLAN_G
50_WLAN_A
HOST_WAKE_BT
BT_WAKE 39
OUT
14
IN
14
BT_WAKE
LBEE5ZHTWC501
27 14
LGA
BT_UART_RXD
BT_UART_TXD
OMIT_TABLE
BT_UART_RTS*
BT_UART_CTS*
BT_PCM_CLK
BT_PCM_SYNC
BT_PCM_OUT
C6109
BT_PCM_IN
4.7UF
R6109_RF
20%
2 6.3V
X5R-CERM1
402
38
37
35
36
BT_UART_RXD
BT_UART_TXD
BT_UART_RTS_L
BT_UART_CTS_L
NC
40
GPIO_2 10
GPIO_3 12
RF_SW_CTRL_3
GPIO_4 7
NO LONGER NEEDED BASED

ON AND GATE REMOVAL
GPIO_5 11
GPIO_12 13
IN
OUT
14
SDIO_DATA<1>
X
X
0
1
14
6
2 A
27 14
IN
1.00M2
1%
1/32W
MF
01005
WLAN_REG_ON_RC
1
C6110_RF
0.22UF
20%
2 6.3V
X5R
0201
14
14
OUT
14
IN
14
OUT
14 27
IN
14 27
PP PP6101_RF
SM
P4MM
IN
14 27
OUT
14 27
OUT
27
R6111_RF
10K
PULL DOWN RESISTORS
53
54
55
56
57
58
59
60
5%
1/32W
MF
2 01005
27 14
HOST_WAKE_WLAN
PP PP6103_RF
27 14
AP_HSIC3_RDY
PP PP6104_RF
27 14
DEV_HSIC3_RDY
PP PP6105_RF
13FEB2012 AMANDA CHANGED OMIT TO OMIT_TABLE AND UPDATED

BOM OPTION TABLES TO ALTERNATE TABLES
REMOVED BOM TABLE FOR C6111_RF (NOW ALWAYS NOSTUFF)
PP PP6102_RF
P4MM
P4MM
P4MM
P4MM
SM
SM
SM
SM
27 14
WLAN_UART_RXD
PP PP6106_RF
SM
27 14
WLAN_UART_TXD
PP PP6107_RF
SM
P4MM
P4MM
U6102_RF
R6112_RF
WLAN_REG_ON
50_WLAN_A_DIPLX
NC
VCC
74AUP1G08GF
SOT891
Y 4
R6114_RF
DEV_HSIC3_RDY
14 27
27
AGG_CHANNEL
0%
1/32W
MF
01005
1 B
5 NC
0.00 2
AGG_CHANNEL
PP PP6109_RF
SM
27 14
50_HSIC_WLAN_DATA
PP PP6110_RF
SM
27 14
50_HSIC_WLAN_STROBE
PP PP6111_RF
SM
HSIC_DEVICE_RDY
PP PP6112_RF
SM
27
WLAN_TX_BLANK
OUT
26
27
GND
P4MM
SYNC_MASTER=N/A
P4MM
PAGE TITLE
SYNC_DATE=N/A
WIFI/BT
P4MM
DRAWING NUMBER
P4MM
Apple Inc.
38
14
WLAN_REG_ON
27 14
10K
HSIC_DEVICE_RDY
C6111_RF
+/-0.1PF
25V
2 COG-CERM
201
+/-0.1PF
25V
COG-CERM
0201
07FEB2012 MUSHTAQ COPIED FROM N41, ADDED J2 ANT MATCH/CONN

C6107 FROM 20PF TO 8.2PF, C6108 FROM 10PF TO 4.7PF
U6104 FROM SOSHIN TO MURATA LFD212G45DS5D355
R6113_RF
27
50_WLAN_G_1
CHANGE LIST
5%
1/32W
MF
2 01005
38
27
PP_WL_BT_VDDIO_AP
IN
BI
HOST_WAKE_WLAN
AP_HSIC3_RDY
WLAN_HSIC3_RESUME
AGG_CHANNEL
WLAN_UART_RXD
WLAN_UART_TXD
HSIC_DEVICE_RDY
SDIO_DATA<2>
MODE
DEFAULT ARM STATE
X
SDIO
IN RESET
0
GSPI
IN RESET
1
HSIC
OUT OF RESET
1
BOOTLESS HSIC
IN RESET
27 14
BI
NOSTUFF
0.2PF
14
14
+/-0.25PF%
25V
NP0-C0G
0201
4.7PF
1
OUT
IN
BT_PCM_CLK
BT_PCM_SYNC
BT_PCM_OUT
BT_PCM_IN
THRML_PAD
17
18
19
20
21
22
1
16
23
26
33
41
43
44
45
48
49
50
51
GND
GPIO6
0
1
1
1
3
5
2
4
GPIO_0 9
GPIO_1 8
10K
5%
1/32W
MF
2 01005
CRITICAL
C6108_RF
0603
27 14
CRITICAL
C6107_RF
U6101_RF
WL_REG_ON
30
BATT_VCC 27
5%
1/32W
MF
2 01005
VBATT_RF_VCC 46
VBATT_RF_VCC 47
10K
PP_WL_BT_VDDIO_AP
0%
1/32W
MF
01005
C6104_RF
5%
2 16V
NP0-C0G
01005
10%
2 6.3V
X5R
01005
15
0.00 2

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
61 OF 154
SHEET
27 OF 39
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
155S0644
155S0274
REF DES
COMMENTS:
TABLE_ALT_ITEM
FL7500,L3620,L5550,L5730
C
CRITICAL
34
=BATT_POS_CONN
J7500
BATT-J2
TP7500
1
F-RT-SMTH
7
6
TP-P55
NOSTUFF
FL7500
240-OHM-0.2A-0.8-OHM
30 5
30
BI
UART5_BATTERY_TRXD
BI
BATTERY_NTC
BATT_SWI_CONN
NET_SPACING_TYPE=ANLG
C7522
33PF
5%
2 25V
NPO-C0G
0201
NOTE: REMOVED R7541

HAS TP7502
29
1
2
3
4
5
0201
C7523
33PF
5%
25V
2 NPO-C0G
0201
C7524
1000PF
10%
2 16V
X7R-CERM
0201
C7525
82PF
C7526
33PF
5%
5%
25V
2 NP0-C0G-CERM
2 50V
C0G-CERM
0201
0402
C7527
4.7PF
+/-0.1PF
2 50V
C0G-CERM
0402
HDQ
THERM
PACK_NEG
PACK_POS
SENSE
BATT_SNS
APN:516S0926
TP7501
1
A
TP-P55
NOSTUFF
TP7502
1
A
TP-P55
NOSTUFF
TP7503
1
A
TP-P55
NOSTUFF
SYNC_MASTER=MADHAVI
SYNC_DATE=12/06/2011
PAGE TITLE
POWER: BATTERY CONNECTOR

DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
75 OF 154
SHEET
28 OF 39
VCC_MAIN BYPASS
CRITICAL
TOTAL CAPS = ~400UF
CRITICAL
CRITICAL
C8165 1
20%
6.3V 2
TANT-1
B15G
20%
6.3V 2
TANT-1
B15G
150UF
PLACE ONE 10UF CAP

AT EACH VDD INPUT
PPVCC_MAIN
C8166 1
10UF
150UF
ESR MAX=70MOHM
C8154
20%
6.3V
2 X5R
603
CRITICAL
1
CRITICAL
C8155
10UF
CRITICAL
C8156
10UF
20%
2 6.3V
X5R
603
C8157
10UF
20%
2 6.3V
CERM-X5R
0402
CRITICAL
1
C8162
10UF
20%
2 6.3V
CERM-X5R
0402
CRITICAL
1
C8187
10UF
20%
2 6.3V
CERM-X5R
0402
20%
2 6.3V
CERM-X5R
0402
CRITICAL
CRITICAL
1
C8188
10UF
20%
2 6.3V
CERM-X5R
0402
C8193
CRITICAL
1
10UF
C8194
10UF
20%
2 6.3V
CERM-X5R
0402
20%
2 6.3V
X5R
603
CRITICAL
1
CRITICAL
C8130
10UF
C8131
1UF
20%
2 6.3V
CERM-X5R
0402
PLACEMENT_NOTE=PLACE NEAR L8225.1
C8163
L8100
8.2PF
39
BUCK0A_LX0
QTY
CRITICAL
IND,1.0UH,20%,59MO,2.74A
L8100,L8101,L8102,L8103,L8109,L8110
CRITICAL
PPVCC_MAIN_CPU0 29
CRITICAL
1
TABLE_5_ITEM
152S1638
IND,1.0UH,20%,64MO,2.3A
L8104
CRITICAL
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
152S1292
138S0676
138S0654
REF DES
C8159
10UF
20%
2 6.3V
CERM-X5R
0402
TABLE_ALT_HEAD
152S1452
COMMENTS:
CRITICAL
PPVCC_MAIN_CPU1 29
34
C8190
CRITICAL
1
10UF
C8158
10UF
20%
6.3V
2 CERM-X5R
0402
20%
2 6.3V
CERM-X5R
0402
CRITICAL
PPVCC_MAIN_SOC
34
CRITICAL
C8189
10UF
CRITICAL
C8160
10UF
20%
2 6.3V
CERM-X5R
0402
C8161
10UF
20%
6.3V
2 CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
CRITICAL
1
39
C8191
10UF
C8192
10UF
20%
6.3V
2 CERM-X5R
0402
DIDT=TRUE
39
L8102
CRITICAL
L8112
FDMC6676BZ
P-TYPE
RDS(ON)
27 MOHM @-4.5V
IMAX
6.9 A
VGS MAX
+/- 25V
39 34 32
S
4
PMEG4030ER
Q8104
FDMC6683
MLP3.3X3.3
R8172
28
DZ8120
BZT52C10LP
S
G 4
C8124
NOTE: 10V ZENER
5
39 34 29
39 34 29
39 34 29
39 34 29
39 29 18
PMU_VCENTER
VOLTAGE=6V
220K
1%
1/20W
MF
201 2
LAYOUT NOTE: PLACE

RIGHT AT THE PIN
29 25
R8196
OVP_SW_EN_L
4.7K 2 OVP_SW_EN_L_R
NOSTUFF
1%
1/20W
MF
201
C8196
0.022UF
LAYOUT NOTE:
R8196, C8196 CAN BE
ANYWHERE BET.TRISTAR
AND PMU
10%
25V
2 X7R
0402
34 29
34 29
C8133
C8132
4.7UF
CRITICAL
C8149
4.7UF
20%
6.3V
X5R-CERM1 2
402
PP3V0_SENSOR
29 PP3V0_IO
29 PP3V0_S2R_TRISTAR
29 PP2V8_CAM
29 PP1V1_SRAM
29 PP1V8_ALWAYS
CRITICAL
C8148
2.2UF
20%
6.3V
X5R-CERM1 2
402
10%
6.3V 2
X5R
402
10%
35V
2 X5R-CERM
0603
LAYOUT NOTE: PLACE

RIGHT AT THE PIN
34 29
CRITICAL
C8126
4.7UF
10%
35V
2 X5R-CERM
0603
39 34 30 29 25 15
CRITICAL
CRITICAL
4.7UF
C8146
CRITICAL
C8145
1UF
20%
6.3V
X5R-CERM1 2
402
2.2UF
10%
6.3V 2
X5R
402
10%
6.3V 2
X5R
402
CRITICAL
C8144
10UF
20%
6.3V
CERM-X5R 2
0402
PPVCC_MAIN_CPU0
A10
VDD_BUCK0A
B10
A6
VDD_BUCK0B
B6
D1
VDD_BUCK0C
D2
A14
VDD_BUCK2_01
B14
A18
B18 VDD_BUCK2_23
H1
VDD_BUCK3
H2
A2
VDD_BUCK4
B2
A22
VDD_BUCK5
B22
L20 VCC_MAIN_S
N15
N16
VCC_MAIN
N17
N18
PPVCC_MAIN_CPU1
PPVCC_MAIN
PPVCC_MAIN_SOC
CRITICAL
C8147
2.2UF
39 34 30 29 25 15
10%
6.3V 2
X5R
402
PPVCC_MAIN
39 34 29
39 34
34
39 34
39 34
39 34
C8169
0.22UF
20%
6.3V
X5R 2
0201
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C8168
4.7UF
20%
6.3V
X5R-CERM1 2
402
C8167
4.7UF
20%
6.3V
X5R-CERM1 2
402
C8153
2.2UF
10%
6.3V
X5R 2
402
C8152
C8151
4.7UF
10%
6.3V
X5R 2
402
39 34 29
N9
N4
N7
N3
N11
N6
N2
N5
N14
PP1V8_S2R
1
C8135
39 34 30 29 25 15
PPVCC_MAIN
1UF
10%
2 6.3V
CERM
402
NOTE: FOR NO BATTERY SITUATION
39 34 32 29
39 34 29
PPBATT_VCC
NOSTUFF
CRITICAL
1
10UF
10UF
20%
6.3V
2 CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
39
R8100
0.5
1%
1/16W
MF
402 2
C8173
PP1V2_S2R
1
NOSTUFF
CRITICAL
C8174
CRITICAL
1
C8170
10UF
20%
6.3V
2 CERM-X5R
0402-1
BATT_POS_RC
CRITICAL
1
C8171
10UF
20%
6.3V
2 CERM-X5R
0402-1
C8134
1UF
10%
2 6.3V
CERM
402
C8136
1 CAP PER PIN N5 N14
1UF
10%
2 6.3V
CERM
402
NET_SPACING_TYPE=CRYSTAL
39
BUCK0B_LX1
39
20%
6.3V
2 CERM-X5R
0402
N1 XTAL1
PMU_XTAL
PMU_EXTAL P1 XTAL2
NET_SPACING_TYPE=CRYSTAL
CRITICAL
39
18PF
5%
25V
NP0-C0G 2
201
39
BUCK0C_LX0
2012-1
C8143
18PF
5%
25V
2 NP0-C0G
201
PART NUMBER
C8123
22UF
NOSTUFF
CRITICAL
C8183
10UF
C8185
10UF
20%
6.3V
2 CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
PP1V1_CPUB
2
PSB25201E-SM
CRITICAL
NOSTUFF
XW8102
BUCK0C_FB
C8104
22UF
C8105
22UF
20%
20%
6.3V
6.3V
2 X5R-CERM-1 2 X5R-CERM-1
603
603
SM
CRITICAL
1
39
BUCK2_LX0
39
BUCK2_LX1
DIDT=TRUE
ADDITIONAL DISTRIBUTED
98UF (NO DERATING)
39
PILE32251E-SM
CRITICAL
39
L8106
BUCK3_FB
39
BUCK4_LX0
39
BUCK4_FB
39
BUCK5_LX0
CRITICAL
LDO5
LDO10
C8118
22UF
CRITICAL
C8119
20%
6.3V
2 X5R-CERM-1
603
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
L8109
DIDT=TRUE
OMIT_TABLE
27UF (NO DERATING)
1.0UH-20%-2.74A-59MOHM
PP1V8_S2R
2
PSB32251E-SM
NOSTUFF
XW8104
CRITICAL
1
C8110
22UF
20%
20%
6.3V
2 6.3V
X5R-CERM-1 2 X5R-CERM-1
603
603
CRITICAL
39
C8109
L8110 OMIT_TABLE
64UF (NO DERATING)
1.0UH-20%-2.74A-59MOHM
39
29 34 39
PP1V2_S2R
2
PSB32251E-SM
NOSTUFF
XW8105
29 34
29 34 39
29 34 39
22UF
C8112
22UF
20%
20%
6.3V
2 6.3V
603
603
CRITICAL
29 34 39
C8111
L8111
32UF (NO DERATING)
2.2UH-20%-3.3A-0.064OHM
29 34 39
29 34 39
PP3V3_OUT
2
PIME051E-SM
CRITICAL
1
NOSTUFF
XW8106
(RON=0.05 OHM MAX)
29 34 39
CRITICAL
CRITICAL
1
SM
29 34 39
29 34 39
CRITICAL
22UF
SM
18 29 39
PP2V8_CAM
PP1V0
PP1V1_SRAM
PP1V8_ALWAYS
SM
29 39
PP3V3_ACC
PP3V0_S2R_TRISTAR
PP3V0_S2R_HALL
PP3V0_IO
20%
2 6.3V
X5R-CERM-1
603
DIDT=TRUE
(50MA; 2.5-3.3V)
(100MA; 1.8-3.3V)
(300MA; 1.7-3.0V)
(150MA; 2.5-3.6V)
(50MA; 1.2-3.1V)
(15MA; 2.0-3.55V)
(300MA; 1.2-3.0V)
(200MA; 2.5-3.55V)
(250MA; 1.7-3.0V)
(150MA; 0.6-1.3V)
(650MA; 1.1V)
(5MA; 1.8V)
22UF
CRITICAL
C8117
20%
6.3V
2 X5R-CERM-1
603
NOSTUFF
XW8103
BUCK5_FB
PP3V0_GRAPE 29 34 39
PP1V7_VA_VCP 19 29 34 39
PP3V2_S2R_USBMUX 29 34
PP3V0_SENSOR
29 34
C8195
20%
2 6.3V
X5R-CERM-1
603
22UF
(150MA; 1.2-3.1V)
C8108
22UF
CRITICAL
1
PILE32251E-SM
DIDT=TRUE
(PP3V3_OUT)
(100MA; 1.65-1.805V; BUCK3)
22UF
L8107
BUCK3_LX0
C8107
34 39
CRITICAL
1.0UH-20%-3.9A-0.035OHM
1
BUCK2_FB
CRITICAL
20%
2 6.3V
X5R-CERM-1
603
PILE32251E-SM
BUCK2_LX2
39
39
CRITICAL
1.0UH-20%-3.9A-0.035OHM
DIDT=TRUE
39
PP1V2_SOC
DIDT=TRUE
34 39
DISTRIBUTED
CRITICAL ADDITIONAL
12UF (NO DERATING)
L8105
A21
BUCK5_LX0
B21
A23
BUCK5_BYP
B23
BUCK5_FB E18
C8113
22UF
34 39
CRITICAL
C8114
22UF
20%
20%
6.3V
2 6.3V
603
603
(RON=0.05 OHM MAX)
PP1V2_S2R
29 34 39
(RON=0.2 OHM MAX)
PMU_VPUMP
VOLTAGE=4.6V
PP1V2
34 39
PP1V8_S2R
29 34 39
PP1V8
32 34 39
TP_PP1V8_GRAPE
C8137
0.01UF
SYNC_MASTER=MADHAVI
10%
10V
2 X5R-CERM
0201
BOM OPTION
C8122
30 39
CRITICAL
22UF
1.0UH-20%-3.9A-0.035OHM
A3
BUCK4_LX0
B3
BUCK4_FB D4
ALTERNATE FOR
PART NUMBER
CRITICAL
C8182
20%
6.3V
2 CERM-X5R
0402
OMIT_TABLE
REF DES
C8138
1UF
TABLE_ALT_HEAD
CRITICAL
C8103
22UF
10UF
SM
DIDT=TRUE
Y8138
1
CRITICAL
1
L8104
G1
BUCK3_LX0
G2
BUCK3_FB H5
VPUMP K3
C8102
CRITICAL
1.0UH-20%-2.3A-64MOHM
A13
BUCK2_LX0
B13
A15
BUCK2_LX1
B15
A17
BUCK2_LX2
B17
A19
NC
BUCK2_LX3
B19
NC
BUCK2_FB E15
VBUCK3 K2
CPU1V8_SW J1
CPU1V8_SW J2
WDIG_SW K1
20%
20%
20%
20%
6.3V
6.3V
6.3V
6.3V
2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1
603
603
603
603
CRITICAL
E1
E2
BUCK0C_FB F5
VBUCK4 M2
CPU1V2_SW L1
CPU1V2_SW L2
NOSTUFF
CRITICAL
22UF
NOSTUFF
XW8101
BUCK0B_FB
BUCK0C_LX0
P9
P4
N8
P2
P8
P10
P3
M6
P11
P6
M1
P5
P14
M16
C8184
10UF
20%
6.3V
2 CERM-X5R
0402
PSB32251E-SM
A5
BUCK0B_LX0
B5
A7
BUCK0B_LX1
B7
BUCK0B_FB E6
VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6
VLDO7
VLDO8
VLDO9
VLDO10
VLDO11
VLDO12
VLDO16
ON_BUF
DIDT=TRUE
A9
BUCK0A_LX0
B9
A11
BUCK0A_LX1
B11
BUCK0A_FB E11
32.768K-20PPM-12.5PF
C8142
VDD_LDO1_6
VDD_LDO2
VDD_LDO3_5_8
VDD_LDO4_7
VDD_LDO9
VDD_LDO10
VDD_LDO11
VDD_LDO12
VDD_LDO16
36
36
CRITICAL
VOLTAGE=4.6V
OMIT_TABLE
SM
2.2UF
20%
6.3V
X5R-CERM1 2
402
D2018
FCBGA
SYM 2 OF 3
E20
E21
F19
F20
F21
G19
G20
G21
VBUS
H19
H20
H21
J19
J20
J21
K20
K21
E19
K19
L23 VBUS_OVP_OFF
CRITICAL
C8125
4.7UF
LDO5
LDO10
39 29
499
1%
1/20W
MF
2 201
CRITICAL
PP1V7_VA_VCP
PP3V2_S2R_USBMUX
PP3V0_S2R_HALL
PP1V0
PP3V3_ACC
39 34 29 19
PPVBUS_USB
LDO BYPASS
PP3V0_GRAPE
R8173
10%
2 25V
X7R
0402
SHORT-0201
2
1
2.2UF
USB REVERSE VOLTAGE PROTECTION

39 34 29
0.022UF
10%
25V
X5R-CERM 2
805
R81301
PPVBUS_USB_DCIN
34
C8172
NOSTUFF
XW8114
CRITICAL
VBUS_PROT_G
D
VOLTAGE=6V
VOLTAGE=6.0V
LLP
MLP3.3X3.3
BATT_SNS_R
NOSTUFF
LAYOUT NOTE R3172- PLACE NEAR BMU

C3172- PLACE NEAR PMU
R3173- PLACE NEAR PMU
FDMC6676BZ
5%
1/20W
MF
201
PPVBUS_PROT
CRITICAL
3
2
1
Q8123
1%
1/20W
MF
201 2
BATT_SNS
CRITICAL
470K
ACT_DIO
25
NOSTUFF
F22
F23
G22
G23
CHG_LX
H22
H23
J22
J23
M14 VBAT
M17 IBAT_S
P15
P16
P17 IBAT
P18
M18 ACT_DIO
E22
E23
VCENTER
K22
K23
PPBATT_VCC
29
CRITICAL
D8100
SOD-123W
R81161
CRITICAL
DCR=32MOHM MAX
U8100
USB/BAT
BUCK
5%
1/20W
MF
201
CHANNEL
10UF
CRITICAL
CRITICAL
L8103
LDO
PIME101E-SM
4.7K 2
MOSFET
PP1V1_CPU1_FET
2
PSB32251E-SM
1.0UH-20%-2.74A-59MOHM
VCC-MAIN
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
C8121
OMIT_TABLE
OMIT_TABLE
SW_CHGA
LDO INPUT
SWITCH POWER
OVP_SW_EN_L
BUCK0B_LX0
DIDT=TRUE
XTAL
R8170
39
2.2UH-20%-4A-32MOHM
PPVCC_MAIN
RDSON=0.0136@VGS=-2.5V
ID=12.0A
29 25
39 34 30 29 25 15
NOSTUFF
CRITICAL
C8181
1.0UH-20%-2.74A-59MOHM
TABLE_ALT_ITEM
C8100,C8101,C8102,C8103,C8104,C8105,C8107,C8108,C8109,C8110,C8111,C8112,C8113,C8114,C8117,C8118,C8119,C8120,C8121,C8222,C8123,C8195
30 39
CRITICAL
CRITICAL
NOSTUFF
20%
6.3V
2 CERM-X5R
0402
SM
TABLE_ALT_ITEM
L8111
C8120
22UF
CRITICAL
C8180
10UF
20%
6.3V
2 CERM-X5R
0402
NOSTUFF
XW8100
C8101
22UF
CRITICAL
PSB32251E-SM
BUCK0A_FB
C8100
22UF
CRITICAL
BUCK0A_LX1
29 34
CRITICAL
NOSTUFF
CRITICAL
CRITICAL
1
22UF
20%
20%
20%
20%
6.3V
6.3V
6.3V
2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1 2 6.3V
X5R-CERM-1
603
603
603
603
PSB32251E-SM
1.0UH-20%-2.74A-59MOHM
BOM OPTION
TABLE_5_ITEM
152S1637
CRITICAL
1
L8101 OMIT_TABLE
ESR MAX=70MOHM
DESCRIPTION
DIDT=TRUE
TABLE_5_HEAD
PART#
OMIT_TABLE
1.0UH-20%-2.74A-59MOHM
C8164
82PF
+/-0.1PF%
5%
25V
25V
2 NP0-C0G-CERM2 CER
0201
0201
20%
2 6.3V
X5R
0201
1
PP1V1_CPU0_FET
CRITICAL
15 25 29 30 34 39
COMMENTS:
20%
2 6.3V
X5R
0201
C8140
1UF
10%
2 6.3V
CERM
402
C8139
1UF
10%
2 6.3V
CERM
402
C8141
PAGE TITLE
1UF
10%
2 6.3V
CERM
402
PMU: ADRIANA PAGE 1

DRAWING NUMBER
Apple Inc.
R
051-9385
128S0339
128S0279
C8165,C8166
197S0392
Y8138

TABLE_ALT_ITEM

A.0.0
TABLE_ALT_ITEM
197S0399
SIZE
REVISION
BRANCH
PAGE
81 OF 154
SHEET
29 OF 39
R8281
NOSTUFF
1%
1/20W
MF
201
(TEMP1
(TEMP2
(TEMP3
(TEMP4
CRITICAL
R8218
CRITICAL
R8222
0201
10KOHM-1%-0.31MA
100PF
XW8201
1
2
BOARD_TEMP8_N
37
H5G)
PMU)
I/O FLEX CONN)
WIFI)
C8223
37 32
XW8202
1
2
BOARD_TEMP3_N
NOSTUFF
PLACE XW AND CAP

CLOSE TO PMU
PLACE XW AND CAP

CLOSE TO PMU
C8220
XW8203
1
2
BOARD_TEMP4_N
SM
2
1
3.92K
0.1%
100PF
402
1/16W
1 MF
5%
6.3V
CERM 2
01005
SM
NOSTUFF
PLACE XW AND CAP
CLOSE TO PMU
R8219
=PPVCC_MAIN_LED
C8226
DCR=106MOHM MAX
SOD-323
37 15
20%
10V
X5R 2
0603-1
OUT
LED_IO_1_A
37 15
CRITICAL
CRITICAL
C8232
4.7UF
CRITICAL
C8233
4.7UF
C8234
CRITICAL
1
4.7UF
10%
35V
2 X5R-CERM
0603
10%
35V
2 X5R-CERM
0603
OUT
LED_IO_2_A
C8235
37 15
OUT
10%
35V
2 X5R-CERM
0603
1.00
1%
1/20W
MF
201
LED_IO_3_A
4.7UF
10%
35V
2 X5R-CERM
0603
39 26 25 4
OUT
OUT
36 25 19 5
IN
36 25 19 5
BI
37 15
OUT
OUT
LED_IO_4_A
1.00
1%
1/20W
MF
201
LED_IO_5_A
OUT
LED_IO_6_A
DCR=106MOHM MAX
4.7UF
C8263
4.7UF
SOD-323
10%
2 35V
X5R-CERM
0603
10%
2 35V
X5R-CERM
0603
CRITICAL
1
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
D5
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
G4 RESET_IN
F4 RESET*
H4 IRQ*
AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_AY
AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_BY
A1 DWI_CK
B1 DWI_DI
C2 DWI_DO
PMU_IREF
PMU_VREF
PMU_VDD_REF
0.1UF
C8209
37
37
37
2
DIDT=TRUE
37
37
R8239
1
LED_IO1_A_R
LED_IO2_A_R
LED_IO3_A_R
LED_IO4_A_R
LED_IO5_A_R
LED_IO6_A_R
1.00
37
37
1%
1/20W
MF
201
37
37
LED_IO1_B_R
LED_IO2_B_R
LED_IO3_B_R
LED_IO4_B_R
LED_IO5_B_R
LED_IO6_B_R
N21
P21
K16
K5
K6
K7
K8
M9
K9
N23
P23
K17
K10
M11
K11
K12
M12
K13
WLED_LXA
VOUT_WLED_A
WLED1_A
WLED2_A
WLED3_A
WLED4_A
WLED5_A
WLED6_A
WLED_LXB
VOUT_WLED_B
WLED1_B
WLED2_B
WLED3_B
WLED4_B
WLED5_B
WLED6_B
VDD_LCM_SW
39
VDD_BOOST_LCM
39
BOOST_LCM_LX
39
VDD_LCM
LCM2_EN
LCM_FB
VLCM1
VLCM2
VLCM3
C8264
4.7UF
37 15
10%
2 35V
X5R-CERM
0603
CRITICAL
1
1UF
10%
2 6.3V
X5R
201
20%
2 6.3V
X5R
0201
PMU_VDD_RTC
PMU_ADC_REF
PMU_GPIO_BT_REG_ON
PMU_GPIO_WLAN_REG_ON
PMU_GPIO_BB_PMU_RST_L
UART5_BATTERY_TRXD
PMU_GPIO_BT_HOST_WAKE
PMU_GPIO_WLAN_HOST_WAKE
PMU_GPIO_BB_HOST_WAKE
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_BBUSBTODOCK_EN
PMU_GPIO_TS_INT
PMU_GPIO_HALL2_IRQ
PMU_GPIO_CODEC_RST_L
PMU_GPIO_HALL_IRQ
NC_PMU_GPIO16 NO_TEST=TRUE
PMU_GPIO_BB_VBUS_DET 30
OUT
17 36
OUT
14 36
OUT
14
OUT
14
OUT
26
IN
5 28
IN
14
IN
14
IN
26
IN
18
OUT
25
IN
5 25
IN
23
OUT
18
IN
22
USED BY Z2
(1.8_S2R PUSH-PULL)
(1.8_S2R;NO PD REQD PER BB TEAM)
(1.8_S2R;NO PD REQD PER BB TEAM)
BB_VBUS_DET STUFFING OPTION

SELECTING GPIO OPTION BY DEFAULT
REMOVE STUFFING RES AND WIRE DIRECTLY FOR PRODUCTION
R8297
CPU1_SWITCH
CPU1_SW_G
CPU1_SW_S
OUT
LED_IO_1_B
OUT
LED_IO_2_B
37 15
C8265
OUT
1.00
1%
1/20W
MF
201
NOSTUFF
CRITICAL
(NOTE: 2MHZ)
2.2UH-1.05A-0.195OHM
1
30
C8236
2.2UF
20%
10V
X5R-CERM 2
402
C8237
10UF
LED_IO_3_B
10%
35V
2 X5R-CERM
0603
37 15
37 15
OUT
OUT
LED_IO_4_B
1.00
1%
1/20W
MF
201
LED_IO_5_B
OUT
LED_IO_6_B
1.00
0.01UF
10%
50V
X7R 2
402
C8266
R8269
1
1.00
C8239
A2
C8238
C8251
1%
1/20W
MF
201
0.01UF
10%
50V 2
X7R
402
1%
1/20W
MF
201
Q8200
BGA
ALTERNATE FOR
PART NUMBER
BOM OPTION
107S0150
107S0208
REF DES
R8292
NC_PMU_DP_HPD
NO_TEST=TRUE
NOSTUFF
R8290
1M
C8290
0.1UF
10%
2 16V
X5R-CERM
0201
39 34
CPU0_SW_G_R
1M
5%
1/20W
MF
2 201
C8291
PP1V1_CPU0
1
Q8201
XW8290
CSD58874W1015
BGA
SM
PP1V1_CPU1_FET
A1
NOSTUFF
29
39
B1
C1
CPU1_SW_G_R
A2
B2
G
S
C2
0.1UF
Q8203
10%
2 16V
X5R-CERM
0201
CSD58874W1015
BGA
B1
C1
PP1V1_CPU1
30 34 39
30
0.01UF
CPU1_SW_S
PLACEMENT_NOTE=PLACE NEAR U8100.K17

10%
50V
PLACEMENT_NOTE=PLACE
NEAR U8100.K17
X7R 2
402
A2
G
S
B2
XW8291
C2
SM
NOSTUFF
SYNC_MASTER=MADHAVI
PAGE TITLE
PMU: ADRIANA PAGE 2

DRAWING NUMBER
Apple Inc.
R
TABLE_ALT_ITEM

A1
COMMENTS:
C2
5%
1/20W
MF
201
NOSTUFF
1
A2
B2
CPU0_SW_S
29 39
PP1V1_CPU0_FET
B1
C1
5%
1/20W
MF
201
NOSTUFF
1
NOSTUFF
R8291
30 34 39
R8216,R8218,R8222,R8280,R8281,R8282
A1
TABLE_ALT_HEAD
PART NUMBER
C2
10%
2 10V
X5R
402
402
C8267
B1
B2
1UF
10%
2 10V
X5R
402
30
PLACEMENT_NOTE=PLACE
NEAR U8100.K16
X7R 2
PPLED_OUT_B
A1
CSD58874W1015
PLACEMENT_NOTE=PLACE NEAR U8100.K16
10%
50V
BGA
NOSTUFF
0.01UF
Q8202
CSD58874W1015
30
39 34
R8270
37 15
C1
VLCM3
NOSTUFF
C8201
0%
1/32W
MF
01005
MAKE_BASE=TRUE
VOLTAGE=6.0V
R8293
26
0.00 2
SOD882
1%
1/20W
MF
201
R8265
4.7UF
1.00
OUT
PMEG2005AEL
R8262
1
C
BB_VBUS_DET
D8230
DIDT=TRUE
1UF
20%
2 25V
X5R-CERM
0603
NOSTUFF
CRITICAL
VLS201612E-SM
NOSTUFF
VLCM3
30
L8229
5%
1/20W
MF
2 201
PPLED_OUT_A
0.00 2
NOSTUFF
1%
1/20W
MF
201
R8296
NOSTUFF
CPUB_EN L22
CPUB_SW_G J3
CPUB_SW_S K4
PMU_GPIO_BB_VBUS_DET
0%
1/32W
MF
01005
NC
CPU0_SWITCH
CPU0_SW_G
CPU0_SW_S
1000PF
10%
6.3V
2 X5R-CERM
01005
NEED RADAR TO STOP GENERATING 32K CLOCK
VOLTAGE=6.0V
N19 PPVCC_MAIN
15 25 29 34 39
P19 PP6V0_LCM_HI
P20 LCM_LX
N13 PP6V0_LCM_VBOOST
F3 TP_LCM2_EN
(INTERNAL PULLDOWN; TE ENABLE)
M20
P13 NC_VLCM1
NO_TEST=TRUE
P12 NC_VLCM2
NO_TEST=TRUE
N12
CPUA_EN M23
CPUA_SW_G J5
CPUA_SW_S J4
C8214
(2.5V ALWAYS ON PU IN BMU)

(INTERNAL PD)
(INTERNAL PD)
(INTERNAL PD; CANT BE USED FOR 32K CLK OUTPUT)
(INTERNAL PU TO PP1V8_S2R)
30
I2C ADDRESS: 0111100X (0X78)
1.00
PLACEMENT NOTE: PLACE NEAR PIN K24
C21
NC
C22
NC
E17
NC
E14
NC
C23
NC
D21
NC
D22
NC
D19
NC
E13
NC
D23
DPHP E4
C8210
0.22UF
10%
2 6.3V
CERM
402
R8257
37 15
C8262
DIDT=TRUE
1%
1/20W
MF
201
PPLED_OUT_B
1
OUT
37
1.00
R8261
CRITICAL
36 5
(INTERNAL PULL-DOWN)
M7
P7
K18
M15
N10
M10
30
20%
10V 2
X5R
0603-1
CRITICAL
IN
TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TDEV6
TDEV7
TDEV8
TBAT
TCAL
IREF
VREF
VDD_REF
VDD_REF_A
VDD_RTC
ADC_REF
(PPLED_OUT_B)
10UF
39 34 30
PMEG4010BEA
2
PIME051E-SM
1.00
1.00
D8258
4.7UH-3.2A
C8256
36 5
DWI_AP_CLK
DWI_AP_DO
DWI_AP_DI
37
CRITICAL
L8255
CRITICAL
IN
1%
1/20W
MF
201
WLED_LX_B
CRITICAL
=PPVCC_MAIN_LED
36 5
L19
K15
K14
M13
M5
M4
L3
M3
L21
M22
E7 SCL
E9 SDA
I2C0_SCL_1V8
I2C0_SDA_1V8
R8232
R8240
34 30
IN
ACC_ID
BRICK_ID
ADC_IN7
ADC_IN31
PMU_RESET_IN (INTERNAL PULL-DOWN)

RST_AP_L
(PULLUP INSIDE H5G)
GPIO_PMU_IRQ_L
37
R8235
37 15
37 15
IN
25
1%
1/20W
MF
201
R8231
PPLED_OUT_A
1
32
M8
M21
L4
L5
E10 KEEPACT
GPIO_PMU_KEEPACT
(INTERNAL PULL-DOWN) H3 SHDN
PMU_SHDWN
(PPLED_OUT_A)
R8227
10UF
39 34 30
IN
WLED_LX_A
PMEG4010BEA
PIME051E-SM
CRITICAL
FW_DPHP_DET
BUTTON1
BUTTON2
BUTTON3
ACC_DET
MAKE_BASE=TRUE
D8228
4.7UH-3.2A
C8212
PLACEMENT NOTE: PLACE NEAR PIN K4
FCBGA
SYM 1 OF 3
CRITICAL
L8225
34 30
IN
CRITICAL
DWI NAMING RELATIVE TO AP
CRITICAL
28
RESISTOR FOR TEMP CALIBRATION
10KOHM-1%-0.31MA
BOARD_TEMP1
BOARD_TEMP2
37 BOARD_TEMP3_P
37 BOARD_TEMP4_P
30 BOARD_TEMP5_P
30 BOARD_TEMP6_P
37 BOARD_TEMP7_P
37 BOARD_TEMP8_P
BATTERY_NTC
PMU_TCAL
37 32
CRITICAL
R8280
5%
6.3V
CERM 2
01005 37
SM
NOSTUFF
100PF
NOSTUFF
SM
PLACE XW AND CAP

CLOSE TO PMU
NEAR
NEAR
NEAR
NEAR
37
0201
5%
6.3V
CERM 2
01005
XW8200
1
2
BOARD_TEMP7_N
37
R8216
100PF
37
SIDE
SIDE
SIDE
SIDE
37
10KOHM-1%-0.31MA
C8217
5%
6.3V
CERM 2
01005
BOTTOM
BOTTOM
BOTTOM
BOTTOM
0201
CRITICAL
0201
10KOHM-1%-0.31MA
C8221
5%
6.3V 2
CERM
01005
PMU_ACC_ID
PMU_USB_BRICKID_R
ADC_IN7
6.34K2
1
PMU_USB_BRICKID
IN
10
100PF
IN
M19
NC_FW_ZENER_PWR
NO_TEST=TRUE
C3
D3
E3
C1
R8299
PLACE XW AND CAP

CLOSE TO PMU
C8215
IN
25
1%
1/20W
MF
2 201
U8100
GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
PMU_E75_ACC_DET_L
PLACE XW AND CAP

CLOSE TO PMU
SM
IN
20 5
200K
0.1UF
D2018
DIGITAL
INPUT
REFERENCES
37
20 5
OMIT_TABLE
10%
6.3V
2 X5R
01005
R8203
C8204
10%
6.3V
2 X5R
201
ANALOG
INPUT
SM
NOSTUFF
IN
0.01UF
10%
6.3V
2 X5R
01005
LCM/GRAPE
37
23 5
C8207
TEMPERATURE
GPIO
XW8282
1
2
BOARD_TEMP6_N
XW8281
1
2
BOARD_TEMP5_N
0.01UF
10%
6.3V
2 X5R
01005
SENSOR LOCATIONS TBD

LOCATION DESCRIPTIONS ARE FROM J2
LED BACKLIGHT
5%
6.3V 2
CERM
01005
C8206
0.01UF
0201
100PF
C8292
WDOG
RESET
I2C & DWI
ANALOG MUX
10KOHM-1%-0.31MA
37
0201
C8282
37
10KOHM-1%-0.31MA
5%
6.3V
CERM 2
01005
CRITICAL
R8282
100PF
BOARD_TEMP5_P 30
BOARD_TEMP6_P 30
CRITICAL
(TEMP5 - TOP SIDE NEAR NAND)

(TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX)
C8281
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
82 OF 154
SHEET
30 OF 39
OMIT_TABLE
U8100
D2018
FCBGA
SYM 3 OF 3
C4
D20
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
G3
G5
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
VSS/VSS_BUCK0A0B
VSS/VSS_BUCK0A2
VSS/VSS_BUCK0B4
VSS/VSS_BUCK0C3
VSS/VSS_BUCK25
A16
B16
A20
B20
VSS/VSSA_BUCK0A
VSS/VSSA_BUCK0B
VSS/VSSA_BUCK0C
VSS/VSSA_BUCK2
VSS/VSSA_BUCK3
VSS/VSSA_BUCK4
VSS/VSSA_BUCK5
E12
E8
G6
E16
H6
E5
F18
VSS/VSS_BUCK2_01
VSS
A8
B8
A12
B12
A4
B4
F1
F2
ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS
VSS_WLED N22
VSS_WLED P22
VSS_LCM N20
VSS
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
SYNC_MASTER=MADHAVI
PAGE TITLE
PMU: ADRIANA PAGE 3

DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
83 OF 154
SHEET
31 OF 39
DEBUG RESET ACCESS

34 5
=PP1V8_S2R_MISC
39 34 29
PPBATT_VCC
NOSTUFF
1
R9000
300
OUT
NOSTUFF
39 34 32 29
R9002
5%
1/20W
MF
2 201
PP1V8
1.5K
NOSTUFF
1%
1/20W
MF
2 201
R9001
300
5%
1/20W
MF
2 201
GPIO_FORCE_DFU
PWR_ON_LED
A
30
NOSTUFF
OUT
PMU_SHDWN
LED9000
RED-50MCD-20MA
0603
SOCHOT TO PMU TDEV1/TDEV2

39 34 32 29
PP1V8
R9020
R9010
SOCHOT1_TDEV1
R9011
100K
100K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
CRITICAL
BOARD_TEMP1
1%
1/32W
MF
01005
D
SOCHOT1
470
30 37
R9021
10K
1%
1/32W
MF
2 01005
Q9020
1 G
OUT
DMN26D0UFB4
DFN
SYM_VER_1
CRITICAL
D
7
IN
SOCHOT1_L
Q9010
1 G
DMN26D0UFB4
R9030
DFN
SOCHOT1_TDEV2
SYM_VER_1
CRITICAL
Q9030
S
470
1%
1/32W
MF
01005
1 G
DMN26D0UFB4
DFN
BOARD_TEMP2
OUT
30 37
R9031
10K
1%
1/32W
MF
2 01005
SYM_VER_1
SYNC_MASTER=MLB
PAGE TITLE
DEBUG/MISC.
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
90 OF 154
SHEET
32 OF 39
PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM
SL4210
TH-NSP
FID4200
FID
0P5SM1P0SQ-NSP
1
SL-1.1X0.4-1.4X0.7
FID4201
FID
SL4201
TH-NSP
0P5SM1P0SQ-NSP
1
FID4202
SL-1.1X0.4-1.4X0.7
FID
0P5SM1P0SQ-NSP
1
SL4212
TH-NSP
FID4203
FID
0P5SM1P0SQ-NSP
SL-1.1X0.4-1.4X0.7
FID4204
FID
SL4213
TH-NSP
0P5SM1P0SQ-NSP
1
FID4205
SL-1.1X0.4-1.4X0.7
FID
0P5SM1P0SQ-NSP
1
SL4214
TH-NSP
SL4204
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
SL4215
TH-NSP
SL4205
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
SL4216
TH-NSP
SL4206
TH-NSP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
SYNC_MASTER=N/A
SYNC_DATE=N/A
PAGE TITLE
TEST/HOLES/FIDUCUALS
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
93 OF 154
SHEET
33 OF 39
POWER CONNECTIONS
BUCK5
BUCK0A
PP1V1_CPU0
39 30
=PPVDD_CPU0_H5
PP3V3_OUT
39 29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=3.3V
VOLTAGE=1.1V
BUCK0B
39 30
PP1V1_CPU1
=PP3V3_NAND
=PP3V3_USB_H5
=PP3V3_LCD
39 30 29 25 15
=PPVDD_CPU1_H5
39 29
PP3V0_IO
=PP3V0_VDDIO30_H5
MAKE_BASE=TRUE
39 30
PPLED_OUT_A
=PPLED_REG_A
15
=PPLED_REG_B
15
VOLTAGE=20.4V
BUCK0C
39 30
PPLED_OUT_B
=PPVDD_CPUB_H5
=PP2V8_CAM
39 29
39 32 29
=PPVDD_SOC_H5
VOLTAGE=1.2V
PP3V0_GRAPE
LDO12
=PP3V0_GRAPE
VOLTAGE=3.0V
PP1V8_S2R
=PP3V0_GRAPE_MARIO1
16
39 29
PP1V0
=PP1V0_MIPI_H5
MAKE_BASE=TRUE
=PP3V0_GRAPE_Z1
=PP3V0_GRAPE_Z2
VOLTAGE=1.0V
17
17
PP1V7_VA_VCP
39 29 19
=PP1V7_VA_VCP
VOLTAGE=1.7V
5 32
VDDIO_WLAN_BT_1V8
14
=PP1V8_S2R_USBMUX
25
=PP1V8_S2R_DDR
11 12
28
=BATT_POS_F_3G
26
CELLULAR RADIO
=BATT_VCC
27
WLAN
=PP1V0_DP_PAD_DVDD_H5
=PP1V0_EDP_PAD_DVDD_H5
=PP1V0_USB_H5
=PP1V0_HSIC_H5
7
39 23
PPVBUS_USB_EMI
PPVBUS_USB_DCIN
29
MAKE_BASE=TRUE
VOLTAGE=6V
4
4
7
LDO16
18 19
MAKE_BASE=TRUE
=PP1V8_S2R_MISC
=BATT_POS_CONN
=PP1V0_MIPI_PLL_H5
39 29
PP1V1_SRAM
=PPVDD_SRAM_H5
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=1.8V
29
USB POWER INPUT
16 17
LDO2
BUCK3
PPBATT_VCC
VOLTAGE=4.2V
MAKE_BASE=TRUE
MAKE_BASE=TRUE
39 29
29
MAKE_BASE=TRUE
LDO1
PP1V2_SOC
29
BATTERY
21
VOLTAGE=2.8V
VOLTAGE=20.4V
MAKE_BASE=TRUE
PP2V8_CAM
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=1.1V
39 29
PPVCC_MAIN_CPU0
PPVCC_MAIN_CPU1
PPVCC_MAIN_SOC
18 19
30
LDO11
MAKE_BASE=TRUE
39 29
BUCK2
=PPVCC_MAIN_AUDIO
=PPVCC_MAIN_LED
VOLTAGE=4.7V
VOLTAGE=3.0V
MAKE_BASE=TRUE
PP1V1_CPUB
PPVCC_MAIN
MAKE_BASE=TRUE
15
BACKLIGHT BOOST
VOLTAGE=1.1V
39 29
CHARGER MAIN
LDO9
13
VOLTAGE=1.1V
LDO3 (NO LONGER NEEDED)

39 29
PP3V2_S2R_USBMUX
=PP3V2_S2R_USBMUX
25
MAKE_BASE=TRUE
VOLTAGE=3.0V
BUCK4
39 29
PP1V2_S2R
39 29
LDO4
=PP1V2_S2R_H5
=PP1V2_S2R_DDR
11 12
MAKE_BASE=TRUE
VOLTAGE=1.2V
39 29
MAKE_BASE=TRUE
VOLTAGE=1.8V
MAX_NECK_LENGTH=3MM
PP3V0_SENSOR
=PP3V0_SENSOR
21
MAKE_BASE=TRUE
LDO6
CPU1V8_SW
PP1V8
=PP1V8_ALWAYS
VOLTAGE=3.0V
BUCK3_SW
32 29
39
PP1V8_ALWAYS
MAKE_BASE=TRUE
VOLTAGE=1.8V
=PP1V8_SENSOR
=PP1V8_AUDIO
21
18
=PP1V8_VDDIO18_H5
=PP1V8_H5
=PP1V8_MIPI_H5
=PP1V8_DP_H5
=PP1V8_EDP_H5
=PP1V8_NAND_H5
=PP1V8_NAND
=PP1V8_PLL_H5
=PP1V8_MISC
4 6 7 9
39 29
PP3V3_ACC
=PP3V3_ACC
25
MAKE_BASE=TRUE
VOLTAGE=3.3V
4 5 7 10
7
7
7
6 9
13
4
LDO7
16
29
PP3V0_S2R_TRISTAR
=PP3V0_S2R_TRISTAR
25
MAKE_BASE=TRUE
VOLTAGE=3.0V
BUCK4_SW
SYNC_MASTER=N/A
PAGE TITLE
CPU1V2_SW
39 29
PP1V2
MAKE_BASE=TRUE
VOLTAGE=1.2V
=PP1V2_VDDQ_DDR
=PP1V2_VDDIOD_H5
=PP1V2_HSIC_H5
LDO8
11 12
8 9
DRAWING NUMBER
Apple Inc.
4
R
39 29
PP3V0_S2R_HALL
I927
=PP3V0_S2R_HALL
21 23
MAKE_BASE=TRUE
VOLTAGE=3.0V
SYNC_DATE=N/A
POWER ALIASES

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
121 OF 154
SHEET
34 OF 39
MLB CONSTRAINTS
TCF VERSION (USING SPACING RULE)

TABLE_SPACING_RULE_HEAD
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
SPACING_RULE_SET
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM
NO_TYPE,BGA,BGA06-06,BGA_P4
MM
16.2
TCF_VERSION
ALLOW ROUTE
ON LAYER?
LAYER
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
0.104 MM
NOTES:
NC_UART5_TXD
0.104 - 11/30/2011
ASSIGNING RULE TO NC NET
SPACING CONSTRAINTS
TABLE_PHYSICAL_RULE_HEAD
MINIMUM NECK WIDTH
WEIGHT
TCF_VERSION
I1
MINIMUM LINE WIDTH
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_ITEM
PHYSICAL CONSTRAINTS
PHYSICAL_RULE_SET
LAYER
DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM
DEFAULT
=45_OHM_SE
=45_OHM_SE
3.0 MM
0 MM
0 MM
STANDARD
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
DEFAULT/BGA SPACING RULES
SPACING_RULE_SET
LAYER
WEIGHT
SINGLE-ENDED PHYSICAL RULES

45 OHMS
DEFAULT
0.100 MM
STANDARD
=DEFAULT
BGA_SPA
=DEFAULT
BGA_P4_SPA
0.200 MM
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
45_OHM_SE
TOP,BOTTOM
0.105 MM
0.055 MM
3.0 MM
DIFFPAIR NECK GAP
45_OHM_SE
ISL2,ISL9
0.055 MM
0.055 MM
3.0 MM
45_OHM_SE
ISL3,ISL8
0.065 MM
0.055 MM
3.0 MM
45_OHM_SE
ISL4,ISL7
0.053 MM
0.055 MM
3.0 MM
45_OHM_SE
ISL5
0.072 MM
0.055 MM
3.0 MM
REGULAR SPACING RULES
SPACING_RULE_SET
ISL6
0.059 MM
0.055 MM
3.0 MM
WEIGHT
1:1_SPACING
LAYER
0.050 MM
0P08_SPACING
0.080 MM
1.5:1_SPACING
0.075 MM
2:1_SPACING
0.100 MM
2.5:1_SPACING
0.125 MM
3:1_SPACING
0.150 MM
4:1_SPACING
0.200 MM
5:1_SPACING
0.250 MM
0P5MM_SPACING
0.5 MM
0P64MM_SPACING
0.64 MM
0P2_SPACING
0.20 MM
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
TOP,BOTTOM
0.090 MM
0.090 MM
0.170 MM
=STANDARD
0.170 MM
MM
~ 4 MIL
0.114
MM
~ 4.5 MIL
0.125
MM
~ 5 MIL
0.140
MM
~ 5.5 MIL
0.15 MM
~ 6 MIL
0.18 MM
~ 7 MIL
0.2
~ 8 MIL
MM
0.25 MM
~ 10 MIL
0.3
MM
~ 12 MIL
0.33 MM
~ 13 MIL
0.4
MM
~ 16 MIL
1.0
MM
= 39.37 MIL
90_OHM_DIFF
ISL2,ISL9
0.062 MM
0.062 MM
=STANDARD
0.190 MM
0.190 MM
90_OHM_DIFF
ISL3,ISL8
0.062 MM
0.052 MM
=STANDARD
0.190 MM
0.190 MM
90_OHM_DIFF
ISL4,ISL7
0.051 MM
0.051 MM
=STANDARD
0.190 MM
0.190 MM
90_OHM_DIFF
ISL5,ISL6
0.052 MM
0.052 MM
=STANDARD
0.105 MM
0.105 MM
0.102
90_OHM_DIFF
~ 3.5 MIL
90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES

PHYSICAL_RULE_SET
~ 3 MIL
MM
45_OHM_SE
MM
0.089
PHYSICAL_RULE_SET
0.075
DDR 45 OHMS SINGLE-ENDED PHYSICAL RULES

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DDR_45_OHM_SE
TOP,BOTTOM
0.105 MM
0.105 MM
3.0 MM
DDR_45_OHM_SE
ISL2
0.055 MM
0.055 MM
3.0 MM
DIFFPAIR NECK GAP

POWER/GND SPACING RULES
SPACING_RULE_SET
LAYER
WEIGHT
DDR_45_OHM_SE
ISL3
0.065 MM
0.065 MM
3.0 MM
DDR_45_OHM_SE
ISL4
0.053 MM
0.053 MM
3.0 MM
DDR_45_OHM_SE
ISL5,ISL6
0.072 MM
0.072 MM
3.0 MM
DDR_45_OHM_SE
0.055 MM
0.055 MM
3.0 MM
PWR_P1SPACING
0.1 MM
GND_P1SPACING
0.1 MM
SWITCHNODE
0.2 MM
DDR 90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
DDR_90_OHM_DIFF
TOP,BOTTOM
0.090 MM
0.090 MM
=STANDARD
0.170 MM
0.170 MM
DDR_90_OHM_DIFF
ISL2
0.062 MM
0.062 MM
=STANDARD
0.190 MM
0.190 MM
DDR_90_OHM_DIFF
ISL3
0.062 MM
0.062 MM
=STANDARD
0.190 MM
0.190 MM
DDR_90_OHM_DIFF
ISL4
0.051 MM
0.051 MM
=STANDARD
0.190 MM
0.190 MM
DDR_90_OHM_DIFF
ISL5,ISL6
0.066 MM
0.066 MM
=STANDARD
0.180 MM
0.180 MM
POWER
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
PWR
0.6MM
0.20 MM
3.0 MM
GND_PH
0.6MM
0.075 MM
3.0 MM
PWR_PMU
0.6MM
0.20 MM
3.0 MM
DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
DDR_90_OHM_DIFF
0.056 MM
0.056 MM
=STANDARD
0.180 MM
0.180 MM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
WIFI PHYSICAL RULES

PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MISC
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_SPA
CLK
BGA
BGA_SPA
GND
GND_P1SPACING
SWITCHNODE
SWITCHNODE
ANLG
3:1_SPACING
BGA_P4
BGA_P4_SPA
WIFI_50S
TOP,BOTTOM
0.245 MM
0.2 MM
=STANDARD
WIFI_50S
=STANDARD
=STANDARD
=STANDARD
WIFI_PWR100
0.10 MM
0.050 MM
=STANDARD
TABLE_SPACING_ASSIGNMENT_ITEM
WIFI_PWR1000
1.00 MM
0.100 MM
=STANDARD
MISC PHYSICAL RULES
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
1:1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
0.08 MM
0.08 MM
SPEAKER
0.5 MM
0.20 MM
10 MM
0.10 MM
0.10 MM
AUDIO_DIFF
0.1 MM
0.09 MM
10 MM
0.10 MM
0.10 MM
LED
0.1 MM
0.09 MM
10 MM
0.08 MM
0.08 MM
TEMP_SENSE
0.1 MM
0.09 MM
10 MM
0.08 MM
0.08 MM
SYNC_MASTER=MIKE
PAGE TITLE
CONSTRAINTS: MLB RULES
BGA AREA PHYSICAL RULES

TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
BGA
BGA_PHY
DRAWING NUMBER
Apple Inc.
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP
BGA_PHY
0.060 MM
0.060 MM
=STANDARD
0.076 MM
0.075 MM

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
150 OF 154
SHEET
35 OF 39
JTAG
AREA_TYPE
USB
Clock Signal Constraints

NET_PHYSICAL_TYPE
PHYSICAL_RULE_SET
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
USB_90D
90_OHM_DIFF
CLK_50S
45_OHM_SE
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
JTAG
2:1_SPACING
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
USB
4:1_SPACING
CLK
3:1_SPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
SPACING
PHYSICAL
I63
I162
I88
I89
I96
I94
CLK_50S
CLK_50S
CLK
CLK
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK
CLK
CLK
CLK
ISP1_CAM_FF_CLK
ISP0_CAM_RF_CLK
I2S_50S
I2S_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
CLK_50S
I130
I131
I157
I158
I234
I235
I256
I257
I15
17 30
I14
14 30
I13
7 22
I20
4 25
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
I5
I6
4
4 10 39
I266
I267
20 22
I268
I269
20 22
I270
I2C
5 36
5 18 36
I271
I258
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
I2C_50S
45_OHM_SE
I259
I260
I261
22
22
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I2C
1.5:1_SPACING
22
I263
I262
22
SPACING
PHYSICAL
4 25
7 22
I2S0_CODEC_ASP_MCK
ISP0_CAM_RF_CLK_R
ISP1_CAM_FF_CLK_R
ISP1_CAM_FF_C
ISP0_CAM_RF_C
ISP1_CAM_FF_FILT
ISP0_CAM_RF_FILT
I2S
I2S
CLK
CLK
CLK
CLK
CLK
CLK
JTAG_AP_TCK
JTAG_AP_TMS
JTAG_AP_TDI
TP_JTAG_AP_TDO
JTAG_AP_TRST_L
JTAG
JTAG
JTAG
JTAG
RST
I16
NET_TYPE
NET_TYPE
I265
I264
USB_AP_P
USB_AP_N
USB_BBMUX_BB_P
USB_BBMUX_BB_N
USB_TS_BBMUX_P
USB_TS_BBMUX_N
USB11_AP_BBMUX_P
USB11_AP_BBMUX_N
CONN_E75_DPAIR1_P
CONN_E75_DPAIR1_N
CONN_E75_DPAIR2_P
CONN_E75_DPAIR2_N
TS_E75_DPAIR1_P
TS_E75_DPAIR1_N
TS_E75_DPAIR2_P
TS_E75_DPAIR2_N
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
4 25
4 25
25 26
25 26
25
25
4 25
4 25
24 25
24 25
24 25
24 25
25
25
25
25
NET_TYPE
UART
AREA_TYPE
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I2C_50S
I1
NET_PHYSICAL_TYPE
PHYSICAL_RULE_SET
I2
UART_50S
45_OHM_SE
I3
I4
I61
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
UART
3:1_SPACING
UART
UART
2:1_SPACING
I62
I98
I99
I100
I101
I102
NET_TYPE
I103
SPACING
PHYSICAL
I228
I229
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
UART_50S
I237
I236
I174
I173
I175
I176
I177
I178
I179
I182
I181
I180
I232
I233
UART2_TS_ACC_RXD
UART2_TS_ACC_TXD
UART4_WLAN_RXD
UART4_WLAN_TXD
UART1_BB_CTS_L
UART1_BB_RTS_L
UART1_BB_TXD
UART1_BB_RXD
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
UART6_AP_RXD
UART6_AP_TXD
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
I124
5 25
I125
5 25
I226
5 14
I227
5 14
SPACING
PHYSICAL
5 19 25 30
HSIC
5 19 25 30
5 22
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
HSIC
45_OHM_SE
5 22
7 22
7 22
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
HSIC
4:1_SPACING
HSIC_RDY
2:1_SPACING
7 22
20 22
20 22
20 22
20 22
20 22
20 22
20 22
20 22
XTAL
5 25 26
NET_TYPE
I192
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CRYSTAL
5:1_SPACING
I195
I196
5 14
5 14
I197
I198
5 14
NET_TYPE
5 25
5 25
SPI
I199
SPACING
HSIC
HSIC
HSIC
HSIC
HSIC_RDY
HSIC_RDY
HSIC_RDY
HSIC_RDY
HSIC_RDY
HSIC3_BB_DATA
HSIC3_BB_STB
HSIC1_WLAN_DATA
HSIC1_WLAN_STB
GPIO_BB_HSIC_HOST_RDY
4 26
4 26
4 14
4 14
5 26
5 26
5 14 36
5 14 36
5 14
SPACING
PHYSICAL
XTAL_AP_24M_I
XTAL_AP_24M_O
AP_24M_O
PMU_XTAL
PMU_EXTAL
CRYSTAL
CRYSTAL
CRYSTAL
CRYSTAL
CRYSTAL
I230
PHYSICAL_RULE_SET
PHYSICAL
HSIC
HSIC
HSIC
HSIC
HSIC
HSIC
HSIC
HSIC
HSIC
I193
5 25 26
5 14
7 22
I194
5 26
I92
AREA_TYPE
5 22
5 26
I93
NET_PHYSICAL_TYPE
5 22
I191
I90
I2C1_SDA_1V8
I2C1_SCL_1V8
I2C0_SDA_1V8
I2C0_SCL_1V8
I2C2_SDA_3V0
I2C2_SCL_3V0
ISP0_CAM_RF_I2C_SCL
ISP0_CAM_RF_I2C_SDA
ISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDA
CONN_I2C1_SDA_1V8
CONN_I2C1_SCL_1V8
CONN_I2C2_SCL_3V0
CONN_I2C2_SDA_3V0
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I231
4
4
4
29
29
SPI_50S
45_OHM_SE
I2S
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SPI
2:1_SPACING
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
I2S_50S
45_OHM_SE
NET_TYPE
I183
I184
I185
I186
I187
I188
I189
I190
I240
I241
I242
I243
PHYSICAL
SPACING
NET_SPACING_TYPE1
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI
SPI
SPI
SPI
SPI3_GRAPE_MISO
SPI3_GRAPE_MOSI
SPI3_GRAPE_SCLK
SPI3_GRAPE_CS_L
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI
SPI
SPI
SPI
SPI2_IPC_MISO
SPI2_IPC_MOSI
SPI2_IPC_SCLK
GPIO_BB_HSIC_RESUME
SPI_50S
SPI_50S
SPI_50S
SPI_50S
SPI
SPI
SPI
SPI
SPI1_CODEC_MISO
SPI1_CODEC_MOSI
SPI1_CODEC_SCLK
SPI1_CODEC_CS_L
5 16
5 26
I140
I143
5 18
I142
5 18
I141
5 18
I159
5 18
I144
SPACING_RULE_SET
I149
I150
2:1_SPACING
I151
I161
NET_TYPE
PHYSICAL
I244
SPACING
I245
DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO
DWI
DWI
DWI
I152
I153
I156
3:1_SPACING
2:1_SPACING
NET_TYPE
DWI
*
I2S
I145
AREA_TYPE
I2S
I2S
5 16
NET_SPACING_TYPE2
SPACING_RULE_SET
5 16
DWI
NET_SPACING_TYPE1
AREA_TYPE
5 16
I148
NET_SPACING_TYPE2
I247
5 30
I246
SPACING
PHYSICAL
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S_50S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_SDOUT
I2S0_CODEC_ASP_MCK
I2S3_CODEC_XSP_BCLK
I2S3_CODEC_XSP_LRCK
I2S3_CODEC_XSP_DIN
I2S3_CODEC_XSP_DOUT
I2S0_CODEC_XSP_SDOUT
I2S2_BT_BCLK
I2S2_BT_LRCK
I2S2_BT_DIN
I2S2_BT_DOUT
5 18
5 18
5 18
5 18
18
5 36
5 18 36
5 18
SYNC_MASTER=MIKE
5 18
PAGE TITLE
5 18
DRAWING NUMBER
Apple Inc.
5 14
R
5 14
5 14
5 14

5 30
5 30
CONSTRAINTS: LOW SPEED BUS
5 18
051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
151 OF 154
SHEET
36 OF 39
EMBEDDED DISPLAYPORT
MIPI
PHYSICAL_RULE_SET
NET_PHYSICAL_TYPE
AREA_TYPE
AREA_TYPE
EDP_90D
90_OHM_DIFF
PHYSICAL_RULE_SET
NET_PHYSICAL_TYPE
AREA_TYPE
BACKLIGHT
NET_PHYSICAL_TYPE
3
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LEDA
3:1_SPACING
LEDB
3:1_SPACING
EDP_50S
45_OHM_SE
LED
LED
PHYSICAL_RULE_SET
NET_SPACING_TYPE1
MIPI_90D
90_OHM_DIFF
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
EDP
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
4:1_SPACING
SPACING_RULE_SET
NET_TYPE
MIPI0C
4:1_SPACING
MIPI1C
4:1_SPACING
PHYSICAL
EDP_90D
EDP_90D
EDP_50S
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
EDP_90D
I435
I436
I437
NET_TYPE
I439
SPACING
PHYSICAL
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
I315
I316
I343
I342
I311
I312
I395
I394
I519
I518
I521
I520
I345
I346
I347
I348
I354
I356
I415
I414
I438
MIPI0C_CAM_RF_CLK_P
MIPI0C_CAM_RF_CLK_N
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI_90D
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI0C
MIPI1C
MIPI1C
MIPI1C
MIPI1C
MIPI1C
MIPI1C
MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_N
MIPI_90D
MIPI_90D
MIPI1C
MIPI1C
I440
7 21
7 21
I442
7 21
I441
7 21
I444
7 21
I443
7 21
I445
20 21
20 21
20 21
20 21
20 21
20 21
I447
I446
I449
I448
I450
I451
I452
7 21
I454
7 21
I453
7 21
I455
7 21
20 21
20 21
I457
I456
I458
20 21
I460
20 21
I459
I462
I461
I463
I464
I465
NET_TYPE
SPACING
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP
EDP_AUX_P
EDP_AUX_N
EDP_HPD
EDP_DATA_P<0>
EDP_DATA_N<0>
EDP_DATA_P<1>
EDP_DATA_N<1>
EDP_DATA_P<2>
EDP_DATA_N<2>
EDP_DATA_P<3>
EDP_DATA_N<3>
EDP_AUX_EMI_P
EDP_AUX_EMI_N
EDP_DATA_EMI_P<0>
EDP_DATA_EMI_N<0>
EDP_DATA_EMI_P<1>
EDP_DATA_EMI_N<1>
EDP_DATA_EMI_P<2>
EDP_DATA_EMI_N<2>
EDP_DATA_EMI_P<3>
EDP_DATA_EMI_N<3>
CONN_EDP_AUX_EMI_P
CONN_EDP_AUX_EMI_N
PHYSICAL
7 15
I482
7 15
I484
7 15
I483
7 15
I485
7 15
I487
7 15
I486
7 15
I489
7 15
I488
7 15
I490
7 15
I491
15
I492
15
I493
15
I494
15
I495
15
I496
15
I497
15
I498
15
I499
15
I500
15
I501
15
I502
15
I503
15
I504
15
I505
SPACING
7 15
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED_IO1_A_R
LED_IO1_B_R
LED_IO2_A_R
LED_IO2_B_R
LED_IO3_A_R
LED_IO3_B_R
LED_IO4_A_R
LED_IO4_B_R
LED_IO5_A_R
LED_IO5_B_R
LED_IO6_A_R
LED_IO6_B_R
LED_IO_1_A
LED_IO_1_B
LED_IO_2_A
LED_IO_2_B
LED_IO_3_A
LED_IO_3_B
LED_IO_4_A
LED_IO_4_B
LED_IO_5_A
LED_IO_5_B
LED_IO_6_A
LED_IO_6_B
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
LEDA
LEDB
30
30
30
30
30
30
30
30
30
30
30
30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15 30
15
15
15
15
15
15
TEMP SENSORS
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
BOARD_TEMP
3:1_SPACING
BOARD_TEMP
AUDIO/SPEAKER
TEMP_SENSE
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
AUDIO
3:1_SPACING
NET_TYPE
PHYSICAL
SPACING
I572
BOARD_TEMP
BOARD_TEMP1
30 32
I574
BOARD_TEMP
BOARD_TEMP2
30 32
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP3_P
BOARD_TEMP3_N
BOARD_TEMP4_P
BOARD_TEMP4_N
BOARD_TEMP5_P
BOARD_TEMP5_N
BOARD_TEMP6_P
BOARD_TEMP6_N
BOARD_TEMP7_P
BOARD_TEMP7_N
BOARD_TEMP8_P
BOARD_TEMP8_N
NET_TYPE
PHYSICAL
AUDIO
AUDIO
HP_MIC_P
HP_MIC_N
AUDIO_DIFF
AUDIO_DIFF
AUDIO
AUDIO
L81_AIN2_P
L81_AIN2_N
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO
AUDIO
AUDIO
AUDIO
SPKR_L_VSENSE_N_FILT
SPKR_L_VSENSE_P_FILT
SPKR_L_VSENSE_N
SPKR_L_VSENSE_P
AUDIO_DIFF
AUDIO_DIFF
I584
I585
I587
I586
SPACING
18
I576
18
I577
I578
18
I579
18
I580
I589
I588
I591
I590
I592
I593
I594
I595
I597
I596
I598
I599
I606
I607
I608
I609
I610
I611
I564
I565
I558
I560
I570
I569
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO_DIFF
AUDIO
AUDIO
AUDIO
AUDIO
SPKR_R_VSENSE_N_FILT
SPKR_R_VSENSE_P_FILT
SPKR_R_VSENSE_N
SPKR_R_VSENSE_P
SPEAKER
SPEAKER
AUDIO
AUDIO
SPKR_L_P
SPKR_L_N
SPEAKER
SPEAKER
AUDIO
AUDIO
SPKR_L_CONN_P
SPKR_L_CONN_N
SPEAKER
SPEAKER
AUDIO
AUDIO
SPKR_R_P
SPKR_R_N
SPEAKER
SPEAKER
SPEAKER
SPEAKER
AUDIO
AUDIO
AUDIO
AUDIO
SPKR_R_CONN_P
SPKR_R_CONN_N
SPKR_L_FLR
SPKR_R_FLR
AUDIO_DIFF
AUDIO_DIFF
AUDIO
AUDIO
SPKR_L_SES_N
SPKR_L_SES_P
AUDIO_DIFF
AUDIO_DIFF
AUDIO
AUDIO
SPKR_R_SES_N
SPKR_R_SES_P
USB_90D
USB_90D
USB
USB
MIKEY_TS_P
MIKEY_TS_N
USB
USB
L81_MBUS_P
L81_MBUS_N
USB_90D
USB_90D
I600
I601
19
I581
19
I582
19
I583
19
I602
I603
19
I604
19
I605
19
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
30
30
30
30
30
30
30
30
30
30
30
30
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
18 25
SYNC_MASTER=MIKE
18 25
PAGE TITLE
CONSTRAINTS: DISPLAY/AUDIO
18
DRAWING NUMBER
18
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
152 OF 154
SHEET
37 OF 39
DDR
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
DDR
AREA_TYPE
SPACING_RULE_SET
3:1_SPACING
DDR_50S
DDR_45_OHM_SE
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
DDR_90D
DDR_90_OHM_DIFF
NAND
WIFI
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
NAND_50S
45_OHM_SE
NET_TYPE
PHYSICAL
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NAND0
2:1_SPACING
SPACING
PHYSICAL_RULE_SET
WIFI_50S
WIFI_PWR100
WIFI_PWR100
WIFI_PWR1000
WIFI_PWR1000
NAND1
2:1_SPACING
I221
I222
I223
I225
I226
I224
I228
I230
I229
I231
I232
I233
I235
I234
I236
I237
I238
I239
I240
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S
DDR0_CA<9..0>
DDR0_DM<3..0>
DDR0_CK_P
DDR0_CK_N
DDR0_CKE<1..0>
DDR0_CSN<2..0>
DDR
DDR
DDR
DDR
DDR
DDR
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR0_ZQ
DDR0_DQ<7..0>
DDR0_DQS_P<0>
DDR0_DQS_N<0>
DDR0_DQ<15..8>
DDR0_DQS_P<1>
DDR0_DQS_N<1>
DDR0_DQ<23..16>
DDR0_DQS_P<2>
DDR0_DQS_N<2>
DDR0_DQ<31..24>
DDR0_DQS_P<3>
DDR0_DQS_N<3>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S
DDR
DDR
DDR
DDR
DDR
DDR
DDR1_CA<9..0>
DDR1_DM<3..0>
DDR1_CK_P
DDR1_CK_N
DDR1_CKE<1..0>
DDR1_CSN<2..0>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR1_ZQ
DDR1_DQ<7..0>
DDR1_DQS_P<0>
DDR1_DQS_N<0>
DDR1_DQ<15..8>
DDR1_DQS_P<1>
DDR1_DQS_N<1>
DDR1_DQ<23..16>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
DDR1_DQ<31..24>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S
DDR
DDR
DDR
DDR
DDR
DDR
DDR2_CA<9..0>
DDR2_DM<3..0>
DDR2_CK_P
DDR2_CK_N
DDR2_CKE<1..0>
DDR2_CSN<2..0>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR2_ZQ
DDR2_DQ<7..0>
DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR2_DQ<15..8>
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR2_DQ<23..16>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
DDR2_DQ<31..24>
DDR2_DQS_P<3>
DDR2_DQS_N<3>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_50S
DDR
DDR
DDR
DDR
DDR
DDR
DDR3_CA<9..0>
DDR3_DM<3..0>
DDR3_CK_P
DDR3_CK_N
DDR3_CKE<1..0>
DDR3_CSN<2..0>
DDR_50S
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR_50S
DDR_90D
DDR_90D
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR3_ZQ
DDR3_DQ<7..0>
DDR3_DQS_P<0>
DDR3_DQS_N<0>
DDR3_DQ<15..8>
DDR3_DQS_P<1>
DDR3_DQS_N<1>
DDR3_DQ<23..16>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
DDR3_DQ<31..24>
DDR3_DQS_P<3>
DDR3_DQS_N<3>
8 11
8 11
NET_TYPE
8 11
8 11
I202
I203
I205
I206
I204
I208
I210
I209
I211
I212
I213
I215
I214
I216
I217
I218
I219
I220
I181
I182
I183
I185
I186
I184
I188
I190
I189
I191
I192
I193
I195
I194
I196
I197
I198
I199
I200
I38
I39
I41
I44
I43
I47
NET_TYPE
SPACING
PHYSICAL
8 11
8 11
I126
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
NAND0
FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
FMI0_ALE
FMI0_CE0_L
TP_FMI0_CE1_L
TP_FMI0_CE2_L
TP_FMI0_CE3_L
TP_FMI0_CE4_L
TP_FMI0_CE5_L
TP_FMI0_CE6_L
TP_FMI0_CE7_L
FMI0_CLE
I128
NAND_50S
NAND0
FMI0_DQS
6 13
I131
NAND_50S
NAND0
FMI0_RE_L
6 13
I133
NAND_50S
NAND0
FMI0_WE_L
6 13
I144
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
NAND1
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
FMI1_ALE
FMI1_CE0_L
I146
NAND_50S
NAND1
TP_FMI1_CE2_L
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND1
NAND1
NAND1
NAND1
NAND1
TP_FMI1_CE4_L
TP_FMI1_CE5_L
TP_FMI1_CE6_L
TP_FMI1_CE7_L
FMI1_CLE
6 13
6 13
I68
I69
11
I70
8 11
I71
8 11
I72
8 11
I73
8 11
I74
8 11
I75
8 11
I76
8 11
I77
8 11
I78
8 11
I120
8 11
I121
8 11
I122
8 11
I123
I125
8 11
I245
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
NAND_50S
I124
I201
AREA_TYPE
WIFI_50S
NET_PHYSICAL_TYPE
6 13
I246
6 13
I247
6 13
I248
6 13
I249
6 13
I250
6 13
I251
PHYSICAL
SPACING
50_WLAN_G
50_WLAN_A
50_WLAN_G_1
50_WLAN_A_DIPLX
50_WIFI_ANT_FD_2
50_WIFI_ANT_FD_1
50_WIFI_ANT_FD
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
WIFI_50S
27
27
27
27
6 13
6 13
6 13
6 13
6 13
8 11
8 11
8 11
8 11
8 11
11
8 11
8 11
8 11
I135
8 11
I136
8 11
I137
8 11
I138
8 11
I139
8 11
I140
8 11
I141
8 11
I142
8 11
I143
8 11
8 12
6 13
6 13
6 13
6 13
6 13
6 13
6 13
6 13
6 13
6 13
8 12
8 12
I148
8 12
I149
8 12
I150
8 12
I151
I152
12
8 12
I154
NAND_50S
NAND1
FMI1_DQS
I156
NAND_50S
NAND1
FMI1_RE_L
6 13
I160
NAND_50S
NAND1
FMI1_WE_L
6 13
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
8 12
DDR VREF
8 12
I48
I37
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I180
12
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
VREF
5:1_SPACING
8 12
8 12
8 12
NET_TYPE
8 12
PHYSICAL
SPACING
8 12
8 12
I166
8 12
I167
8 12
I169
8 12
I168
8 12
I244
8 12
I243
8 12
I241
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
I242
PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA
PPVREF_DDR1_DQ
PPVREF_DDR2_CA
PPVREF_DDR2_DQ
PPVREF_DDR3_CA
PPVREF_DDR3_DQ
11 39
SYNC_MASTER=MIKE
11 39
PAGE TITLE
CONSTRAINTS: DDR/FMI
11 39
11 39
DRAWING NUMBER
12 39
Apple Inc.
12 39
R
12 39
12 39

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
153 OF 154
SHEET
38 OF 39
PWR
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
PP_PWR
PWR_PMU
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PWR
3:1_SPACING
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
GND
GND_PH
NET_TYPE
VOLTAGE
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.1V
1.2V
1.2V
1.2V
1.2V
1.2V
1.8V
1.8V
1.8V
1.2V
1.2V
1.2V
1.1V
1.1V
3.3V
3.0V
1.7V
3.0V
I221
I1
I2
I3
I4
I5
I6
I7
I8
I9
I12
I11
I10
I13
I15
I14
I16
I17
I18
I19
I20
I21
I23
I22
I24
I25
I26
I28
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
NET_TYPE
SPACING
BUCK0A_LX0
BUCK0A_LX1
BUCK0A_FB
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PP1V1_CPU0_FET
BUCK0B_LX0
BUCK0B_LX1
BUCK0B_FB
PP1V1_CPU1_FET
BUCK0C_LX0
BUCK0C_FB
PP1V1_CPUB
BUCK2_LX0
BUCK2_LX1
BUCK2_LX2
BUCK2_FB
PP1V2_SOC
BUCK3_LX0
BUCK3_FB
PP1V8_S2R
BUCK4_LX0
BUCK4_FB
PP1V2_S2R
BUCK5_LX0
BUCK5_FB
PP3V3_OUT
PP3V0_GRAPE
PP1V7_VA_VCP
PP3V2_S2R_USBMUX
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
LDO5
1.8V
1.8V
4.7V
4.2V
6.0V
6.0V
6.0V
5.25V
1.1V
1.1V
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PWR500
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
I61
20.4V
20.4V
1.8V
1.0V
1.8V
1.8V
3.3V
3.3V
20.4V
20.4V
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PWR500
PP_PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PPLED_OUT_A
PPLED_OUT_B
PP1V8_PL0_F
PP1V0_MIPI_PLL_F
PP1V8_EDP_AVDD_AUX
PP1V8_DP_AVDD_AUX
PP3V3_S0_LCD_FERR
PP3V3_LCDVDD_SW_F
PPLED_BACK_REG_B
PPLED_BACK_REG_A
I64
6V
PP_PWR
PWR
PPVBUS_USB_EMI
0.6V
0.6V
0.6V
PP_PWR
PP_PWR
PP_PWR
PWR
PWR
PWR
PPVREF_DDR0_CA
PPVREF_DDR0_DQ
PPVREF_DDR1_CA
0.6V
0.6V
0.6V
0.6V
0.6V
I222
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PPVREF_DDR1_DQ
PPVREF_DDR2_CA
PPVREF_DDR2_DQ
PPVREF_DDR3_CA
PPVREF_DDR3_DQ
4.6V
4.6V
1.8V
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
PP_PWR
I227
3.55V
PP_PWR
PWR
LDO10
3.2V
3.3V
3.0V
3.0V
3.0V
3.0V
2.8V
1.0V
1.1V
1.8V
1.2V
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I40
I41
I42
I43
I44
I45
I46
I47
I49
I51
I50
I53
I52
I54
I55
I56
I57
I58
I59
I60
I67
I68
I69
I70
I71
I72
I73
I74
I76
I75
PHYSICAL
I223
PP3V3_ACC
PP3V0_S2R_HALL
PP3V2_S2R_USBMUX
PP3V0_IO
PP3V0_SENSOR
PP2V8_CAM
PP1V0
PP1V1_SRAM
PP1V8_ALWAYS
PP1V2
VOLTAGE=0V
GND
GND
GND
I200
VOLTAGE=0V
GND
GND
GND_AUDIO_CODEC
LCM_LX
PP6V0_LCM_VBOOST
PP5V25_VLCM1
PP1V1_CPU0
PP1V1_CPU1
DAC_AP_VREF
BATT_POS_RC
BATT_VCC_WLAN
PP_WLAN_VDDIO_1V8
29
29
18
29 30
29
29
I203
VOLTAGE=0V
29
I207
VOLTAGE=0V
GND
GND
GND
GND
GND_SPKR_AMP1
GND_SPKR_AMP2
VOLTAGE=0V
GND
GND
AGND_U3000
GND
GND
GND
GND
GND
GND
J2200_29_GND
J2200_36_GND
J2200_43_GND
29 30
29
29
I217
29 34
29
29
I224
VOLTAGE=0V
I225
VOLTAGE=0V
I226
VOLTAGE=0V
16
15
15
15
29
29
29 34
29
29
RST
29 34
29
29
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
RST
4:1_SPACING
29 34
29
29
NET_TYPE
29 34
29 34
19 29 34
I165
29 34 39
I167
29
I171
29 34
I169
29 34
I170
29 34 39
I168
29 34
I172
29 34
I174
29 34
I173
29 34
I175
29 34
I176
29 34
I177
29 34
DSP_SW
PP1V8
PP1V8_GRAPE
PPVCC_MAIN
PPBATT_VCC
PP6V0_LCM_HI
SPACING
PHYSICAL
I199
29
I166
I29
NET_SPACING_TYPE1
GND
I178
I179
29 32 34
I181
15 25 29 30 34
I182
29 32 34
I183
30
PHYSICAL
SPACING
RST
RST
RST
RST
RST
RST
RST
RST
RST
RST
RST
GRAPE
RST
RST
RST
RST
BB_TRST_L
DBG_RST
DEBUG_RST_L
GSM_TXBURST_IND
JTAG_AP_TRST_L
RST_AP_1V8_L
RST_AP_L
GPIO_BB_RST_L
RST_BB_PMU_L
RST_BT_L
RST_DET_L
RST_GRAPE_L
RST_L63_L
RST_PMU_IN
RST_WLAN_L
SIMCRD_RST
RST
RST
UD881_RST
UD882_RST
C
4 10 36
4 25 26 30
5 26
30
30
30 34
30 34
30 34
30 34
4
7
7
15
15
15
15
23 34
11 38
11 38
11 38
11 38
12 38
12 38
12 38
12 38
7
29
27
27
SYNC_MASTER=MIKE
PAGE TITLE
CONSTRAINTS: POWER / GND
18 29
DRAWING NUMBER
Apple Inc.
R

051-9385
SIZE
REVISION
A.0.0
BRANCH
PAGE
154 OF 154
SHEET
39 OF 39

Ipad 4 Schematic-1 PDF

Încărcat de

Informații document

Titlu original

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Ipad 4 Schematic-1 PDF

Încărcat de

Drepturi de autor:

Formate disponibile

www.mobile-files.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

iPad 4th Gen

LAST_MODIFIED=Thu Jul 26 10:29:36 2012

PDF CSA CONTENTS

BLOCK DIAGRAM: SYSTEM

AP: MISC & ALIASES

PMU: ADRIANA PAGE 3

CONSTRAINTS: MLB RULES

CONSTRAINTS: LOW SPEED BUS

CONSTRAINTS: POWER / GND

PDF CSA CONTENTS

VIDEO: EDP CONNECTOR

AUDIO: L81 CODEC

AUDIO: SPEAKER AMP

SENSOR FLEX CONN

SENSOR CONN FILTERS 1

SENSOR CONN FILTERS 2

E75 DOCK SUPPORT

POWER: BATTERY CONNECTOR

PMU: ADRIANA PAGE 1

PMU: ADRIANA PAGE 2

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PRIMARY CELLULAR ANT

BLOCK DIAGRAM: SYSTEM

NOTICE OF PROPRIETARY PROPERTY:

SCH AND BOARD P/N

Power aliases required by this page:

TOSHIBA PPN1.5 16GB

32GB FLASH CONFIGURATIONS

TOSHIBA PPN1.5 32GB

64GB FLASH CONFIGURATIONS

BARCODE LABEL/EEEE CODES

TOSHIBA PPN1.5 64GB

EEEE FOR 639-3736 (MLB A 16G)

EEEE FOR 639-3737 (MLB A 32G)

EEEE FOR 639-3738 (MLB A 64G)

EEEE FOR 639-4176 (MLB A 128G)

EEEE FOR 639-3263 (MLB B 16G)

128GB FLASH CONFIGURATIONS

EEEE FOR 639-3739 (MLB B 32G)

EEEE FOR 639-3740 (MLB B 64G)

EEEE FOR 639-4177 (MLB B 128G)

EEEE FOR 639-3741 (MLB C 16G)

EEEE FOR 639-3742 (MLB C 32G)

EEEE FOR 639-3743 (MLB C 64G)

EEEE FOR 639-4178 (MLB C 128G)

TOSHIBA PPN1.5 128GB

NOTICE OF PROPRIETARY PROPERTY:

CHANGE TO USB 3.3V TO AVOID

USB 1.1 BASEBAND/TRISTAR

MLB OPTION USED FOR FF

USB11_DP E32 USB11_AP_BBMUX_P BI

5.4MA USB_DVDD R30

NOTICE OF PROPRIETARY PROPERTY:

L81 CODEC ASP

L81 CODEC XSP

USED FOR DEBUG

NEED TO CHARACTERIZE RISE TIME

NOTICE OF PROPRIETARY PROPERTY:

NOTICE OF PROPRIETARY PROPERTY:

EDP_DATA_P<0> A30 EDP_PAD_TX0P