DIgSILENT PowerFactory

Technical Reference Documentation

Sample and Hold

ElmSamp

DIgSILENT GmbH
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72810 - Gomaringen
Germany
T: +49 7072 9168 0
F: +49 7072 9168 88
http://www.digsilent.de
info@digsilent.de
Version: 2016
Edition: 1

Copyright 2016, DIgSILENT GmbH. Copyright of this document belongs to DIgSILENT GmbH.
No part of this document may be reproduced, copied, or transmitted in any form, by any means
electronic or mechanical, without the prior written permission of DIgSILENT GmbH.
Sample and Hold (ElmSamp)

Contents

Contents
1 General Description

2 Dynamic Simulation

3 Example Configuration

A Parameter Definitions

B Signal Definitions

List of Figures

List of Tables

Sample and Hold (ElmSamp)

Dynamic Simulation

General Description

Analog signals can not be connected to digital signal processing modules directly. The analog
signal must be sampled first. Usually a sample and hold module is setting the output at the
rising edge of the clock signal. The output value is constant up to the next clock pulse. The
Sample and Hold model of PowerFactory is providing exactly this functionality. In the following
S&H denotes Sample and Hold.
In PowerFactory the S&H model will produce the following output.

1.20

cl2 x= 1.4500 s

cl3 x= 1.5500 s

1.0726

DIgSILENT

cl1 x= 1.3500 s

1.60

1.0130
0.8135

0.80
0.40
0.0007

0.00

0.0007

0.0008

-0.40
1.30

1.40
Sample & Hold: Input Signal

1.50

1.60

[s]

1.70

[s]

1.70

Clock: Output
1.60
1.20
0.80
0.40
-0.00

1.3500 s
1.0726

-0.40
1.30

1.4500 s
0.8135
1.40

1.5500 s
1.0130

1.50

1.60

Sample & Hold: Output

Clock: Output

Figure 1.1: Plot Sample & Hold Output

In the example given in 1.1 the clock period is 100 ms. The upper plot shows the input signal of
the clock. The plot on the bottom shows the output signal. At every rising edge of the clock pulse
the input of the S&H model is read and written to the output. The intersection point between the
vertical bars in the upper plot and the curve show the sampled value. The output of the S&H
model is constant up to the next rising edge of the clock.

Dynamic Simulation

The input signals input and cl must always be connected for using the model in the simulation.
input A, input B and input C need not to be connected. Input values not connected are set to 0.

Sample and Hold (ElmSamp)

Example Configuration

Single Phase

Three Phase
input_A

output_A

input_B

output_B

input_C

output_C

input

output

cl

cl

Figure 2.1: Input/Output Definitions

Example Configuration

Figure 3.1 shows a typical configuration for the use of the S&H model. An analog signal is
connected to the input of the S&H model. The output of the S&H is the connected to the input
of a register (ElmReg). The size of the register is one. Both, the register and the S&H model
are connected to the same clock source. The plots show input and output of the S&H model
and the output of the register.

DIgSILENT

Due to the register size of one there is a delay of one clock period between the input and the
output of the register.

Sample & Hold + Register:

cl
Clock
ElmClock

input
Input File
ElmFile

Sample & Hold

ElmSamp

Register
ElmReg
1

Figure 3.1: Block Diagram

Sample and Hold (ElmSamp)

Example Configuration

Table 3.1: Example settings

Element

Classname

Variable

Value

Initial Conditions

ComInc

Clock

ElmClock

Sample & Hold

Register

ElmSamp
ElmReg

iopt sim
iopt net
dtgrd and dtout
tstart
cFreq
Tp
tonTp
nphase
nphase
nsamp
iopt mod

RMS values (Electromechanical Transients)

Balanced, Positive Sequence
0.05 ms
0.05 ms
0.01 kHz
100 ms
0.5
1
1
1
Register

Sample and Hold (ElmSamp)

Example Configuration

cl1 x= 1.350 s

1.60

cl2 x= 1.450 s

cl3 x= 1.550 s

cl4 x= 1.650 s

DIgSILENT

1.272
1.20

1.073

1.013
0.813

0.80

0.40
0.001

0.00

0.001

0.001

0.001

-0.40
1.30

1.40

1.50

1.60

[s]

1.70

Sample & Hold: Input Signal

Clock: Output
1.60
1.350 s
1.073

1.450 s
0.813

1.550 s
1.013

1.650 s
1.272

1.20

0.80

0.40

0.00

-0.40
1.30

1.40
Sample & Hold: Output

1.50

1.60

[s]

1.70

Clock: Output
1.60
1.450 s
1.073

1.550 s
0.813

1.650 s
1.013

1.20

0.80

0.40

0.00

-0.40
1.30

1.40

1.50

1.60

[s]

1.70

Register: Output
Clock: Output

Figure 3.2: Example plots

Sample and Hold (ElmSamp)

Signal Definitions

Parameter Definitions
Table A.1: Sample and Hold Parameters

Parameter

Description

Unit

loc name
outserv
nphase

Name
Out of service
Number of phases

Signal Definitions
Table B.1: Input/Output signals
Name

Description

input A
input B
input C
input
cl
output A
output B
output C
output

Input
Input
Input
Input signal
Clock signal
Output
Output
Output
Output signal

Sample and Hold (ElmSamp)

Unit

Type

Model

IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT

RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT
RMS, EMT

List of Figures

List of Figures
1.1 Plot Sample & Hold Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Input/Output Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Example plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sample and Hold (ElmSamp)

List of Tables

List of Tables
3.1 Example settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Sample and Hold Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.1 Input/Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sample and Hold (ElmSamp)