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Department of Electronics and Communication Engineering, S.V.I.T.S, Indore, Madhya Pradesh, India
Department of Electronics and Communication Engineering, S.V.I.T.S, Indore, Madhya Pradesh, India
Abstract
This paper proposes a new design to monitor the Heart Rate from Electrocardiogram (ECG) signal. The proposed design is based
on the concept of identifying the voltage level of the R-wave complex component of the ECG signal above a threshold level. A 100
Hertz sample rate is selected to sample the complex ECG signal. A dual-counter based calculation method is used to obtain the
mathematical value of Heart Rate. The proposed FPGA based ECG Heart Rate monitoring system can operate with high
performance with respect to the low-power and high speed. The system is designed using Verilog hardware design language and
Xilinx XC3s500E FPGA.
2. ELECTROCARDIOGRAM
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3. PROPOSED METHOD
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Fig. 3: Input signal range and Threshold level for heart rate calculation
START
Compare the sample value with the threshold value to identify the of peak signal region of Rwave component
No
Is sample value < threshold value?
Yes
Is sample value > or = threshold
value?
No
Yes
Set the counters to initial count (zero)
Increment counter1
Is sample value < threshold value?
No
Increment
counter-2
Yes
No
Is sample value > or = threshold
value?
Yes
Calculate Heart Rate (heart beats per minute):
Heart Rate = 6000 / (counter-1 + counter-2)
END
Fig. 4: Decision Flow Chart of ECG Monitoring System to calculate the Heart Rate
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4. CONCLUSION
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4-input LUTs
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REFERENCES
[1]
Fig. 5: counter1 and counter2 active regions in the complex
ECG wave
[2]
(1)
[3]
(2)
[4]
(3)
[5]
[6]
(4)
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[7]
[8]
[9]
[10]
[11]
[12]
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