Sta Aot v07

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide
Static Timing Analysis on

Schematic-based Mixed-Signal
Design: Workshop User Guide
Click here to download the RAK database
Product Version: Virtuoso IC 6.1.6 ISR6, Innovus 15.11- s048_1, QRC 14.23.099,
Tempus 15.11s049_1, Liberate 14.11-s005_1 & Spectre 14.1 ISR10
Workshop Version: 0.7
Date: April 2016
2002-2016 Cadence Design Systems, Inc. All rights reserved.
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Contents
1
WORKSHOP OVERVIEW ................................................................................................................5

1.1
OBJECTIVE OF THE WORKSHOP......................................................................................................................................... 5
1.2
OVERVIEW OF THE MODULES ........................................................................................................................................... 6
1.3
DESIGN AND PROCESS NODE ............................................................................................................................................. 8
1.3.1 Blocks of interest.......................................................................................................................................................... 8

1.3.2 Timing paths of interest ............................................................................................................................................... 9
1.4
DATABASE STRUCTURE .................................................................................................................................................. 11
1.5
WORKSHOP SETUP .......................................................................................................................................................... 12
WORKSHOP MODULES.................................................................................................................13
2.1
RUNNING OADBCHECKER ............................................................................................................................................. 13
2.1.1 Finding the location of oaDBChecker SKILL script .................................................................................................. 14

2.1.2 Loading oaDBChecker SKILL script into CIW.......................................................................................................... 15
2.1.3 Running oaDBChecker on LP_pll_dig_combo block ................................................................................................ 16
2.1.4 Running oaDBChecker on pll_fbdiv block ................................................................................................................ 20
2.1.5 Running oaDBChecker on LP_pll block .................................................................................................................... 23
2.2
SETTING UP THE DESIGN FOR ANALYSIS IN INNOVUS ...................................................................................................... 35
2.2.1 Loading an AOT design with PCell into Innovus using GUI ..................................................................................... 36
2.2.2 Setting the Pcell environment variables and generating an ExpressPcell cache ...................................................... 39
2.2.3 Importing an AOT design into Innovus using the TCL command .............................................................................. 42
2.2.4 Generating a Verilog stub netlist and adding net connection to wire ....................................................................... 48
2.2.5 Running verilogAnnotate ........................................................................................................................................... 55
2.2.6 Opening a cellview with no PRBoundary .................................................................................................................. 57
2.2.7 Adding PRBoundary into a cellview .......................................................................................................................... 59
2.3
RUNNING STA ON AN AOT DESIGN IN INNOVUS USING THE FLAT APPROACH ................................................................ 62
2.3.1 Examining the design ................................................................................................................................................. 63

2.3.2 Assembling the first level ........................................................................................................................................... 67
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2.3.3 Assembling the second level ...................................................................................................................................... 71

2.3.4 Running RC extraction and timing analysis .............................................................................................................. 80
2.3.5 Running Global Timing Debug .................................................................................................................................. 82
2.4
RUNNING STA ON AN AOT DESIGN IN INNOVUS USING THE FTM APPROACH ................................................................ 89
2.4.1 Generating FTM for pll_fbdiv block .......................................................................................................................... 90

2.4.2 Generating FTM for LP_pll_dig_combo block ......................................................................................................... 92
2.4.3 Running timing analysis at the top level using FTM ................................................................................................. 94
2.5
RUNNING THE FLAT APPROACH USING THE AUTO-FLATTENING ASSEMBLEDESIGN ....................................................... 100
Running assembleDesign across multiple hierarchies ..................................................................................................... 101

2.5.1 Running auto-mode of assembleDesign ................................................................................................................... 103
2.5.2 Running auto-mode of assembleDesign with exceptBlocks option ........................................................................ 109
2.6
CHARACTERIZING A CUSTOM DIGITAL LOGIC GATE TO RUN STA.................................................................................. 112
2.6.1 "No constrained path" due to missing timing library .............................................................................................. 113
2.6.2 Generating template file for Liberate ...................................................................................................................... 119
2.6.3 Running Liberate to characterize the cell ................................................................................................................ 122
2.6.4 Running Innovus with the newly created timing library .......................................................................................... 127
2.7
RUNNING STA ON OA-BASED DESIGN USING TEMPUS ................................................................................................. 130
2.7.1 Creating a flattened OA-based design for Tempus using Innovus ........................................................................... 131
2.7.2 Running QRC extraction and timing analysis in Tempus ........................................................................................ 132
CONCLUSION AND FUTURE WORK .......................................................................................136
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Workshop Overview
1.1
Objective of the Workshop
In the analog mixed signal (AMS) designs, digital logic is commonly embedded deep inside the design
hierarchy. To analyze the timing of these digital logic paths across different sub-blocks, the AMS design
with certain physical and logical levels has to be brought into Innovus to perform static timing analysis
(STA).
The main purpose of this workshop is to illustrate how to perform STA on the designs that are in OA
database format and are Virtuoso XL-compliant.
First, to verify whether the designs meet the requirements to run STA, it is recommended to run a SKILL
utility called OADBChecker in Virtuoso to check the designs prior to running STA. This workshop is
intended to help you acquire basic understanding in running the OADBChecker and fixing simple issues
to make the design ready for timing analysis.
There are two ways of running STA on the AMS designs. These are explained in this workshop in detail.
The first is to flatten the design to a certain physical level so that the timing paths to be analyzed are
visible and extractable by Innovus. The second approach is to generate the full timing models (FTM) for
the blocks containing the timing paths to be analyzed. The FTM contains the full logical netlist
information and RC parasitic information of the blocks that enable STA to be done in Innovus without the
need to feed Innovus the physical layout of the blocks.
After going through this workshop, you will learn how to run STA on an AMS design using the flat
approach or the full timing model (FTM) approach. For a design with simple custom logic gates, this
workshop has a module to show how to use Liberate to generate timing library for a simple custom logic
gate. Finally, there is also an exercise to help you understand how to run STA in Tempus with the OA
design to sign off the timing.
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1.2
Overview of the Modules
There are seven modules to run exercises to help you understand the various aspect of running STA on an
analog-on-top (AOT) design. In this workshop, there is only one placed-and-routed block not represented
by a schematic, and hence not implemented using Virtuoso. The top-level design and all the other blocks
are implemented in Virtuoso chip level. Through OA database, the blocks to be analyzed are brought into
Innovus to run STA.
One of the main requirements for an OA design to be analyzed and timed by Innovus is XL compliance.
For example, XL compliance requires a design to have the PRBoundary object and the wires to have net
connection or logical connectivity information. The first module shows how a SKILL-based utility called
OADBChecker is used to check the designs for VXL compliance. It also shows how to use
OADBChecker to check for the pipeline character in the instance names. It is quite common to see the
name of the instances in the physical layout implemented by Virtuoso containing the pipeline character.
For each statement in the timing constraint file, if the timer cannot not find the specified instance name in
the layout, the particular constraint statement will get rejected. Thus, you need to ensure that the instance
names referenced in the timing constraint file match with the corresponding names in the physical layout.
Other important checks shown in this module using OADBChecker are the checks for bus annotation and
mosaics.
Generally, you might have two issues when bringing an AOT design into Innovus. The first issue is the
handling of Pcells (Parameterized cells) in the design. If certain settings are not done and the Pcell cache
is not present, Innovus will not be able to load in the design successfully. The second issue is that of bus
annotation when the blocks have bus terminals. The bus annotation affects the connectivity of the design
when the loaded design is saved in Innovus. This issue typically occurs on the designs implemented using
the older versions of Virtuoso (older than IC615 ISR11). The second module shows how to resolve these
issues. The second module also shows how the simple XL compliance issues, such as missing
PRBoundary object and missing net connection for a wire, can be resolved in Virtuoso. Advanced users
can go directly to the third module.
The third module provides the step-by-step guidance on how to physically flatten the design to a certain
level so that the logical timing paths to be analyzed can be extracted and timed by Innovus. There is
detailed explanation on how the flattening process affects the logical and physical hierarchies of the
design. In its last section, this module shows how Global Timing Debug, a debugging feature in Innovus,
is used to do timing debugging and cross-probing between timing paths and the layout.
The fourth module shows the steps to generate FTM for the sub-blocks and how to run STA at the top
level in Innovus using these FTMs. There are some similarities between the flat approach (third module)
and the FTM approach (fourth module). Both approaches might require you to use the same Innovus
command to perform physical flattening on the design. However, the steps and commands to run timing
analysis are different for the two approaches. Major differences between the two approaches will be
described in the fourth module.
The fifth module demonstrates a new enhancement introduced in Innovus 14.2. The third module is about
selectively specifying the block (names) to be flattened. In this module, you let Innovus identify the list of
blocks and sub-blocks of lower levels to be flattened. Innovus is able to automatically flatten the blocks
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that either have the cells bound with the timing libraries or sub-blocks at lower level containing the cells
bound with the timing libraries. This new feature makes the run of flattening flow easier.
In the sixth module, there is a custom logic gate in the design that requires the timing library file to be
generated in order to run STA. This module shows the steps to run Liberate to characterize this logic gate
into a timing library file, and how to add this newly created timing library file to the existing scripts to run
STA.
The seventh module illustrates how to run STA in Tempus with the OA-based design. To prepare the
design for Tempus, the top-level design is loaded into Innovus and the blocks of interest are flattened.
After the flattened design is saved by Innovus, Tempus is invoked to load the saved design. Through the
interface provided by Tempus, standalone QRC is selected to run the signoff grade RC parasitic
extraction. Timing analysis can be performed after the RC extraction is done.
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1.3
Design and process node
The mixed signal design used in this workshop is a PLL design called Zambezi. It is an analog-on-top
(AOT) design consisting mostly of analog blocks and a few digital blocks. In this design, one digital
block (LP_pll_dig_wSPI) is implemented using Innovus with a Verilog netlist as input. The rest of the
blocks are implemented using Virtuoso with schematic views as input.
The technology process node is GPDK045, based on a 45nm process development kit developed by the
internal Flow team at Cadence. It has a standard cell library, gsclib045, which consists of typical standard
cells and low power cells such as always-on-buffers, level shifters, and so on. The following diagram
shows the physical hierarchy of Zambezi design:
1.3.1 Blocks of interest

The blocks of interest in this workshop are LP_pll_dig_wSPI, pll_fbdiv, LP_pll_dig_combo, and LP_pll.
LP_pll_dig_wSPI is a pure digital block. It consists of standard logic cells and is placed and routed in
Innovus. This digital block is a low power block with two power domains. The default power domain is
an always-on power domain, while the other domain can be shut off. In this workshop, there are logical
timing paths to be analyzed, which start from the registers inside this block.
pll_fbdiv is a custom digital block. It consists of standard logic cells and is implemented in Virtuoso. In
this workshop, the logical timing paths to be analyzed stop at the registers inside this block.
LP_pll_dig_combo is the parent block of LP_pll_dig_wSPI. It has level shifters that connect the digital
block, LP_pll_dig_wSPI to its outside world.
LP_pll is the top level design. The LP_pll as the top level in Innovus is chosen because this is high
enough level to contain the logical timing paths to be analyzed.
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1.3.2 Timing paths of interest
The diagram shows one of the timing constraints. This type of path to be measured is from a register
inside a digital block (LP_pll_dig_wSPI) to a register inside a custom digital block (pll_fbdiv). This type
of path traverses through a few physical hierarchies, with instances and wires at different levels.
The content of timing constraint to analyze this type of paths in this design is:
set_max_delay 1 -from
I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[0]/CK -to |u_fbdiv/u_0_0/D

You might wonder why there is a | (pipeline) character in the timing constraint statements. This is
because, in this workshop, the instance names in the layout view have the pipeline character. Innovus
builds the connectivity for the design from the layout view. Thus, the instance and pin objects (for
example, |u_fbidv/u_5_0/D) referenced in the timing constraint file must match the actual instance names
in the physical layout. If not, Innovus will reject these timing constraint statements.
Another timing path of interest is a register-to-register path inside the pll_fbdiv block. The timing
constraint statement for this path is:
create_clock name clk_in period 5 [get pins |u_fbdiv/clkin]
set_propagated_clock [get_clocks clk_in]
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Note: Timing analysis for this block can also be done at a lower physical design level (pll_fbdiv instead
of LP_pll) because the timing path is local to this block.
The last timing path of interest involves a custom logic gate that has no timing library file initially.
Without the timing library, Innovus sees a broken path between the two registers. There is guidance in the
workshop showing how the library characterization can be done on this custom NOR gate.
In summary, this workshop illustrates how you can do static timing analysis on:
1) Timing paths at a global level between different blocks.
2) Timing paths local to a particular block.
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1.4
Database structure
This workshop is built off the AMS Foundation Flow (AMSFF) database, which includes the reference
libraries and design libraries.
Reference libraries (OA) for this workshop are gpdk045 and gsclib045, located at:
LPAMS45_*/TECH/GPDK045/gpdk045
LPAMS45_*/LIBS/GPDK045/gsclib045
LPAMS45_*/LIBS/GPDK045/giolib045
Design Libraries (OA) are zambezi45 located at:
LPAMS45_*/DESIGNS/GPDK045/FRACNPLL/oa/zambezi45
Workshop modules are executed underneath:
LPAMS45_*/WORK/zambezi45/LPMS_WS/AOT_STA
The following terminology convention has been used throughout the document:
Chip level - Refers to LP_pll_chip cell, which has LP_pll block and bondpads
Top level - Refers to the Current Level of the block you are working on (for example, LP_pll
block)
Digital block - Refers to LP_pll_dig_wSPI block, which is implemented by Innovus P&R
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1.5
Workshop setup
ACTION 1: Untar the database to generate sta_aot_v07/LPAMS45_*/ directory (* stands for

yymmdd_hhmm, the time this DB was built). In the command line, type:
% tar zxf <your download path>/sta_aot_v07.tar.gz
ACTION 2: Initialize the database by fixing any absolute path issues. Configure the database. In the
command line, type:
% cd sta_aot_v07/LPAMS45_*/WORK/zambezi45/LPMS_WS
% ./scripts/init.sh
ACTION 3: In the command line, type:
% source proj.cshrc
You have to set the environment variables for product installation paths to your tools path. The tools you
have to set are Innovus, Tempus, Virtuoso, Spectre, Liberate and QRC.
ACTION 4: Modify the CDS_LIC_FILE environment variable to your local license servers.
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Workshop Modules
2.1
Running OADBChecker
In this module, you will learn how to:

1) Find the location of the oaDBChecker SKILL script.
2) Run the oaDBChecker to check for the pipeline character in instance names, bus annotation and
VXL compliance such as the presence of PRBoundary object, and whether the wires have the
logical connectivity information.
3) View and understand the report generated by the oaDBChecker.
The OADBChecker is a SKILL-based utility that can be run in the Virtuoso environment. It is a file
called oaDBChecker.il, which can be found at the sub-directory of the Innovus installation directory:
base_dir/release_number/lnx86/share/innovus/gift/AoT/OAChecker/oaDBChecker.il
Here, base_dir specifies the Innovus installation path, and release_number specifies the Innovus
Implementation System version number.
You will run the oaDBChecker check on three cellviews. Each cellview is modified intentionally to fail
certain checks:
1) LP_pll_dig_combo: For this cellview, the OADBChecker will flag the messages on the instances
with the pipeline character in names. Some of the bus terminals for this cellview have no bus
order (ascending or descending) information. The OADBChecker will flag such a design
condition.
2) pll_fbdiv: There is no PRBoundary object in this cellview. It will fail the XL compliance check of
the OADBChecker.
3) LP_pll: In this cellview, some shapes (wire) that are part of timing path have no net connection
or logical connectivity information. It will fail the XL compliance check of the OADBChecker.
There are some mosaics present in the cellview. Although mosaics are not fully interoperable
between Innovus and Virtuoso, because of not being part of timing path in this design, the
messages flagged by the OADBChecker about these can be ignored.
In summary, some results of the checks done by the OADBChecker indicate the real issue for timing
analysis and must be fixed. If not, timing analysis cannot be performed. On the other hand, there are some
checks that will not affect timing analysis and are meant more for the interoperable flow that involves
changing the design and round tripping between Innovus and Virtuoso.
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2.1.1 Finding the location of oaDBChecker SKILL script

ACTION 1: cd to the working directory for this module and set up cds.lib and others.
% cd AOT_STA/_check_oadb
% make setup
% source scripts/oadb_checker.cshrc
ACTION 2: View the content of oadb_checker.cshrc sourced in the previous step. In the UNIX
command line, type:
% more scripts/oadb_checker.cshrc
The content of this file is:
#!/bin/csh -f
setenv OADB_CHECKER_DIR `which innovus |\
sed 's?/tools/bin/innovus?/share/innovus/gift/AoT/OAChecker?'`
ACTION 3: The sourced C-shell script (oadb_checker.cshrc) is written to help locate the
oaDBChecker SKILL script. Verify that the SKILL script, oaDBChecker.il, is found. In the UNIX
command line, type:
% ls $OADB_CHECKER_DIR
The system should return:
oaDBChecker.il
ACTION 4: To see how the locations of the Innovus binary and OADBChecker SKILL script relate
with each other, in the UNIX command line, type the following two statements:
% which innovus
% echo $OADB_CHECK_DIR
Suppose the binary code of Innovus is in:
/icd/flow/INNOVUS/INNOVUS151/15.11-s048_1/lnx86/tools/bin/innovus
As a result, the SKILL script of OADBChecker will be in:

/icd/flow/INNOVUS/INNOVUS15115.11-s048_1/lnx86/share/innovus/gift/AoT/OAChecker
ACTION 5: Copy the SKILL script to current working directory. Type:

% cp $OADB_CHECKER_DIR/oaDBChecker.il .
In the next section, this file will be loaded into Virtuoso to start the OADBChecker.
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2.1.2 Loading oaDBChecker SKILL script into CIW

ACTION 1: Invoke Virtuoso. In the UNIX command line, type:
% virtuoso log CDS.log1 &
After all the windows are opened, you might want to close What's New in IC6.1.6 Overview by LMB
File from the top menu of its window followed by selecting Close.
ACTION 2: In the Command Interpreter Window (CIW), enter the following:
load "oaDBChecker.il"
The system will respond by showing a t in the CIW. The script is parsed and compiled.
ACTION 3: In the top menu of CIW, select Tools followed by OA DB Checker.
Tools => OA DB Checker
The Innovus Interoperability Checker form will appear.
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2.1.3 Running oaDBChecker on LP_pll_dig_combo block

ACTION 1: LMB Design tab near the top-left of the Innovus Interoperability Checker form.
LMB Design Library Checker.
LMB the browser buttons (red boxes with white arrow) to select the following:
Lib: zambezi45
Cell: LP_pll_dig_combo
View: layout
In the Report File Name field, edit the filename from oaDBChecker.rpt to oaDBChecker_combo.rpt.
ACTION 2: LMB the OK button near the bottom-right of the form to perform the check.
By default, Virtuoso invokes VI editor to open up the report file.
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ACTION 3: Close the form of Non-Default Rules Report by LMB the Close button at the bottom-right
of the form.
ACTION 4: If you prefer using any other type of the text editor, you can close the report file by doing the
following:
Move the mouse cursor to the report file. Type :q and hit the Enter key to close the file.
ACTION 5: Use your preferred text editor to view the report. Look at the first section of the report. It
checks for the "|" character in instance names. You will see something like the following:
Performing Check for existence of leading '|' char in instance names....
INFO : Instance '|u_cdmiso' has leading '|' char in its name.
INFO : Instance '|u_pll_dig_wSPI' has leading '|' char in its name.
INFO : Instance '|u_ls_rst' has leading '|' char in its name.
This section provides a list of instances that have "|" as the leading character of names.
If you continue to scroll down the report, you will see the following:
INFO : Found instances with leading '|' character in the names. This can cause
mismatch with names specified in a SDC file. Use envSetVal("layoutXL"
"prefixLayoutInstNamesWithPipe" 'boolean nil) before running schematic driven layout
generation process in VLS-XL to avoid creation of such names.
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ACTION 6: In the UNIX command line, type:

% head scripts/LP_pll.sdc n 3
|u_fbdiv/u_0_0/D
I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[0]/CK -to
|u_fbdiv/u_1_0/D
|u_fbdiv/u_2_0/D
You will notice that the timing constraint file has "|" (for example, |u_pll_dig_wSPI) in the constraint
statement. Without the "|" character in the hierarchical name of the instance, the constraint statement will
not be accepted by the timer of Innovus. Innovus will report that it cannot find the specified instance in
the layout cellview.
ACTION 7: Scroll down to view the next section that checks for bus annotation:
Checking for correct Bus information...
INFO : Found busterm scan_in<1> with busOrder "none"
INFO : Found busterm scan_in<0> with busOrder "none"
INFO : Found busterm scan_out<1> with busOrder "none"
INFO : Found busterm scan_out<0> with busOrder "none"
This section reports bus terminals that have no bus ordering (ascending or descending) information in the
layout database. Without the bus ordering information, Innovus will not be able to make the right
connection.
The next module (module 2.2) will describe how to detect and fix this issue in Innovus.
ACTION 8: Scroll down to view the section that checks for the presence of textDisplay objects.
Because the presence of these objects does not affect static timing analysis, you can disregard the reported
error:
Checking for presence of textDisplay objects in the design....
ERROR : Design has textDisplay objects. textDisplay is not supported in Innovus and
so it won't be round tripped.
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ACTION 9: Scroll down to view the next section that checks for incompatible wires/wire segments.
Again, because the conversion of unsupported wires/wire segments to SPECIALNETS does not affect the
static timing analysis (as long as Quantus is able to extract the RC parasitics from the special wires), you
can ignore this section:
Checking the incompatible wires/wire segments....
INFO : Signal route from begin point (105.485 48.305) to end point (101.035 48.305)
on layer 'Metal3' for net 'ls_atbdec<2>' has variable begin style but the begin width
is not valid (For variable style, either the width should be equal to zero or half
width of the segment or the minWidth constraint from technology for that layer.
FAILED: Incompatible wires/ wiresegments found in the design. Unsupported wires/wire

segments will be converted into DEF SPECIALNETS. Please look into
"incompatibleWires.rpt" for all the unsupported wire and wire segments.
ACTION 10: Scroll down until the Final Summary is shown:

Final Summary
Type of checks
PASSED
FAILED
-----------------------------------------------------------------------------Design Library Checks:
'|' char in instance names
Bus Annotation check
Power/Ground Checks
Shapes on drawing purpose
Pins on drawing purpose
Pins on non-routing layer check
Presence of textDisPlay object check
Validity of gapFill/fill/fillOPC
Presence of conic shape check
Status of interface bit check
Unsupported routing shapes
Non default rules check
Show non default rules
MS constraints check
PCell cache check
Presence of Mosaic check
XL Compliancy check
FAILED
FAILED
PASSED
PASSED
PASSED
PASSED
FAILED
PASSED
PASSED
PASSED
FAILED
PASSED
PASSED
PASSED
PASSED
PASSED
PASSED
The final summary reports show that only four checks failed. Out of this four failures, only two failures
(pipeline character and bus annotation) are of concern during static timing analysis.
ACTION 11: Close the text report. For VI editor, enter :q.
The OADBChecker will be run on another cellview in the next section.
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2.1.4 Running oaDBChecker on pll_fbdiv block

ACTION 1: Open the OADBChecker GUI form again from the Tools menu of CIW.
Tools => OA DB Checker
ACTION 2: Make sure the Design tab is selected and Design Library Checker is ticked.
Lib: zambezi45
Cell: pll_fbdiv
View: layout
In the Report File Name, edit it to change to oaDBChecker_fbdiv.rpt.
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ACTION 3: LMB the OK button near the bottom-right of the form to start the check.
ACTION 4: You can choose to browse the report, oaDBChecker_fbdiv.rpt, if you are familiar with the
VI text editor. Else, you can close the report and use your preferred text editor to open and view the
report. Close the Non-Default Rules Report by LMB the Close button at the bottom-right of the form.
ACTION 5: Scroll down the report until you see the following:
Performing Check for
INFO : Routing layer
existence of
'Metal4' has
'Metal2' has
'Metal2' has
'Metal4' has
non-drawing shapes....
shape with purpose 'pin'.
shape with purpose 'pin'.
total 2 shape(s) with purpose other than drawing.
total 12 shape(s) with purpose other than drawing.
For this cellview, the reported shapes do not affect timing analysis. There are 12 shapes of Metal4 layer
used as Labels. There are 2 shapes of Metal2 layer used as the pin shape for power terminals that will also
be reported in the next section. You might want to open the cellview {zambezi45 pll_fbdiv layout} to
view these.
ACTION 6: Scroll down the report to the next section:
Performing Check for existence of non-drawing pin shapes....
INFO : Terminal 'VDD' has pin shapes with purpose other than drawing. These pin
shapes are not inter-operable with Innovus.
INFO : Terminal 'VSS' has pin shapes with purpose other than drawing. These pin
shapes are not inter-operable with Innovus.
Innovus will convert to 'drawing' purpose the shapes of terminal (port) that uses 'pin' purpose. Such a
conversion does not affect timing analysis. It only affects the round trip back to Virtuoso if the design is
opened and saved in Innovus.
Page 21 of 136
Checking for XL compliancy.....
INFO : CellView does not have an associated PRBoundary.
In this case, the cellview fails the XL compliance check because it does not have a PRBoundary object.
ACTION 8: Scroll down to view the Final Summary:
Final Summary
Type of checks
PASSED
FAILED
Power/Ground Checks
PCell cache check
XL Compliancy check
PASSED
PASSED
PASSED
FAILED
FAILED
PASSED
FAILED
PASSED
PASSED
PASSED
FAILED
PASSED
PASSED
PASSED
PASSED
PASSED
FAILED
For this cellview, the only concern is failure of the XL compliance check, which is due to the missing
PRBoundary object. The next module (2.2), explains how to detect and fix this issue in Innovus.
ACTION 10: Exit Virtuoso. LMB File in CIW and select Exit. LMB Yes when prompted to exit
Virtuoso.
Page 22 of 136
2.1.5 Running oaDBChecker on LP_pll block

ACTION 1: Use your preferred text editor to edit the .cdsinit file. For example, if you prefer to use VI
editor, use:
% vi .cdsinit
ACTION 2: Append the following into the last line of this file. Close the file (:wq for VI editor) once it is
done.
Before appending, the last statement is:
ddsOpenLibManager()
After appending, the last two statements are:

ddsOpenLibManager()
Entering the load statement into .cdsinit ensures that the OADBChecker menu is always available on the
CIW when you invoke Virtuoso.
ACTION 3: Invoke Virtuoso. In the UNIX command line, type:
After all the windows are opened, you might want to close What's New in IC6.1.6 Overview by LMB
File from the top menu of its window followed by selecting Close.
ACTION 4: Open the OADBChecker GUI form from the Tools menu of CIW.
Page 23 of 136
The Innovus Interoperability Checker form will appear.
ACTION 5: LMB the Design tab and tick the box next to Design Library Checker.
Lib: zambezi45
Cell: LP_pll
View: layout
In the Report File Name, edit it to become oaDBChecker_lppll.rpt.
Page 24 of 136
ACTION 6: LMB the OK button near the bottom-right of the form to start the check.
ACTION 7: Close the form of Non-Default Rules Report by LMB the Close button at the bottom-right
of the form.
ACTION 8: You can choose to browse the report, oaDBChecker_lppll.rpt, if you are familiar with the
VI text editor. Else, you can close the report and use your preferred text editor to open and view the
report. The results of the following checks will be skipped because these have done in the previous
sections:
1) Checking of the pipeline character : Has impact on timing constraint
2) Presence of textDisplay object : No impact on MS-STA
3) Unsupported routing shapes : No impact on MS-STA
Checking for correct Bus information...PASSED.
This means that there is no bus annotation issue for the cellview.
Page 25 of 136
ACTION 10: Scroll down the report to view the result of the interface bit check:
Checking for status
INFO :Interface bit
INFO :Interface bit
INFO :Interface bit
of
on
on
on
interface bit for all blocks in the current view...

terminal 'atbdec_h<1>' of cell 'pll_cp' is set to false.
terminal 'atbdec_h<0>' of cell 'pll_cp' is set to false.
terminal 'atbdec_h<0>' of cell 'pll_reg' is set to false.
Setting the Interface bit on terminal to false might affect the connectivity (If there is a connectivity issue,
the generated Verilog netlist from Innovus might show missing connection). However, in this design,
because you are not going to time any path between the two cellviews (pll_reg and pll_cp) so that the
result does not impact MS-STA. In addition, because there is no bus annotation issue reported, it is okay
that the interface bit of the bus bit terminal is false.
ACTION 11: Scroll down the report to view the results of NDR check:
Performing Check for completeness of all Constraint Groups (NDRs) in the design....
Checking 'catenaDesignRules' Constraint Group for valid layers, appropriate spacing
values etc.....
INFO : 'catenaDesignRules' Constraint Group is empty.
WARNING : NDR catenaDesignRules does not have valid layers defined, hence this NDR
will not be usable in Innovus.
For MS-STA, this result does not matter because the STA does not involve any routing (re-routing) of
nets.
ACTION 12: Scroll down the report to view the results of checking for the presence of mosaics:
Checking for presence of mosaics ......
INFO: Mosaics found in the design. The mosaics will be read in Innovus as scalar
instances and will cause loss of connectivity on the instance terminals.
This section of the report indicates that there are mosaic instances in the design. Mosaics are not fully
interoperable between Innovus and Virtuoso. View the layout to see the mosaics.
Page 26 of 136
ACTION 13: Use Library Manager to open up the cellview. LMB the + sign on the left of
FracN_PLL_45 in the Library section to expand it. zambezi45 will appear. LMB zambezi45 to show
the available cells in the Cell section. LMB LP_pll to display all its associated views in the View section.
RMB layout in the View section and select Open With to invoke the Open File form.
Once the Open File form appears, select Open with Layout XL and LMB the OK button near the
bottom-right of the form.
Page 27 of 136
ACTION 14: From the top menu of the layout canvas, LMB Window followed by Workspaces and then
select Floorplan. You will see Navigator and Property Editor appear on the left side of the layout
canvas.
Window
Assistants
Toolbars
Workspaces
Basic
Classic
Constraints
EAD
Floorplan
ACTION 15: From the top menu of the layout canvas, LMB Tools and select Find/Replace... .
ACTION 16: In the Find/Replace form, use the red button (with white arrow) to select the following
two fields:
Search for array in the current cellview.
LMB Zoom to Figure to enable the zooming to the found figure.
LMB Find.
The Figure Count field will show 2. It means that two mosaics are found by the tool.
Page 28 of 136
ACTION 17: LMB Add Select of the Find/Replace form to highlight the figure found first.
You will see the tool zoom in and highlight the mosaic found first.
Mosaic
On the left side, the Navigator will indicate that the cell name of the mosaic is pll_bypclf. The Property
Editor also shows some attributes of the mosaic. You might need to expand these to view the entire line.
ACTION 18: In the Find/Replace form, LMB Deselect All followed by the Next button.
Page 29 of 136
ACTION 19: LMB Add Select of the Find/Replace form to highlight the figure found first.
You will see the tool zoom in and highlight the second found figure.
Mosaic
On the left side, the Navigator will indicate that the cell name of the mosaic is pll_bypclf, and the
Property Editor also shows some attributes of the mosaic.
Because all the mosaics found are of the cell, pll_bypclf, and there is no timing path from or to this cell,
you do not have to worry about the presence of these. Proceed to view the result of the next check.
ACTION 20: Scroll down the report to view results of the XL compliance check. The first and the last
few statements are shown:
Checking for
INFO : Shape
connection.
INFO : Shape
connection.
INFO : Shape
connection.
INFO : Shape
connection.
XL compliancy.....
((118.83 517.505) (120.04 517.585)) on layer Metal3 found without net

ACTION 21: On the layout window, view the wire shape pointed by the last statement of the report by
zooming in (click the right mouse button, hold and draw a box) near the following coordinate:
X = 200.0 Y= 395.88
LMB the wire shape (highlighted if clicked) shown on the next page and type q to query the shape
property. The other (bottom) wire shape will show ndiv<2>.
Page 30 of 136
Click this piece of wire to query.

Coordinate of lower-left corner of the wire is 200, 395.88.
The Route Properties form will appear.
ACTION 22: LMB the Connectivity tab if not already selected.
You will see that the Route Net Name field is empty. This means that this wire has no connectivity
information. It will be viewed as a floating net or wire when this cellview is opened in Innovus.
If you further trace this wire, you will notice that these shapes physically connect the terminal ndiv<2> of
the pll_fbdiv block to terminal ndiv<2> of the LP_pll_dig_combo block.
Page 31 of 136
ACTION 23: Move the mouse pointer to the layout window and type f to fit the window. LMB the block
pll_fbdiv. Alternatively, you can LMB the block/instance using the Navigator.
Select this block.

Or click this line.
ACTION 24: Under Connectivity of the top menu of the layout canvas, select Nets followed by
Propagate.
The Propagate Nets form will appear.
It can be seen that logically, the terminal ndiv<2> of the pll_fbdiv block is not connected.
Page 32 of 136
ACTION 25: LMB Cancel to close the Propagate Nets form.

ACTION 26: LMB the LP_pll_dig_combo block or select I1 (LP_pll_dig_combo) using Navigator.
Select this block.

Or click here.
Propagate.
The Propagate Nets form will appear.
You might have to scroll down the form to check the connection of terminal ndiv<2>. It can be seen that
ndiv<2> terminal of the LP_pll_dig_combo block is not connected logically either.
Page 33 of 136

ACTION 29: Finally, take a quick look at the Final Summary of the OAChecker report:
Final Summary
Type of checks
PASSED
FAILED
Power/Ground Checks
PCell cache check
XL Compliancy check
FAILED
PASSED
PASSED
PASSED
PASSED
PASSED
FAILED
PASSED
PASSED
FAILED
FAILED
FAILED
PASSED
PASSED
PASSED
FAILED
FAILED
For this cellview, you learned how to look for mosaics and wires that have no connectivity information.
ACTION 31: Exit Virtuoso. LMB File in CIW and select Exit. LMB Yes if prompted to exit Virtuoso.
In this module, you learned to run the OADBChecker to perform several checks on three cellviews and
flag out issues that will affect timing analysis. Next module will cover fixing of these issues.
Page 34 of 136
2.2
Setting up the design for analysis in Innovus

1) Load an AOT design into Innovus using the GUI form.
2) Load an AOT design into Innovus using TCL commands.
3) Set the environment variables to load an AOT Design with Pcells into Innovus.
4) Generate a P-cell cache using Virtuoso and enable Innovus to read a design that has Pcells.
5) Create a Verilog stub netlist using Virtuoso and run verilogAnnotate to handle the bus annotation
issue.
6) Add PRBoundary object to a cellview that has no PRBoundary object, which prevents the cellview
from being loaded into Innovus successfully.
7) Fix a simple wire connectivity issue by adding connectivity information to wires in a cellview that
makes it XL compliant.
Page 35 of 136
2.2.1 Loading an AOT design with PCell into Innovus using GUI
% cd AOT_STA/_setup_design
% make setup
ACTION 2: Start Innovus. In the UNIX command line, type:
% innovus
ACTION 3: On the top menu of Innovus, LMB File and select Import Design .
The Design Import GUI form will appear.

ACTION 4: In the Design Import form, under the Netlist: section, select the OA radio button. You can
either type in or use the arrow button (red button with white arrow) on the right to fill in the following for
Netlist: section:
Library: zambezi45
Cell:
LP_pll
View: layout
Under the Technology/Physical Libraries section, fill in the following for OA sub-section:
Reference Libraries:
gsclib045
Alternatively, you can LMB the ellipsis button () on the right to open up the Select OA Library form.
LMB the Add button of the Select OA Library form to open up the Add OA Library form.
Move the scroll bar to select gsclib045 and LMB the OK button of the Add OA Library form. When this
is done, gsclib045 will appear in the Select OA Library form (LMB the OK button of the Select OA
Library form):
Page 36 of 136
After these steps are done, the Design Import form will look similar to the following. LMB the OK
button to start the import.
After the OK button is hit, Innovus starts to load the physical libraries and the design.
You will see an ERROR message box pop up after a short while.
You will see the following ERROR message appear in the log file:
**ERROR: (IMPOAX-949): Express Pcell feature is disabled. Check
'CDS_ENABLE_EXP_PCELL' environment variable and any previous messages.
.
**ERROR: (IMPOAX-931): Found Pcell instances in the design but Express Pcells are
not enabled (Environment variable CDS_ENABLE_EXP_PCELL is not defined). Layout data
for the pcell instances can not be read from the pcell cache directory. Enable
Express Pcells in the environment and retry.
Page 37 of 136
These messages mean that the design has Pcells and you need to run some steps before you can invoke
Innovus to read the design. You will learn how to generate an ExpressPcell cache and enable ExpressPcell
feature in the next section.
ACTION 5: Exit Innovus. In the Innovus command line, type:
> exit
Page 38 of 136
2.2.2 Setting the Pcell environment variables and generating an

ExpressPcell cache
% source scripts/pcell.cshrc
The first step is to set the environment variables. If you open up the file pcell.cshrc in the scripts
directory, you will see it basically contains the setting of two environment variables.
setenv CDS_ENABLE_EXP_PCELL true
setenv CDS_EXP_PCELL_DIR ./.expressPcells
The first statement enables the ExpressPCell feature. The second statement instructs Innovus to find the
pcell cache in the current .expressPcells directory. You might want to type the following in the UNIX
command line to verify these environment variables are stored in the system now:
% env
CDS_ENABLE_EXP_PCELL=true
CDS_EXP_PCELL_DIR=./.expressPcells
ACTION 2: Start Virtuoso to generate the PCell cache. In the UNIX command line, type:
ACTION 3: Use Library Manager to open the cellview zambezi45 LP_pll layout. LMB the + sign on
the left side of FracN_PLL_45 in the Library section to expand it. zambezi45 will appear. LMB
zambezi45 to show the available cells in the Cell section. LMB LP_pll to display all its associated views
in the View section. RMB layout in the View section and choose Open With to invoke the Open File
form.
When the Open File GUI form appears, select Open with Layout XL and LMB the OK button.
Page 39 of 136
ACTION 4: On the top menu of layout window, LMB Tools and select Express Pcell Manager
The Express Pcell Manager GUI form will appear.

ACTION 5: In the Express Pcell Manager form, enable the two buttons if these are not already enabled:
Enable Express Pcells and Auto Save. You need to keep the Express Pcells directory as
./.expressPcells (to be consistent with the environment variable you set in the previous step). LMB Save
Cache to generate the ExpressPcell cache. The form will get updated:
LMB Ok button to exit the form.
Page 40 of 136
You might want to run the following optional step in the UNIX command line to verify that there is new
data created in the .expressCells directory.
% ls .expressPcells
1ec349a0e31c8c8b11ec49cdb629d61d.cds
98332dc98f1e363d705bf8bd4d4d3ab8.cds
30e464275f77faed8ec0f3fbddbc4b2a.cds
9a3e253122a5a9f8608cf7f847ee1332.cds
325a6a779dc6a1b1b952fefeeaa0001f.cds
a788211680b89595c06da63442697ee2.cds
367872604d2c8e9d1d90abb47c77907e.cds
a924b219c2b0b2703044808e9c78c6c1.cds
3a4f1c20502136132d4b9cc01cd2642f.cds
c1ac6250ba2c905348e07361cda31185.cds
3b1a56cae7c77434c7806db94ed48fdf.cds
c24c7b906f296f7630648cc06f3b4e68.cds
3c45bafcc3d0ddd4a1335b40195bb099.cds
cachedPCell_index.cds
483b4e1cfe107a32f01b40def033eb2f.cds
d0ade7a4fedbf2c23affb0b1fbfc833b.cds
7268cea137c46d4eb6be1acd4aa17943.cds
e1a05f4dfa246a91875022e71c303ab6.cds
83ffc7b5f457e7b5cb45cfa569262133.cds
eedde47e45fd3f3011978e98b262eb21.cds
87251ab700a93bc8b3a4a73cd0808412.cds
f3bfd69e7789b96069c7777a73ae7ad0.cds
8ee98622c327ca8c32ddcd44009f3d29.cds
Virtuoso.
Page 41 of 136
2.2.3 Importing an AOT design into Innovus using the TCL command
% innovus init scripts/load_init.tcl
You have learned how to start Innovus using the GUI form previously. In this section, you will learn how
to start Innovus using the TCL command. You need a text file that stores the init variables that you
entered in the GUI form in the previous exercise. You can open up the load_init.tcl file and see it
contains two lines of the TCL command:
source scripts/LP_pll.globals
init_design
Open up the global file, LP_pll.globals, and you will see the following:
set
set
set
set
set
init_design_netlisttype {OA}
init_oa_design_lib {zambezi45}
init_oa_design_cell {LP_pll}
init_oa_design_view {layout}
init_oa_ref_lib {gsclib045}
The init_design command is to instruct Innovus to read all the init variables and start initializing the
design.
After Innovus loads the design, you will see a summary of messages:
*** Summary of all messages that are not suppressed in this session:
Severity
ID
Count
Summary
WARNING
IMPFP-3961
1 The techSite '%s' has no related cells i...
WARNING
IMPSYT-7328
1 The design has been initialized in physi...
WARNING
IMPDB-1256
4 Pin %s of instance '%s' is a POWER type ...
WARNING
IMPPP-547
5 Cut '%s' does not fit in viaRule '%s'.
WARNING
IMPOAX-1037
1 There were %d cells with a total of %d p...
WARNING
IMPOAX-571
1 Property '%s' from OA is a hierarchical ...
WARNING
IMPOAX-1218
1 Path segment from (%g,%g) to (%g,%g) ass...
WARNING
IMPOAX-252
1 Found busBit terminals of bus '%s' of ce...
One WARNING message to be concerned about is IMPOAX-252. The message will be looked into in
detail later.
ACTION 2: Open the Innovus main window. In the Innovus command line, type:
> win
Page 42 of 136
ACTION 3: LMB Log Viewer under the Tools top menu of the layout window of Innovus.
A GUI form will appear to prompt you to select the log file to view.
ACTION 4: LMB the current Innovus log file. If this is the second time Innovus is running in the current
working directory, select innovus.log1 and LMB Open.
The Log Viewer window will appear. It shows all the TCL commands executed so far.
ACTION 5: LMB Edit on the top menu of Log Viewer and select Find.
Page 43 of 136
ACTION 6: Enter OAX-252 in the Find Text: field. LMB the Find Next button after the entry is done.
The Log Viewer will show more messages now.
Expand the Log Viewer if necessary. You will see the warning message of ENCOAX-252:
**WARN: (IMPOAX-252): Found BusBit terminals of bus 'scan_in[1]' of cell
'LP_pll_dig_combo' without bus ordering information in OA library 'zambezi45'. This
may lead to problems during saveOaDesign. It is recommended to run verilogAnnotate on
the library for annotating bus ordering information to such terminals.
You see this type of message because, in this Zambezi design, the LP_pll_dig_combo block
implemented by Virtuoso has bus terminals with no bus ordering (ascending or descending) information
in the corresponding layout database. Without the bus ordering information, Innovus will not be able to
make the right connection. To resolve this issue, you need to generate a Verilog stub netlist for this block.
After that, you run an OA utility to annotate the right bus ordering information into the layout database
using the Verilog stub netlist as a source.
Page 44 of 136
ACTION 7: In the Innovus command line, type:

saveDesign cellview {zambezi45 LP_pll layout_t1}
If you scroll back, you will notice some warning messages similar to the following:
**WARN: (IMPOAX-684):
cannot find definition of BUS Term 'vcobnd' of Cell
'LP_pll_dig_combo' in reference library. This could lead to further errors while
saving the OA database. Possible reasons could be that VerilogAnnotate is not run on
the OA reference library that has the definition for this cell. Either run
VerilogAnnotate on the reference library to fix this problem or use command
'setOaxMode -allowBitConnection true' before saving design to make bitwise connection
of terminals.
...
Without resolving the bus annotation issue, you cannot save the design properly into a new cellview in
Innovus.
zoomBox 198 395 201 397
You will see the wire connecting to ndiv[2] terminal of the pll_fbdiv block is marked as
_FLOATING_NET_RESERVED. Compared to the wire on its left (ndiv[1]), which connects to the
terminal ndiv[1] of the pll_fbdiv block, Innovus does not recognize this net, and will not able to see a
connectivity between pll_fbdiv and the other block.
Select this wire.
Page 45 of 136
ACTION 9: LMB the wire (highlighted in the diagram) and enter q to see its attribute.

> savenetlist debug.v
Examine the netlist debug.v. Search for pll_fbdiv and it can be seen that Innovus does not see a
connection between ndiv[2] terminal of the pll_fbdiv block. It becomes FE_UNCONNECTED$1 and
FE_UNCONNECTED$0.
LP_pll_dig_combo I1 (.vcocalen(vcocalen),
.ndiv({ ndiv[6],
ndiv[5],
ndiv[4],
ndiv[3],
FE_UNCONNECTED$1,
ndiv[1],
ndiv[0] }),
pll_fbdiv \|u_fbdiv (.rst_n(rst_fn),

.oclk(oclk),
.ndiv({ ndiv[6],
ndiv[5],
ndiv[4],
ndiv[3],
FE_UNCONNECTED$0,
ndiv[1],
ndiv[0] }),

> exit
Page 46 of 136
In this section, you learned how Innovus responds to missing bus order information and the wire that does
not have net connectivity. In the following sections, you will learn how to:
1) Generate a Verilog stub netlist using Virtuoso.
2) Annotate the bus ordering information to the design using an OA utility called
VerilogAnnotate so that Innovus can read the bus terminals with the right order.
3) Fix the connectivity issue for the wire connecting ndiv[2] terminals of the pll_fbdiv and
LP_pll_dig_combo blocks in Virtuoso.
Page 47 of 136
2.2.4 Generating a Verilog stub netlist and adding net connection to

wire
ACTION 1: Start Virtuoso. In the UNIX command line, type:
ACTION 2: Open up the cellview: zambezi45 LP_pll_dig_combo schematic.
Open with: Schematics L.

After LMB the OK button of the Open File GUI form, the schematic window will appear.
ACTION 3: On the top menu of Virtuoso Schematic Editor, LMB Create and select Cellview, followed
by selecting From Cellview....
Page 48 of 136
The Cellview From Cellview form will appear.

ACTION 4: In the Cellview From Cellview form, select Verilog-Editor for Tool/Data Type. In To
view Name field, enter verilog_stub as shown in the following screenshot. LMB the OK button.
The steps are to create a new cellview (zambezi45 LP_pll_dig_combo verilog_stub).

ACTION 5: If the following message box appears, LMB Close to close it.
You will see a window similar to the screenshot in the following page. Basically, it shows the content of a
Verilog netlist that contains only the input and output port definitions of the LP_pll_dig_combo module.

% ls stubs
LP_pll_dig_combo_stub.v
LP_pll_stub.v
Page 49 of 136
There are two stub files created for the LP_pll and LP_pll_dig_combo cellviews. If you open up
LP_pll_dig_combo_stub.v, you will see the same content as before. These Verilog stub files in the stubs
directory are pre-created files generated by running the previous steps.
ACTION 7: Use Library Manager to open up the cellview:
Library: zambezi45
Cell:
LP_pll
View: layout
Open with: Layout XL.
LMB the OK button near the bottom-right of the Open File form.
ACTION 8: From the top menu of the layout canvas, LMB Window followed by Workspaces and then
select Floorplan.
Window
Assistants
Toolbars
Workspaces
Basic
Classic
Constraints
EAD
Floorplan
Page 50 of 136
You will see Navigator and Property Editor appear on the left side of the layout canvas. If necessary,
expand the width of Navigator to clearly see the instance and cell name.
ACTION 9: Zoom in the layout window to view a floating wire. The coordinate of its lower left corner is
X = 200.0 Y= 395.88.
LMB the wire shape (highlighted if clicked) shown on next page and type q to query the shape property.
LMB this piece of wire to query.

Coordinate of the lower-left corner is 200, 395.88.
The Route Properties form will appear.

ACTION 10: LMB the Connectivity tab if not shown.
You will see similar thing in the Property Editor. The right field of + Route Net is empty.
Page 51 of 136
ACTION 11: Enter ndiv<2> into the Route Net Name field and LMB the OK button.
By adding the net connectivity information, the tool will be able to trace and see the connectivity between
the terminals ndiv<2> of the pll_fbdiv and LP_pll_dig_combo blocks. Verify these in the next few
steps.
Now the Property Editor shows that the wire has a net name:
ACTION 12: Move the mouse to the canvas and type f to fit the window. LMB the block pll_fbdiv as
shown in the following image (Alternatively, you can LMB the block/instance using the Navigator):
Select this block.

Or LMB here.
Page 52 of 136
Propagate.
You will see that the terminal ndiv<2> of the pll_fbdiv block is now connected to the net ndiv<2>.
ACTION 15: LMB the LP_pll_dig_combo block, or select it through Navigator.
Select this block.

Or LMB here.
Page 53 of 136
Propagate.
You might have to scroll down the form to check the connection of terminal ndiv<2>. It will now be
connected to ndiv<2>.
ACTION 17: LMB File from the top menu of the layout window and select Save to save the cellview.
ACTION 18: Close the windows of all schematic, layout cellview and Library Manager by LMB File of
the top menu and selecting either Close or Exit. Exit Virtuoso by LMB File in CIW and selecting Exit.
LMB Yes when prompted to exit Virtuoso.
Page 54 of 136
2.2.5 Running verilogAnnotate

In this section, you will learn to run verilogAnnotate to annotate the bus order information for the
LP_pll_dig_combo block using the Verilog stub file in the stubs directory.
%source scripts/verilog_annotate.cshrc
***********************************************************************
Tool:
verilogAnnotate
22.43.033
***********************************************************************
Running: verilogAnnotate -verilog "stubs/LP_pll_dig_combo_stub.v" -libDefFile cds.lib
-refLibs "zambezi45" -refViews "layout"
Started: xxx xx xx:xx:xx 2015 (Hostname: xxxx-xxxxxx)
Finished:
verilogAnnotate
Time elapsed:
x.xx seconds
CPU Time:
x.xxxxxx seconds
System Time:
x.xxxxxx seconds
Peak VM:
xxxxxxx bytes
Messages:
0 errors, 0 warnings
When you open up verilog_annotate.cshrc, you will see the following content:
verilogAnnotate -verilog stubs/LP_pll_dig_combo_stub.v -refLibs zambezi45 -libDefFile
cds.lib -refViews "layout"

By looking at the message summary, verify that Innovus no longer issues the IMPOAX-252 message.
win
zoomBox 198 395 201 397
Not floating anymore
LMB this wire and type q to verify that the wire has net information.
Page 55 of 136

> savenetlist debug.v
Examine the debug.v netlist and it can be seen that Innovus now sees a connection between ndiv[2]
terminals of the pll_fbdiv and LP_pll_dig_combo blocks:
wire [6:0] ndiv;
.ndiv(ndiv),
pll_fbdiv \|u_fbdiv
.oclk(oclk),
.ndiv(ndiv),
(.rst_n(rst_fn),

> exit
Page 56 of 136
2.2.6 Opening a cellview with no PRBoundary

% innovus init scripts/pll_fbdiv_init.tcl
The purpose is to load the cellview of {zambezi45 pll_fbdiv layout} into Innovus.
The content of pll_fbdiv_init.tcl is:
source scripts/pll_fbdiv.globals
init_design
And the content of the pll_fbdiv.globals file is:

set
set
set
set
set
init_oa_design_cell {pll_fbdiv}
> win
Due to insufficient data, there is nothing to see in the main window.

In the log file, there is an error message:
**ERROR: (IMPOAX-815): PRBoundary is not present in OA design. Cannot restore the
design from given OA database. Add the PRBoundary information to the cellview and
retry loading the database.
Type 'man IMPOAX-815' for more detail.
Page 57 of 136

> man IMPOAX-815
You will see a more detailed description of the error message:
DESCRIPTION
While reading an OpenAccess database into Innovus from the layout in
Virtuoso, user gets the above error with the oaIn command and is unable
to load the OpenAccess database into Innovus.
The error is stating that the PRBoundary object is not present in the
OpenAccess database.
In order to resolve this, user needs to add the PRBoundary object.
Adding a shape on prBoundary:boundary LPP (layer purpose pair) to the
Layout does not work, the boundary must be the correct object type.
User needs to add it interactively through this Virtuoso
in the layout.
menu
command
Example on Virtuoso menu command in the layout :

Create -> P&R Objects -> P&R Boundary.
This is equivalent to the DIEAREA in DEF.
In the section, you will fix the problem by following the instructions in this message.
> exit
Page 58 of 136
2.2.7 Adding PRBoundary into a cellview

ACTION 1: Start Virtuoso. In the UNIX command line, type:
ACTION 2: If Library Manager is not opened, LMB Tools inside CIW to invoke Library Manager.
Open up the cellview: zambezi45 pll_fbdiv layout.
ACTION 3: When the Open File GUI form appears, select Layout XL and LMB the OK button.
The canvas will show the layout of the pll_fbdiv cellview.

ACTION 4: Under Create of the top menu, select P & R Objects followed by P & R Boundary.
Page 59 of 136
ACTION 5: Use the left mouse key to draw a PRBoundary object (click, hold, draw a box and release the
mouse button) that covers all the placed and routed objects. At this point, do not worry about the
coordinates of the corners or the size of the PRBoundary. The size will be fine-tuned later.
PR Boundary object
ACTION 6: On the left side of the layout canvas, check if the Objects window appears. Expand
Boundaries to view P&R Boundary, and check if the corresponding V (viewable) and S (selectable)
buttons are clicked. If not, LMB the button to enable it.
ACTION 7: Use the left mouse key to select the PR Boundary object and click q (to query). Edit the
Points field to match the following:
(0 0) (0 17.235) (19.9 17.235) (19.9 0)
Page 60 of 136
ACTION 8: Save and close the cellview. If prompted to save the changes made, LMB Yes.
Virtuoso.
ACTION 10: Load the cellview again in Innovus. In the UNIX command line, type:
% innovus init scripts/pll_fbdiv_init.tcl
> win
With the PR Boundary object existing, you are able to view and analyze the layout now.
Exit Innovus. In the Innovus command line, type:
> exit
Page 61 of 136
2.3
Running STA on an AOT design in Innovus using the flat approach
In this module, you will learn:

1) How to run assembleDesign to physically flatten a block within an AOT design so that the
instances and wires inside the block are brought to the top level.
2) How does assembleDesign affect the physical hierarchy of the cellview that gets flattened.
3) How does assembleDesign affect the logical hierarchy of the cellview that gets flattened.
4) What are the commands run to analyze the timing of a low power design with multiple power
domains after assembleDesign.
5) How to use Global Timing Debug to debug timing and perform cross-probing between the layout
and timing report.
Page 62 of 136
2.3.1 Examining the design

% cd AOT_STA/_flat_sta
% make setup
% innovus init scripts/flat.tcl
You might want to view the content of flat.tcl in the scripts directory. The first few lines in this file are:
setOaxMode -allowAnalysisOnly true
init_design
The content of LP_pll.globals in the scripts directory is:

set
set
set
set
set
set
set
set
init_oa_design_cell {LP_pll}
init_mmmc_file {scripts/LP_pll.viewDefinition.tcl}
init_pwr_net {dvdd avddlf avddhf avdd_h VDDsw}
init_gnd_net {dgnd agndlf agndhf agnd_h}
In this .globals file, you specify the design library, and cell and view names through three variables
(init_oa_design_lib, init_oa_design_cell and init_oa_design_view). The standard cell library,
gsclib045, is specified through the init_oa_ref_lib variable so that Innovus reads all the abstract
cellviews in this library for the standard cells.
Note that you have a variable init_mmmc_file that points to LP_pll.viewDefinition.tcl for the LP_pll
block. This viewDefinition.tcl file contains the multi-mode, multi-corner specification for the LP_pll
block. The specification includes the timing libraries for the logic standard cells for each power domains
and QRC technology files to do RC extraction. The specification also lists the timing constraint file
(LP_pll.sdc), which resides in the scripts directory.
Note: After the init_design command is run, you will see Innovus issue some warning and error messages
(for example, TCLCMD-513, TCLCMD-1170, TCLCMD-917, TCLCMD1109) in the log file when it
reads the timing constraint file. This is expected because, at this stage, the design does not have the
specified instances at the top level. These specified instances are at a lower physical level and not seen by
Innovus. In the subsequent steps, you will run some actions to understand why Innovus does not see these
instances, and issues these messages.
The setOaxMode allowAnalyaisOnly true statement is for later use when running the assembleDesign
command to flatten blocks.
Page 63 of 136

> report_timing -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]/CK
You can cut and paste from the content of flat.tcl.
You do not see any reporting back from the software.
> grep _reg innovus.log
You will see the following warning in the resulting message:
**WARN: (TCLCMD-513):
The software could not find a matching object of the
specified type for the pattern 'I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]/CK'
(File scripts/LP_pll.sdc, Line 2).
In the timing constraint (LP_pll.sdc in the scripts directory), there is a statement like the following:
|u_fbdiv/u_1_0/D
In this step, you will try to get Innovus to report the worst timing from the CK pin of the source object
(I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]). However, Innovus cannot find this object
because, at this point, this object is not there in the Innovus database. Thus, the warning message is
issued. You will try to get Innovus to report timing to the D pin of destination object (|u_fbdiv/u_1_0) as
well.
> report_timing -to |u_fbdiv/u_1_0/D
Innovus cannot find this object in the database. You will learn the reason for this in subsequent steps.
ACTION 6: Open the main Innovus window to display the layout. In the Innovus command line, type:
> win
Page 64 of 136
ACTION 7: On the top menu of Innovus, LMB Tools and select Design Browser. Type in ndiv[4]
and hit the Enter key. LMB + Net ndiv[4] (SIGNAL PINs:2). This step is to select and highlight this
net in the layout window.
ACTION 8: Turn off the visibility button for Net in the section on the right side of the layout window.
This section controls the layer visibility and selectivity.
ACTION 9: Zoom in to the top-left corner. In the Innovus command line, type:
> zoomBox -4 359 237 536
You will see the LP_pll_dig_combo (instance name is I1) and pll_fbdiv (instance name is |u_fbdiv)
blocks are represented as hard macros.
LP_pll_dig_combo
pll_fbdiv
Basically, Innovus sees only one level of physical hierarchy when the layout.oa file of this LP_pll block
is imported into Innovus. It sees only the wire connection between the LP_pll_dig_combo and pll_fbdiv
blocks. All the blocks under LP_pll become hard macros. Physically, Innovus sees these blocks as
abstract with pins and cell blockages. It does not see any instances inside the blocks.
Page 65 of 136
ACTION 10: Generate the Verilog netlist of LP_pll. In the Innovus command line, type:
> saveNetlist LP_pll_flat.v
When you look at the netlist file (LP_pll_flat.v), you notice there is only one (logical) module in the file.
The LP_pll_dig_combo and pll_fbdiv blocks appear as leaf instances in the netlist. The following shows
the key content of this netlist:
module LP_pll (
refclk,
SV_n);
pll_fbdiv \|u_fbdiv
(.rst_n (rst_fn),
.VSS(agndlf),
.VDD(avddlf));
.SCLK(SCLK));
endmodule
ACTION 11: Quit the Design Browser by LMB the x button and reopen it.
Click on the + sign of Blocks (9) to expand it. The Design Browser shows the block information
(LP_pll_dig_combo and pll_fbdiv are hard blocks), which matches with what you see in the layout
window and Verilog netlist.
Thus, to run STA, you have to physical-flatten the LP_pll_dig_combo and pll_fbdiv blocks so that the
logical instances inside these blocks are brought up to the LP_pll level.
Page 66 of 136
2.3.2 Assembling the first level

> assembleDesign block {zambezi45 LP_pll_dig_combo layout} block {zambezi45 pll_fbdiv
layout} -keepPinGeometry
LP_pll_dig_wSPI
pll_fbdiv module
You will see the LP_pll_dig_combo and pll_fbdiv blocks disappear. The standard cells inside the
pll_fbdiv block will appear. The instances (for example, level shifters) inside the LP_pll_dig_combo
block will also appear.
However, you are not yet done with the physical-flattening process, because you still see another hard
block, LP_pll_dig_wSPI (instance name is I1/|u_pll_dig_wSPI), which appears after the physicalflattening of the LP_pll_dig_combo block.
ACTION 13: Turn on the visibility button for the NET button under the layer control section of the
layout window.
ACTION 14: Zoom in to the pll_fbdiv block. In the Innovus command line, type:
> zoomBox 198.5 394.5 200.5 397
Page 67 of 136
In previous step, the keepPinGeometry option has been specified for assembleDesign. The purpose of
this option is to keep the I/O pins of the assembled block as special wires after assembly. Without this
option, the result of the assembly for the pll_fbdiv block will be similar to the following (There will be a
physical disconnection for ndiv[2] net):
Regular wire
Special wire
As can be seen from the diagram, the keepPinGeometry option is needed to make the connection if
either of the wires at the top level or the block level are special wires. Innovus does not need this option to
make the connection between regular wires at both the top level and inside the block level.
ACTION 15: Turn off the visibility button (left button) for NET under the layer control section of the
layout window.
Page 68 of 136

> saveNetlist LP_pll_asm1.v
You will now see the new netlist (LP_pll_asm1.v) has three modules (previously, it had one). You can
find combinational logics and registers inside the pll_fbdiv module and the LP_pll_dig_wSPI block
inside the LP_pll_dig_wSPI module. However, LP_pll_dig_wSPI appears as a leaf instance in the
Verilog netlist.
module pll_fbdiv (
VSS);
input rst_n;
DFFSX1 u_2_0 (
),
endmodule
module LP_pll_dig_combo (
SCLK);
output vcocalen;
LP_pll_dig_wSPI \|u_pll_dig_wSPI
);
endmodule
module LP_pll (
SV_n);
output refclk;
pll_fbdiv \|u_fbdiv (
);
LP_pll_dig_combo I1 (
);
endmodule
Page 69 of 136
From the layout window and the Verilog netlist, you can conclude that Innovus sees the
LP_pll_dig_wSPI block as a hard block. One more assembleDesign is needed to flatten the sub-block
(LP_pll_dig_wSPI) to time the path that starts from a register inside this pure digital block
(LP_pll_dig_wSPI).
Page 70 of 136
2.3.3 Assembling the second level

> assembleDesign block {zambezi45 LP_pll_dig_wSPI layout} -keepPinGeometry
> zoomBox -4 350 237 536
After one more round of assembleDesign, you see the standard cells inside the LP_pll_dig_wSPI block
appear in the Innovus window.
ACTION 19: Quit the Design Browser by LMB the x button and reopen it. LMB the + sign of
PowerDomains to expand it.
In the Design Browser, it shows only one power domain (PD_cal). This is not right.
Page 71 of 136
ACTION 20: In the Innovus command line, enter the following two commands:
> loadCPF scripts/LP_pll.cpf
> commitCPF -keepRows
You have to load and commit the CPF (Common Power Format) file because CPF provides information
about the power domain an instance belongs to. It is possible that an instance placed in one power domain
and another instance placed in another power domain are of the same cell type (same physical design).
However, when these are placed in different power domains with connections to different power signals
(one is dvdd and the other is VDDsw), a CPF is necessary to let Innovus know which timing library set it
should use for these two instances. In this design, the digital block (LP_pll_dig_wSPI) and custom digital
block (pll_fbdiv) are driven with different supply voltages. Based on the CPF file, Innovus knows which
library sets to pick (0.9V and 1.1V timing libraries for the digital block and 1.08V and 1.32V timing
libraries for the custom digital block) to do multi-corner timing analysis.
The main purpose of specifying the keepRows option is to instruct Innovus to keep the rows of the
digital block (LP_pll_dig_wSPI). It is recommended to use this option for commitCPF in the
hierarchical flow (after assembleDesign is used). Without this option, the default behavior of
commitCPF will remove and recreate the existing rows. If rows of the assembled block is not aligned
with the rows on the top, the newly create row will get misaligned with the instances:
Top edges not aligned
Page 72 of 136
The following table shows the main definition of the CPF macromodel for each hard block:
Macro Name
Nominal
Voltage
Power
Pin
1.0V, 1.2V
dvdd,
avddlf
1.0V, 2.5V
dvdd,
avdd_h
pll_ls_porh
pll_cdsmiso
Ground
Pin
Mode
agndlf
pd_dvdd_agnd @1.0V,
pd_avddlf_agndlf @1.2V
agnd_h
pd_dvdd_agnd @1.0V,
pd_avdd_h_agnd_h @2.5V
1.0V, 2.5V
dvdd,
avdd_h
agnd_h
pd_dvdd_agnd_h @1.0V,
1.0 V
dvdd
dgnd
pd_dvdd_dgnd @1.0V
1.2V, 2.5V
avddlf,
avdd_h
agndlf
pd_avddlf_agndlf @1.2V,
pd_avdd_h_agndlf @2.5V
pll_lpf
1.2V, 2.5V
vddlf,
vdd_h
agnd_h
pd_avddhf_agndhf @1.2V,
pd_avddh_agndh @2.5V
pll_reg
2.5V
vdd_h
agnd_h
pll_ls_dvdd2avdd
pll_ls_dvdd2avddh
pll_cp
The following table shows a quick overview of the nominal voltage and power mode definition at the top
level:
Top Level Nominal
Name
voltage
Ground
Power Pin Pin
LP_pll
1.0 V
VDDsw
dgnd
1.0 V
dvdd
dgnd
1.2 V
avddhf
agndhf
1.2 V
avddlf
agndlf
2.5 V
avdd_h
agnd_h
Mode
{ PD_def@1.0V PD_cal@0V
pd_avdd_h_agnd_h@2.5V
pd_avddlf_agndlf@1.2V
pd_avddhf_agndhf@1.2V
pd_dvdd_dgnd@1.0V
pd_dvdd_agnd_h@1.0V},
{PD_def@1.0V PD_cal@1.0V
pd_avdd_h_agnd_h@2.5V
pd_avddlf_agndlf@1.2V
pd_avddhf_agndhf@1.2V
pd_dvdd_dgnd@1.0V
pd_dvdd_agnd_h@1.0V}
Page 73 of 136
The following table shows the power domains and corresponding instances that you are interested in this
timing analysis exercise:
Power Domains
Instances
Description
PD_def
Default
Default power domain
PD_cal
I1/|u_pll_dig_wSPI/u_pll_dig/u_rcal,
I1/|u_pll_dig_wSPI/u_pll_dig/u_vcocal
Shut off power domain for

modules inside pure
digital block
pd_avddlf_agndlf
|u_fbdiv,
|u_pfd,
I1/|u_ls_rst, Power domain for custom
I1/|u_ls_ndiv[0],
I1/|u_ls_ndiv[1], digital block
I1/|u_ls_ndiv[2],
I1/|u_ls_ndiv[3],
I1/|u_ls_ndiv[4],
I1/|u_ls_ndiv[5],
I1/|u_ls_ndiv[6]
ACTION 21: In the Innovus command line, enter the following three commands:
> setObjFPlanBox group pd_avddlf_gndlf 189.455 377.31 212 398
> modifyPowerDomainAttr pd_avddlf_agndlf addBlockBox {|u_pfd}
> modifyPowerDomainAttr pd_avddlf_agndlf addBlockBox {{ I1/|u_ls_rst I1/|u_ls_ndiv(0)
I1/|u_ls_ndiv(1) I1/|u_ls_ndiv(2) I1/|u_ls_ndiv(3) I1/|u_ls_ndiv(4) I1/|u_ls_ndiv(5) I1/|u_ls_ndiv(6) }}
Note: In the CPF file, these instances (for example, |u_fbdiv) are specified as instances belonging to the
pd_avddlf_agndlf power domain. These instances are placed in Virtuoso. Innovus is not going to replace
these because this workshop is a timing analysis exercise that involves no place and route operation. It is
recommended to specify the floorplan shape for this power domain using the command such as
setObjFPlanBox or modifyPowerDomainAttr. It does not matter whether the blocks are fully placed
inside the power domain shape. However, you should at least specify a physical location or boundary for
Innovus to understand where this power domain should be placed physically.
Page 74 of 136
ACTION 22: Quit Design Browser and reopen it. LMB the + sign of PowerDomains to expand it. Now,
the Design Browser shows multiple power domains.
ACTION 23: LMB the All Colors button in the layer control section. The Color Preferences form will
appear. LMB the Custom tab. Turn off the Psub layer by LMB the S button followed by V buttons next
to it. LMB the Close button at the bottom of this form to close the Color Preferences form.
Psub Layer
ACTION 24: Zoom to the pll_fbdiv block:
> zoomBox 184 373 214 402
You see the pll_fbdiv module has a different power domain: pd_avddlf_agndlf.
Page 75 of 136
ACTION 25: In the Design Browser, expand the + sign next to pd_avddlf_agndlf. Further expand
|u_fbdiv and its StdCells. You will see the names of all the cells of the |u_fbdiv block, which belongs to
the pd_avddlf_agndlf power domain.
ACTION 26: Generate Verilog netlist. In the Innovus command line, type:
> saveNetlist LP_pll_asm2.v
The netlist now has more levels of module hierarchy.
For example, you can view how each module is defined and instantiated under the following logical
hierarchy order:
LP_pll (top level)
=> LP_pll_dig_combo
=> LP_pll_dig_wSPI
=> LP_pll_dig
=> pll_dig_dsm
=> ls_ndiv_reg[0]
The key content of the netlist is:
module LP_pll_dig_wSPI (
LP_pll_dig u_pll_dig (.FE_OFN37_scan_en(FE_OFN37_scan_en),
));
endmodule
module LP_pll_dig (
pll_dig_dsm u_dsm (
));
endmodule
Page 76 of 136
module pll_dig_dsm (
SDFFRHQX1 \ls_ndiv_reg[0]
));
endmodule
(.SI(ls_ndiv[1]),
module pll_fbdiv (
endmodule
module LP_pll_dig_combo (
LP_pll_dig_wSPI \|u_pll_dig_wSPI
));
endmodule
(.pmc(pmc),
module LP_pll (
pll_fbdiv \|u_fbdiv (.rst_n(rst_fn),
);
LP_pll_dig_combo I1 (vcocalen,
);
endmodule
You can expand the Design Browser to view the module hierarchy (Tip: minimize PowerDomains and
keep expanding Modules).
Page 77 of 136
Here is a summary of what assembleDesign does to the design:

1) It physically flattens the selected block and brings up all the instances and wires inside the block
to the top.
2) In the logical connectivity, it increases the level of logical (or modular) hierarchy. In this example,
before assembleDesign, Innovus sees only one module. After assembly, the digital block
LP_pll_dig_wSPI that has embedded modular hierarchy is preserved and becomes visible to
Innovus.
3) It flattens one physical level of hierarchy for each specified block.
ACTION 27: Turn on the two NET buttons under the layer control section. Expand NET and disable
Special Net under the Net section.
ACTION 28: Zoom to the timing path between the LP_pll_dig_wSPI and pll_fbdiv blocks. In the
Innovus command line, type:
> zoomBox 81 355 231 535
> source scripts/selectnet.tcl
The content of the file, selectnet.tcl, is:
selectNet
selectNet
selectNet
selectNet
ndiv[1]
|u_fbdiv/i_ndiv[1]
|u_fbdiv/i_cnt[1]
I1/ls_ndiv[1]
This script is to highlight all the nets of one timing path.

ACTION 29: You can LMB View on the top menu and select Dim Background. It improves the
visibility with the selected wires highlighted while the display of the rest dimed. You will get the
following left screen by doing the Dim once. Do Dim once more to get the right screen as shown in the
following screen:
Page 78 of 136
You can see that the design is ready for extraction now. All the instances and wires are visible and
extractable by Innovus.
ACTION 30: Do Dim Background once to revert to the original display (no dimming).
Page 79 of 136
2.3.4 Running RC extraction and timing analysis

ACTION 31: Run extraction using high effort. In the Innovus command line, type:
> setDesignMode process 45
> setExtractRCMode -engine postRoute effortLevel high -lefTechFileMap
scripts/QRC_LEF.layermap_10lm.new
The postRoute option of setExtractRCMode is typically used when the design is fully routed. The effort
level is set to high to invoke the Integrated QRC (IQRC) extraction engine.
ACTION 32: Run timing analysis. In the Innovus command line, type:
> report_timing to |u_fbdiv/u_1_0/D
Innovus will show the timing report in the log file:
Path 1: VIOLATED Path Delay Check
Endpoint:
|u_fbdiv/u_1_0/D
(v)
Beginpoint: I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]/Q (v) triggered
by leading edge of 'dsmclk'
Path Groups: {default}
Analysis View: av_max
Path Delay
1.000
= Required Time
1.000
- Arrival Time
1.246
= Slack Time
-0.246
Clock Rise Edge
0.000
+ Clock Network Latency (Prop) 0.274
= Beginpoint Arrival Time
0.274
+----------------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
| Delay | Arrival | Required |
|
|
|
|
| Time
|
Time
|
|---------------------------------------------------+-------------+-----------+-------+---------+----------|
| I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1] | CK ^
|
|
|
0.274 |
0.028 |
| I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1] | CK ^ -> Q v | SDFFRHQX1 | 0.305 |
0.579 |
0.333 |
| I1/|u_ls_ndiv(1)
| A v -> Y v | LSLHX1_TO | 0.307 |
0.886 |
0.640 |
| |u_fbdiv/u_1_4
| A v -> Y v | MX2X1
| 0.221 |
1.107 |
0.861 |
| |u_fbdiv/u_1_2
| B v -> Y v | MX2X1
| 0.139 |
1.246 |
1.000 |
| |u_fbdiv/u_1_0
| D v
| DFFSX1
| 0.000 |
1.246 |
1.000 |
+----------------------------------------------------------------------------------------------------------+
ACTION 33: Set the timing format to display supply voltage, input slew and output load of each
instance. In the Innovus command line, type:
> set_global report_timing_format {instance arc cell delay arrival slew load voltage}
ACTION 34: Report the timing again. In the Innovus command line, type:
> report_timing to |u_fbdiv/u_1_0/D
You will see that the table looks different. Due to the length of the table and limited space in this page, the
names of some instances are not fully shown here:
+----------------------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
| Delay | Arrival | Slew | Load | Voltage |
|
|
|
|
| Time
|
|
|
|
|-------------------------------------------+-------------+-----------+-------+---------+-------+-------+---------|
| I1/|u_pll_dig_wSPI//u_dsm/ls_ndiv_reg[1] | CK ^
|
|
|
0.274 | 0.060 | 0.054 | 0.900
|
| I1/|u_pll_dig_wSPI//u_dsm/ls_ndiv_reg[1] | CK ^ -> Q v | SDFFRHQX1 | 0.305 |
0.579 | 0.110 | 0.006 | 0.900
|
| I1/|u_ls_ndiv(1)
| A v -> Y v | LSLHX1_TO | 0.307 |
0.886 | 0.304 | 0.020 | 1.080
|
| |u_fbdiv/u_1_4
| A v -> Y v | MX2X1
| 0.221 |
1.107 | 0.056 | 0.002 | 1.080
|
| |u_fbdiv/u_1_2
| B v -> Y v | MX2X1
| 0.139 |
1.246 | 0.044 | 0.001 | 1.080
|
| |u_fbdiv/u_1_0
| D v
| DFFSX1
| 0.000 |
1.246 | 0.044 | 0.001 | 1.080
|
+-----------------------------------------------------------------------------------------------------------------+
Page 80 of 136
ACTION 35: Run timing analysis for the local register-to-register path inside the pll_fbdiv module. In
the Innovus command line, type:
> report_timing from |u_fbdiv/u_divclk/CK
Path 1: MET Setup Check with Pin |u_fbdiv/u_0_0/CK
Endpoint:
|u_fbdiv/u_0_0/D
(^) checked with leading edge of 'clk_in'
Beginpoint: |u_fbdiv/u_divclk/QN (v) triggered by leading edge of 'clk_in'
Path Groups: {clk_in}
Other End Arrival Time
0.069
- Setup
0.109
+ Phase Shift
5.000
= Required Time
4.960
- Arrival Time
0.824
= Slack Time
4.137
Clock Rise Edge
0.000
0.069
+-----------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
| Delay | Arrival | Slew | Load | Voltage |
|
|
|
|
| Time
|
|
|
|
|-------------------+--------------+----------+-------+---------+-------+-------+---------|
| |u_fbdiv/u_divclk | CK ^
|
|
|
0.069 | 0.036 | 0.004 | 1.080
|
| |u_fbdiv/u_divclk | CK ^ -> QN v | DFFRX2
| 0.357 |
0.426 | 0.049 | 0.004 | 1.080
|
| |u_fbdiv/I33
| A v -> Y v
| CLKBUFX8 | 0.080 |
0.507 | 0.042 | 0.010 | 1.080
|
| |u_fbdiv/u_0_4
| S0 v -> Y ^ | MX2X1
| 0.170 |
0.677 | 0.052 | 0.002 | 1.080
|
| |u_fbdiv/u_0_2
| B ^ -> Y ^
| MX2X1
| 0.147 |
0.824 | 0.042 | 0.001 | 1.080
|
| |u_fbdiv/u_0_0
| D ^
| DFFRX1
| 0.000 |
0.824 | 0.042 | 0.001 | 1.080
|
+-----------------------------------------------------------------------------------------+
Page 81 of 136
2.3.5 Running Global Timing Debug

At the top menu of the Innovus window, LMB Timing and select Debug Timing
The Display/Generate Timing Report GUI form will appear.
ACTION 36: Make sure the Generate button is ticked and setup is selected for Check Type. Innovus
will generate a timing report called top.mtarpt. This report will get loaded before invoking the Global
Timing Debug window. LMB the OK button.
The Timing Debug window will appear.
In this window, you see a path histogram and there is a summary section on its right. When the OK
button of the Display/Generate Timing Report GUI form is clicked, internally, Innovus runs the
following command to generate a report that has timing slack not more than 0.75ns:
Page 82 of 136
report_timing -machine_readable -max_points 10000 -max_slack 0.75 -path_exceptions all >

top.mtarpt
On the Category Summary section of the Timing Debug window, it shows that there are 7 failing
timing paths and 55 timing paths that have positive timing slacks not more than 0.75ns.
Note that although the histogram shows a total of 61 timing paths, in fact, there are more valid timing
paths. This analysis is done based on timing paths that have no more than 0.75ns positive slacks and there
are 61 timing paths equal to or less than 0.75ns slack.
ACTION 37: To see a histogram that covers all the valid timing paths regardless of the slack value, in
the Innovus command line, type:
> report_timing -machine_readable -max_points 10000 -path_exceptions all > all.mtarpt
After this report (all.mtarpt) is generated, you will learn to load this report into Global Timing Debug in
the next few steps.
ACTION 38: In the Timing Debug Window, LMB the browser button next to Report File(s) top.mtarpt
to invoke the Display/Generate Timing Report GUI form.
ACTION 39: Deselect the Generate button because you have already generated the report. LMB the
browser button to open up the file browser (The title of the form is Timing Report File). Select
all.mtarpt and LMB the Open button.
Browser
Deselect the Generate Button.
Page 83 of 136
You will see the Display/Generate Timing Report window get updated. LMB the OK button in the
Display/Generate Timing Report GUI form.
You will see the Timing Debug window get updated. It shows that there are 1030 valid timing paths.
ACTION 40: In the Timing Debug window, LMB the browser button next to Report File(s) top.mtarpt
to invoke the Display/Generate Timing Report GUI form. Enter top.mtarpt in the Timing Report File
field. LMB OK when it is done.
The histogram will revert to analysis of 62 timing paths. Next, you will learn the cross-probing feature of
Global Timing Debug.
Page 84 of 136
ACTION 41: In the Timing Debug window, double LMB Path 1 of the Path List section.
It will show the Timing Path Analyzer window for path 1. You can expand the window to see the whole
path. Each row in the Data delay table shows either the cell or net delay. The columns show the
instance/net name, timing arcs, cell name, load, slew, wire length (if it is a net), and so on.
If you are concerned about whether a net (especially between a digital block and an analog block) is
properly buffered, the numbers shown under the Slew (transition) and Wire Length columns will be
useful for you.
Page 85 of 136
ACTION 42: LMB the row (I1/ls_ndiv[6]) shown selected. You will see the main layout window zoom
to the highlighted net.
Page 86 of 136
ACTION 43: LMB another row (|u_fbdiv/u_5_2) shown selected. The main layout window now zooms
in to the highlighted instance and its input and output net.
Page 87 of 136
ACTION 44: LMB the schematic tab of Timing Path Analyzer to view the schematic diagram of this
timing path. Expand the window if you need to see the number more clearly. The numbers shown are
either the cell delay of the instance or net delay of the net.
Schematic tab

> exit
Page 88 of 136
2.4
Running STA on an AOT design in Innovus using the FTM approach

1) Generate FTM for each block that has logical paths to be timed.
2) Generate FTM for a block that has digital logic in one of its sub-blocks. assembleDesign is
needed to flatten that digital sub-block before creating FTM for the block.
3) Run timing analysis using FTM at the top level.
Page 89 of 136
VSS
VDD
2.4.1 Generating FTM for pll_fbdiv block
clkin
rst_n
dsmclk
pll_fbidv
ndiv[6:0]
fbclk
oclk
% cd LPAMS45_*/WORK/zambezi45/LPMS_WS/AOT_STA/_ftm_sta
% make setup
ACTION 1: Start a new Innovus session by typing the following in the UNIX command line:
% innovus
> source scripts/pll_fbdiv.globals
> init_design
This step is to source the global file and run the init_design command to load the libraries and design.
You can open up gen_fbdiv_ftm.tcl and cut and paste the command. You might want to look at the
global file to see its content:
set
set
set
set
set
set
set
set
init_oa_design_cell {pll_fbdiv}
init_mmmc_file {scripts/pll_fbdiv.viewDefinition.tcl}
init_pwr_net {VDD}
init_gnd_net {VSS}

> setDesignMode -process 45
> source scripts/writeFTM_mmmc.tcl
Page 90 of 136
This step is to read writeFTM_mmmc.tcl in the TCL script. This text file contains a procedure,
writeFTMDataDir, which generates a SPEF file for each RC corner and a full Verilog netlist for the
block.
> setExtractRCMode -engine postRoute -effortLevel high lefTechFileMap
This step sets the extraction engine to postRoute stage and high-effort level before extracting the parasitic
RC of the wires.
> writeFTMDataDir pll_fbdiv_FTM
This step is run to create FTM (SPEF files and Verilog netlist) for the pll_fbdiv block under a directory
named pll_fbdiv_FTM.

ls pll_fbdiv_FTM/mmmc/ilm_data/pll_fbdiv
You will see the following files in the specified directory. The TCL script writeFTM_mmmc.tcl sourced
in the previous step helps to generate these files and place in the specific directory. In the later section of
this module, when you specify pll_fbdiv_FTM as the FTM block directory in Innovus, Innovus will
know where to pick up the netlist and the SPEF files from.
File name
Description
pll_fbdiv_postRoute_rc_best.spef.gz and gzipped SPEF files, one for each RC corner

pll_fbdiv_postRoute_rc_worst.spef.gz
(rc_best and rc_worst corners)
pll_fbdiv_postRoute.v.gz
gzipped verilog netlist of pll_fbdiv block

> exit
Page 91 of 136
2.4.2 Generating FTM for LP_pll_dig_combo block

ACTION 1: You can skip the manual steps by running the following statement (it automates the FTM
creation process for LP_pll_dig_combo block):
% innovus init scripts/gen_combo_ftm.tcl
Alternatively, to create the FTM in a step-by-step manner, start a new Innovus session by entering the
following in the UNIX command line:
% innovus
> source scripts/LP_pll_dig_combo.globals
> init_design
The content of the global file (LP_pll_dig_combo.globals) is:
set
set
set
set
set
set
set
set
init_oa_design_cell {LP_pll_dig_combo}
init_pwr_net {dvdd avdd avdd_h VDDsw}
init_gnd_net {dgnd agnd agnd_h}
init_mmmc_file {scripts/LP_pll_dig_combo.viewDefinition.tcl}

> assembleDesign block {zambezi45 LP_pll_dig_wSPI layout} -keepPinGeometry
Because the LP_pll_dig_combo block has a sub-block, LP_pll_dig_wSPI, which contains the digital
paths to be analyzed, this step is necessary to bring in the digital sub-block to a higher level so that the
instances and wires inside the sub-block are visible and extractable by Innovus.
> loadCPF scripts/LP_pll_dig_combo.cpf
Because the design after assembly has power domains with low power cells, Innovus needs to read and
commit the CPF. The next few actions are the same as done for the pll_fbdiv block.
Page 92 of 136
ACTION 5: In the Innovus command line, type the following commands:

> source scripts/writeFTM_mmmc.tcl
> setExtractRCMode -engine postRoute -effortLevel high lefTechFileMap
> writeFTMDataDir LP_pll_dig_combo_FTM
These steps are to create FTM for the LP_pll_dig_combo block under a directory named
LP_pll_dig_combo_FTM. You might want to type the following in the Innovus command line to check
that the FTM data is imported to the specified directory:
> ls LP_pll_dig_combo_FTM/mmmc/ilm_data/LP_pll_dig_combo

> exit
Page 93 of 136
2.4.3 Running timing analysis at the top level using FTM

% innovus
> source scripts/LP_pll.globals
> init_design
Source the global file and run the init_design command to load the libraries and design.
Note: You can cut and paste from ftm_sta.tcl in the scripts directory.
> setExtractRCMode -engine postRoute -effortLevel high -lefTechFileMap
> specifyIlm -cell LP_pll_dig_combo -dir LP_pll_dig_combo_FTM
> specifyIlm -cell pll_fbdiv -dir pll_fbdiv_FTM
> flattenIlm
The specifyIlm command is to instruct Innovus where to find the Verilog netlist and SPEF file for the
corresponding block. The flattenIlm command switches Innovus from the default blackbox mode into
ILM mode in which the netlist and SPEF of the FTM are read by Innovus. Under this mode, Innovus sees
the instances and nets inside the FTM blocks. Thus, the timer of Innovus is able to see the logical
connection from the instance inside the LP_pll_dig_wSPI block to another instance, pll_fbdiv block
(through the additional Verilog netlist provided by the FTM block). The RC parasitic information in the
FTM blocks is back-annotated by the timer of Innovus for timing delay calculation.
> loadCPF scripts/LP_pll.cpf
> setObjFPlanBox group PD_cal 8.4 384.73 91.6 442.92
> setObjFPlanBox group pd_avddlf_agndlf 189.455 377.31 212 398
This is for the floorplan shape for the power domains.
Page 94 of 136
ACTION 7: Display the layout window. In the Innovus command line, type:
> win
ACTION 8: On the top menu of Innovus, LMB Tools and select Design Browser. Type in I1/*pll* in
the Find Instance field of Design Browser and press the Enter key. *
This step is to show that Innovus has the netlist information of the digital block (LP_pll_dig_wSPI) in its
database. The hierarchical module for this is I1/u_pll_dig_wSPI. You might want to do the same for the
pll_fbdiv block by entering *fbdiv* in the Find Instance field of Design Browser.
ACTION 9: Dump out the Verilog netlist of the LP_pll block including the FTM netlist of the pll_fbdiv
and LP_pll_dig_combo FTM blocks. In the Innovus command line, type:
ilmView 1> saveNetlist ilm LP_pll_ilm.v
Note that the ilm option can only be run in the ILM mode (after flattenILM). This command can be
used to debug if the FTM netlist is being read into Innovus database properly.
Page 95 of 136

ilmView 2> update_constraint_mode -name PM_cal -ilm_sdc_files {scripts/LP_pll.sdc}
Once flattenIlm is run, Innovus enters into the ILM mode. In this mode, Innovus sees more instances and
nets due to the addition of netlist from the LP_pll_dig_combo and pll_fbdiv FTM blocks. Thus, you
have to specify the SDC file for the ILM mode, which is different from the default mode. Without doing
this step, when you report_timing later, Innovus will return:
No constrained timing paths found.

ilmView 3> set_global report_timing_format {instance arc cell delay arrival required annotation
voltage}
ilmView 4> report_timing -to |u_fbdiv/u_1_0/D
From the timing report, it can be seen that the instances in the lower-level hierarchy of the pure digital
block LP_pll_dig_wSPI (instance is I1/|u_pll_dig_wSPI) and custom digital block pll_fbdiv (the
instance name is |u_fbdiv) are visible from the timing perspective.
Page 96 of 136

ilmView 5> report_timing -from |u_fbdiv/u_divclk/CK
Endpoint:
|u_fbdiv/u_0_0/D
(^) checked with leading edge of 'clk_in'
Beginpoint: |u_fbdiv/u_divclk/QN (v) triggered by leading edge of 'clk_in'
Path Groups: {clk_in}
0.069
- Setup
0.109
+ Phase Shift
5.000
= Required Time
4.961
- Arrival Time
0.825
= Slack Time
4.136
Clock Rise Edge
0.000
0.069
+-------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
Arc
| Voltage |
|
|
|
|
| Time
|
Time
| Annotation |
|
|-------------------+--------------+----------+-------+---------+----------+------------+---------|
| |u_fbdiv/u_divclk | CK ^
|
|
|
0.069 |
4.206 |
SPEF | 1.080
|
| |u_fbdiv/u_divclk | CK ^ -> QN v | DFFRX2
| 0.357 |
0.427 |
4.563 |
SPEF | 1.080
|
| |u_fbdiv/I33
| A v -> Y v
| CLKBUFX8 | 0.081 |
0.507 |
4.643 |
SPEF | 1.080
|
| |u_fbdiv/u_0_4
| S0 v -> Y ^ | MX2X1
| 0.170 |
0.678 |
4.814 |
SPEF | 1.080
|
| |u_fbdiv/u_0_2
| B ^ -> Y ^
| MX2X1
| 0.147 |
0.825 |
4.961 |
SPEF | 1.080
|
| |u_fbdiv/u_0_0
| D ^
| DFFRX1
| 0.000 |
0.825 |
4.961 |
SPEF | 1.080
|
+-------------------------------------------------------------------------------------------------+
Page 97 of 136
Note: In the FTM approach, both the LP_pll_dig_combo and pll_fbdiv blocks are not physically
flattened (Innovus sees the timing perspective only through the Verilog netlist and SPEF). Thus, in the
layout window, you do not see the instances and wires of both the blocks appearing at the top level. This
is one of the main differences between the flat and FTM approaches.
The following table shows a comparison between the FTM and flat approaches.
FTM
Flat
Requirements on
Connectivity
(VXL-compliant)
Same
Same
Dealing
Physical
hierarchy
No assembleDesign on top level
Runs one or more assembleDesign till

the instances are seen on top level
How the block is

represented
The block is represented by a Verilog

netlist and SPEF file(s) for the RC
parasitic that makes it portable.
Does not require to write out the logical

connectivity in the Verilog netlist and
RC parasitic in the form of SPEF
Usability
Debugging
Useful only when the Verilog netlist

and SPEF file of a block (IP) are
available (no layout view is given)
Requires layout view of the block
with
and
Instances and timing path inside FTM

block are not visible in layout window
specifyILM
and
flattenILM
commands are to be run prior to
running report_timing.
Able to see instances on the layout

window
Does not require to create the FTM
block and understanding of the ILM
commands
Page 98 of 136

ilmView 6> unflattenIlm
This step is to return to the blackbox mode in which Innovus does not see the instances inside the FTM
block. You will expect to see some ERROR messages. (For example, ENCMSMV 1521 and ENCDB1212). These error messages are expected because, after unflattening, the instances inside the FTM blocks
are not visible. Hence, certain content of the CPF is not valid in the current blackbox mode.
> exit
Page 99 of 136
2.5
Running the flat approach using the auto-flattening assembleDesign

1) How to run assembleDesign to flatten the cellviews of more than one level of physical hierarchy
with one statement of the command.
2) How to run assembleDesign with the allTimingBlocks options that enable the auto-detection
and assembly of blocks with the digital content.
3) How to use the exceptBlocks option with the allTimingBlocks option to exclude blocks from
being flattened.
4) How the -allTimingBlocks option of assembleDesign decides as to which block to be flattened.
5) Where to look for information on how assembleDesign decides as to which block to be flattened.
Page 100 of 136
Running assembleDesign across multiple hierarchies

% cd AOT_STA/_auto_asm
% make setup
The content of load_init.tcl in the scripts directory is:
init_design
The diagram shows the physical hierarchy tree of the LP_pll design. In module 2.3, the assembleDesign
command is run twice to flatten two levels of physical hierarchy. The first assembleDesign flattens the
LP_pll_dig_combo and pll_fbdiv blocks. The second assembleDesign flattens the LP_pll_dig_wSPI
block. The reason for flattening each level separately is to let you analyze how assembleDesign changes
the physical and logical aspect of the design. In this module, you will learn to run assembleDesign once
to flatten to the required level.
> assembleDesign block { zambezi45 LP_pll_dig_combo layout} block {zambezi45
LP_pll_dig_wSPI layout} block {zambezi45 pll_fbdiv layout} keepPinGeometry
You can refer to scripts/flat_report.tcl and cut and paste from it.
> win
Page 101 of 136

> source scripts/report.tcl
loadCPF scripts/LP_pll.cpf
commitCPF -keepRows
setObjFPlanBox group pd_avddlf_agndlf 189.455 377.31 212 398
modifyPowerDomainAttr pd_avddlf_agndlf -addBlockBox {{I1/|u_ls_rst I1/|u_ls_ndiv(0)
I1/|u_ls_ndiv(1) I1/|u_ls_ndiv(2) I1/|u_ls_ndiv(3) I1/|u_ls_ndiv(4) I1/|u_ls_ndiv(5)
I1/|u_ls_ndiv(6)}}
setDesignMode -process 45
setExtractRCMode -engine postRoute -effortLevel signoff -lefTechFileMap
report_timing -to |u_fbdiv/u_1_0/D
Basically, this file loads the power domain definition and performs timing analysis.
Note that the RC extraction engine is set to postRoute and effort level is set to signoff. These two options
are set to give the highest level of accuracy and handle complex wire shapes previously implemented in
Virtuoso, located at lower level of physical hierarchy, but now, after the physical boundary is flattened by
assembleDesign, appear on the top level.
After sourcing the report.tcl into Innovus, the following report will be generated:
Endpoint:
|u_fbdiv/u_1_0/D
(v)
Path Delay
1.000
= Required Time
1.000
- Arrival Time
1.245
= Slack Time
-0.245
Clock Rise Edge
0.000
0.274
+----------------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
|
|
|
|
| Time
|
Time
|
|---------------------------------------------------+-------------+-----------+-------+---------+----------|
|
|
|
0.274 |
0.029 |
0.579 |
0.334 |
| I1/|u_ls_ndiv(1)
| A v -> Y v | LSLHX1_TO | 0.306 |
0.885 |
0.640 |
| |u_fbdiv/u_1_4
| A v -> Y v | MX2X1
| 0.221 |
1.106 |
0.861 |
| |u_fbdiv/u_1_2
| B v -> Y v | MX2X1
| 0.139 |
1.245 |
1.000 |
| |u_fbdiv/u_1_0
| D v
| DFFSX1
| 0.000 |
1.245 |
1.000 |
+----------------------------------------------------------------------------------------------------------+

> exit
Page 102 of 136
2.5.1 Running auto-mode of assembleDesign

> assembleDesign allTimingBlockskeepPinGeometry
You can cut and paste from scripts/auto_flat.tcl.
The allTimingBlocks option is to enable Innovus to perform automatic detection and flattening of the
block and sub-blocks at lower levels and have digital content.
> win
In the layout, you will notice that it flattens quite a few blocks.
If you scroll up the log file, you can see the summary:
*** assembleDesign summary ***
* Assembled 24 partition(s): LP_pll_dig_combo LP_pll_dig_wSPI pll_lpf
pll_lpf_decode1of16 pll_lpf_cal pll_lpf_cal_amp pll_lpf_cal_comp pll_lpf_cal_res
pll_lpf_amp pll_lpf_res pll_lpf_res_half pll_vcodiv pll_iqdiv2 pll_vco
pll_vco_cbank_half1 pll_vco_thermdecode pll_vco_cbank_half0 pll_vco_thermdecode
pll_vco_calsw pll_fbdiv pll_ls_dvdd2avdd pll_pfd pll_cp pll_cp_igen
Page 103 of 136
A GUI form will appear to prompt you to select the log file to view.
ACTION 5: If this is the second time of running Innovus, select innovus.logv1 and LMB Open. The
verbose log file provides more information for viewing and debugging.
The Log Viewer window will appear.
ACTION 6: LMB the + sign next to Innovus Starting Message to expand the messages.
You will see something similar to the following (the date and time will be different):
ACTION 7: LMB the + sign near **WARN:IMPPP-547):
Page 104 of 136
ACTION 9: Enter keepPin in the Find Text: field. LMB Search Backwards. Then, LMB the Find
Next button thrice.
The purpose of doing this is to view the reason why certain blocks are flattened while others are not. Only
the verbose log file provides such information.
Page 105 of 136
ACTION 10: Enter pll_pfd in the Find Text: field. Disable Search Backwards. Then, LMB the Find
Next button.
You will see the word highlighted in the following message:

Block zambezi45/pll_pfd/layout would be assembled as it has instance of standard
cell.
ACTION 11: Enter pll_reg/layout in the Find Text: field. Then, LMB the Find Next button.
Page 106 of 136

Block zambezi45/pll_reg/layout would NOT be assembled as it does not have any
instance of leaf cell or timing library cell inside.
This explains why the pll_reg block is not flattened. It is not flattened because there is no standard cell or
timing cell in this cellview at the current physical level and in cellviews or sub-block at lower physical
levels.
ACTION 12: Enter pll_fbdiv in the Find Text: field. Then, LMB the Find Next button.

Block zambezi45/pll_fbdiv/layout would be assembled as it has instance of timing
library cell.
ACTION 13: Enter vcodiv in the Find Text: field. Then, LMB the Find Next button.
You will see the word get highlighted in the following message:
Block zambezi45/pll_vcodiv/layout would be assembled as it has sub block
(zambezi45/pll_vco/layout) which is detected to be assembled.
This explains why the pll_vcodiv block is to be assembled. It is because its sub-block is detected to be
assembled. If you further trace the log file, you will notice that there is a cellview that has the instance of
standard cell at the lower level of physical hierarchy under the pll_vcodiv block.
Block zambezi45/pll_vco_thermdecode/layout would be assembled as it has instance of
standard cell
Some of these blocks have no timing path. You might want to instruct assembleDesign not to flatten
these. In the next section, you will learn how to do this by using the exceptBlocks option.
Page 107 of 136

This file is to load in the power domain specification and RC extraction setting, and it generates a timing
report. The tool will show the following timing report:
Endpoint:
|u_fbdiv/u_1_0/D
(v)
Path Delay
1.000
= Required Time
1.000
- Arrival Time
1.248
= Slack Time
-0.248
Clock Rise Edge
0.000
0.274
+----------------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
|
|
|
|
| Time
|
Time
|
|---------------------------------------------------+-------------+-----------+-------+---------+----------|
|
|
|
0.274 |
0.026 |
0.579 |
0.331 |
| I1/|u_ls_ndiv(1)
| A v -> Y v | LSLHX1_TO | 0.308 |
0.887 |
0.639 |
| |u_fbdiv/u_1_4
| A v -> Y v | MX2X1
| 0.222 |
1.108 |
0.861 |
| |u_fbdiv/u_1_2
| B v -> Y v | MX2X1
| 0.139 |
1.248 |
1.000 |
| |u_fbdiv/u_1_0
| D v
| DFFSX1
| 0.000 |
1.248 |
1.000 |
+----------------------------------------------------------------------------------------------------------+

> exit
Page 108 of 136
2.5.2 Running auto-mode of assembleDesign with exceptBlocks

option
> assembleDesign allTimingBlocks exceptBlocks { pll_lpf pll_vcodiv pll_reg pll_cp pll_pfd}
keepPinGeometry
> win
If you scroll up the log file, you can see the summary:
*** assembleDesign summary ***
* Assembled 4 partition(s): LP_pll_dig_combo LP_pll_dig_wSPI pll_fbdiv
pll_ls_dvdd2avdd
ACTION 5: If this is the third time running of Innovus, select innovus.logv2 and LMB Open.
Page 109 of 136
The Log Viewer window will appear.
ACTION 6: LMB the + sign next to Innovus Starting Message to expand the messages.
You will see something similar to the following (the date and time will be different):
ACTION 7: LMB the + sign near **WARN:IMPPP-547):
Page 110 of 136
ACTION 9: Enter pll_pfd in the Find Text: field. LMB Search Backwards. Then, LMB the Find Next
button once.
You will see the log Viewer highlight the word in the following sentence (expand the Log Viewer if
needed):
Block zambezi45/pll_pfd/layout would NOT be assembled as it is excluded by user.
The reason it is not flattened is that it is specifed as one of the blocks with the exceptBlocks option in
ACTION 2.
You will see the following report generated:
Endpoint:
|u_fbdiv/u_1_0/D
(v)
Path Delay
1.000
= Required Time
1.000
- Arrival Time
1.245
= Slack Time
-0.245
Clock Rise Edge
0.000
0.274
+----------------------------------------------------------------------------------------------------------+
|
Instance
|
Arc
|
Cell
|
|
|
|
| Time
|
Time
|
|---------------------------------------------------+-------------+-----------+-------+---------+----------|
|
|
|
0.274 |
0.029 |
0.579 |
0.334 |
| I1/|u_ls_ndiv(1)
| A v -> Y v | LSLHX1_TO | 0.306 |
0.885 |
0.640 |
| |u_fbdiv/u_1_4
| A v -> Y v | MX2X1
| 0.221 |
1.106 |
0.861 |
| |u_fbdiv/u_1_2
| B v -> Y v | MX2X1
| 0.139 |
1.245 |
1.000 |
| |u_fbdiv/u_1_0
| D v
| DFFSX1
| 0.000 |
1.245 |
1.000 |
+----------------------------------------------------------------------------------------------------------+

> exit
Page 111 of 136
2.6
Characterizing a custom digital logic gate to run STA

1) How to run Liberate to characterize a custom digital logic gate and generate the timing library files
for it.
2) How to modify viewDefinition.tcl to include the newly created timing library file to run STA.
3) Some simple debugging skills to check if a certain path is constrained and if an instance has a
timing library associated with it.
In this module, the goal is to time a path from |u_fbdiv/u_0_0 (launching register) to |u_fbdiv/u_cnteq0
(capturing register).
Page 112 of 136
2.6.1 "No constrained path" due to missing timing library

% cd LPAMS45_*/WORK/zambezi45/LPMS_WS/AOT_STA/_char_lib
% make setup
% innovus init scripts/flat.tcl
If you open up flat.tcl, you will see the following content. Basically, the script serves to load the LP_pll
design and flatten the |u_fbdiv (cell name is pll_fbdiv) block to run STA on a path inside the block.
source LP_pll.globals
init_design
assembleDesign - -block {zambezi45 pll_fbdiv layout} -keepPinGeometry
setExtractRCMode -engine postRoute -effortLevel high -lefTechFileMap

> report_timing -to |u_fbdiv/u_cnteq0/D
You can cut and paste from flat.tcl.
Innovus will report the following:
No constrained timing paths found.
Paths may be unconstrained (try '-unconstrained' option).
There are many possible reasons for Innovus to report this message. If there is no create_clock statement
in the timing constraint file that drives the two registers or no constraint like set_max_delay that
constrains the timing path, Innovus will report that it finds no valid constrained timing path to the pin D
of the |u_fbdiv/u_cnteq0 instance.
It is also possible that there is a create_clock statement in the timing constraint file intended for this
timing path. However, the instance name or pin name referenced in the create_clock statement in the
timing constraint file might not match the one in the layout.
For examples, the statement in the timing constraint file for the two cases might be the following:
case1: "create_clock -name clk_in -period 5 [get_pins u_fbdiv/clkin]"
case2 : "create_clock -name clk_in -period 5 [get_pins |u_fbdiv/clk_in]"
Page 113 of 136
However, in the design, the instance name is |u_fbdiv and the pin name is clkin.
In both cases, the create_clock statement will be rejected by Innovus.
As a result, Innovus still finds no constrained timing path to the D pin of the |u_fbdiv/u_cnteq0 instance.
Another possibility is that the path between the two registers are broken due to missing timing library for
any of the instances along the path. Without the timing library that represents each instance, Innovus is
not able to "trace" through these and see valid connections between each instance that forms a timing
path.
To check if the launching and capturing registers are constrained, run the following tests to debug the
issue:
> report_timing -from |u_fbdiv/u_cnteq0/CK
You can cut and paste from flat.tcl.
You will see the following report:
Path 1: MET Setup Check with Pin |u_fbdiv/u_divclk/CK
Endpoint:
|u_fbdiv/u_divclk/D (^) checked with leading edge of 'clk_in'
Beginpoint: |u_fbdiv/u_cnteq0/Q (^) triggered by leading edge of 'clk_in'
0.069
- Setup
0.111
+ Phase Shift
5.000
= Required Time
4.958
- Arrival Time
0.535
= Slack Time
4.423
Clock Rise Edge
0.000
0.069
+------------------------------------------------------------------------+
|
Instance
|
Arc
| Cell
|
|
|
|
| Time
|
Time
|
|-------------------+-------------+---------+-------+---------+----------|
| |u_fbdiv/u_cnteq0 | CK ^
|
|
|
0.069 |
4.492 |
| |u_fbdiv/u_cnteq0 | CK ^ -> Q ^ | DFFRX4 | 0.303 |
0.372 |
4.795 |
| |u_fbdiv/u_xnor
| A ^ -> Y ^ | XNOR2X1 | 0.163 |
0.535 |
4.958 |
| |u_fbdiv/u_divclk | D ^
| DFFRX2 | 0.000 |
0.535 |
4.958 |
+------------------------------------------------------------------------+
This shows that there is a clock, clk_in, which drives the clock pin (CK) of the capturing register
(|u_fbdiv/u_cnteq0). Do the same for the launching register (|u_fbdiv/u_0_0).
Page 114 of 136

> report_timing -from |u_fbdiv/u_0_0/CK

Endpoint:
|u_fbdiv/u_0_0/D (^) checked with leading edge of 'clk_in'
Beginpoint: |u_fbdiv/u_0_0/QN (^) triggered by leading edge of 'clk_in'
0.069
- Setup
0.109
+ Phase Shift
5.000
= Required Time
4.961
- Arrival Time
0.529
= Slack Time
4.432
Clock Rise Edge
0.000
0.069
+---------------------------------------------------------------------+
|
Instance
|
Arc
| Cell | Delay | Arrival | Required |
|
|
|
|
| Time
|
Time
|
|----------------+--------------+--------+-------+---------+----------|
| |u_fbdiv/u_0_0 | CK ^
|
|
|
0.069 |
4.501 |
| |u_fbdiv/u_0_0 | CK ^ -> QN ^ | DFFRX1 | 0.315 |
0.384 |
4.816 |
| |u_fbdiv/u_0_2 | A ^ -> Y ^
| MX2X1 | 0.145 |
0.529 |
4.961 |
| |u_fbdiv/u_0_0 | D ^
| DFFRX1 | 0.000 |
0.529 |
4.961 |
+---------------------------------------------------------------------+
The result shows that the capturing register, |u_fbdiv/u_0_0, is also driven by the same clock (clk_in).
To confirm once again, you might want to open the timing constraint file and verify if the following is
there in LP_pll.sdc in the scripts directory.
create_clock -name clk_in -period 5 [get_pins |u_fbdiv/clkin]
Page 115 of 136

> report_timing -to |u_fbdiv/u_cnteq0/D -unconstrained
You will see the following report:
Path 1:Endpoint:
|u_fbdiv/u_cnteq0/D (v)
Beginpoint: |u_fbdiv/u_0_3/Y
(v) (unconstrained input)
Arrival Time
0.000
+------------------------------------------------------+
|
Instance
| Arc | Cell | Delay | Arrival |
|
|
|
|
| Time
|
|-------------------+-------+--------+-------+---------|
| |u_fbdiv/u_0_3
| Y v
|
|
|
0.000 |
| |u_fbdiv/u_cnteq0 | D v
| DFFRX4 | 0.000 |
0.000 |
+------------------------------------------------------+
From this, it appears that Innovus can only back trace from the capturing register (|u_fbdiv/u_cnteq0) to
the output pin (Y) of the instance (|u_fbdiv/u_0_3). Apparently, Innovus is not able to back trace the
instance (|u_fbdiv/u_0_3) from its output pin (Y) to its input pin, which leads to a broken path. Check if
the instance, |u_fbdiv/u_0_3, has a timing library associated with it by running a command called
report_instance_library.

> report_instance_library instance |u_fbdiv/u_0_3
Instance
Analysis View
Power Domain
Op Cond
:
:
:
:
|u_fbdiv/u_0_3
av_max
P->1.000000, V->1.080000, T->125.000000 (1v08_max_oc_virtual)
The result shows that there is no timing library associated with it.
Page 116 of 136
ACTION 8: On the top menu of Innovus, LMB Tools and select Design Browser. Type
|u_fbdiv/u_0_3 and hit the Enter key. This is done to find out the relevant cell name and pin names. Note
that the cell name is NOR3X1c and it has A, B and C as the input pins and Y as the output pin. You will
use this information in a later section.

> all_library_sets
Innovus will return the following:
1v32_min 1v08_max
This shows that there are two library_sets created: 1v32_min and 1v08_max.
If you open up LP_pll.viewDefinition.tcl in the scripts directory, you will see the following content:
create_library_set -name 1v32_min\
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/fast_vdd1v2.lib]
create_library_set -name 1v08_max\
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/slow_vdd1v2.lib]
LP_pll.viewDefinition.tcl is specified in the LP_pll.globals file (the first statement in flat.tcl, the script
you loaded in the previous steps) using the following command:
set init_mmmc_file {scripts/LP_pll.viewDefinition.tcl}
Next, you will find out the location of the library files specified under these library sets.
Page 117 of 136

> get_library_set 1v32_min -timing
Innovus will return:
<your_workshop_installation_directory>/sta_aot_v07/LPAMS45_121112_1717
/LIBS/GPDK045/gsclib045/timing/fast_vdd1v2.lib
If you install this workshop in the /grid/ws directory, Innovus will return the following:
/grid/ws/sta_aot_v07/LPAMS45_121112_1717/LIBS/GPDK045/gsclib045/timing/fast_vdd1v2.li
b

> get_library_set 1v08_max -timing
<your_workshop_installation_directory>/sta_aot_v07/LPAMS45_121112_1717/LIBS/GPDK045/g
sclib045/timing/slow_vdd1v2.lib
After determining the location of the timing library files, use the result to check if the cell NOR3X1c
exists in these timing library files.
% grep NOR3X1c <your_workshop_install_location>/sta_aot_v07/LPAMS45_121112_1717
/LIBS/GPDK045/gsclib045/timing/*.lib
The result will show that nothing is found. This exercise is to verify that you do not have this timing
information of this cell in your existing timing library files. This explains why Innovus reports "No
constrained timing paths found." Due to the missing library cell, Innovus cannot trace through the
cell NOR3X1c and sees a broken path between the two registers. In the next two sub-sections, you will
use Liberate to generate a timing library for this cell.
> exit
Page 118 of 136
2.6.2 Generating template file for Liberate

ACTION 1: Open up write_template.tcl in the scripts directory to view its content. This is the script to
be run with Liberate to create a template file.
set PROJECT
$env(PROJECT)
read_library $PROJECT/LIBS/GPDK045/gsclib045/timing/slow_vdd1v2.lib
write_template -verbose -cells {NOR3X1} template_base
Liberate requires a template file that defines the loads and input slews to use during characterization. In
this exercise, you will extract template information from the timing library file you have and reuse it for
the characterization of the cell NOR3X1c.
In this case, a standard cell, NOR3X1, in your timing library file appears to be similar to the custom logic
gate you want to characterize. Thus, you make use of this cell.
Note: It does not matter if you find any cell in the existing library similar to the cell you want to
characterize. The templates in the timing library file apply to all cells. Here, it happens that there is a cell
similar to the gate you want to characterize, so you pick this cell. If no similar cell can be found, just pick
another cell.
ACTION 2: Run Liberate to generate the template. In the UNIX command line, type:
% liberate scripts/write_template.tcl |& tee gen_template.log
A file called template_base.tcl will be created in the current working directory. You will copy this file
and modify it to make it the template file used for the characterization of the NOR3X1c cell.
% cp template_base.tcl scripts/template.tcl
Page 119 of 136
ACTION 4: Use your preferred text editor to modify the content of template.tcl in the scripts directory:
1) Delete all statements after the define_cell section.
2) Replace all the cell names of NOR3X1 with NOR3X1c.
3) Remove set_var statements for the following:
set_var
set_var
set_var
set_var
def_arc_msg_level
max_transition 2.8e-10
min_transition 8e-12
min_output_cap 8e-15
Eventually, you only need the following content:

set_var
set_var
set_var
set_var
slew_lower_rise
slew_lower_fall
slew_upper_rise
slew_upper_fall
0.1
0.1
0.9
0.9
set_var
set_var
set_var
set_var
measure_slew_lower_rise
measure_slew_lower_fall
measure_slew_upper_rise
measure_slew_upper_fall
set_var
set_var
set_var
set_var
delay_inp_rise
delay_inp_fall
delay_out_rise
delay_out_fall
0.1
0.1
0.9
0.9
0.5
0.5
0.5
0.5
set cells { \
NOR3X1c \
}
define_template -type delay \
-index_1 {0.008 0.04 0.08 0.12 0.16 0.224 0.28 } \
-index_2 {0.01 0.016 0.05 0.08 0.12 0.2 0.25 } \
delay_template_7x7
define_template -type power \
-index_1 {0.008 0.04 0.08 0.12 0.16 0.224 0.28 } \
-index_2 {0.01 0.016 0.05 0.08 0.12 0.2 0.25 } \
power_template_7x7
define_cell \
-input { A B C } \
-output { Y } \
-pinlist { A B C Y } \
-delay delay_template_7x7 \
-power power_template_7x7 \
NOR3X1c
Note: There is a template_ref.tcl in the scripts directory for your reference.
Page 120 of 136
Here is some explanation of the parameters and commands specified:

The slew_* parameters are used to control how output transition times are stored in the delay tables. In
this case, choose the threshold points to be at 10 to 90 percent of the output waveform. It is possible to
have these parameters set to a value different from the measure_slew_* parameters. For example, if the
slew_* parameters are set to the threshold points of 0.1 to 0.9 and the measure_slew_* parameters are set
to the threshold points of 0.3 to 0.7, the resulting timing library file will have the
slew_derate_from_library attribute to be 0.5 and slew_*_threshold_pct_* to be 30 to 70 (equivalent to
the measure_slew_* parameters multiplied by 100).
The measure_slew_* parameters are used to control how the output transition times are measured after
the SPICE simulation. In this case, choose the threshold points to be at 10 to 90 percent of the output
waveform.
The delay_* parameters set the input and output rising and falling transition crossing-points to measure
delays. In this case, the threshold points have been chosen to be at 50 percent of the input and output
waveforms.
The delay template type is used for the cell delay and output transition characterization using input slew
and output load.
The power template type is used for switching and hidden (internal) power characterization using input
slew and output load.
The define_cell command contains the minimum information needed to characterize a cell. It provides the
cell name, pin name and pin type. It has the load/slew template definitions for the characterization of the
cell delay, output_transition, switching power and internal power for the cell NOR3X1c.
Page 121 of 136
2.6.3 Running Liberate to characterize the cell

ACTION 1: Open the script char_worst.tcl in the scripts directory. The purpose of each section is
explained in the comment line:
set
set
set
set
WORK_DIR
IN_DIR
OUT_DIR
SCRIPTS_DIR
[pwd]
${WORK_DIR}/data
${WORK_DIR}/out
${WORK_DIR}/scripts
# specify names of power and ground net and their respective voltage
# names are from netlist of cells
set_vdd VDD 1.08
set_gnd VSS 0.00
# specify temperature and default voltage
# these values go into operating_conditions group in .lib file
set_operating_condition -voltage 1.08 -temp 125
# source template for cells
source $SCRIPTS_DIR/template.tcl
# specify cell list for characterization and
# override cell list read from template
set cells { \
NOR3X1c \
}
# specify spice model (worst (SS) corner)
# spice model file must be in absolute directory
set spice "${IN_DIR}/model_ss"
# create list of spice netlist for all cells
foreach cell $cells {
lappend spice "${IN_DIR}/${cell}.spx"
}
# specify directory for all spice simulation related files to be saved
set_var extsim_deck_dir ${OUT_DIR}/decks_SLOW
# save all SPICE decks and
set_var extsim_save_passed
# save all SPICE decks and
set_var extsim_save_failed
listings for successful simulations

all
listings for failing simulations
all
# include spice model in spide deck using ".inc/include" constructs

#set_var extsim_model_include "${IN_DIR}/model_ss"
# set this variable to 0 so that cell netlist file is not flattened
# in the netlist in the generated spice and
# .inc SPICE command is used to load cell netlist file
# when define_leafcell command exists.
set_var extsim_flatten_netlist 0
# stop at these leafcells when parsing the spice model
define_leafcell -type nmos {g45n1svt}
Page 122 of 136
define_leafcell -type
pmos {g45p1svt}
# read spice model and netlist

read_spice -format spectre $spice
# characterize cells using spectre simulator
char_library -cells $cells -extsim spectre
# write Liberate internal database into file for later use.
write_ldb ${OUT_DIR}/ldb.ldb
# write lib consisting of NLDM timing and power
write_library -cells $cells -user_data $USER_DATA -overwrite -filename
${OUT_DIR}/customlogic_worst.lib customlogic_worst
To summarize, the following inputs files are needed to run the characterization:
1) TCL command file to run Liberate
2) Template file
3) Spice model files of each corner
4) Extracted spice netlist for the cells to be characterized
5) User data attribute file if including the additional attributes and overriding the attributes in the
generated .lib file are desired
Note: A NLDM (Non Linear Delay Model) timing library has been generated in this case. Liberate also
supports the ECSM (Effective Current Source Model) and CCS (composite current source) models.
ACTION 2: Run Liberate to generate a timing library for the worst (slowest) delay corner. In the UNIX
command line, type:
% liberate scripts/char_worst.tcl |& tee char_worst.log
Liberate will generate a timing library, customlogic_worst.lib, in the out directory.
Open up this library file and search for the area. You will see the following statement:
cell (NOR3X1c) {
area : 0;
cell_leakage_power : 0.0461599;
leakage_power () {
Apparently, it indicates that the cell has 0 area. This is because, by characterization, you can only
calculate values that can come through simulations. But for the attributes like the area or footprint (not
shown in this workshop), these pieces of information do not come out from characterization. To override
the attribute or to include additional attribute, you need to create a file that specifies the attribute and uses
the user_data option of write_library to do the job. This file is already created in the scripts directory
and is named user_data_worst.lib.
Page 123 of 136
ACTION 3: Open up user_data_worst.lib in the scripts directory:

library (user_data) {
delay_model : table_lookup;
in_place_swap_mode : match_footprint;
power_supply () {
default_power_rail : RAIL_VDD;
power_rail( RAIL_VDD, 1.08 );
power_rail( RAIL_VSS, 0 );
}
cell (NOR3X1c) {
area : 1.710000;
rail_connection( VDD,
rail_connection( VSS,
pin(A) {
input_signal_level :
}
pin(Y) {
output_signal_level
}
pin(B) {
}
pin(C) {
}
}
}
RAIL_VDD );
RAIL_VSS );
RAIL_VDD;
: RAIL_VDD;
RAIL_VDD;
RAIL_VDD;
Assume the area to be 1.71 unit (copy from the NOR3X1 cell in the existing timing library file). You
want to add additional attribute to the library and the cell. All this information is specified in this file.
ACTION 4: Open up the script, write_lib_worst.tcl, in the scripts directory to view the content. This
file will be used to run with Liberate to update the attributes.
set WORK_DIR
[pwd]
set OUT_DIR
${WORK_DIR}/out
set SCRIPTS_DIR ${WORK_DIR}/scripts
set cells { \
NOR3X1c \
}
# write Liberate internal database into file for later use.
read_ldb ${OUT_DIR}/worst_ldb.ldb
# for updating library and cell attributes with user data library file
set USER_DATA ${SCRIPTS_DIR}/user_data_worst.lib
# write lib consisting of NLDM timing and power
Page 124 of 136
write_library -cells $cells -user_data $USER_DATA -overwrite -filename

${OUT_DIR}/customlogic_worst.lib customlogic_worst
# write datasheet
exec mkdir -p ${OUT_DIR}/DATASHEET
write_datasheet -format text -conditional -dir ${OUT_DIR}/DATASHEET -cells $cells filename ${OUT_DIR}/DATASHEET/customlogic_worst.txt customlogic_worst
# writing verilog models
write_verilog -cells $cells ${OUT_DIR}/verilog.v
You have run the characterization in the previous step and saved the characterized database as
worst_ldb.ldb. In this script, you only reload the saved database, worst_ldb.ldb, and write the timing
library again with the user_data option. In this script, you also instruct Liberate to write out the
datasheet and Verilog file for this cell.
ACTION 5: Run Liberate to generate a timing library for the worst (slowest) delay corner with the user
data attributes included. In the UNIX command line, type:
% liberate scripts/write_lib_worst.tcl |& tee write_lib_worst.log
You might want to open up again the timing library file, customlogic_worst.lib, and spot the difference.
For example, the NOR3X1c cell has more attributes now as shown here:
cell (NOR3X1c) {
area : 1.71;
cell_leakage_power : 0.0461599;
rail_connection (VDD, RAIL_VDD);
rail_connection (VSS, RAIL_VSS);
leakage_power () {
ACTION 6: Run Liberate to generate a timing library for the best (fastest) delay corner. In the UNIX
command line, type:
% liberate scripts/char_best.tcl |& tee char_best.log
You might want to view the content of char_best.tcl. Most of the statements are similar to
char_worst.tcl. The key differences will be the operating_condition (voltages and temperate) and the
spice model files.
set_operating_condition -voltage 1.32 -temp 0
set spice "${IN_DIR}/model_ff"
Note that, for the best corner, the same spice netlist file for NOR3X1c is being used. In this case, you will
use the typical case and assume that the variation of the parasitic RC in the logic gate is negligible. For
better accuracy, the different corners of the spice netlist file for the cells to be characterized should be
used.
In this script, go ahead to write the timing library file with the user data attributes.
Page 125 of 136
After the run, as a simple check, you might want to open up the timing library file for the fast corner,
customlogic_best.lib, and verify the timing numbers are faster than that of customlogic_worst.lib.
For example, the cell_rise table of the NOR3X1c cell in customlogic_worst.lib is:
cell_rise (delay_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.271509, 0.406082, 1.16857, 1.84133, 2.73834, 4.53236, 5.65344", \
"0.282981, 0.4176, 1.18017, 1.85292, 2.75017, 4.54401, 5.66509", \
"0.295624, 0.430304, 1.19294, 1.86585, 2.76278, 4.55675, 5.67789", \
"0.307321, 0.442058, 1.20474, 1.87756, 2.7746, 4.56865, 5.6897", \
"0.318524, 0.453267, 1.21603, 1.88886, 2.78587, 4.57996, 5.70106", \
"0.335802, 0.470574, 1.23342, 1.90628, 2.8035, 4.59739, 5.71847", \
"0.350773, 0.485489, 1.24839, 1.92124, 2.81837, 4.61245, 5.73351" \
For the same type of table in customlogic_best.lib, the values are:

cell_rise (delay_template_7x7) {
index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");
index_2 ("0.01, 0.016, 0.05, 0.08, 0.12, 0.2, 0.25");
values ( \
"0.0976801, 0.146242, 0.421291, 0.663902, 0.987441, 1.63454, 2.03885", \
"0.102905, 0.151538, 0.426674, 0.669343, 0.992878, 1.63998, 2.0443", \
"0.108178, 0.15681, 0.432034, 0.674743, 0.998264, 1.64544, 2.04971", \
"0.113241, 0.161889, 0.437217, 0.679823, 1.00343, 1.65051, 2.05484", \
"0.118337, 0.166936, 0.442243, 0.684969, 1.00854, 1.65567, 2.06001", \
"0.126296, 0.175143, 0.450362, 0.69291, 1.01648, 1.66358, 2.0679", \
"0.132614, 0.182434, 0.45749, 0.70027, 1.02392, 1.67092, 2.07534" \
Page 126 of 136
2.6.4 Running Innovus with the newly created timing library

% cp scripts/LP_pll.viewDefinition.tcl scripts/LP_pll.viewDefinition2.tcl
ACTION 2: Modify the content of the file LP_pll.viewDefinition2.tcl in the scripts directory.
Insert the newly created timing library file names with location (out/custom_best.lib and
out/custom_worst.lib) in the create_library_set statements for 1v32_min and 1v08_max library sets,
respectively.
Original statements:
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/fast_vdd1v2.lib]
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/slow_vdd1v2.lib]
Amended statements:
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/fast_vdd1v2.lib\
out/customlogic_best.lib]
-timing\
[list $PROJECT/LIBS/GPDK045/gsclib045/timing/slow_vdd1v2.lib\
out/customlogic_worst.lib]
Note: There is already a file, LP_pll.viewDefinition2_ref.tcl, stored in the scripts directory for your
reference.
% cp scripts/flat.tcl scripts/flat2.tcl
The script, flat2.tcl, will be used later to run Innovus with the added timing library files.
Page 127 of 136
ACTION 4: Add the following statement after assembleDesign:

source scripts/LP_pll.viewDefinition2.tcl
Original statement:
assembleDesign block {zambezi45 pll_fbdiv layout} -keepPinGeometry
setDesignMode process 45
Amended statement:
assembleDesign block {zambezi45 pll_fbdiv layout} -keepPinGeometry
source scripts/LP_pll.viewDefinition2.tcl}
setDesignMode process 45
The purpose of doing this is to get Innovus to read a new viewDefinition.tcl. This new viewDefinition.tcl
(LP_pll.viewDefinition2.tcl) has the amended library sets that contain the newly characterized timing
library files. After this, you are ready to run Innovus and will see the difference.
Note: There is already a file, flat2_ref.tcl, stored in the scripts directory for your reference.
% innovus init scripts/flat2.tcl
> report_instance_library instance |u_fbdiv/u_0_3
Instance
: |u_fbdiv/u_0_3
Analysis View
: av_max
Power Domain
: pd_avddlf_agndlf
Library/Libset(early) : customlogic/1v08_max
Library File (early) :
<your_workshop_installation_directory>/sta_aot_v07/LPAMS45_121112_1717/WORK/zambezi45
/LPMS_WS/AOT_STA/_char_lib/out/customlogic_worst.lib
Library/Libset(late) : customlogic/1v08_max
Library File (late) :
/LPMS_WS/AOT_STA/_char_lib/out/customlogic_worst.lib
Op Cond
: P->1.000000, V->1.080000, T->125.000000 (1v08_max_oc_virtual)
Cell Type
: gateCell
This exercise is to verify that the |u_fbdiv/u_0_3 instance has a timing library (customlogic_worst.lib)
associated with it.
Page 128 of 136

> report_instance_library instance |u_fbdiv/u_0_3 view av_min
Instance
: |u_fbdiv/u_0_3
Analysis View
: av_min
Power Domain
: pd_avddlf_agndlf
Library/Libset(early) : customlogic_best/1v32_min
Library File (early) :
/LPMS_WS/AOT_STA/_char_lib/out/customlogic_best.lib
Library/Libset(late) : customlogic_best/1v32_min
Library File (late) :
/LPMS_WS/AOT_STA/_char_lib/out/customlogic_best.lib
Op Cond
: P->1.000000, V->1.320000, T->0.000000 (1v32_min_oc_virtual)
Cell Type
: gateCell
This exercise is to verify that the instance is associated with a timing library (customlogic_best.lib) in the
best corner that belongs to the analysis view av_min. After verification, you are good to go.
> report_timing -to |u_fbdiv/u_cnteq0/D
Path 1: MET Setup Check with Pin |u_fbdiv/u_cnteq0/CK
Endpoint:
|u_fbdiv/u_cnteq0/D (^) checked with leading edge of 'clk_in'
Beginpoint: |u_fbdiv/u_0_0/Q
(v) triggered by leading edge of 'clk_in'
0.069
- Setup
0.126
+ Phase Shift
5.000
= Required Time
4.944
- Arrival Time
0.422
= Slack Time
4.522
Clock Rise Edge
0.000
0.069
+------------------------------------------------------------------------+
|
Instance
|
Arc
| Cell
|
|
|
|
| Time
|
Time
|
|-------------------+-------------+---------+-------+---------+----------|
| |u_fbdiv/u_0_0
| CK ^
|
|
|
0.069 |
4.592 |
| |u_fbdiv/u_0_0
| CK ^ -> Q v | DFFRX1 | 0.277 |
0.346 |
4.868 |
| |u_fbdiv/u_0_3
| B v -> Y ^ | NOR3X1c | 0.076 |
0.422 |
4.944 |
| |u_fbdiv/u_cnteq0 | D ^
| DFFRX4 | 0.000 |
0.422 |
4.944 |
+------------------------------------------------------------------------+

> exit
Page 129 of 136
2.7
Running STA on OA-based design using Tempus

1) Prepare and load an OA design into Tempus.
2) Run signoff extraction using standalone Quantus QRC through the interface in Tempus.
3) Run timing analysis in Tempus with an OA-based design.
Page 130 of 136
2.7.1 Creating a flattened OA-based design for Tempus using Innovus

% cd LPAMS45_*/WORK/zambezi45/LPMS_WS/AOT_STA/_tempus_sta
% make setup
% innovus init scripts/asm_save.tcl
You might want to view the content of asm_save.tcl in the scripts directory. The script will look familar
if you have gone through the sub-module 2.3 (running STA on AOT design in Innovus using the flat
approach). The LP_pll.globals file shown in the first statement of this script contains the specification of
a file, LP_pll.viewDefinition.tcl. This LP_pll.viewDefinition file is required to run timing analysis. It
provides information such as timing library specification, QRC technology file specification, RC corners,
timing constraint file and other timing related specifications to be used later by Tempus. Another key
purpose of this script (asm_save.tcl) is to flatten the blocks of interest in the design to the required levels
and to save it into a new design. The new design that contains the logical and physical information of the
flattened blocks together with the top level design information will be loaded by Tempus in the later
section to run RC extraction and timing analysis. The content of asm_save.tcl are:
init_design
assembleDesign -block {zambezi45 LP_pll_dig_combo layout} -block {zambezi45 pll_fbdiv
layout} -keepPinGeometry
assembleDesign -block {zambezi45 LP_pll_dig_wSPI layout} -keepPinGeometry
loadCPF scripts/LP_pll.cpf
commitCPF -keepRows
setObjFPlanBox group pd_avddlf_agndlf 189.455 377.31 212 398
modifyPowerDomainAttr pd_avddlf_agndlf -addBlockBox {|u_pfd}
modifyPowerDomainAttr pd_avddlf_agndlf -addBlockBox {{I1/|u_ls_rst I1/|u_ls_ndiv(0)
I1/|u_ls_ndiv(1) I1/|u_ls_ndiv(2) I1/|u_ls_ndiv(3) I1/|u_ls_ndiv(4) I1/|u_ls_ndiv(5)
I1/|u_ls_ndiv(6)}}
saveDesign -cellview {designLib LP_pll asm}
exit
Page 131 of 136
2.7.2 Running QRC extraction and timing analysis in Tempus

ACTION 1: Invoke Tempus. In the UNIX command line, type:
% tempus
ACTION 2: On the top menu of Tempus, LMB File and select Read Design
LMB File
Select Read Design

ACTION 3: In the Restore Design form, LMB the red arrow button on the right of each field to select
the following names for the Library, Cell and View specifications. LMB Read Physical Data so that
the read tick appears inside the box.
Library: zambezi45
Cell:
LP_pll
View: asm
LMB the OK button when all the entries are done.
Page 132 of 136
Instead of making entries through the GUI, alternatively, you can type the following in the Tempus
command line:
tempus > source scripts/tempus_load.tcl
This script has the following content:
read_design -physical_data -cellview {zambezi45 LP_pll asm}
Specifying the -physical_data option or clicking the Read Physical Data button in the GUI form means
that the Tempus will read in the physical data and you can view the layout in Tempus.
Once the design is loaded, the schematic of the design will be shown.
ACTION 4: LMB the + sign next to the Schematic tab.
LMB the + sign and select Layout.
You will see the layout of the LP_pll design and a table on the right for you to control the layer display.
Move the mouse pointer to the layout and type f to fit the display.
Page 133 of 136
ACTION 5: In the Tempus command line, type:

tempus 1 > set_extract_rc_mode -lefTechFileMap scripts/QRC_LEF.layermap_10lm.new
To run QRC, it requires a QRC technology file. It is possible that the layer names contained in this file do
not match with the layer names in the OA tech file (or the LEF file for the lef flow).
The lefTechFileMap option is specified to provide a layer mapping file to map the layers specified in
the Techfile and the layer specified in the QRC techfile.
ACTION 6: Run RC extraction using standalone QRC. In the Tempus command line, type:
tempus 2> extract_rc
ACTION 7: In the Tempus command line, type:
tempus 3 > report_timing -to |u_fbdiv/u_1_0/D
Endpoint:
|u_fbdiv/u_1_0/D
(v)
Beginpoint: I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]/Q (v) triggered by leading edge of 'dsmclk'
Path Delay
1.000
= Required Time
1.000
- Arrival Time
1.245
= Slack Time
-0.245
Clock Rise Edge
0.000
0.274
-----------------------------------------------------------------------------------------Instance
Arc
Cell
Delay
Arrival
Required
Time
Time
-----------------------------------------------------------------------------------------I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]
CK ^
0.274
0.029
I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]
CK ^ -> Q v
SDFFRHQX1
0.305
0.579
0.334
I1/|u_ls_ndiv(1)
A v -> Y v
LSLHX1_TO
0.306
0.885
0.640
|u_fbdiv/u_1_4
A v -> Y v
MX2X1
0.221
1.106
0.861
|u_fbdiv/u_1_2
B v -> Y v
MX2X1
0.139
1.245
1.000
Page 134 of 136

|u_fbdiv/u_1_0
D v
DFFSX1
0.000
1.245
1.000
------------------------------------------------------------------------------------------
ACTION 8: Exit Tempus. In the Tempus command line, type:

tempus > exit
Page 135 of 136
Conclusion and future work
The following are the key points of doing STA in schematic-based mixed signal design workshop:
Use initDesign of Innovus or its Design Import GUI form to import a design originally
implemented in Virtuoso.
Use assembleDesign of Innovus to flatten the physical hierarchy of the design to the level where
the instances to be analyzed are visible to Innovus.
Use specifyIlm and flattenIlm of Innovus to specify the FTM blocks and switch to the ILM mode
to run timing analysis.
Use saveDesign of Innovus to prepare and save a flattened OA-based design for Tempus.
Use read_design or Restore Design GUI form of Tempus to load up the saved OA design.
The names of the objects (for example, instance and pin name) referenced in the timing constraint
file must match the actual naming in the layout of the design.
To ensure Innovus sees the connectivity of the design, the design must be VXL-compliant (VXL
must be used) and the database must be OA based.
In the future, the following module will be added to this workshop:
A module that explains why the logical hierarchy (schematics) of the design must match with
physical hierarchy of the design for the timing constraints (if the timing constraints are derived
from schematics) to be acceptable by Innovus.
Page 136 of 136

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Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

Static Timing Analysis on

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2002-2016 Cadence Design Systems, Inc. All rights reserved.

All other trademarks are the property of their respective holders.

in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

WORKSHOP OVERVIEW ................................................................................................................5

OBJECTIVE OF THE WORKSHOP......................................................................................................................................... 5

OVERVIEW OF THE MODULES ........................................................................................................................................... 6

DESIGN AND PROCESS NODE ............................................................................................................................................. 8

1.3.1 Blocks of interest.......................................................................................................................................................... 8

DATABASE STRUCTURE .................................................................................................................................................. 11

WORKSHOP SETUP .......................................................................................................................................................... 12

RUNNING OADBCHECKER ............................................................................................................................................. 13

2.1.1 Finding the location of oaDBChecker SKILL script .................................................................................................. 14

SETTING UP THE DESIGN FOR ANALYSIS IN INNOVUS ...................................................................................................... 35

2.3.1 Examining the design ................................................................................................................................................. 63

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2.3.3 Assembling the second level ...................................................................................................................................... 71

2.4.1 Generating FTM for pll_fbdiv block .......................................................................................................................... 90

Running assembleDesign across multiple hierarchies ..................................................................................................... 101

CHARACTERIZING A CUSTOM DIGITAL LOGIC GATE TO RUN STA.................................................................................. 112

RUNNING STA ON OA-BASED DESIGN USING TEMPUS ................................................................................................. 130

CONCLUSION AND FUTURE WORK .......................................................................................136

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

Objective of the Workshop

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

Overview of the Modules

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

Design and process node

1.3.1 Blocks of interest

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

1.3.2 Timing paths of interest

I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[0]/CK -to |u_fbdiv/u_0_0/D

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

ACTION 1: Untar the database to generate sta_aot_v07/LPAMS45_*/ directory (* stands for

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

In this module, you will learn how to:

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2.1.1 Finding the location of oaDBChecker SKILL script

As a result, the SKILL script of OADBChecker will be in:

ACTION 5: Copy the SKILL script to current working directory. Type:

2002-2016 Cadence Design Systems, Inc. All rights reserved.

Static Timing Analysis on Schematic-based Mixed-Signal Design: Workshop User Guide

2.1.2 Loading oaDBChecker SKILL script into CIW

Tools => OA DB Checker

The Innovus Interoperability Checker form will appear.

ACTION 1: Untar the database to generate sta_aot_v07/LPAMS45_/ directory ( stands for