Think Extensible.

Zynq-7000
Extensible Processing Platform
Design Workshop
for Hardware Engineers
WEDNESDAY, MARCH 28, 2012
EMBEDDED SYSTEMS CONFERENCE
SAN JOSE, CA

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Zynq-7000 EPP Design Workshop: For Hardware Engineers

Introduc tion

This lab reviews the preferred flow for creating an embedded Zynq extensible processing system and
attaching it to peripherals in both the processor system (PS) and programmable logic (PL).
The overall system that you will be constructing in this lab is as follows:

Figure 1-1: System Block Diagram

The use of the PlanAhead tool as the top-level design environment enables expansion of this design.
This includes logic in the PL portion of the EPP that can be connected to the PS or completely independent.
The general-purpose I/O (GPIO) module used in this design controls the LEDs and resides in the PL
although it is managed as part of the PS. Other peripherals, such as the DDR3 and flash interfaces, have
their own dedicated I/Os and are managed from within the PS. The UART is part of the I/O peripheral (IOP)
block inside the PS.

Figure 1-2: Processing System Block Diagram

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The bank of LEDs that you will control in this lab is present almost due "north" of the Zynq EPP part (with the
FMC connectors at the north and the power switch and connector on the west).

Figure 1-3: ZC702 Board

Objec tives
After completing this lab, you will be able to:

Create an XPS project from the PlanAhead tool

Configure the PS and add IP in the programmable logic

Test the hardware using an application developed in SDK

P roc edure
This lab uses the preferred flow for constructing an embedded design.
This lab is separated into steps that consist of general overview statements that provide information on the
detailed instructions that follow. Follow these detailed instructions to progress through the lab.
This lab comprises four primary steps: First, you will create a PlanAhead tool project; then you will add an
embedded system and configure it. Next, you will create a "wrapper" for your embedded processes in the
PlanAhead tool. Finally, you will export the hardware project to SDK and write your own "Hello World"
application and run it on the ZC702 board.
You will use three Xilinx tools to complete this flow: the PlanAhead tool to do the top-level project, Xilinx
Platform Studio (XPS) to develop your embedded system, and SDK to do your software development.

Figure 1-4: Lab Tool Flow

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Lab Workbook

Zynq-7000 EPP Design Workshop: For Hardware Engineers

Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab
from www.xilinx.com/training/downloads.htm. These are the original lab files and do not contain any work
that you may have previously completed.

G eneral F low

Creating the PlanAhead Tool Project

Step 1

The recommended flow for developing an embedded system is to begin with a

PlanAhead tool project. The processing system (PS) can then be added as though it were
a hierarchically subordinate moduleeven though the PS often controls the action on the
entire chip.
This step will walk you through the process of creating a PlanAhead tool project, importing
existing source code, and creating an XPS project from within the PlanAhead tool
environment.
1-1.

Begin by launching the PlanAhead tool and creating a new project.

1-1-1.

Select Start > All Programs > Xilinx ISE Design Suite 14.1 > PlanAhead > PlanAhead (32) for
32-bit systems or PlanAhead for 64-bit systems to launch the PlanAhead software.

1-1-2.

Click Create New Project.

Figure 1-5: Creating a New Project in the PlanAhead Software

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The Create a New PlanAhead Project dialog box appears and introduces the wizard.

Figure 1-6: The Create New PlanAhead Project Wizard Introduces Itself
1-1-3.

Click Next.

1-1-4.

Browse to the C:\training\ESC\Hardware_Development directory and click Select.

Figure 1-7: Browsing to the Project Location

1-1-5.

In the Project name field, enter base_system and click Next.

1-1-6.

Select Specify RTL Sources and leave the import check box de-selected.

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This will enable you to add new sources without having to have an XST or Synplify project.

Figure 1-8: Specifying the Design Sources

1-1-7.

Click Next.
The Add Sources dialog box allows you to import any source files.
For this lab, no additional files are required.

1-1-8.

Continue clicking Next until the Add Constraint Files dialog box opens.
You will now add the project constraint file, which has been completely constructed for you.
The constraint file that has been provided for you is in the UCF format.

1-1-9.

Select UCF and click Add Files.

Figure 1-9: Selecting the UCF Format when Adding Constraints

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1-1-10. Browse to the C:\training\ESC\Support directory and select ESC_LED_locs. Click OK.

Figure 1-10: Selecting the Constraints File

This constraint file contains the locations of the LEDs on the ZC702 board.
1-1-11. Click Next.
You can now select the target device by filtering the parts list and specifying the board that you will
be working with.
1-1-12. Select Boards under Specify. Select Zynq-7000 from the Family drop-down list. Select ZYNQ-7
ZC702 from the board search results and click Next, then Finish.

Figure 1-11: Selecting Zynq Part by Board Filter

The PlanAhead software GUI is launched.

1-2.

Now it is time to build the PS.

1-2-1.

In Flow Navigator, under Project Manager, click Add Sources (

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Select Add or Create Embedded Sources from the list of source types and click Next.

Figure 1-12: Creating the Embedded Project/Source

1-2-3.

Click Create File.

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In the Module Name field, enter processor_system. Click OK.

Figure 1-13: Naming the Embedded System

1-2-5.

Click Finish.
Xilinx Platform Studio is launched. You will use XPS to construct the embedded system.

Building the Embedded System in XPS

Step 2

Now that the PlanAhead tool and XPS projects have been created, you will define the
components comprising the PS and connect a PL peripheral (a peripheral that connects
to the processing system but physically resides in the programmable logic).

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2-1.

At this point, the XPS tool has opened (or will open shortly) and the XPS
project has been created. A dialog box identifies this as a (currently) blank
Zynq EPP project and invites you to add a processing system.

2-1-1.

Click Yes.

Figure 1-14: Blank Zynq Project Dialog Box

2-1-2.

Select the ZYNQ tab from the System Assembly View to view and configure the overall PS.

Figure 1-15: Select the ZYNQ tab to View and Configure the PS
Next you will open the Zynq EPP system configuration view. This perspective will enable you to
select most of the important PS capabilities.
A configuration specific to the ZC702 board has been provided for you.
2-1-3.

Click the Import Zynq Configurations (

configuration.

) icon next to the help icon to access this

You will be invited to choose from a set of existing configuration templates.

2-1-4.

Click OK to select the configuration template.

Figure 1-16: Selecting the xc7z020 Device

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Click Yes to acknowledge the current configuration of the embedded system will be replaced by
this Zynq EPP configuration.
This will overwrite the Microprocessor Hardware Specification (MHS) file. This file describes each
component in this embedded system, their connections, and settings.
You will modify the existing configuration in the following steps.

Question 1
What is included in the default configuration for the 7z020? (Answers are in the last section of this lab)

2-2.

Because you are now provided with a complete basic system, you only need
to select or de-select various peripherals to meet your needs.

2-2-1.

Click the Clock Generation block in the diagram in order to configure the clocks being passed from
the PS to the PL.

Figure 1-17: Locating the Clock Generator Module

Notice that there is a clock for each peripheral in the IOP as well as four clocks available for the PL.

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Confirm that FCLK_CLK0 is set to 50 MHz and click Validate Clocks (bottom right) to see if the
configuration is legal.

Figure 1-18: Changing the Clock to the PL to 50 MHz

Messages from the validation process appear in the console view.
2-2-3.

Click OK to save your changes and exit the Wizard.

Not all the peripherals included in the IOP block are required. You will now remove unneeded
peripherals from the IO Peripheral block.

2-2-4.

Click anywhere in the I/O Peripheral block or in the I/O Mux block.

2-2-5.

De-select all peripherals except UART 1 and Quad SPI Flash by clicking the check mark to toggle
the selection.

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Notice the pull-down menu next to the UART. This menu enables you to select the pin pairBecause
the ZC702 board is already built, you must choose peripherals and pins that correspond to how the
board is physically laid out. In this case, you must use UART1 and select pins 48..49 for the I/O.

Figure 1-19: Deselecting all but UART 1

2-2-6.

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Click Close.

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2-3.

Now that the peripherals within the PS are configured, the PL peripheral can
be added.

2-3-1.

In the IP Catalog, expand EDK Install > General Purpose IO. Double-click the AXI General
Purpose IO peripheral to add it to your system.

Figure 1-20: The IP Catalog - Finding the GPIO Peripheral

2-3-2.

Click Yes to acknowledge the addition of the IP.

Figure 1-21: Confirm the Addition of the GPIO Peripheral

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Expand the Channel 1 field and change the GPIO Data Channel Width to 8 to specify the width of
the GPIO peripheral. Rename the peripheral from its default to GPIO_LED_8bit.

Figure 1-22: GPIO Peripheral with New Name and 8-bit Width
2-3-4.

Click OK to add this customized peripheral to your design.

This peripheral has to be connected to the PS via an AXI port. The tools detect that there are no AXI
ports extant and automatically creates an AXI connection for you. If other AXI ports were available,
you would have the option to select which one you want to connect to.

2-3-5.

Click OK to accept the default connection.

Figure 1-23: Accepting the Default AXI Connection

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2-4.

Connections between the peripherals is most easily viewed via the Ports
Tab. In this view you will set the clock and reset for the AXI interconnect.

2-4-1.

In the Ports tab, expand the axi_interconnect_1 signal. Click in the Connected Port field of
INTERCONNECT_ARESETN and select processing_system7_0 from the source device (left
column) drop-down list. Select the M_AXI_GP0_ARESETN signal name from the available signals
(right column) drop-down list. Click anywhere outside the selection area to close the selection
fields.

Figure 1-24: Connecting the AXI Reset

2-4-2.

Click in the Connected Port field of INTERCONNECT_ACLK and select processing_system7_0

from the source device (left column) drop-down list. Select the FCLK_CLK0 signal name from the
available signals (right column) drop-down list. Click anywhere outside the selection area to close
the selection fields.

Figure 1-25: Connecting the AXI Clock

2-5.

The AXI clock for processing_system7_0 needs to be tied to the same clock
source.

2-5-1.

Expand processing_system7_0.

2-5-2.

Expand the processor_system7_0's (BUS_IF) M_AXI_GP0 branch.

2-5-3.

Click in M_AXI_GP0_ACLK's Connected Port field and attach it to the PS's own FCLK_CLK0.
Click anywhere outside the selection area to close the selection fields.

Figure 1-26: Connecting the PS's AXI Clock with CLK0

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Zynq-7000 EPP Design Workshop: For Hardware Engineers

Next, the GPIO must be connected. There are GPIOs within the IO
Peripherals block that connect directly through the Processor System's
dedicated pins. There are also GPIOs within the IO Peripherals block that
connect through Programmable Logic to package pins; and GPIOs that can
be implemented in fabric and connected to the PS via a GP AXI master
connection.
This lab will use PL based GPIOs. The reason for this is that none of the PS's
dedicated pins signals are routed to the LEDs on the ZC-702 board. You
must use pins in the programmable logic's domain to connect the GPIOs to
the necessary pins on the package.
Alternatively, it is possible to use the GPIOs in the IO Peripheral block and
route these signals through the EMIO (an internal connection between the
PS and PL).

2-6-1.

Expand GPIO_LED_8 > (BUS_IF) S_AXI. Click in the Connected Port field next to S_AXI_ACLK.
Select processing_system7_0 and FCLK_CLK0 from the drop-down lists. Click anywhere
outside the selection area to close the selection fields.

Figure 1-27: Connecting the AXI Clock for the GPIO_LED_8 Peripheral
This connects the GPIO_LED_8's AXI clock.
At this point, all of the AXI connections are made. All that remains is that the GPIO peripheral be
connected to the outside world so that it can drive the LEDs.
2-6-2.

Expand the (IO_IF) gpio_0 entry.

Notice that the GPIO_IO port (a bidirectional port) is connected to the outside world. You know that
the connection is output only because you are driving LEDs.

2-6-3.

Right-click GPIO_IO and select No Connection to remove this connection.

Figure 1-28: Disconnecting the Bidirectional Port on the GPIO Peripheral

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Right-click the GPIO_IO_O port and select Make External to make the output only port on the
GPIO peripheral available external to the design.

Figure 1-29: Making the GPIO Output-Only Port "External"

Question 2
How can you tell if a port is bidirectional, input, or output?

Question 3
How can you tell if the components are connected?

2-7.

Now that all the peripherals have been added and everything is connected,
the peripherals must be assigned locations in memory. Recall that as
peripherals are added to the design, they are automatically given addresses
based on where they are attached. In this step, you will verify that all the
addresses are assigned properly.

2-7-1.

Select the Addresses tab and expand the processing_system7_0's Address Map.
Peripherals that have not yet been assigned addresses will appear in the Unmapped Addresses
field.

2-7-2.

If any peripherals appear in the Unmapped Addresses field, select the memory "size" (that is,
decode region) and click the Generate Address icon ( ) in the upper right of the GUI.
Note that the GPIO peripheral has a properly assigned address. The UART peripheral is part of the
PS and has a fixed address which does not appear here.

2-8.

Run a Design Rule Check, launch SDK, and exit XPS

2-8-1.

Click Project > Design Rule Check to run the DRC.

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Issues are displayed in the console window.

There are two possible next steps. You might elect to create a netlist from within XPS or simply exit
and generate a netlist from the PlanAhead tool environment. However, this process can take a bit
of time.
2-8-2.

Select File > Exit to close and exit XPS and return to the PlanAhead tool.

Question 4
If you were building your own board, how might you implement the GPIOs?

Building the Embedded System Wrapper

Step 3

3-1.

At this point, the processing system has been created. Now you will create a
top-level wrapper so that the PlanAhead tool can synthesize, implement,
and generate a bitstream for the processing system system.

3-1-1.

In the Flow Navigator, under Project Manager, click Project Settings. Select VHDL from the
Target Language drop-down list to set the language preference.

Figure 1-30: Opening the Project Settings and Selecting the Target Language
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Wrappers and templates will be generated in the language selected by the Target Language field.
3-1-2.

Click the Synthesis icon in the Project Settings to the left and select PlanAhead Defaults from the
Strategy drop-down list to set the tool options.

Figure 1-31: Setting the Synthesis Strategy

These various strategies contain tool-specific settings to give you the best chance of meeting your
specific goal.

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Click the Implementation icon in the Project Settings to the left and select ISE defaults from the
Strategy drop-down list to set the tool options for the implementation tools.

Figure 1-32: Setting the Implementation Options

3-1-4.

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Click OK to save the changes.

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In the Sources window, select processor_system, then right-click processor_system, and select
Create Top HDL to create the top-level wrapper for the embedded system.

Figure 1-33: Generating Top Level Wrapper for the Embedded System
This feature builds an editable wrapper for the embedded system in the language you selected
earlier (in this case, VHDL).
Optionally, you can double click processor_system_stub to see what was created.

3-2.

Normally, the next step is to run the tools to build a bitstream. Because this
process takes about 20-30 minutes, the completed bitstream has been
provided for you.
This concludes the hardware design portion of the lab. From here, you will
export the hardware information to the Software Development Kit (SDK),
where you will program the device and develop a simple application to run
in the processor.

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Select File > Export > Export Hardware.

Figure 1-34: Exporting the Hardware Design to SDK

You might usually export all three items; however, because the bitstream is provided to you
separately (to save you about 30 minutes of implementation time), you will not include the bitstream
in this lab.
3-2-2.

Select Export Hardware and Launch SDK and click OK. Note that the bitstream field is grayed out
since the bitstream was not generated.

Figure 1-35: Exporting Hardware from PlanAhead

Building and Running the Software

Step 4

At this point in the design, you have created all the necessary hardware and launched
SDK with the necessary files to fully describe the hardware. All that remains is to create a
small software application, configure the board, and load the software. Note that the
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hardware platform has been created for you automatically when you exported from the
PlanAhead tool. If you were to have launched SDK in standalone mode, you would have
had to create this yourself.
4-1.

SDK should be open at this point. If not, execute the last step of the previous
section.
Create a new project and add the existing source code.

4-1-1.

Select File > New > Xilinx C Project.

Figure 1-36: Creating a C Application Project

4-1-2.

Select the Peripheral Tests project template. Click Next.

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This template will generate a series of exercises for all the peripherals in the system.

Figure 1-37: Creating the Peripheral Tests Project

A board support package (BSP) provide a collection of useful functions for a standalone platform or
OS.

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Leave the settings at their default and click Finish.

Figure 1-38: Selecting the BSP for the Peripheral Tests Project

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4-2.

You will need to make sure that this code executes out of the proper
location in memory. The linker script dictates where each section of code
resides.

4-2-1.

In the Project Explorer tab, right-click peripheral_tests_0 and select Generate Linker Script.

Figure 1-39: Generating a Linker Script

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In the Basic tab, select ps7_ddr_0_S_AXI_BASEADDR from the Place Code Sections, Place
Data Sections, and Place Heap and Stack drop-down lists to set the memory destination.

Figure 1-40: Selecting Memory Targets in the Linker Script Wizard

4-2-3.

Click Generate.

4-2-4.

Click Yes if a dialog box indicates an existing linker script exists.

This will overwrite the existing file.

Figure 1-41: Acknowledge that a Linker Script Exists and Overwrite it

All the code for Peripheral Tests application will be recompiled and re-targeted to the DDR memory
on the ZC702.

4-3.

Recall that this design contains a GPIO peripheral that is implemented in the
PL. In order to use this peripheral, you must configure the programmable
logic.

4-3-1.

Select Xilinx Tools > Program FPGA.

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Browse to the C:\training\ESC\Support directory and select processor_system_stub.bit. Click

Open.

Figure 1-42: Selecting the Bitstream to Download to the Programmable Logic

4-3-3.

Click Program.
It will take about a minute to configure the programmable logic.

4-4.

Next, you will configure a serial terminal window in which you can see the
output produced by the PS.

4-4-1.

Select the Terminal tab in the messages area (bottom) of the screen.

Figure 1-43: Locating the Terminal Tab

4-4-2.

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Click the Settings icon (

session.

) to set the baud rate and other parameters for the communications

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The Terminal Settings dialog box opens. Your COM port may be different from the one shown. Ask
your instructor for the proper COM port value.

Figure 1-44: Terminal Configuration - Check with your Instructor for the Proper COM Port
Number
4-4-3.

Click OK to accept these settings and begin the session.

Any serial messages emanating from the ZC702 board will appear in this window.

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4-5.

Finally, you can now run the software.

4-5-1.

In the Project Explorer tab, right-click peripheral_tests_0 and select Run As > Run
Configuration.

Figure 1-45: Selecting the Run Configuration for peripheral_tests_0

The Run Configurations dialog box opens to help you manage run configurations.
4-5-2.

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Because this is the first Run Configuration of the project, double-click Xilinx C/C++ ELF.

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This will create a run configuration for the peripheral_tests_0 application.

Figure 1-46: Initial Run Configurations Dialog Box

4-5-3.

Accept the default settings and click Run to launch the program.
A dialog box may appear asking if it is ok to reset the whole system.

4-5-4.

*** Notice!!! *** when you click OK, the software will be run after a very short delay. The flashing of
the LEDs will happpen very, very quickly and you may miss it. The text sent to the terminal window
will be viewable after the program has completed.
Click OK to allow the run to continue.
You may need to switch back to the Terminal window to see the output.

4-5-5.

Observe messages in the Terminal window and the LEDs will blink once on the ZC702 board.

C onc lus ion

This lab walked you through the basics of building a complete embedded system, including both hardware
and software. First, you created a PlanAhead tool project, then added an embedded system. You then
configured the processing system (PS) and added programmable logic (PL) peripherals using XPS. You
then returned to the PlanAhead tool and created a wrapper for the embedded system and exported the
hardware information to SDK. While in SDK, you created and ran one of the Xilinx project template
programs, which tested the peripherals and watched the software produce output on the serial port and
LEDs.

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Ans wers
1. What is included in the default configuration for the 7z020?
The default configuration includes:

DDR3 configuration

Clock generation for the peripherals

Collection of activated peripherals located in the IOP

This can be quite a time saveryou are basically starting from a working configured system and will
now make changes to the system to customize it to your needs.
2. How can you tell if a port is bidirectional, input, or output?
Look at the direction columnboth the direction and width of the connection is displayed.

Figure 1-47: Finding the Port Direction and Width

3. How can you tell if the components are connected?
Look at the AXI column in the Bus Interfaces tab. At this point in the lab, it should look like this:

Figure 1-48: Bus Interfaces View of Attached AXI Connections

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Note that the axi_interconnect_1 is tied to the green shaded area, but none of the other components
are. This is one way of seeing that the other components are not connected.

Figure 1-49: Bus Interface View Prior to Connecting the Components

Another way is to look at the bus name associated with the component. If it is blank, then there is no
connection.

Figure 1-50: Looking for the Connection in the Bus Name Column
However, there are more connections than between the peripheral and the processor. A number of
these signals must be interfaced to the outside world: How will the signals from the rotary switch be
received? What about the LCD and LED components?
4. If you were building your own board, how might you implement the GPIOs?
There are four 32-bit GPIOs built into the IOP block. These can be directly connected to the LCD, LED,
or any other peripheral by using a single 32-bit GPIO, or multiple GPIOs. Two of the four GPIOs in the
IO Peripheral block connect via the I/O multiplexer and must share the 54 dedicated IOP pins with other
peripherals in the IOP. The remaining two GPIOs can be routed through the EMIO to any other
available pin in the package.

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Singapore 486040
Tel: +65-6407-3000
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