EE330 Final

Design Project
By: Brendan Bartels & Adam Cha

Project
Project 12 Self-Defined: Reverse Polish Calculator

16 Button Inputs
Handles 10-bit unsigned numbers
Only Addition and Subtraction
Result displays on four 4-digit seven-segment displays
Example usage

If you want: 2 + 40 = 42
Type: <2> <enter> <4> <0> <+>

Initial Design Flow (Process of Lab 11)

1.
2.
3.
4.
5.

Verilog Design
Verilog Simulation
RTL Synthesis
Placement and Route
Post-Layout Simulation

First Attempt...

Verilog Design and Simulation worked

RTL Compiler would always crash

LVS Passed
Post-layout Simulation wouldnt work

Is our circuit too big? (Dividers/Multipliers)

Solution: dont execute with GUI

Virtuoso would only import the cell as a functional block instead of a schematic (which
cant be simulated)
Reason: Virtuoso wont import schematics when assign statements are present

Also observed post-layout simulation was wrong

New Strategy

Re-Design verilog without complicated algorithms (division)

Improve workflow by scripting RTL synthesis and Encounter Place/Route

And avoiding dependence on pos-edge events (timing issues)

Save time, and reduce human error

Get a new design flow...

Updated Design Flow

1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Master Mux
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Master Max
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Master Mux
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Controller Finite State Machine

IDLE

Release
Button

Append
Number

Load
R2 -> R3

Decide

Add

Sub

Load
R1 -> R2

Load
R2 -> R1

Load
R0 -> R1

Load
R3 -> R2

Clear
R0

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Calculator (whole thing)

1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Calculator (whole thing)

1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Calculator (whole thing)

1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Design

Digit Shifter

ALU

Controller

Master Mux

10-bit Register File

4-digit 7-seg
Display Drivers

Driver
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Calculator
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Dimensions:
485u x 441u
DRC and LVS
passed

Driver
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Dimensions:
571u x 562u
DRC and LVS
passed

Calculator
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Driver
1.
2.
3.
4.
5.
6.

Verilog Design
Verilog Simulation
RTL Synthesis
Post-Synthesis Simulation
Placement and Route
Post-Layout Simulation

Final Integration
Total Components

Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)

Final Integration
Total Components

Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)

China Young Sun LED Technology Co., LTD Data Sheet

China Young Sun LED Technology Co., LTD Data Sheet Cont.

Final Integration
Total Components

Calculator circuit
Driver Circuit
4-digit 7-segment Display
Button Input (User Interface)

Push Button Keyboard: Debouncer Circuit

Push Button Keyboard: Debouncer Button Circuit Theory

Switch Opened:
The capacitor will be charged by R1 and the diode.
Over time, the capacitor will charge and the voltage going into the inverter will be 0.7V less of
Vdd.
Since the signal will be around 4.3V (logic 1) going into the inverter, then the actual output after
the inverter will be a logic of 0.
Switch Closed:

The capacitor will be charged by R2.

Over time, the capacitor will discharge and the voltage going into the inverter will be 0V.
Since the signal will be 0V (logic 0) going into the inverter, then the actual output after the
inverter will be a logic of 1.

Final Integration

Sixteen Debouncer Push Buttons

Calculator
Four Drivers
4-Digit 7-Segment Displays

Questions?