EC1031 VLSI Lab List of Experiment

Lab Experiment #1
Objective: To learn the design of combinational logic circuits in Verilog then simulating and
synthesizing using EDA tools
Problem 1: Write a Verilog code to implement Ripple Carry Adder.
The following points should be taken care of:
1. Use assign statement to design sub module half adder
2. Use gate primitives to design full adder using half adder
3. Construct the top module ripple carry adder using 1-bit full adder
Problem 2: Write a Verilog code to implement Multiplexer.
The following points should be taken care of:
1. Use ternary operator to design 2x1 Mux
2. Use initial and always statement to design 4x1 Mux
3. Use Gate Level Model to design 8x1 Mux using two 4x1 Mux and one 2x1 Mux
Problem 3: Write a Verilog code to implement Decoder
The following points should be taken care of:
1. Use dataflow model and behavioral model to design 3x8 decoder
2. Use 3x8 decoder to design 4x16 decoder
3. Use Generate Statement to design 4x16 decoder using 2x4 decoder.

Lab Experiment #2
Objective: To learn the design of sequential circuits in Verilog then simulating and synthesizing
using EDA tools
Problem 1: Write a Verilog code to implement Flip flops.
The following points should be taken care of:
1. Use If statement to design positive edge triggered SR flip
2. Use case statement to design negative edge triggered JK and T flip flop
3. Use Blocking and Non-Blocking statement to design negative edge triggered D flip flop
with asynchronous clear input.

Problem 2: Write a Verilog code to implement Counters.

The following points should be taken care of:
1. Use behavioral model to design mod n Counter with active high synchronous reset input.
2. Use behavioral model to design Up-Down Counter. When mode =1 do up counting and
for mode=0 do down counting.
3. Use T flip flop as a sub module to design Decade Counter active low asynchronous reset
input.
Problem 3: Write a Verilog code to implement Shift Registers.
1. Use behavioral model to design a n-bit SISO shift register using active high synchronous
reset input
2. Use behavioral model to design a n-bit SIPO shift register using active high
asynchronous reset input.
3. Use D flip flop with negative edge clock and asynchronous clear input to design n bit
PIPO shift register.

Lab Experiment #3
Objective: To learn the design of VLSI multipliers in Verilog then simulating and synthesizing
using EDA tools
Problem 1: Write a Verilog code to implement Braun Array multiplier
The following points should be taken care of:
1. Use structural model to design Braun array multiplier
2. Use Generate Statement to design Braun array multiplier
Problem 2: Write a Verilog code to implement Baugh-Wooley Array multiplier.
The following points should be taken care of:
1. Use structural model to design Baugh-Wooley array multiplier
2. Baugh-Wooley parametrized multiplier using Generate Conditional

Lab Experiment #4
Objective: To learn the design of Multiply-Accumulate circuits in Verilog then simulating and
synthesizing using EDA tools

Problem 1: Write a Verilog code to implement unsigned MAC Unit using data flow model
Problem 2 : Implement MAC Unit using structural model

Lab Experiment #5
Objective: To learn the design of Digital Filter in Verilog then simulating and synthesizing using
EDA tools
Problem 1: Write a Verilog code to implement N order FIR filter. Use parameter statement to
define the filter coefficients.

Lab Experiment #6
Objective: To learn the design of FSM for any application in Verilog then simulating and
synthesizing using EDA tools
Problem 1: Implement Sequence Recognizer for detecting three successive 1s using Verilog
code

Lab Experiment #7

Objective: To learn the design of Microprocessor parts in Verilog then simulating and
synthesizing using EDA tools
Problem 1: Write a Verilog code to implement General Purpose Register block that has 8 eightbit register which are used for data manipulation.

The following points should be taken care of:

1. The register block has three 3-bit address inputs which are used to index the registers.
2. The input_select input determines which register receives a value from the data bus if
read_data is high; output_select determines which register is written when write_data is
high.
3. The alu_output_value bus goes directly to the ALU and is always active. The
alu_output_select address determines which register is sent directly to the ALU on this
bus.
4. The register pairing is not due to any hardware feature within the register block - the
registers are
implemented simply as an 8-element array of 8-bit registers. The pairing is performed by
the control signals module

General Purpose Register Block Diagram

Problem 2: Write a Verilog code to implement ALU block that all of the arithmetic operations.
The following points should be taken care of:

1. Operation performed in ALU are addition, subtraction, multiplication, logical AND and
OR, left and right logical shifts, left and right arithmetic shifts, bitwise complement, and
negation.
2. The output is only 8 bits, except for the multiply, which is 16 bits. The zero flag is
defined for every operation: if the result is all zeros, the flag is set. Likewise, the negative
flag is set whenever the highest bit of the result is a 1, which indicates a negative number
in the two's complement system. The behavior and meaning of the carry flag is dependent
on the operation. For add and subtract, it indicates a carry out or borrow in; for shifts, it
indicates the bit that was shifted out.

ALU Block diagram

Problem 3: Implement 64-bit x 8-bit single-port RAM design with common read and write
addresses.