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Frequency Response
Reading: Sedra & Smith: Sec. 1.6, Sec. 3.6 and Sec. 9
(MOS portions),
(S&S 5th Ed: Sec. 1.6, Sec. 3.7 (capacitive effects), Sec.
4.8, Sec. 4.9, ,Sec. 6. (Frequency response sections,
i.e., 6.4, 6.6, ), Sec. 7.6
Observation on the
frequency response of an Amplifier
Observations:
Analytical solution of amplifiers in frequency domain is complicated!
Response (e.g., gain) of an ideal linear amplifier should be independent
of frequency (otherwise signal shape would be distorted by the
amplifier). Thus:
o A practical amplifier acts as an ideal linear amplifier only for a range of
frequencies, called the mid-band.
o The lower and the upper cut-off frequencies (fL and fH) identify the
frequency range over which the amplifier acts linearly.
o Amplifier response at high frequencies (near the upper cut-off frequency ,
fH) is important for stability considerations (gain and phase margins).
For the above two limits, circuit becomes a resistive circuit and
we do NOT need to solve the circuit in the frequency domain.
Thus, ignoring capacitors means that we operate at either a high
enough or at a low enough frequency such that capacitors become
either open or short circuits, leading to a resistive circuit.
o Note that the circuit is modified by the presence of the capacitors
(e.g., elements may be shorted out).
| Z | = R || (1 / C )
R << (1 / C ) | Z | = R || (1 / C ) R
R << (1 / C ) << (1 / RC )
Capacitor approximates a short circuit at high frequencies:
R >> (1 / C ) | Z | = R || (1 / C ) (1 / C ) 0
R >> (1 / C ) >> (1 / RC )
We cannot ignore the capacitor when
R ~ (1 / C ) ~ (1 / RC )
This defines the reference frequency for high-f and low-f
Note: The above circuit is like a low-pass filter with a cut-off frequency of 1/RC
F. Najmabadi, ECE102, Fall 2012 (5/59)
o To find fL all high-f capacitors will be open circuit (because fL << fH)
o To find fH all low-f capacitors will be short circuit (because fH >> fL)
f
All Caps are short.
This limit is used
to find highfrequency Caps.
f0
All Caps are open.
This limit is used
to find lowfrequency Caps
Computing fL:
High-f caps are open.
Low-f caps included.
F. Najmabadi, ECE102, Fall 2012 (7/59)
Mid-band:
High-f caps are open
Low-f caps are short.
Computing fH :
High-f caps are included.
Low-f caps are short
CL open:
No change in vo
Does NOT contribute to fL
CL short:
vo = 0
Contributes to fH
Computing fL:
High-f caps are open.
Low-f caps included.
Mid-band:
High-f caps are open
Low-f caps are short.
Computing fH :
High-f caps are included.
Low-f caps are short
Low-Frequency Response
Vsig
s + p1 s + p 2 s + p 3
(Set s = j to find Bode Plots)
If one pole is at least a factor of 4 higher than others (e.g., fp2 in the above
figure), fL is approximately equal to that pole (e.g., fL fp2 in above within 20%)
F. Najmabadi, ECE102, Fall 2012 (12/59)
Cc2 open:
vo = 0
Cs open:
Gain is reduced substantially
(from CS amp. to CS amp. With RS)
Vo
s
s
s
= AM
Vsig
s + p1 s + p 2 s + p 3
AM =
RG
g m (ro || RD || RL )
RG + Rsig
p1 =
1
1
, p3 =
Cc1 ( RG + Rsig )
Cc 2 ( RD || ro + RL )
p2
1
,
Cs [ RS || [(ro + RD || RL ) /(1 + g m ro )]
1
2Rn Cn
f p1 =
1. Consider Cc1 :
1
2 Cc1 ( RG + Rsig )
Terminals of Cc1
1
2 CS [ RS || [(ro + RD || RL ) /(1 + g m ro )]
ro + RD || RL
1 + g m ro
1. Consider CS :
ro + RD || RL
1 + g m ro
ro + RD || RL
1 + g m ro
Terminals of CS
f p3 =
1. Consider Cc2 :
1
2 Cc 2 ( RL + RD || ro )
Terminals of Cc2
High-Frequency Response
o Amplifier gain falls off due to the internal
capacitive effects of transistors as well as
possible capacitors in the circuit.
Forward Bias
Cj + Cd
C j 2 C j0
Cd =
rD
F. Najmabadi, ECE102, Fall 2012 (20/59)
T ID
VT
Reverse Bias
Cj =
C j0
(1 + VR / V0 ) m
Cd = 0
3. Junction capacitance
between Source and Body
(Reverse-bias junction)
2. Capacitance between
Gate & Source and Gate &
Drain due to the overlap of
gate electrode
(Parallel-plate capacitor)
4. Junction capacitance
between Drain and Body
(Reverse-bias junction)
MOS High-frequency
small signal model
Low-pass
filter
Input Pole
F. Najmabadi, ECE102, Fall 2012 (23/59)
Mid-band Low-pass
Amp
filter
Output Pole
Cgd between
drain & ground
C L = C L + Cdb + C gd
Cin = C gs + Csb
Node vi :
Node vo :
vi vsig
Rsig
vi
v vo
g m ( vi ) + i
=0
1 / sCin
ro
vo
vo
v v
+
+ g m (vi ) + o i = 0
RL 1 / sC L
ro
Input Pole
Mid-band Gain
Node vo :
vo
+ sC L vo g m (vi ) = 0
RL
vo
g m RL
=
vi 1 + sC L RL
Output Pole
vo
Ri
1
1
=
( g m RL )
vsig Ri + Rsig
1 + sCin ( Rsig || 1 / g m ) 1 + sC L RL
F. Najmabadi, ECE102, Fall 2012 (25/59)
p1
p2
+ ...
1. Set vsig = 0
2. Consider each capacitor separately, e.g., Cj (assume others are open circuit!)
3. Find the total resistance seen between the terminals of the capacitor, e.g., Rj
(treat ground as a regular node).
4. b1 = nj =1 R j C j
1
2 b1
Terminals of Cin
ro + RL
1 + g m ro
1. Consider Cin :
ro + RL
1 + g m ro
F. Najmabadi, ECE102, Fall 2012 (27/59)
ro + RL
1 + g m ro
2 = C L [ RL || ro (1 + g m Rsig )]
1. Consider CL :
ro (1 +g m Rsig )
ro (1 +g m Rsig )
Cin = C gs + Csb
AM = +
Ri
g m (ro || RL )
Ri + Rsig
Ri = (ro +RL ) / g m ro
1
2 b1
1
2 ( 1 + 2 )
vsig 1 / g m + Rsig
1 + sCin ( Rsig || 1 / g m ) 1 + sC L RL
AM
F. Najmabadi, ECE102, Fall 2012 (29/59)
Input pole :
p1 = 1 / 1
Output pole :
p2 = 1/ 2
Cgd is between
output and input!
Input Pole?
Output Pole?
Millers Theorem
Consider an amplifier with a gain A with an impedance Z attached
between input and output
V1 and V2 feel the presence of Z only through I1 and I2
We can replace Z with any circuit as long as a current I1 flows out of
V1 and a current I2 flows out of V2.
V2 = A V1
I1 =
V1 V2 (1 A) V1
=
Z
Z
I2 =
V2 V1 ( A 1) V1 ( A 1) V2
=
=
Z
Z
ZA
I1 =
V1
V
= 1,
Z /(1 A) Z1
I2 =
V2
V
Z
= 2 , Z2 =
ZA /( A 1) Z 2
11/ A
Z1 =
Z
(1 A)
V2 = A V1
V2 = A V1
Z
Z1 =
1 A
F. Najmabadi, ECE102, Fall 2012 (32/59)
Z2 =
Z
1
1
A
Rf
1 + A0
Z
Z2 =
11/ A
Rf
A0
Rf 2 =
Rf
1 + 1 / A0
Rf
A0 ( R f / A0 )
R1 + ( R f / A0 )
vo R f
vi
R1
Rf
R1 + ( R f / A0 )
Z
Z1 =
1 A
Z=
Large capacitor at
the input for A >> 1
Z2 =
Z
1
1
A
j C
Z
Z1 =
C1 = (1 A) C
1 A
Z
Z2 =
C2 = (1 1 / A) C
11/ A
A=
vd
= g m (ro || RL )
vg
C gd ,i = C gd (1 A) = C gd [1 + g m (ro || RL )]
C gd ,o = C gd (1 1 / A) = C gd [1 + 1 / g m (ro || RL )]
C gd *
Cin = C gs + C gd ,i
C L = Cdb + C gd ,o + C L
1 = Cin Rsig
1
2 f H
F. Najmabadi, ECE102, Fall 2012 (36/59)
2 = C L (ro || RL )
g m (ro || RL ) (1 sC gd / g m )
vo
=
1 + b1s + b2 s 2
vsig
b1 = Cin Rsig + C L (ro || RL )
b2 = [(C L + Cdb )(C gs + C gd ) + C gs C gd ]
Rsig (ro || RL )
Cin = C gs + C gd [1 + g m (ro || RL )]
C L = Cdb + C gd + C L
F. Najmabadi, ECE102, Fall 2012 (37/59)
Because the amplifier gain in the presence of Cgd is smaller than the midband gain (we are on the high-f portion of the Bode gain plot), Millers
approximation overestimates Cgd,i and underestimates Cgd,o
o There is a substantial error in individual input and output poles. However, b1
and fH are estimated well.
i=0
v gs 0 = Z i =
sz =
F. Najmabadi, ECE102, Fall 2012 (39/59)
gm
,
C gd
g m v gs
s z C gd
fz =
gm
2 C gd
f p1
Case of
fz
f p1
f z >> f p 2 > f p1
Case of
f p2
fz
f p2
f p 2 > f z > f p1
Since,
b1 =
p1
p2
H
+ ...
p1
p2
+ ...
2
p1
2
p2
2
p3
+ ...
Cgs between
output and input
F. Najmabadi, ECE102, Fall 2012 (44/59)
Node vi :
Node vo :
vi vsig
Rsig
+ sC gd vi + sC gs (vi vo ) = 0
vo
+ s (C L + C sb )vo + g m (vi vo ) + sC gs (vo vi ) = 0
RL || ro
(1 + sC gs / g m )
vo
g m (ro || RL )
=
Zero : s z =
gm
,
C gs
fz =
gm
2 C gs
Cgd :
CL + Csb:
1/ gm
1 = C gd Rsig
F. Najmabadi, ECE102, Fall 2012 (46/59)
2 = (C L + Csb )(1 / g m || RL )
Vx = v gs
KVL Vx = I x Rsig + ( RL || ro )( I x g m v gs )
Vx = I x Rsig + ( RL || ro ) I x g m ( RL || ro )Vx
Vx [1 + g m ( RL || ro )] = I x [ Rsig + ( RL || ro )]
Vx Rsig + ( RL || ro )
Rgs =
=
I x 1 + g m ( RL || ro )
3 = C gs Rgs
1
2 f H
= b1 = 1 + 2 + 3 = C gd Rsig
Rsig + ( RL || ro )
+ (C L + C sb )(1 / g m || RL ) + C gs
1 + g m ( RL || ro )
i=0
i = g m v gs
i=0
0 v gs = Z i =
sz =
F. Najmabadi, ECE102, Fall 2012 (49/59)
gm
,
C gs
g m v gs
s z C gs
fz =
gm
2 C gs
Millers
v
A = d 1 = g m (ro1 || ro 2 || RL ) g m RL
v g1
C gd 1,i = C gd 1 (1 A) = C gd 1 (1 + g m RL )
C gd 1,o = C gd (1 1 / A) = C gd 1 (1 + 1 / g m RL )
Cin = C gs1 + C gd 1,i
C L = C L + C gd 1,o + C gd 2 + Cdb1 + Cdb 2
C L : R = ro1 || ro 2 || RL
2 = C L (ro1 || ro 2 || RL )
1
2 f H
sz =
F. Najmabadi, ECE102, Fall 2012 (52/59)
gm
,
C gd
fz =
gm
2 C gd
C L = C L + C gd 2 + Cdb 2
Millers
Between D1
& ground
Csb1 is
shorted out.
Ro2
ro 2 +RL
= RL1
1 + g m 2 ro 2
Ri2
Av1 = g m1 (ro1 || Ri 2 )
C gd 1,i = C gd 1 (1 Av1 )
C gd 1,o
Millers
= C gd (1 1 / Av1 ) Capacitors
ro1
C L = C L + C gd 2 + Cdb 2
C1 = C gd 1,o + C gs 2 + Cdb1 + Csb 2
Cin = C gs1 + C gd 1,i
= b1 = 1 + 2 + 3
2 = C1 (ro1 || Ri 2 )
3 = C L ( Ro 2 || RL )
sz =
g m1
,
C gd 1
fz =
g m1
2 C gd 1
vo ,d
vd
= 2
vo ,1d
vd
vo ,1d
0.5vd
Example:
Ro
1 / f p = 2 C L ( RL || Ro )
Typically the required CL is large and CL is located outside the
chip (i.e., between output terminal and ground).
1 / f p = 2 | A | CM ( Rsig || Ri )
Example:
Ri
1 / f p = 2 | A | CM ( Rsig || Ri )
1. Usually not used in the first-stage as we do NOT know what Rsig is.