ELE107 - ELE107 Week8 2014 PDF

ELE 107-Week 8: Computer Architecture and Organization
Architecture and Organization

Why should we know computer architecture and
organization ?
Understand the system capabilities and limitations.
Specify computer systems to meet application
requirements.
Design better programs for specific processing
needs, including system software such as operating
systems, translators, and device drivers.
Maximize system availability and performance.
Make sure that the computer system is secure.
Recognize the tradeoffs among price, performance,
time, and space.
Computer Architecture and

Organization
ELE 107
Computers and Programming I
ELE 107 Dr. Derya Altunay
Computer organization
Describes how the system components are organized
internally and interconnected to realize the computers
architecture.
Includes all physical aspects of computer systems.
Organization is how features are implemented.
For example: control signals, memory technology,
interfaces.
For example: Is multiplication done by a hardware
multiply unit or is it done by repeated addition?
How does a computer work?
Refers to the way the system and its resources appear

to the user/programmer.
Logical aspects of system implementation as seen by
the programmer/user.
For example: instruction sets, instruction formats,
data types, data formats, I/O mechanisms, addressing
techniques.
For example: Is there a multiply instruction ?
How to design a computer?
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Structure & Function
Even with these definitions, there is no obvious

distinction among matters related to the architecture and matters related to the organization.
Some authors might claim that a description of the
instruction set is an architectural issue; others may
describe the instruction set as a part of computer
organization.
Some authors use the term architecture to
encompass the whole of the computer, including
instruction set architecture, organization, and HW.
Computer architecture
Structure is the way in which components

relate to each other
Function is the operation of individual
components as part of the structure
All computer functions are:
Data processing
Data storage
Data movement
Control
Functional view
Data movement
e.g. keyboard to monitor
Operating Environment:
Source & destination of data
Processing
Data
Processing
Facility
Data
Movement
Apparatus
Movement
Control
Mechanism
Control
Storage
Data
Storage
Facility
Storage
Processing from/to storage
e.g. Internet download to hard disk
e.g. updating a student record

Processing
Movement
Processing
Control
Movement
Storage
Storage
Processing from storage to I/O
Stored Program concept

Main memory storing programs and data
ALU operating on binary data
Control unit interpreting instructions from
memory and executing
Input and output equipment operated by
control unit
Princeton Institute for Advanced Studies (IAS)
Completed 1952
Processing
Control
Storage
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von Neumann/Turing
e.g. printing a bank account
Movement
Control
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The von Neumann Model
The System Bus Model

A refinement of the von Neumann model, the
system bus model has a CPU (ALU and
control), memory, and an input/output unit.
Communication among components is handled
by a shared pathway called the system bus,
which is made up of the data bus, the address
bus, and the control bus. There is also a power
bus, and some architectures may also have a
separate I/O bus.
The von Neumann model

consists of five major
components:
1) Input unit
2) Output unit
3) Arithmetic Logic Unit
4) Memory Unit
5) Control Unit
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Levels of Machines
A computer system can also be abstracted as
having a number of levels in a computer, from
the user level down to the transistor level.
Progressing from the top level downward, the
levels become less abstract as more of the
internal structure of the computer becomes
visible.
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Levels of Machines
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Levels of Machines
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CPU Connection

Bus
All the various functions performed can be

classified in three general categories:
Processor (CPU)
Memory
Input-Output
Control Unit
ALU
Store data and program

Execute program
Do arithmetic/logic operations
requested by program
Microprocessor-initiated operations
Internal data operations
Peripheral (externally initiated) operations
Communicate with
"outside world", e.g.
Screen
Keyboard
Storage devices
...
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CPU Connection
CPU Connection
Microprocessor-initiated operations : There

are basically four operations (in addition to other
operations):
Internal data operations : The internal

architecture of the microprocessor determines
how and what operations can be performed with
the data. Some operations are:
Memory Read: Reads data/instructions from

memory.
Memory Write: Writes data/instructions into
memory.
I/O Read: Reads data from input devices.
I/O Write: Sends data to output devices.
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Store data.
Perform arithmetic and logic operations.
Test for conditions.
Sequence the execution of instructions.
CPU Connection
CPU Connection
Peripheral operations : External devices or

signals can initiate the following operations, for
which individual pins on the microprocessor chip
are assigned:
Interrupt : The P can be interrupted from the normal

execution of instructions and asked to perform some
other instructions called a service routine. The P
resumes its previous operation after completing the
service routine.
Ready : This signal makes the microprocessor enter
into a wait state. It is primarily used to synchronize
slower peripherals with the microprocessor.
Hold : When this signal is asserted by an external
device, the microprocessor gives up control of buses
and allows the peripheral to use them (For example,
Direct Memory Access (DMA) data transfer).
Reset : It provides that the program execution starts

from the beginning (PC is cleared). However, all
internal operations are suspended and data
manipulated are lost.
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Buses
What is a Bus?
A data pathway that links parts of the CPU
together and components to the CPU.
Usually broadcast.
Often grouped
The microprocessor performs these functions

using communication lines called buses.
There are a number of possible interconnection
systems.
Single and multiple BUS structures are most
common.
e.g. Control/Address/Data bus (PC)
e.g. Unibus (DEC-PDP)
A number of channels in one bus

e.g. 32 bit data bus is 32 separate single bit channels
More lines, the faster data can travel

64 bit data bus is faster than a 32 bit
Power lines may not be shown.

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Buses
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Single Bus Problems
What do buses look like?
Lots of devices on one bus leads to:
Parallel lines on circuit boards

Ribbon cables
Strip connectors on motherboards
e.g. PCI
Sets of wires
Propagation delays
Long data paths mean that co-ordination of
bus use can adversely affect performance
If aggregate data transfer approaches bus
capacity
Most systems use multiple buses to

overcome these problems.
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Address bus
Data Bus
The address bus is unidirectional and runs only

between the CPU and RAM, and carries nothing
but memory addresses for the CPU to use.
The address bus identifies the source or
destination of data
e.g. CPU needs to read an instruction (data) from a
given location in memory.
Address bus width determines maximum memory

capacity of system
e.g., 8085 microprocessor has 16 bit address bus
giving 64K address space.
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The data bus is birectional and carries data

There is no difference between data and
instruction at this level
The data bus width determines how many bits

can be transmitted between the CPU and
other devices.
Data bus width is a key determinant of
performance
8, 16, 32, 64 bit
e.g., Intel 80386/80486 has 32-bit data bus
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Control Bus
Bus Interconnection
The control bus is composed of various individual

lines that carry synchronization signals.
The control bus provides control and timing
information
Memory read/write signal

I/O read/write signal
Interrupt request
Clock signals
The control bus determines the direction of data

flow, and when each device can access the bus.
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Bus Interconnection
Memory
Receives and sends data
Receives addresses (of memory locations)
Receives control signals
Read
Write
Timing
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Memory
Memory
Memory, (also called RAM)
She is 107.
Consists of many memory cells (storage units) of a fixed

size. Each cell has an address associated with it.
All accesses to memory are to a specified address.
A cell is the minimum unit of access (fetch/store a
complete cell).
The time it takes to fetch/store is the same for all cells.
I am staying at 107.
It costs 107.
There is 107.
My office is 107.
When the computer is running, both
In each case, how do we know

what 107 is?
From the context in which it
is used! The same is true for
data and addresses. The same
number is data on one instance
and address on another.
Program
Data (variables)
Stop in front of 107.
Write 107 at 0x0F40.
are stored in the memory.
My house is 107.
Write 107 at 107.
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Memory
Need to distinguish
between the address of a
memory cell and the
content of a memory cell.
Memory width (W):
How many bits is each
memory cell, typically
one byte (=8 bits)
Memory
Address width (N):
N
0000000000000001
1 bit
0
1
2
2N
...
How many bits used to

represent each address,
determines the maximum
memory size = address space
If address width is N-bits,
then address space is 2N
(0,1,...,2N-1)
2N-1
N
0000000000000001
1
2
2N
...
2N-1
W
W
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Memory Units (specification)

What is to specify in the design of a memory unit?
Typical memory in a personal computer (PC):
The number of bits.
2GB 8GB
This gives the total number of bits that the memory

unit can store.
Memory sizes:
Kilobyte (KB)= 210 = 1,024 bytes ~ 1 thousand
Megabyte (MB) = 220 = 1,048,576 bytes ~ 1 million
Gigabyte (GB) = 230 = 1,073,741,824 bytes ~1 billion
The grouping of bits into words.
Memory Access Time (read from/write to memory)

measured in nanoseconds (1 ns = 10-9 sec.)
RAM is
Accessing one bit at a time might be inconvenient, so,

grouping bits into words is often done.
Common examples of word sizes are 4, 8, 16, 32, 64 bits
The number of words in the memory unit (addressable

words).
volatile (can only store when power is on)

relatively expensive
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Memory Size / Speed
This is a function of the word size and total # of bits.

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Memory Units (description)
Memory Examples
In describing the capacity of a memory unit, the

following notation is used:
# addresses word size (Example: 1M 8)

If a memory unit is described as 1Mx8, then it has
1M = 220 =1,048,576 addresses,
8 bits per word at each address location,
8 data lines for the 8 bit words,
Memory
Total bits
1K4
4,096
# of
# of address
addresses
lines
1,024
# of data
lines
10
1M8
8,388,608 1,048,576
20
2M4
8,388,608 2,097,152
21
4M1
4,194,304 4,194,304
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2M32
20 address lines to specify the 1M = 220 =1,048,576

addresses, and 220 8 = 220 23 = 223 = 8,388,608 bits
in the entire memory unit.
1 bit
16K64
8M8
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Operations on Memory
Structure of the Memory
Fetch (address):
Fetch (address)
Fetch a copy of the content of memory cell with the

specified address.
Non-destructive, copies value in memory cell.
Load the address into MAR.

Decode the address in MAR.
Copy the content of memory cell
with specified address into MDR.
Store (address, value):

Store the specified value into the memory cell specified
by address.
Destructive, overwrites the previous value of the
memory cell.
Memory Address Register (MAR)

Memory Data Register (MDR)
Fetch/Store signal (Read/Write signal)
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Memory
decoder
circuit
Load the address into MAR.

Load the value into MDR.
Decode the address in MAR
Copy the content of MDR into
memory cell with the specified
address.
Fetch/Store
controller
...
44
Cache
Input/Output
High-speed memory, integrated

on the CPU
Processor (CPU)
10 times faster than RAM
Relatively small (1MB - 4MB) Memory
Cache
Similar to memory from computers viewpoint

Output
I/O
Stores data most recently used

Principle of Locality
MDR
F/S
Store (address, value)
The memory system is interfaced via:
MAR
Input
Control Unit
When CPU needs data:

First looks in the cache, only if not
there, then fetch from RAM.
If cache full, new data overwrites
older entries in cache.
Receive data from peripheral

Send data to computer
ALU
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Receive data from computer

Send data to peripheral
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Input/Output
Input/Output
Handles devices that allow the computer system to:
Receive control signals from computer

Send control signals to peripherals
Communicate and interact with the outside world

Screen, keyboard, printer, ...
e.g. spin disk
Store information (mass-storage)
Receive addresses from computer
Hard-drives, floppies, CD, tapes,
e.g. port number to identify peripheral
Mass-Storage Device Access Methods:

Direct Access Storage Devices (DASDs)
Send interrupt signals (control)
Hard-drives, floppy-disks, CD-ROMs, ...
Sequential Access Storage Devices (SASDS)

Tapes (for example, used as backup devices)
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Structure of the I/O
I/O Controllers
Speed of I/O devices is slow compared to RAM
Interrupt signal (to processor)
Data
from/to
memory
RAM
~ 50 ns
Hard-Drive ~ 10 ms = (10,000,000 ns)
I/O controller
Solution:
I/O Buffer
I/O Controller, a special purpose processor:

Has a small memory buffer, and a control logic to
control I/O device (e.g. move disk arm).
Sends an interrupt signal to CPU when done read/write.
Control/Logic
Data transferred between RAM and memory buffer.

Processor free to do something else while I/O controller reads/writes data from/to device into I/O buffer.
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I/O device
Structure of the ALU
ALU
The ALU (Arithmetic/Logic Unit) performs
Registers:
arithmetic operations (+, - , , / , )

logic operations (=, <, >, and, or, not, ...)
Very fast local memory cells, that

store operands of operations and
intermediate results.
CCR (condition code register), a
special purpose register that stores
the result of <, = , > operations
In todays computers integrated into the CPU

Consists of:
Rn
Contains an array of circuits to do

mathematical/logic operations.
ALU circuitry
Bus:
Data path interconnecting the
registers to the ALU circuitry.
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The Control Unit
GT EQ LT
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Machine Language Instructions
Program is stored in memory
A machine language instruction consists of:

Operation code, telling which operation to perform
Address field(s), telling the memory addresses of the
values on which the operation works.
as machine language instructions, in binary
The task of the control unit is to execute

programs by repeatedly:
Example: ADD X, Y (Add contents of memory locations

X and Y, and store the result back in memory location X).
Assume: opcode for ADD is 9, and addresses X=99,
Y=100
Fetch from memory the next instruction to be

executed.
Decode it, that is, determine what is to be done.
Execute it by issuing the appropriate signals to
the ALU, memory, and I/O subsystems.
Continues until the HALT instruction.
R0
R1
R2
ALU circuitry:
Circuits to do the arithmetic/logic operations.

Registers (fast storage units) to store intermediate
computational results.
Bus that connects the two.
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Opcode (8 bits) Address 1 (16 bits) Address 2 (16 bits)
00001001 0000000001100011 0000000001100100

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Typical Machine Instructions
Machine Instructions
Notation:
Arithmetic/Logic
We use X, Y, Z to denote RAM locations

Assume only one register R (for simplicity)
Use mnemonics (English-like descriptions) (should
be binary)
Data Transfer Instructions

LOAD X
Copy contents of memory location X to R
STORE X
Copy contents of R to memory location X
Compare
R CON(X)
COMPARE X, Y
Compare the contents of memory cell X to the contents
of memory cell Y and set the condition codes (CCR)
accordingly.
CON(X) R
MOVE X, Y Copy the contents of location Y to loc. X
CON(X) CON(Y)
e.g., if CON(X) = CON(Y) then set EQ=1, GT=0, LT=0

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ADD X, Y, Z
CON(X) CON(Y) + CON(Z)
ADD X, Y
CON(X) CON(X) + CON(Y)
ADD X
R CON(X) + R
similar instructions for other operators, SUBTR,OR,etc
Example
Machine Instructions
Branch
JUMP X
Pseudo-code: Set A to B + C
Assuming variable:
Load next instruction from memory

location X
A stored in memory cell 100, B stored in memory

cell 150, C stored in memory cell 151
JUMPGT X
Load next instruction from memory location X only
if GT flag in CCR is set, otherwise load statement
from next sequence location as usual.
In mnemonics (actually in binary)

LOAD 150
ADD 151
STORE 100
JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ
Control
HALT
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or with three-address instruction format
Stop program execution.
ADD 100, 150, 151

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Structure of the Control Unit

PC (Program Counter):
stores the address of next instruction to fetch
IR (Instruction Register):
stores the instruction fetched from memory
Instruction Decoder:
Decodes instruction and activates necessary circuitry
PC
+1
IR
Instruction
Decoder
10
How does it all work together?
Program Execution
Fetch phase
Program Execution:
PC is set to the address where the first program

instruction is stored in memory.
Repeat until HALT instruction or fatal error
Fetch
Decode
Execute
Store
MAR PC (put address in PC into MAR)

Fetch signal (signal memory to read value into MDR)
IR MDR (move value to Instruction Register)
PC PC + 1 (increase address in program counter)
Decode Phase
Instruction decoder IR (decode instruction in IR)
Instruction decoder will then generate the signals to
activate the circuitry to carry out the instruction.
End of loop
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Program Execution
Program Execution
Execute and Store Phases: Differs from one

instruction to the next.
Processor-memory: Data transfer between CPU
and main memory
Processor I/O: Data transfer between CPU and
I/O module
Data processing: Some arithmetic or logical
operation on data
Control: Alteration of sequence of operations
e.g. JUMP, JUMPGT, JUMPEQ
Combination of above
START
0000
0001
0010
0011
0100
0101
0110
Instructions stored in memory are actually

represented in binary.
In our example computer, suppose the instruction
format is as follows:
Execute Cycle
HALT
memory address:
212 = 4,096 memory locations
can be addressed
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64
Operation
Meaning
LOAD X
STORE X
CLEAR X
ADD X
INCREMENT X
SUBTRACT X
DECREMENT X
COMPARE X
R CON(X)
CON(X) R
CON(X) 0
R R + CON(X)
CON(X) CON(X) + 1
R R - CON(X)
CON(X) CON(X) 1
If CON(X) > R then GT = 1 else 0
If CON(X) = R then EQ = 1 else 0
If CON(X) < R then LT = 1 else 0
Get next instruction from memory cell X
Get next instruction from memory cell X if GT=1
Get next instruction from memory cell X if LT=1
Get next instruction from memory cell X if EQ=1
Get next instruction from memory cell X if EQ=0
Input an integer value and store in X
Output, in decimal notation, contents of mem. cell X
66
Stop program execution
0111
12 bits
The decoders duty is to detach the op code and the

memory address from the binary representation.
Fetch Cycle
Opcode
Program Execution
memory
4 bits
cell
operation code:
24 = 16 possible
codes
Execute + Store
Instruction Cycle
63
Fetch + Decode
1000
1001
1010
1011
1100
1101
1110
ELE
107
1111
JUMP X
JUMPGT X
JUMPLT X
JUMPEQ X
JUMPNEQ X
IN X
OUT X
Dr.HALT
Derya Altunay
11
Program Execution
Example
Example:
LOAD X (load value in address X into register)
Suppose the following memory locations

contain the given instructions and data:
MAR IR_address
Fetch signal
R MDR
100
101
102
103
104
(Nxt) 105
.....
500
501
502
503
CLEAR X
ADD X
SUBTRACT X
67
The memory locations actually contain

binary numbers
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
.....
16
75
0
0
68
Step 1: To execute the program, initialize PC to 100

Step 2: Fetch instruction and increment PC
Bus
address
Bus
contents
100
101
102
103
104
(Nxt) 105
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
address
Control Unit
instructions
contents
100
101
102
103
104
(Nxt) 105
PC
IR
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
Control Unit
instructions
100 101 PC
LOAD X IR
...........
...........
CCR
(X) 500
(Y) 501
(Z) 502
503
16
75
0
0
Memory
CCR
(X) 500
(Y) 501
(Z) 502
503
data
Arithmetic-Logic Unit
CPU
69
16
75
0
0
Memory
data
CPU
70
Step 3: (Decode and) Execute

Step 4: Go to Step 2
Step 2: Fetch instruction and increment PC

Bus
address
Bus
contents
100
101
102
103
104
(Nxt) 105
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
address
Control Unit
instructions
101
100
101
102
103
104
(Nxt) 105
PC
LOAD X IR
16
contents
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
Control Unit
instructions
101 102 PC
ADD Y IR
16
...........
CCR
(X) 500
(Y) 501
(Z) 502
503
16
75
0
0
Memory
...........
CCR
(X) 500
(Y) 501
(Z) 502
503
data
CPU
71
16
75
0
0
Memory
data
CPU
72
12
Step 3: (Decode and) Execute

Step 4: Go to Step 2
and so on ...
Example
Bus
address
Pseudo-code:
Set Balance to Balance - Withdrawal
Assuming variables Balance stored in memory
contents
100
101
102
103
104
(Nxt) 105
LOAD X
ADD
Y
STORE Z
JUMP Nxt
SUBTRACT X
CLEAR X
Control Unit
instructions
102
PC
cell FF0 with contents 009E, and Withdrawal

stored in memory cell FF1 with contents 0014.
ADD Y IR
16 91
...........
AB0
AB1
AB2
.....
FF0
FF1
R
CCR
(X) 500
(Y) 501
(Z) 502
503
16
75
0
0
Memory
data
CPU
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LOAD FF0
Using the given instruction
SUBTRACT FF1 set table, show at each step,
STORE FF0
the contents of registers PC,
.....
IR, R, and relevant memory
009E
locations in hex.
0014
Example
Memory
Example
CPU registers
Memory
AB0 0FF0
AB0 PC
AB0 0FF0
AB1 5FF1
IR
AB1 5FF1
AB2 1FF0
AB2 1FF0
...
...
...
FF0 009E
FF1 0014
FF1 0014
75
0FF0 IR
009E R
...
...
FF0 009E
FF1 0014
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Copy two numbers from memory cells X and Y, and

add them together. Store the addition result in memory
cell Z.
Copy a number from memory cell X, find its absolute
value, and store it back into the same memory cell.
Write a simple code that inputs a number (N) and
computes the summation from 1 to N.
Pseudo code:
AB1 PC
AB2 1FF0
Examples
CPU registers
AB1 5FF1
AB1 PC
0FF0 IR
Example
AB0 0FF0
CPU registers
...
FF0 009E
Memory
74
Complete the rest of

the steps, and show
final contents, as an
exercise.
Set sum to 0
While (N > 0)
Update sum by sum + N
Decrement N by one
End.
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13
Interrupts
Interrupts
There are two types of interrupts:
An interrupt is an event that interrupts the

microprocessor from its normal sequence of
operations.
Interrupts can be generated internally or externally.
Interrupts signals can be software generated or
hardware generated.
Interrupts can be generated by expected events or
unexpected events.
Interrupts are provided to improve processing
efficiency.
Non-Maskable: Can not be disabled by software instructions.

Maskable: Can be disabled by software instructions or by
hardware flags. For some interrupt signals there is a general
enable signal and a local enable signal that has to be provided.
Typical applications of interrupts:

To indicate that an I/O device needs to be attended by the CPU.
To synchronize programs or operations.
To indicate illegal operations or errors in the execution of
instructions.
To execute or initiate a program when a specific event occurs.
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Interrupts
Transfer of Control via Interrupts
Class of interrupts:
Program: Generated by some condition that occurs as a result
of an instruction execution such as arithmetic overflow division
by zero, attempt to execute an illegal machine instruction, and
reference outside a users allowed memory space.
Timer: Generated by a timer within the processor. This allows
the operating system to perform certain functions on a regular
basis. Used in pre-emptive multi-tasking.
I/O: Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of error
conditions.
Hardware failure: Generated by a failure such as power
failure or memory parity error.
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The processor and the operating system are responsible for

suspending user program and resuming it at the same point.
References
1) Technology In Action, Complete, 10/E, Evans, Martin and
Poatsy, Pearson.
Interrupts disabled
Interrupts enabled
Fetch and
Decode
Execute and
Store
Check and
process
interrupt
2) Tomorrows Technology and You, Complete, 10/E,

Beekman, Pearson.
3) Computers Are Your Future, Complete, 12/E, Laberta,
Pearson.
Interrupt Cycle
HALT
82
Instruction Cycle with Interrupts
START
80
4) Computer Science: An Overview, 11/E, Brookshear,

Addison Wesley.
5) Invitation to Computer Science, 6/E, Schneider and
Gersting, Cengage Learning.
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ELE 107-Week 8: Computer Architecture and Organization

Architecture and Organization

Computer Architecture and

Architecture and Organization

Refers to the way the system and its resources appear

Architecture and Organization

ELE 107 Dr. Derya Altunay

Structure & Function

Even with these definitions, there is no obvious

Architecture and Organization

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

Structure is the way in which components

ELE 107-Week 8: Computer Architecture and Organization

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

Processing from/to storage

e.g. Internet download to hard disk

e.g. updating a student record

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

Processing from storage to I/O

Stored Program concept

ELE 107 Dr. Derya Altunay

e.g. printing a bank account

ELE 107 Dr. Derya Altunay

ELE 107-Week 8: Computer Architecture and Organization

The von Neumann Model

The System Bus Model

The von Neumann model

ELE 107 Dr. Derya Altunay

The System Bus Model

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

ELE 107-Week 8: Computer Architecture and Organization

The System Bus Model

All the various functions performed can be

Store data and program

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

Microprocessor-initiated operations : There

Internal data operations : The internal

Memory Read: Reads data/instructions from

ELE 107 Dr. Derya Altunay

Peripheral operations : External devices or

Interrupt : The P can be interrupted from the normal

Reset : It provides that the program execution starts

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

ELE 107-Week 8: Computer Architecture and Organization

The microprocessor performs these functions

A number of channels in one bus

More lines, the faster data can travel

Power lines may not be shown.

ELE 107 Dr. Derya Altunay

ELE 107 Dr. Derya Altunay

Single Bus Problems

What do buses look like?

Lots of devices on one bus leads to:

Parallel lines on circuit boards