Analog and Mixed-Signal Center, TAMU

Sample-and-Hold Circuit

S/H:

S
t

Vi

S/H
circuit

Vo

Vo
S/H command

Block Diagram

Vi

Idealized Response

Performances of S & H
Realistic Transient Response:
Track
Error

Input &
Output
Voltage

Pedestal

Vin
Voltage Drift
Vout
t
CK
ta

th
t

S/H Circuit Waveforms and Performance Parameters

H

H
Vi
Vi
Vo

Vi

Hold
step
tap

Vo

Droop

tac

ts

Droop

Feedthrough

Vo

Desired
output

Design of Track and hold

Performance Definition
Acquisition Time: the required time for the output transient after
the sampling signal.
Hold Settling Time: the time after the hold signal required for the
output to settle within an acceptable error.
Pedestal Error: due to the transition of sample to hold mode.
Voltage Drift: the rate of discharge of the sampling capacitor
during the hold mode.
Dynamic Range: the ratio of the maximum and minimum input level,
which can be sampled with a given resolution.

Performance Definition
Nonlinearity Error: the maximum deviation of the Vout/Vin

characteristic from the straight line passed through the end points.

Gain Error: the deviation of the slope of the straight line from unity.
Vout

Q
Nonlinearity
Error
1

G
Gain Error= 1 - G

P
0
0

Vin
Analog and Mixed-Signal Center, TAMU

Track and hold

Performance Definition
Hold Mode Feedthrough: the percentage of the input signal that
appears at the output during the hold mode.

CK

Parasitic capacitors
S

Cp
Vin

CS

Vout

Performance Definition
Aperture Error: the random variation of the turn off time of the
switch results in an uncertain sampling time.
t max =

Maximum Allowable
Aperture Error for 1/2 LSB:
f

Vin

10nsec
1nsec

Ideal sampling
point
Sampling
Error

ts
bi s
t
6
bi ts
8
bi ts
bi

10

100psec

12

10psec

1
N +1
f in 2

Aperture
Error
CK

1MHz 10MHz 100MHz 1GHz

fin

Performance Definition
Definition
Performance
Signal-to-Noise Ratio (SNR): the ration of the signal power to the
noise power at the output. The sources of noise are the input and
output buffer, switch, and clock jitter.
Signal to Noise + Distortion Ratio (SNDR): the ration of signal power
to the total noise and harmonic power at the output. The source of
harmonics are the nonlinearity of the buffers and the switch.
CK

* nBin
Vin

nsw *

* nBout
Vout

Sample-and-Hold Basic Architectures

f clk

Q1

Vin

Analysis
QCH COX WLVeff 1
QC
=
=
hld
2
2
where Veff 1 is given by

Vout

Chld
Fig. 1 An open-loop track and hold
realized using MOS technology.
f clk

Vin

Q1

Vout

Veff 1 = VGS1 Vtn = VDD Vtn Vin

V =

QC hld

Chld

C hld

COX WLVeff 1
=
2Chld

COX WLOV (VDD VSS )

Chld

f clk
Fig. 2 An open-loop track and hold realized
using a CMOS transmission gate.

f clk

Vin

Q1

Input
Buffer
1

f clk

Q2

.. .

Vin
1

Vout

COXWL (VDD Vtn Vin )

2Chld

CK

.
C
.

X
S

Chld
Fig. 3 An open-loop track and hold realized using
an n-channel switch along with a dummy
switch for clock-feedthrough cancellation.

Analog and Mixed-Signal Center, TAMU

Output
Buffer
1

Vout

Buffered Sample & Hold Circuit

Input and Output Buffer:
The capacitor voltage during the hold mode can be affected by
the current drawn by the following circuit. Therefore, the output
voltage is buffered.

CK
Bin
Vin

Bout
Vout

Analog and Mixed-Signal Center, TAMU

Unity Gain Buffer Circuit:

BJT and CMOS implementations
Bipolar Technology

CMOS Technology

Vcc

VDD
M3

Rc

M4

Q3
Vin

Q1

Q2

IEE

Vout
IF

Vin

M1

M2

ISS

Vout
IF

Track & Hold (T&H) Circuit

Simple Closed-Loop Architecture:
During the sampling time, the drain and source voltage of MOS
switch are closed to ground. Thus the charge injection and clock
feedthrough introduce an offset voltage at the output and is
independent of the input voltage.

Vin

CK
Gm

V1

V-

Vout

Disadvantage: stability problems and low speed.

T&H Circuit: Closed-Loop Architecture

Offset Voltage Cancellation:
The charge injection and clock feedthrough can be cancel out by
applying a replica of the offset voltage to the positive terminal
of the second amplifier (common-mode voltage).

CK
+

Vin

Gm

Cs
M1

V1

V-

CK

M2

Vout

T&H Circuit: Switched Capacitor

Switched-Capacitor Architecture:
This architecture consists of sampling capacitor CS, amplifier
Gm, and MOS switches.
CK
Vin

M3
CK

Gm
Vout

Track Mode (CK=1)

CK

Vin

CS

M2
M1

CS

CS

Gm
Vout

Vin

Gm
Vout

Hold Mode (CK=0)

Evolution of S/H Architectures

CH

CK

Gm

Vin

clk

Vout

A0

Vin

Fig A. Closed-loop sample-and-hold architecture.

Q3
clk

Vin

Q1

Chld

C. Adding on additional switch to the S/H of

Fig B to minimize slewing time.

Vout

Chld

clk

Opamp 1
+

clk

Fig B. Including an opamp in a feedback loop

of a sample and hold to increase the
input impedance.

clk

Q2

Q1

Vin

Q1

clk

Chld

Q2

Vout

+
Opamp 2

Vout
Fig D An improved configuration for an S/H as
compared to that of Fig C

Design of Track and hold

T&H Circuit: Current-Mode

Current-Mode Architecture:
Advantages: high-speed (over 100MHz) and low voltage (<1.2).
The speed depends on the time constant given by:
VDD
I

AI

Iin

Iout

M1

M2
CS

CS
g m1

CS

CK
Iin

CK

2
C ox (1 + A) W1 L1
3

Iout

g m1

= C ox

W
( VGS VTn )
L

Two Op Amps S/H Circuit

RF

D1
-

D2

A2

SW

A1

+
Vi

S/H

CH

+
Vo

Switch
driver

VCC
R1
Vi

2k

+ A
1
LT118A
-

A1
LT11010

C1
50pF

R3
20
S

R2

S/H

R7
2k

D1

R5 150pF
Q3

HP2810

1k

R6
1k

2N2907

- A
3
LT118A
+

Q1
2N5432

2k
C2

Cds

Q2
2N2222

Cgd

C3
100pF

+
A4
LT118A
R8

CH
1nF

D2
6.2V

5k
C5
10pF

R9

+
Vo
-

R10

10k 50k
R11
6.2k

R7
200k

VEE

A 5 MHz track-and-hold circuit, using discrete components,

with charge compensation to minimize the hold step.

ts1 actual
Vin

f clk

ts 2 ideal

ts1 ideal

ts 2 actual

Sampling jitter

Fig. The clock waveforms for V in and clk used to illustrate how a finite slope for the sampling
clock introduces sampling-time jitter.

CH

CK
+

Vin

Gm

M1

CK

M2

.
.

A0
+

.
Vout

C2

Fig. Closed-loop sample-and-hold architecture with pedestal cancellation.

S/H Open Loop Architecture with Miller Capacitance

CK

M1

Vin

M2
Y.

A0
+

C2

C1

Vin

Vout

Y.

.Z

A0

Vout

(a)
-

A0
+

C1

C1

Vout

.Z

C2

(b)

.Z

C2
(c)
Fig. Open-loop architecture with Miller capacitance. (a) Basic circuit; (b) equivalent circuit in
the acquisition mode; (c) equivalent circuit in the hold mode.
The open-loop architecture with Miller capacitance employs two different values of capacitance
in the acquisition and hold modes to achieve high speed and small pedestal error. This is
accomplished using a Miller amplifier that multiplies the effective value of the sampling capacitor
by a large number when the SHA enters the hold mode.

Switched-Capacitor S/H Implementations

2

vin

C1

.
.

.
.

C2

vout

A switched-capacitor sample and hole and low-pass filter.

2A
1A

S4
CS

vin

S1

2B

S5

CH

..

1B
1B

S2

S3

COF

2S

.
CX

S6
1B

S7
1

A switched-capacitor S/H.

.
.
.

Vout

MULTIPLEXED-INPUT ARCHITECTURES
Gm1

Vin

R2

. .

Vout

R1

CH
CK

Vin
Gm2

+-

Gm1
-+

+-

R
-+

Vout

C1
CK
-+

CK
(a)

.
.

Gm2
+-

S1

S2

CK C2
A

Rout
X

Vout

Fig. 15(a) Dual-loop multiplexed architecture.

CH

Multiplexed-input architecture. (a) Basic (single-ended) circuit;

(b) equivalent circuit in the hold mode.
R1
Vin

+-

R2

+-

+-

Gm1

-+

-+

C1

-+

Vout

C1

Vout
-+

Gm1

+-

Y
C2

(b)

(c)
C2

Equivalent circuits of dual-loop multiplexed-input architecture. (b) Acquisition mode; (c) hold mode.

T&H Circuit: Current-Mode

Closed-Loop Current-Mode Architecture:
This architecture needs stability and speed considerations.
The distortion of Gm2 affects directly the output current [21].

CK
+
-

Gm1

Cs
M1

Iin

V-

CC

+
-

Gm2

Iout

T&H Circuit: Example

BiCMOS Track & Hold Amplifier (12-Bit & 50Msps):
This circuit consists of input buffer, hold section, and output
buffer [3].
Vcc
VBB1

M1

M3

VBB2

M2

M4

Q5

CS=3pF
CFF is a feedforward
compensation
capacitor for
the charge
injection of Q 4

Vin

Q10

CFF

VBB3

GND

Q1

Q2

Q3
CK
(Track)

CS
Q6
Q4

Q7

Q8

D1

Q9
Vout

CK
(Hold)

Q11

Q12

Q13

Q14

R1

R2

R3

R4

Q15
R5

RECYCLING S/H ARCHITECTURE

S5

.
.

S1
Vin

B1

C1

S2

S4

..

Gm
+

Vout

B2
Y1

S3

X1

.
.

C2

B1

B2
Y1

X1
C1

C2

..

C3

Gm
+

B1

B2
Y1

X1
C1

C2
Gm
+

C3

(a)

Fig. 16 Recycling architecture.

Vout

Vout

Vin

C3

(b)

Fig. 17 Equivalent circuits of recycling architecture.

(a) Sampling mode; (b) hold mode.

Integratating Amplifier S/H Circuit

VCC

Vi

Offset

CH

SW

A1
-

Cgd

A2
+

+
Vo
-

S/H
SW driver

Improved S/H Circuit

SW3
R

Vi

Buffer

CH

SW1

+
Vo
-

S/H
SW driver

SW2

C(=CH)

L.Dai and R. Harjani, CMOS Switched-Op-Amp Based Sample

and Hold Circuit,IEEE JSSC, January 2000, pp 109-113

Charge injection and clock feedthrough mechanism

ON
OFF

Cgs

R
vi

Cgd
q

+
-

M1

Q ch

= WLC ox (VGS

'

V =

''

k Q ch
Ch

V =

( VDD

VSS )C para

C para

Ch

VT )

kWLC ox (VGS
Ch
Ch

+1

VT )

vo

Channel charge in (top) triode and (bottom) saturation

S

VG

VG

SOP
+

Vin

Vout

+1
Ch

Switched-Op-Amp-Based S/H Circuit

R1=100k

R2=100k
-

Vin-

S1

Vin+

Ib=5u
M1
4/2

Gm

1m

Vdd=5V

S2
M2
4/2

Gm
1m

+1

Vout+

Ch1=1p

Ch2=1p

Ib=5u
Vdd=5V

+1

Vout-

Simplified model of the pseudo-differential SOP-based S/H

Folded cascode switched op-amp in the unity-gain feedback configuration

Vdd
clk
pbias

M19

M3

M4

M5

pcas

M6
M8
M1

M2

Vin

M7

clk

VPerr

clk

Vout
M15

M10

M11
2

Ch

M16 M12

M14

M9

M13

VNerr

M18

ncas
nbias

Vbuf

C Npara
Ch

C Npara

C Ppara
Ch

C Ppara

M17

VN GS
VPGS

clk

Simulation results of the

spectrum of the sampledand-held waveform
PSD of Input (dB/Hz)

Differential Input / Output (V)

Simulation results for a

complete cycle of sampledand-held waveform

Time(us)

Frequency (kHz)

References
[1] U.L. McCreary and P.R. Gray, All-MOS charge redistribution analog-to-digital conversion
techniques, IEEE J. Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975.
[2] P. Van Peteghem and W. Sanaen, Single versus complementary switches: A discussion of
clock feedthrough in SC circuits, in Proc. 12th Eur. Solid-State Circuits Conf. (ESSCIRC
86), Delft, the Netherlands, Sept. 1986, pp. 16-18.
[3] C. Eichenberger and W. Guggenbuhl, Dummy transistor compensation of analog MOS
switches, IEEE J. Solid-State Circuits, vol. 24, pp. 1143-1146, Aug. 1991.
[4] M. Nayebi and B.A. Wooley, A 10-bit video BiCMOS track-and-hold amplifier, IEEE J.
Solid-State Circuits, vol. 24, pp. 1507-1516, Dec. 1989.
[5] P.J. Lim and B.A. Wooley, A high-speed sample-and-hold technique using a miller hold
capacitance, IEEE Solid-State Circuits, vol. 26, pp. 643-651, Apr. 1991.
[6] G.C. Temes, Y. Huang, and P.F. Ferguson Jr., A high-frequency track-and-hold stage with
offset and gain compensation, IEEE Trans. Circuits Syst. II, vol. 42, pp. 559-560. Aug.
1995.
[7] S. Brigati, F. Maloberti, and G. Torelli, A CMOS sample and hold for high-speed ADCs,
in Proc. IEEE Int. Symp. Circuits and Systems Circuits and Systems Connecting the
World, vol. 1, May 1996, pp. 163-166.
[8] J.H. Shieh, M. Patil, and B.J. Sheu, Measurement and analysis of charge injection in
MOS switches, IEEE J. Solid-State Circuits, vol. SC-22, pp. 277-281, Apr. 1986.
[9] G. Wegman, E.A. Vittoz, and F. Rahali, Charge injection in analog MOS switches, IEEE
J. Solid-State Circuits, vol. SC-22, pp. 1091-1097, Dec. 1987.
[10] D. Jons and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
[11] J. Crols and M. Steyaert, Switched-opamp: An approach to realize full CMOS switchedcapacitor circuits at very low power supply voltages, IEEE J. Solid-State Circuits,
vol. 29, no. 8, Aug. 1994.