7851.PCIe Designguides PDF

Board Design Guidelines
for PCI Express Architecture

Zale Schoenborn
Co-Chair, PCI Express Electrical WG
Copyright 2004, PCI-SIG, All Rights Reserved
Agenda
Background
Layout considerations
System board requirements
Add-in card designs
Signal validations
Summary
PCI-SIG APAC Developers Conference
Background
Meet setup/hold timing

Multi-drop parallel I/O
Single strobe, multiple data
Match all data to strobes
MCH
CLK
T/s
M
533
CONN
AGP source synchronous
CONN
PCI common clock
CONN
Bus Topology Evolution
T/s
M
133
MCH
T/s
G
+
2.5
PCI Express serial differential

CONN
Embedded clock
Point-to-point, match per data pair only
Longer route, creative device placement
MCH
PCI
PCI Express
Express pt-to-pt
pt-to-pt routing
routing is
is straightforward
straightforward
Background
Serial Differential
Add-in card
System board
RX
AC caps
TX
Transmitter &
package
PCI Express
Connector
D+
D-
TX
RX
RX
Receiver &
package
Diff pairs
AC coupled
Lane-to-lane
de-skew
Polarity
inversion
On-chip
equalization
(de-emphasis)
800 mV
TX Spec
Eye
Interconnect
Loss < 13.2 dB
Jitter < 0.3 UI
On-chip
terminations
RX
Spec 175 mV
0.4 UI
UI = Unit Interval = 400ps
(TX eye shown without de-emphasis)
0.7 UI
Background
PCI Express Routing

Trace length matching between pairs
is not required
Embedded clock simplifies
routing rules
Longer motherboard traces

12+ inches possible
TX pairs usually route on top layer

AC coupling caps on TX traces on
system board
AC Coupling Caps
PCI Express x16 Connector
Trace Serpentines Not Required
Background
Interconnect Budget
Loss and jitter are key parameters

Target impedance not as critical
Maintain differential pair symmetry
Design tradeoffs: loss vs. trace length, etc.
Recommended Solution Space:

System board traces:
Up to 12 inches
Add-in card traces:
Up to 3.5 inches
Chip-to-chip routes:
System board traces:
Up to 15 inches
Graphics Add-In Card

Via
Graphics
Engine
Manufacturing
Probe Point
AC-Coupling
Caps
GMCH
Manufacturing
Probe Point
Top
Vcc
Gnd
Bottom
Via
X16 Connector
Manage
Manage loss
loss and
and jitter
jitter to
to meet
meet budget
budget
Stackup Design
No new PCB
technology
required
Standard 4-layer
stackup 0.062
thick PCB
T
Microstrip oz Cu
plated
-OR Stripline 1 oz Cu
T = ~62 mils
(6+ layers)
Follow
Follow simple
simple layout
layout rules
rules &
& design
design tradeoffs
tradeoffs
Trace Geometry & Impedance

Wide pair-to-pair spacing minimize crosstalk
Close intra-pair spacing
Same geometry for interleaved/non-interleaved

Example impedance targets:
Single-end Zo of 60 15%
Differential Impedance of ~100 20%
Tx
Tx
Tx
Tx
5 7 5 20 mil
Tx
Non-interleaved topology example

Rx
Tx
Rx
Interleaved topology example
Microstrip
Tx
5 5 5
Tx
20 mil
Stripline
FR4 Loss Considerations

Stackup: FR4 material
Glass Material
Resin Material
Narrow traces loss
Copper roughness loss
Dielectrics with more resin material
loss
Non-homogeneous dielectrics
Localized Zo variation due to
material weave loss
FR4 cross-section
Wide differential impedance

variation on strip traces
Etching and plating process loss
Trace Length
Longer trace length loss
~0.25 to 0.35 dB inherent loss per inch for FR4
microstrip traces at 1.25GHz
Manage trace lengths to minimize loss

Example: 12 board, 3.5 add-in card lengths
1.25GHz
freq
-5.23dB
20-inch line
dB
Example VNA measurements for

differential strip trace insertion loss
10
Trace Symmetry & Matching

No matching needed pair-to-pair
Match each differential pair per segment
Match overall length 5 mils (recommended)
Symmetric routing for each pair
Preferred
matching
Match
near
mismatch
45 mils
Alternative
matching
11
Bends and Small Serpentines

Avoid tight bends
No 90 bends; impact to loss
and jitter budgets
Keep angles >= 135 (a)

Maintain adequate air gap
A >= 4x the trace width
Lengths of B, C >= 1.5x the

width of the trace
>3w
w
Serpentines length is at least

3w for jog
S1 < 2 S
12
Package Pin Field Breakout

Use side-by-side breakout for package to maintain
symmetry
Avoid tight bends
Side-by-side Best
Adjacent w/ small
serpentine OK
Adjacent w/ bend Fair
Diagonal routing Fair
13
Reference Plane
Full GND plane reference
recommended
Stitching vias required for
layer transition
Keep clearance from
plane voids
Avoid plane splits
Avoid trace over
anti-pad
Gnd stitching via
Plane Void
Long trace routes
14
AC Coupling Caps
Size: 0402 best, 0603 ok
No 0805 size or C-packs
Symmetric placement best
Cap size: 0.1uF best

Same sizes for both D+/D Cap location:
Along Tx pairs on system board
Along Tx pairs on add-in card
15
Test Points & Vias

Minimize via usage
Up to 0.25 dB loss per via
Use via pad size 25 mil, hole size 14 mil; standard
anti-pad size of 35 mil
Put test points or LAI pads in series (if used)

No stubs
Place symmetrically
Provide GND pads for single-ended probing
LAI pads
Probe pads
GND pads
16
Reference Clock
Clocks have no phase relationships
Length matching for clocks is NOT required!
Deliver diff clock to each device and connector

Use same trace geometries as other diff pairs
Clock driver requirements:

100MHz with SSC support (e.g. CK410)
System board (source) termination only
Rise/fall slew rate requirements need to be met
0.5 3.5
22 - 33
5%
Rs
Clock Driver
1 14PCI Express
PCI Express Card
Connector
L1
L2
L4
L5
L1'
L2'
L4'
L5'
0.5
max
Rs
00.2
L3'
Rt
L3
0 0.2
Rt
49.9 1%
17
Connector Layout
Connector with standard PTH
Connector sizes: x1, x4, x8, x16
Pinout optimized for differential routing
& crosstalk reduction
Polarity inversion allowed
Loss & crosstalk part of system

board budget
Side B: Side A:
Tx
Rx
D+
D-
Gnd
Gnd
D+
D-
Gnd
Gnd
Gnd= Green
TX= Red
Rx= Blue
Improved
Improved PTH
PTH connector
connector for
for PCI
PCI Express
Express
18
Power Rails
Increased current capability for x16 connector
ate
d
Up
Additional +12V pin; 1.1 Amp per pin capability
Helpful grouping of power supply pins

Eases power delivery routing
ATX power supply connector

2x12 (recommended)
Power Rail
+3.3V
Voltage Tolerance
Current
+12V
Voltage Tolerance
Current
+3.3Vaux
Voltage Tolerance
Current: Wake
Non-Wake
x16 Connector Spec

9% (max)
3.0 A (max)
8% (max)
5.5A (max)
9% (max)
375 mA (max)
20 mA (max)
19
Power Consumption
ate
d
Up
PCI Express introduces a spec for 75W cards

Available for x16 connectors
Allows for performance graphics cards
75W can be fully drawn thru x16 connector
Note: 25W at initial power-up
(75W after configuration as a high power device)
Up to 25W allowed for x1,x4,x8 cards

Connector Size Power Consumption Allowances
X1
Standard height
10 W 1
(max)
Low profile card
10 W (max)
25 W
(max)
x4/x8
x16
25 W (max)
25 W1
(max)
10 W (max)
25 W (max)
75 W
(max)
1. Max at initial power-up only.
PCI
PCI Express
Express spec
spec support
support for
for 75W
75W cards
cards
20
Power Delivery - 75W Support

Ensure +3.3V & +12V tolerances at add-in card
Max of 2%~3% MB +12V voltage drop (e.g. 360mV)
Typical power supply = 5% drop
Balance trace width vs. length
Example: 100 mils min trace width,
= 12 length for +12V with 1oz Cu
Example uATX +12V layout
Proper power decoupling

Max current slew rate of 0.1A/s
Suppress high freq coupling noise
Tune capacitor type/location
2x12 Power Supply Connector
to board needs
21
Thermal & Acoustic Management

Platforms need to deliver cool air to x16 slot
Use side panel vents, ducting
o
75W card recommendation: 55 C air temp at graphics
card fan intake
Use larger fans for better acoustics
Cool Air
Source
Recommended PCI Express

Side Panel Vent
22
Add-in card requirements
Card Edge Fingers

Remove ref plane under edge
Outer Layer Differential Pair
finger pads
Signal Traces
Better impedance match
Layer 2
Ref Plane
PRSNT1#, PRSNT2# Pins
Outer Layer
Edge Fingers
1mm shorter: last-mate, first

Layer 3 Ref Plane
break Hot-Plug support
Multiple PRSNT2# pins
(x4,x8,x16 cards)
PRSNT1# to PRSNT2#
Cards must strap PRSNT1#
Strapping Example
with furthest PRSNT2# signal
System board Hot-Plug support
optional
23
Card Retention
Card allows for chassis & system board-based retention
Fixed card height & keep outs
Hockey-stick near edge fingers
PCI-SIG* design guideline for retention solution
ate
d
Up
Clip for system board, card hockey-stick

Supports up to 350g for 75W cards
OEMs free to innovate independent solutions
Requires two, 80-mil

diameter holes
Hockey-Stick Retention Mechanism

24
Card Physical Dimensions

End bracket
Top edge keep out and fixed

height to enable chassis
level retention solutions
Hockey-stick to allow for

new retention solutions
Fixed height for I/O cards

(allowance for low profile compliance)
25
Gfx Thermal & Acoustic

Limit heat re-circulated thru Gfx card heat sink
Use shroud to separate fan intake and heat sink
exhaust
Place fan intake near air source- direct away the
exhaust
Reduce fan noise and low speed chatter
Use diode and/or thermister for fan speed control
cool air source (e.g. from chassis vent)
intake
shroud
exhaust
exhaust
26
Signal validations
Lab Signal Measurements

PCI Express devices generate
compliance pattern per spec
Use compliance boards for signal
validation
Compliance Base Board (CBB) for add-in
card measurements
Compliance Load Board (CLB) for system
board measurements
PCI Express connector
CBB Example
Measure eye diagrams with real time

scope
6+ GHz analog bandwidth
20+ Gs sampling bandwidth
Scope vendor should have eye diagram
signal analysis SW tool
CLB Example
27
Signal validations
Acquiring & Interpreting Results

Example
Transition Bit Eye
Probe locations
Tx Signals: measure at 50 loads
Rx Signals: measure at package input
pins
Scope post-processing software

Create transition bit eye
Create de-emphasized eye
Determine:
Example
De--emphasized Bit Eye
De
Max jitter
Min eye voltage margin (high/low)
Max AC common mode voltage
Validate
Validate eye
eye diagrams
diagrams using
using real
real time
time scope
scope
28
Summary
Summary
PCI Express point-to-point layout is
straightforward
Manage loss and jitter from PCB to meet
interconnect budget
Follow basic layout rules and design tradeoffs to
implement typical topologies
Improved connector & add-in card features support for 75 Watt cards
Validate compliance eye diagrams using
compliance boards and real time scope
29
Collateral
For additional and updated information on PCI
Express Architecture, visit
http://www.pcisig.com
30
Thank you for attending the

2004 PCI-SIG Asia-Pacific
Developers Conference.
For more information please go to

www.pcisig.com
31
32

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Board Design Guidelines

for PCI Express Architecture

Copyright 2004, PCI-SIG, All Rights Reserved

PCI-SIG APAC Developers Conference

Copyright 2004, PCI-SIG, All Rights Reserved

Meet setup/hold timing

AGP source synchronous

PCI common clock

Bus Topology Evolution

PCI Express serial differential

Copyright 2004, PCI-SIG, All Rights Reserved

PCI-SIG APAC Developers Conference

Copyright 2004, PCI-SIG, All Rights Reserved

PCI Express Routing

Longer motherboard traces

TX pairs usually route on top layer

Copyright 2004, PCI-SIG, All Rights Reserved

Loss and jitter are key parameters

Recommended Solution Space:

Graphics Add-In Card

Copyright 2004, PCI-SIG, All Rights Reserved

Copyright 2004, PCI-SIG, All Rights Reserved

Trace Geometry & Impedance

Same geometry for interleaved/non-interleaved

Non-interleaved topology example

Interleaved topology example

Copyright 2004, PCI-SIG, All Rights Reserved

FR4 Loss Considerations

Wide differential impedance

Copyright 2004, PCI-SIG, All Rights Reserved

Manage trace lengths to minimize loss

Example VNA measurements for

Trace Symmetry & Matching

PCI-SIG APAC Developers Conference

Copyright 2004, PCI-SIG, All Rights Reserved

Bends and Small Serpentines

Keep angles >= 135 (a)

A >= 4x the trace width

Lengths of B, C >= 1.5x the

Serpentines length is at least

Copyright 2004, PCI-SIG, All Rights Reserved

Package Pin Field Breakout

Copyright 2004, PCI-SIG, All Rights Reserved

Gnd stitching via

Copyright 2004, PCI-SIG, All Rights Reserved

Cap size: 0.1uF best

Copyright 2004, PCI-SIG, All Rights Reserved

Test Points & Vias

Put test points or LAI pads in series (if used)

Copyright 2004, PCI-SIG, All Rights Reserved

System board requirements

Deliver diff clock to each device and connector

Clock driver requirements:

PCI Express Card

PCI-SIG APAC Developers Conference

Copyright 2004, PCI-SIG, All Rights Reserved

System board requirements

Loss & crosstalk part of system

Copyright 2004, PCI-SIG, All Rights Reserved

System board requirements

Additional +12V pin; 1.1 Amp per pin capability

Helpful grouping of power supply pins

ATX power supply connector