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UEEA2223/UEEG4223
Digital CMOS IC
Design
Prepared by
Dr. Lim Soo King
20 Jan 2011.
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Figure 5.1:
Figure 5.2:
Figure 5.3:
Figure 5.4:
Figure 5.5:
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Figure 5.8:
Figure 5.9:
Figure 5.10:
Figure 5.11:
Figure 5.12:
Figure 5.13:
Figure 5.14:
Figure 5.15:
Figure 5.16:
Figure 5.17:
Figure 5.18:
Figure 5.19:
Figure 5.20:
Figure 5.21:
Figure 5.22:
Figure 5.23:
Figure 5.24:
Figure 5.25:
Figure 5.26:
Figure 5.27:
Figure 5.28:
Figure 5.29:
Figure 5.30:
Figure 5.31:
Figure 5.32:
Figure 5.33:
Figure 5.34:
Figure 5.35:
Figure 5.36:
Figure 5.37:
Figure 5.38:
Figure 5.39:
Figure 5.40:
Figure 5.41:
Figure 5.42:
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Figure 5.43: Domino circuit of a 3-input OR gate with feedback control to charge keeper pMOS transistor ...............................................................................................175
Figure 5.44: A domino 3-input OR gate with inverter feedback to charge keeper p-MOS
transistor.........................................................................................................175
Figure 5.45: A basic bi-stable element ...............................................................................176
Figure 5.46: CMOS circuit of a bi-stable element .............................................................176
Figure 5.48: The layout of the bi-stable element................................................................177
Figure 5.49: SR flip-flop ....................................................................................................178
Figure 5.50: CMOS circuit of a SR flip-flop......................................................................178
Figure 5.51: A D flip-flop ..................................................................................................179
Figure 5.52: CMOS circuit of a D flip-flop........................................................................179
Figure 5.53: Transmission gate design of a D flip-flop......................................................180
Figure 5.54: Compact design of D flip-flop .......................................................................180
Figure 5.55: A master/slave D flip-flop .............................................................................181
Figure 5.56: Logic circuit of a JK flip-flop ........................................................................182
Figure 5.57: CMOS circuit design of a JK flip-flop...........................................................182
Figure 5.58: T flip-flop.......................................................................................................183
Figure 5.59: CMOS circuit design of a T flip-flop.............................................................183
Figure 5.60: Block diagram of a 1kx8 SRAM ...................................................................184
Figure 5.61: The six-transistor static RAM cell .................................................................185
Figure 5.62: A three-transistor dynamic RAM cell............................................................186
Figure 5.63: A 1-bit dynamic RAM cell ............................................................................187
Figure 5.64: The voltage bias condition of an inverter or NOT gate .................................188
Figure 5.65: The transient response of a NOT gate............................................................189
Figure 5.66: Switching of the NOT gate ............................................................................193
Figure 5.67: RC model of the inverter................................................................................194
Figure 5.68: The transistor level circuit of a NAND gate ..................................................199
Figure 5.69: Transition table and (b) condition of transistor of NAND gate .....................200
Figure 5.70: NAND circuit for transient response calculation...........................................201
Figure 5.71: Transistor level design of a 2-input NOR gate ..............................................203
Figure 5.72: (a) Transition table and (b) condition of transistor of NOR gate...................204
Figure 5.73: VTC plot of NOR gate, NAND gate and NOT gate ......................................205
Figure 5.74: NOR circuit for transient response calculation..............................................206
Figure 5.75: The drain current versus input voltage of the NOT gate at different mode of
operation ........................................................................................................208
Figure 5.76: Charging and discharging circuits of a NOT gate .........................................208
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Chapter 5
Digital CMOS IC Design
5.0 Introduction
In the CMOS design, p-MOS and n-MOS transistor are used complimentary. PMOS transistor is a logic 0 asserted high output device, which means that when
p-MOS transistor is switched on with logic 0. According to the biasing
condition of p-MOS transistor, the source voltage VS should be larger than drain
voltage VD. Thus, the source of p-MOS transistor is usually connected to VDD
power rail. Therefore, when the p-MOS transistor is switched on, the output will
provide logic 1.
n-MOS transistor is a logic 1 asserted low output device. This shall mean
that logic 1 is used to switch on n-MOS transistor. According to the biasing
condition of n-MOS transistor, drain voltage VD should be larger than source
voltage VS. This shall mean logic 1 asserted low output transistor should be
connected to ground rail or VSS rail. Thus, when the n-MOS transistor is
switched on, the output will provide logic 0.
In this chapter, we shall discuss the transistor level design of logic circuit
and static combinational circuit. The chapter will cover the tri-state circuit. The
designs using pseudo n-MOS transistor, pass-transistor and transmission gate
are discussed in details. Other method for designing the logic circuit such as
mirror logic circuit is discussed.
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Figure 5.13: Pseudo n-MOS transistor circuit of carry out portion of a full adder
The similar approach can be used to design the sum part of the full adder. The
pseudo n-MOS transistor version of the circuit is shown in Fig. 5.14. We shall
discuss the physics of pseudo n-MOS transistor design in details in Section 5.4.
Figure 5.14: Pseudo n-MOS transistor circuit of sum portion of a full adder
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5.3 Pass-Transistor
In this section, the characteristics of MOS transistor when the transistor is used
as pass-transistor are analyzed. The study covers the transfer of voltage from
source to drain and vice versa with the gate used as the control, and the
application of pass-transistor for designing logic circuit.
dVout n
=
(VDD Vout (t ) Vtn )2
dt
2
(5.1)
Integrating equation (5.1) with the condition at time t = 0 output voltage Vout(t)
= 0V, the output voltage Vout(t) is found to be equal to
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t /(2 n )
1 + t /(2 n )
(5.2)
C out
. From equation
n (VDD Vtn )
(5.2), it can be shown that the maximum output voltage Vout(max)(t) is equal to
(VDD-Vtn) for time t . Since the maximum output voltage for an n-channel
MOS pass-transistor is VDD- Vtn, therefore, it is usually claimed that this type of
pass-transistor passes a weak logic 1 and the loss of the output is said to be
threshold voltage loss. It is obvious to maintain conduction, the gate-source
voltage VGS must have a minimum value of Vtn.
5.3.1.2 Pass Logic 0
Lets analyze the circuit when logic 0 is passed through this transistor. The gateto-source voltage VGS is equal to VGS = VDD, whilst the drain-to-source voltage
is VDS = Vout(t). Once can see that the transistor is in linear mode since VDS is
equal to Vsat, which is Vout(max) at time t = 0. The drain-to-source current IDS shall
be
IDS = C out
dVout ( t )
V 2 (t )
= n (VGS Vtn )Vout ( t ) out
dt
2
(5.3)
Integrating this equation with the applied condition yields the output voltage
Vout(t) equal to
Vout(t) = (VDD Vtn )
2 exp( t / n )
1 + exp( t / n )
(5.4)
C out
. For time t,
n (VDD Vtn )
Vout(t) = 0V. Thus, it is claimed that n-channel MOS pass-transistor can pass a
strong logic 0.
5.3.1.3 Switching Time
This section analyzes the low-to-high transition time tLH and the high-to-low
transition time tHL of the n-channel MOS pass-transistor. Equation (5.2) is used
to calculate the low-to-high transition time tLH. Rearrange equation (5.2) yields,
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t = 2 n
1
Vout ( t )
1 V
out (max)
(5.5)
To find tLH time, it is done by setting Vout(t) = 0.9Vout(max). Thus, the low-to-high
transition time tLH is equal to tLH = 18n.
The high-to-low transition time tHL is determined by setting Vout(t) =
0.1Vout(max) using equation (5.4). Rearranging equation (5.4), it yields,
2Vout (max)
t = n ln
1
Vout ( t )
(5.6)
dVout p
=
2(VDD | Vtp |)( VDD Vout ( t )) (VDD Vout ( t )) 2
dt
2
(5.7)
Integrating equation (5.7) with the condition at time t = 0, output voltage is
Vout(t) = |Vtp|, the output voltage Vout(t) is found to be equal to
Vout(t) = VDD (VDD | Vtp |)
2 exp( t / p )
1 + exp( t / p )
(5.8)
C out
. From equation
p (VDD | Vtp |)
(5.8), it can be shown that the maximum output voltage Vout(max)(t) is equal to
VDD for time t. Since the maximum output voltage Vout(max) for a p-channel
MOS pass-transistor is VDD, therefore, it is usually claimed that p-channel passtransistor can pass a strong logic 1.
5.3.2.2 Pass Logic 0
Lets analyze the circuit when logic 0 is passed through this transistor. This is
done by assuming that Vout(t) = VDD at time t = 0. The source-to-gate voltage
VSG is equal to VSG = = Vout(t), whilst the source-to-drain voltage is VSD =
Vout(t). It is obvious to see that the transistor is in saturation mode, which is
Vout(max) at time t = 0. The drain-to-source current IDS shall be
IDS = C out
dVout ( t ) p
(VSG | Vtp |)2
=
dt
2
(5.9)
Integrating this equation with the applied condition yields the output voltage
Vout(t) equal to
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Vout(t) = | Vtp | +
VDD | Vtp |
1 + t / 2 p
(5.10)
For time t, Vout(t) = |Vtp|. Thus, it is claimed that p-channel MOS passtransistor can pass a weak logic 0. This is understood that p-channel MOS
transistor requires at least a VSG voltage of |Vtp| to maintain conduction.
5.3.2.3 Switching Time
This section analyzes the The low-to-high transition time tLH is determined by
setting Vout(t) = 0.9Vout(max) using equation (5.8). Rearranging equation (5.8)
yields.
VDD 2 | Vtp | + Vout ( t )
t = p ln
VDD Vout ( t )
(5.11)
t = 2 p
1
Vout ( t ) | Vtp |
(5.12)
To find the tHL time, it is done by setting Vout(t) = 0.1Vout(max). Thus, the high-tolow transition time tHL is equal to tHL = 18p.
The result shows that it takes 6.1 times the duration to pass logic 0 than
logic 1 through a p-channel MOS pass-transistor.
Owing to threshold voltage loss, it causes static power consumption for in
both p-MOS pass-transistor and n-MOS pass-transistor.
Vout shall be at logic 0 after passing through transistors MnA, MnB, and MnC
for Vin equal to logic 0.
For the case of input is logic 1, the maximum output VA is equal to (VDD Vtn).
Since the gate is connected to VDD, the maximum output VB and VC is also
equal to (VDD Vtn). Thus, for a series-connected n-channel pass-transistor with
input Vin equal to logic 1, the maximum output is equal to (VDD- Vtn).
For series-connected p-channel MOS pass-transistor, the minimum output
is equal to |Vtp| when the input Vin is logic 0.
For a series-connected n-channel MOS pass-transistor configuration shown
in Fig. 5.18, the circuit suffers dual threshold-loss when the input is at logic 1.
The maximum output Vout is equal to (VDD-2Vtn), since the maximum gate
voltage applied to transistor MnB is (VDD- Vtn).
For a series-connected p-channel MOS pass-transistor with the
configuration shown in Fig. 5.18, the minimum output is equal to 2|Vtp| when
the input Vin is logic 0.
Thus, student is remained that design with such configuration is not
recommended due to double threshold loss.
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The design using n-MOS pass-transistor shown in Fig. 5.19 can only pass strong
logic 0 and weak logic 1. One may add two inverters in front of the pass
transistor to get the strong logic 0 and logic 1.
For the circuit to be able to pass both strong logic 0 and logic 1, a design
with both p-MOS and n-MOS pass-transistors are required. Figure 5.20 shows
the design. Again one may add two inverters in front of the pass transistor to get
the strong logic 0 and logic 1.
Figure 5.20: Exclusive NOR gate design using p-channel and n-channel pass-transistors
Lets consider to design a 2-input AND gate. The logic function of the gate is
f(A, B) = A B . The design is shown in Fig. 5.21 using both n-channel and pchannel transistors for obtaining strong logic 0 and logic 1. It is necessary to the
p-channel transistor to provide logic 0, which is B B = 0 , otherwise when input
B has logic 0, the output will be at high impedance or undefined state.
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Figure 5.21: 2-input AND gate design using p-channel and n-channel pass-transistors
The design of a 3-input AND gate with function f(A, B,C) = A B C is shown
in Fig. 5.22. Note p-channel MOS transistors are used to pass logic 0, when
either input B or C or both are at logic 0. Otherwise, the output will be at high
impedance state or undefined state.
Figure 5.22: 3-input AND gate design using p-channel and n-channel pass-transistors
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(a)
(b)
Figure 5.23: (a) A pseudo n-MOS inverter and (b) The voltage transfer characteristic of the
inverter
For the p-MOS transistor, the source-to-drain voltage VSDp is equal to VSDp =
VDD Vout and source-to-gate voltage VSGp is equal to VDD. For the n-MOS
transistor, the gate-to-source voltage VGSn is equal to Vin and the drain-to-source
voltage VDSn is equal to Vout. For input Vin equal to VDD, Vout is equal to VOL,
thus, VGSn = VDD and VSDn = VOL. This is a clear indication that the n-MOS
transistor is in linear mode. For the p-MOS transistor, VSDp = VDD-VOL and VSGp
= VDD. This is an indication that the p-MOS transistor is in saturation mode if
VOL < |Vtp|. Equating the drain current flowed from p-MOS transistor to n-MOS
transistor would obtain equation (5.13).
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2
2(VDD Vtn )VOL VOL
= P VDD Vtp
2
2
(5.13)
P
(VDD Vtp ) 2 ,
n
which indicates that for low VOL, condition n > p is required. The sheet
resistance of the p-MOS transistor is about 2.5 times higher than the sheet
resistance of the n-MOS transistor. As the rule of thumb, the resistance value of
p-MOS transistor should be 5 times the resistance value of n-MOS transistor.
This shall mean (L/W)p = 2(L/W)n. This implies that (W/L)n = 2(W/L)p.
The layout of a complex logic circuit function (A B) + C design with
pseudo n-MOS gate is shown in Fig. 5.34. Notice that the dimension of the nMOS transistor network is two times larger than the grounded p-MOS
transistor.
Figure 5.24: Layout of a complex logic function (A B) + C designed with pseudo n-MOS
gate design concept
created for standalone device that allows user to program for different
functionality. The capability of PLA is limited and has been replaced by
significantly more powerful field programmable gate arrays FPGA. Designer
usually likes to develop PLA into a highly regular, multiple output structure for
the ease of automatic layout generation. Indeed ROM is also designed using this
concept.
The block of a PLA is shown in Fig. 5.25. It consists of an input buffer that
provides both non-inverting and inverting input and a two-level combinational
circuits that provide sum-of-product SOP logic functions. The AND block is
responsible for generate product term and the OR is responsible for selection
of product term to form the desire logic output.
The design examples of logic circuit using PLA is shown in Fig. 5.26.
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The circuit consists of a 2-input AND gate, a 2-input NOR gate, and an
exclusive OR gate. The input buffer provides the inverting and non-inverting
logic, which are A, B, A , and B . The row provides the product term. Row 1
shows the pseudo n-MOS A + B gate, which is also the product term A B . Row
2 shows the pseudo n-MOS A + B gate, which is also the product term A B .
Row 3 shows the pseudo n-MOS A + B gate, which is also the product term
A B . Row 4 shows the pseudo n-MOS A + B gate. Column 1 has a pseudo nMOS inverter, whereby its input is connected to A + B , which will yield (A+B).
However, after connected to an inverter, it yield back A + B logic. Column 2 has
the input of the pseudo n-MOS inverter connected to (A B) , which will result
A B . However, after the inverter, it yields (A B) logic. Column 3 has a 2-input
pseudo n-MOS NOR gate, whereby its inputs are respectively connected to A B
and A B , which would result exclusive NOR gate. However, after the inverter,
it yields back exclusive OR logic.
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shown gives rise to the equation for output voltage. The complicating factor in
solving this equation is depending upon the conduction states of MOS transistor
change as the output capacitor is charged or discharged. To understand the
behavior of the transmission gate, we will separately study the cases for which
correspond respectively to transferring logic 1 through the transmission gate TG
and followed by logic 0 transfer.
5.5.1.1 Transfer Logic 1
The transfer of logic 1 is shown in Fig. 5.28 whereby the input X is set at VDD
and the output Y is Vout with initial condition at 0V. The flow of current is from
left to right.
The drain-to-source voltage of n-MOS transistor VDSn = VDD Vout, whilst the
gate-to-source voltage is equal to VGSn = VDD Vout. Thus, the n-MOS transistor
is at saturation mode at time t = 0 and it will not in linear mode through the
transfer. The n-MOS transistor is in switched off mode if VGSn < Vtn, which is
VDD Vout < Vtn. This shall mean that the n-MOS transistor is in switched-off
mode when Vout > VDD Vtn. Since after switched-off, the transistor will be at
saturation mode, thus, the n-MOS transistor will be in saturation mode if Vout <
VDD Vtn.
The drain-to-source voltage of p-MOS transistor is VDSp = Vout VDD, whilst
the source-to-gate voltage VSGp = -VDD. The p-MOS transistor is in saturation
mode when VDSp > VGSp |Vtp|, which is Vout VDD > - VDD - |Vtp|. Thus, the pMOS transistor will be linear mode Vout > |Vtp|. The p-MOS transistor will be
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switched mode if VGSp < |Vtp|. This implies that |Vtp| > VDD, which cannot be
happened. Therefore, the p-MOS transistor is never in switched-off mode.
Since Vout voltage is gradually increased from 0V to VDD, one can see that
the n-MOS transistor is changing from saturation mode to cut-off mode when
Vout > VDD Vtn. The p-MOS transistor changes from saturation mode to linear
mode when Vout > |Vtp|.
The analysis also shows that there are three operating regions for the
transmission gate. The first region both n-MOS and p-MOS transistors are in
saturation mode until the Vout is equal to |Vtp|. The second region is for Vout
ranges from Vtp to (VDD Vtn). In this region, the n-MOS transistor is in
saturation and p-MOS transistor is in linear region. The third region is for Vout
ranges from (VDD Vtn) to VDD. In this region, the n-MOS transistor is in cut-off
mode and p-MOS transistor is in linear mode.
The channel resistance for various regions can be analyzed based on the
equation for channel resistance, which is Rp,n =
VDS,p ,n
I D,p ,n
2(VDD
2
Vtp ) (VDD Vout )
(5.14)
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Figure 5.29: The Mode condition of n-MOS and p-MOS transistors during output transition
from logic 0 to logic 1
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Since Vout voltage is gradually decreased from VDD to 0V, this draws the
conclusion that there are three operating regions for the transmission gate. The
first region both n-MOS and p-MOS transistors are in saturation mode until the
Vout is equal to (VDD Vtn). The second region is for Vout ranges from (VDD
Vtn) to Vtp. In this region, the p-MOS transistor is in saturation and n-MOS
transistor is in linear region. The third region is for Vout ranges from Vtp to 0. In
this region the p-MOS transistor is in cut-off mode and n-MOS transistor is in
linear mode.
In third region, only n-MOS transistor is operating in linear region,
therefore, the channel resistance Rn is
Rn =
[2(VDD
2
Vtn ) (Vout )]
(5.15)
Figure 5.31 summaries that mode state of the n-MOS and p-MOS transistors
during the output transition from VDD to 0V.
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Figure 5.31: The Mode condition of n-MOS and p-MOS transistors during output transition
from logic 1 to logic 0
Figure 5.32: RC model of a transmission gate with input node X and output node Y
The input to the transmission is a step function Vin(t) = VDDu(t) for transfer from
a logic 0 to logic 1. The output voltage Vout(t) is seen as the charging of
capacitance Cout, which is comprised of CY and the load capacitance CLoad
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through resistance of transmission gate RTG. Thus, the Vout(t) is equal to Vout(t)
= VDD[1-exp(-t/TG)]. CY is equal to CGSn+Kn(0,VDD)CSBn+CGDp+
Kp(0,VDD)CDBp.
For a transfer of logic 1 to logic 0, the Vin(t) is Vin(t) = VDD[1u(t)]. The
output voltage Vout(t) is seeing discharging of through RTG and Cout. Thus, the
output voltage Vout(t) is Vout(t) = VDDexp(-t/TG). Note that u(t) = 0 for t = 0 and
u(t) = 1 for t 0.
The resistance of the transmission gate RTG is generally calculated using
equation (5.16).
RTG =
VTG
I Dp + I Dn
(5.16)
Figure 5.34 shows the resistance of the transmission gate with various output
voltage Vout condition for logic 0 transfer.
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transfer, while P1 is connected in series with the transmission gate. The logic
circuit of 2-to-1 multiplexer is shown in Fig. 5.35.
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Domino circuit is always used in cascade design. The output of each stage is
connected to a MOS transistor in next stage and the output of the later stage is
then connected to a MOS transistor in the forward stage and so on. The example
of the domino logic circuit of Boolean function of a three input OR gate is
shown in Fig. 5.41.
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Since charge leakage problem can lead to error, this problem can be overcome
by adding in the charge keeper p-MOS transistor Mp1 as shown in the domino 3
input OR gate design in Fig. 5.42. If there is any leakage of the capacitor C after
the pre-charge stage, the charge keeper p-MOS transistor Mp1 will be able to
restore the charge of the capacitor C since it is always in the switched-on mode.
Figure 5.42: A domino 3-input OR gate with charge keeper p-MOS transistor
Another improve version of the charge keeper circuit is shown in Fig. 5.43. The
charge keeper p-MOS transistor is biased by the output of the circuit. If the
output is at logic 0, it switches-on the charge keeper p-MOS transistor and
restores the charge due to leakage in the capacitor C. If the output is at logic 1
the charge keeper transistor is in switched-off mode. It also shows that the
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evaluated result is logic 0, which shall mean that the capacitance should lose all
the charges.
Figure 5.43: Domino circuit of a 3-input OR gate with feedback control to charge keeper pMOS transistor
In order to prevent from the parasitic effect, an extra inverter Z can be added as
feedback to the charge keeper p-MOS transistor Mp1. It also frees the output
from slowdown due to induced flipping state of the feedback network. The 3
input OR gate domino circuit with the feedback inverter is shown in Fig. 5.44.
Figure 5.44: A domino 3-input OR gate with inverter feedback to charge keeper p-MOS
transistor
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When logic 1 is connected to input A, the output Q is at logic 0. The logic state
is input to second NOT gate and its output Q will be at logic 1, which is the
same state as the input A. In this manner, the output Q and Q would stay at its
respective logic state even if the logic 1 at input A is removed.
When logic 0 is connected to input A, the output Q will be at logic 1. The logic
state is input to second NOT gate and its output Q will be at logic 0, which is
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the same state as the input A. In this manner, the output Q and Q would remain
at its respective logic state even if the logic 0 at input A is removed. Combining
both conditions of logic states, the bi-stable element forms the basic memory
bit. The layout of the bi-stable element is shown in Fig. 5.48.
The bi-state element has two stable states and one unstable state. The unstable
state occurs at the mid-point voltage. At this point all transistors are in
saturation mode and also at the highest potential energy.
The SR flip-flop is shown in Fig. 5.49. The output Q is Q = S CLK + Q
and Q = R CLK + Q . Using DeMorgans theorem, Q is also equal to Q =
(S + CLK ) Q , which forms the p-MOS transistor circuit of the output Q . Output
Q is also equal to (R + CLK ) Q , which forms the p-MOS transistor circuit of
output Q.
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- 178 -
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Another compact way to design a D flip-flop is shown in Fig. 5.54. The output
at node X is D Load + D Load , which is equal to D. Thus, data D is latched
when Load is equal to logic 1.
In order to avoid wrong data being latch into the D flip-flop, the D flip-flop can
be designed with master/slave operation that utilizing transmission gate and
NOT gates. Figure 5.55 shows the CMOS design of a master/slave D flip-flop.
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Transmission gate B and D are used to prevent the output of master flip-flop
and slave flip-flop from driving the output of transmission gate A and C. Unless
the output of transmission gate A and C is able to sink or source sufficient
current to overcome the output drive from output of master flip-flop and slave
flip-flop, wrong data latch would occur. Besides having transmission gate B and
D, the aspect ratio W/L of transmission gate A and C can be designed sufficient
large as compare with the aspect ratio of other transistor.
At node X, the logic function is Load D and the logic function at node Y is
Load D . The logic function at node Y is Load D Load = (Load D) + Load and the
logic function at node Z is (Load D) + Load = D, which is the data D.
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Based on the output equations mentioned above, the CMOS circuit design of the
JK flip-flop is shown in Fig. 5.57.
= Q T CLK + Q = ( Q + T + CLK ) Q .
- 182 -
Based on the output equations, the CMOS circuit design of the T flip-flop is
shown in Fig. 5.59.
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This memory device has 128 row addresses and 8 column addresses. The
memory has 8 matrix blocks and each block has 128x8 cells. The other main
parts of the memory are the sense amplifier, control unit, input/output data
control, output data control, address bus, and data bus.
We shall discuss the approaches used to design memory cell static and
dynamic cell, the sense amplifier, and the address decoders row and column
decoders, and I/O data control circuits.
During the write cycle, the desired logics are placed on bit line and BIT line.
When the WORD line is asserted, the desired data will be latched into the bistable memory element. For an example, to write logic 1 into the memory, the
BIT line is set at logic 1, whilst the BIT line is at logic 0.
However, due to high pack density of the memory cell whereby many
column memory cells are connected in the same bit line, the total drain-bulk
capacitance of the pass-transistors is sufficiently large that the charging and
discharging of the bit lines would take long time. Thus, during the read cycle,
the BIT and BIT lines are pre-charged to the pre-defined level, which is usually
0.5 of VDD voltage level. These lines are then allowed to float. When the
WORD line is asserted, the BIT line and BIT line begin to charge or discharge
that reflect the logic level stored in memory cell. The small change in voltage
level is passed to the sense amplifier for output user. The read cycle is a
destructive cycle whereby the data stored in the memory can be erased.
Therefore, it is necessary to refresh the memory. Other mean to prevent the bit
data being erased is to design the pass-transistor to have large width and length.
But this is not desired because in the modern design, scale down is necessary to
save cost and fast access time.
- 185 -
The BIT value is logic 0 then the gate voltage shall be 0V. If the BIT value is at
logic 1 then the gate voltage will be at logic 1 that has voltage (VWrite Vtn(M2)).
This voltage is held on as long as the Read transistor M3 is not switched on.
During the read cycle, transistor M3 is switched on and if the BIT value is
logic 1 then the BIT line would turn logic 0. Likewise, if the BIT value is logic
0 then upon reading the BIT line would turn to logic 1 that has maximum value
(VRead Vtn(M3)).
- 186 -
Read cycle is a destructive operation. Thus, the data must be re-written into the
memory capacitor CM.
maximum values of the VGSp are 0 and VDD respectively. Similarly, VGSn also
has the same minimum and maximum values.
When the value of either VGSn or |VGSp| is increased from 0V to VDD volt,
the state of n-MOS transistor and p-MOS transistor moved from cut-off to
saturation region and then move into linear region. This is clearly demonstrated
when the value of VGSn or VGSp are less than the value of Vtn or |Vtp|, the
transistors are in cut-off state. When the values of VGSn or VGSp are greater than
the value of Vtn or |Vtp|, the transistors move into saturation region. This is
because VDS of transistor is greater the value of (VGSn vtn) or (VGSp - |Vtp|). The
transistors finally move to linear state when the values of (VGSn vtn) or (VGSp |Vtp|) are greater than VDS.
The voltage transfer characteristic VTC of a NOT gate or inverter is shown
in Fig. 5.65. It is a plot of output voltage Vout versus input voltage Vin. When the
input voltage is VDD, the output voltage Vout will swing to 0V, which is VOL =
0V. When input voltage Vin is set at 0V, the output will swing to VDD, which is
VOH and it is equal to VDD.
The voltage transfer characteristic VTC of an inverter has three distinct regions;
the low input region where Vin < VIL, the transition region where VIL Vin
VIH, and the high input region Vin > VIH. The output has two transitions, one at
Vin = VIL and one at Vin = VIH. The transition is defined as the region between
point 2 and 4 where the slope = -1.
- 188 -
VOH is the minimum output voltage that will establish a high-level logic 1. VOL
is the maximum output voltage that will establish a low-level logic 0. VIL is the
maximum positive voltage that can be applied to an input terminal of a gate and
still be recognized as logic 0. VIH is the minimum positive voltage that can be
applied to an input terminal of a gate and still be recognized as logic 1.
In transition region, the output is undefined. The width of the transition
region VTW is a measure of ambiguity and is defined as
VTW = VIH VIL
(5.17)
A low VTW is desirable to reduce ambiguity in the input logic-state. Logic swing
VLS is also a measure of ambiguity in logic-state and is defined as
VLS = VOH VOL
(5.18)
- 189 -
n
(Vin Vtn )2 = P 2(VDD Vin | Vtp |)( VDD Vout ) (VDD Vout ) 2
2
2
(5.19)
To derive
dVout
= 1 , one needs to perform partial differentiation at both sides of
dVin
(5.20)
(5.21)
(5.22)
One may take equation (5.19) and (5.22) to solve for two unknowns, which are
Vin = VIL and Vout = VOH respectively.
Point 3 is the mid-point voltage point, where the input voltage Vin is equal
to output voltage Vout. At mid-point voltage VM or switching voltage, both nMOS and p-MOS transistors are in saturation mode. The mid-point voltage VM
can be derived by equating the saturation current of the p-MOS and the n-MOS
- 190 -
(V
n
(VM Vtn )2 =
2
DD
VDD | Vtp | +
VM =
n
Vtn
p
(5.23)
n
1+
p
n
. In order to get symmetrical inverter VTC, the mid-point
p
n
= 1. This shall
p
n
value gives lower mid-point
p
voltage VM.
At point 4, the p-MOS transistor is in saturation region and n-MOS
transistor is in linear region. This point corresponds to the end of transition and
output begins to go to logic 0. This is the region where the gradient of the VTC
is also equal to -1, where the input high voltage VIH and actual output low
voltage VOL can be determined. Based on the condition at this point saturation
p-MOS transistor current is equal to linear n-MOS transistor current. Thus,
p
2
(V
DD
Vin | Vtp |) =
2
n
2
2(Vin Vtn )Vout Vout
2
]
(5.24)
- 191 -
To derive
dVout
= 1 , one needs to partial differentiation both sides of equation
dVin
(5.19), which dependent on voltage Vin at left-hand side and dependent on Vin
and Vout at right-hand side. Thus,
dI Dp
dVin
dVin =
I Dn
I
dVin + Dn dVout
Vin
Vout
(5.25)
I Dn
Vin
dVout dVin
=
I Dn
dVin
Vout
= 1
(5.26)
(5.27)
One may take equation (5.24) and (5.27) to solve for two unknowns, which are
Vin = VIH and Vout = VOL respectively.
In region 5, the p-MOS transistor is in cut-off region, whilst the n-MOS
transistor is in ohmic region. This is the region where the output is at logic 0.
- 192 -
The RC model of the NOT gate is shown in Fig. 5.67. Rp and Rn are the channel
resistances of the p-MOS and n-MOS transistors, which can be calculated from
the ohmic equation of the MOS transistor by assuming the largest possible gateto-source voltage VGS be equal to VDD. Thus, the channel resistance is Rn =
n (VDD Vtn )
simplicity is equal to 1. Applying = 1 to the channel resistance of the nMOS and p-MOS transistors respectively, they become
Rn =
Rp =
(5.28)
n (VDD Vtn )
1
p (VDD | Vtp |)
(5.29)
Rsn and Rsp are sheet resistances of n-MOS and p-MOS transistor respectively.
For 0.12m and VDD = 1.2V technology, the sheet resistances are respectively
equal to Rsn = 1.8k/ and Rsp = 5.5 k/ respectively.
- 193 -
CDp and CDn are the total diffusion capacitance of p-MOS and n-MOS transistors
that were defined earlier. They are defined as
CDp = CGSp + CDBp =
1
C ox LWp + C jp ( WX) p + C jswp (2 W + 2X) p (5.30)
2
1
C ox LWn + C jn ( WX) n + C jswn (2 W + 2X) n (5.31)
2
As for the diffusion capacitance values of sidewall and bottom of drain, what
are specified in equation (5.30) and (5.31) are maximum values, which do not
include the variation due to biasing of the substrate and switching event. The
precise way is to include the linear time-invariant LTI factor. LTI factors for the
sidewall and bottom capacitance are respectively equal to equation (5.32) and
(5.33).
3V
K 1 / 3 (0, VDD ) = bisw
2VDD
V
1 + DD
Vbisw
2/3
and
- 194 -
(5.32)
2Vbisbott
K 1 / 2 (0, VDD ) =
VDD
V
1 + DD
Vbibott
1/ 2
(5.33)
(5.34)
(5.35)
(5.36)
If the inverter drives three NOT gates then the load capacitance CL is equal to
3(CGn + CGp) plus metal interconnect capacitance Cmetal, where CGn and CGp are
the gate capacitance of the n-MOS and p-MOS transistors of the circuit driven
by the inverter. Note that in this case, the Fan-out value FO is equal to three.
(5.37)
t = n ln VDD
(5.38)
Vout
The fall time tf is defined as the time taken for the output to fall from 90% of its
maximum output value to 10% of its maximum output value. Thus, fall time tf is
equal to
tf = n ln VDD -n ln VDD
0.1VDD
0.9VDD
= n ln(9) =
2.2n
(5.39)
2.2C out
. Since VDD >> Vtn,
n (VDD Vtn )
2.2C out
therefore, the fall time tf can be estimated as tf =
. The fall time tf is also
n VDD
(5.40)
where p is the time constant equals to CoutRp. Rewriting equation (5.40) as time
t, it yields equation (5.41).
tr = p ln
VDD
VDD Vout
(5.41)
The rise time tr is defined as the time taken for the output to rise from 10% of its
maximum output value to 90% of its maximum output value. Thus, rise time tr
is equal to
tr= p ln
VDD
VDD
VDD
- p ln
0.9VDD
VDD 0.1VDD
- 196 -
= p ln(9) =
2.2p
(5.42)
2.2C out
. Since VDD >> |Vtp|,
p (VDD | Vtp |)
2.2C out
.
p VDD
The fall time tf is known as tHL time, the high-to-low transition time since
it is the time taken to transit from logic 1 to logic 0. Similarly, the rise time tr is
also known as tLH, the low-to-high transition time since it is the time taken for
the output to transit from logic 0 to logic 1.
The reciprocal of the sum of fall time tf and rise time tr is a time value
used to determine the maximum operating frequency fmax of the NOT gate,
which is shown in equation (5.43).
fmax =
1
t f + tr
(5.43)
Knowing that time constant n = RnCout, p = RpCout and total capacitance Cout =
CFET + CL, the fall time tf and rise time tr are arranged respectively equal to
tf = 2.2n = 2.2 Rn(CFET + CL) = tf0 + pCL
(5.44)
(5.45)
where tf0 = 2.2RnCFET and tr0 = 2.2RpCFET are design dependent values. p and
n are respectively equal to p = 2.2Rp and n = 2.2Rn. From equation (5.44)
and (5.45), one can see that the fall time tf and rise time tr of the NOT gate are
dependent on the external load capacitance CL.
t nf + t pr
(5.46)
where tnf is the time taken for the output to fall from its maximum output
voltage to 50% of its maximum output voltage. Thus, from equation (5.38), tnf is
- 197 -
equal to nln(2). Tpr is the time taken for the output to rise from zero volt to 50%
of its maximum output voltage. From equation (5.41), tpr is equal to pln(2).
Based on the above analysis, the propagation delay time tp is equal to
tp =
ln 2
(n + p)
2
(5.47)
Knowing that n = RnCout, p = RpCout and Cout = CFET + CL, equation (5.47) shall
be
tp =
ln 2
(CFET + CL)(Rn + Rp)
2
(5.48)
From equation (5.48), one can see that the propagation delay time tp of the NOT
is dependent on the load capacitance CL, which has the same conclusion as
shown by equation (5.44) and (5.45) for fall time and rise time.
(5.49)
1
W1 / L1 + W2 / L 2 + ... + Wn / L n
- 199 -
(5.50)
(a)
(b)
Figure 5.69: Transition table and (b) condition of transistor of NAND gate
(5.51)
L1 L 2
L
+
+ ..... + n
W1 W2
Wn
(5.52)
Based on the similar approach, the analysis is similar for the transition from
logic 1 to logic 0. This shall also mean that for simultaneous transition, the
NAND gate can be treated as inverter that has device transconductance
parameter 2p and n/2 respectively for p-MOS and n-MOS transistors. From
the mid-point voltage or inversion threshold voltage equation (5.23), the midpoint voltage of NAND gate during simultaneous input transition is
- 200 -
VM =
n / 2
Vtn
2 p
(5.53)
n / 2
1+
2 p
The result shows that there is a shift of inversion threshold voltage VM toward
the right side of inverters VTC curve since VM value is larger.
Consider the NAND gate transistor circuit shown in Fig. 5.70, the output
capacitance Cout is equal to Cout = CFET + CL, where CFET is equal to CDn + 2CDp
and CL is the load capacitance.
The reason that CFET is equal to CDn + 2CDp is based on worst case scenario.
Since transistor M1 and M2 are connected in parallel, the worst case capacitance
is 2CDp. Since transistor M3 and M4 are connected in series than the worst case
capacitance is CDn.
From equation (5.28) and (5.29), the channel resistances of n-MOS and pMOS transistors are respectively equal to Rn =
1
n (VDD Vtn )
and Rp =
1
.
p (VDD | Vtp |)
During the charging phase, Cout capacitance is charged from 0 volt to VDD volt.
The output voltage Vout is equal to
- 201 -
(5.54)
The time constant p is equal to RpCout, which has the worst case Rp resistance.
Since rise time tr is defined as time taken for Vout to rise from 0.1VDD to 0.9VDD,
therefore, the rise time tr is equal to tr = 2.2p. This equation can be written as
tr = 2.2Rp(CFET + CL)
(5.55)
(5.56)
or
where t0 = 2.2RPCFET is the non load rise time and 0 is equal to 2.2Rp. If both
M1 and M2 transistors are conducting then the channel resistance should be
RP/2. This would give a best case scenario since p in this case is half of the
previous case.
During the discharging of Cout capacitance discharges from VDD volt to 0
volt, the output voltage Vout is equal to
Vout = VDDexp(-t/n)
(5.57)
(5.58)
tf = 2.2n = t1 + 1CL
(5.59)
or
- 202 -
- 203 -
(a)
(b)
Figure 5.72: (a) Transition table and (b) condition of transistor of NOR gate
VM =
2 n
Vtn
p / 2
2 n
1+
p / 2
(5.60)
The result shows that there is a shift of VM toward the left side of inverters
VTC curve since VM is smaller.
The graphs in Fig. 5.73 show the plots of voltage characteristic curves for
NOR gate, NAND gate, and NOT gate.
- 204 -
Figure 5.73: VTC plot of NOR gate, NAND gate and NOT gate
Consider the NOR gate transistor circuit shown in Fig. 5.74, the output
capacitance Cout is equal to Cout = CFET + CL, where CFET is equal to 2CDn + CDp
and CL is the load capacitance.
The reason that CFET is equal to 2CDn + CDp is based on worst case scenario.
Since transistor M3 and M4 are connected in parallel, the worst case capacitance
is 2CDn. Since transistor M1 and M2 are connected in series than the worst case
capacitance is CDp.
- 205 -
The channel resistances of n-MOS and p-MOS transistors are respectively equal
to Rn =
1
n (VDD Vtn )
and Rp =
1
.
p (VDD | Vtp |)
During the charging of Cout capacitance charges from 0 volt to VDD volt, the
output voltage Vout is equal to
Vout = VDD[1- exp(-t/p)]
(5.61)
The time constant p is equal to 2RpCout + RpCY, which has the worst case
channel resistance equal to 2Rp. CY is the inter transistor capacitance of p-MOS
transistor. CY is usually equal to the sum of CDp of transistor M1 and CSp of
transistor M2. Thus, the tr rise time is
tr = 2.2Rp(2CFET + CY + 2CL)
(5.62)
(5.63)
or
where t0 = 2.2RP(2CFET +CY) is the non load rise time and 0 is equal to 4.4Rp.
- 206 -
(5.64)
(5.65)
tf = 2.2n = t1 + 1CL
(5.66)
or
Figure 5.75: The drain current versus input voltage of the NOT gate at different mode of
operation
The output is charged to VDD during transition to logic 1 and discharged to logic
0 during transition to logic 0. The sum of charging and discharging time is
considered as equal to the period T of the input frequency. Thus, the dynamic
current iDD is equal to Q/T, where Q is the charge of output capacitor Cout, which
is also equal to VDDCout. The dynamic power Pdyn is equal to
Q
T
2
Pdyn = VDDiDD = VDD = Cout VDD
f
(5.67)
(a) Input voltage (b) Charging output capacitance Cout (c) Discharging output capacitance
Cout
Figure 5.76: Charging and discharging circuits of a NOT gate
After adding the static power PDC, the total power dissipation PD of the NOT
gate is
2
PD = VDDIDDQ + Cout VDD
f
- 208 -
(5.68)
Exercises
5.1.
5.2.
5.3.
The initial output condition of the transmission gate is 0V. Its input is
then connected to VDD. Calculate the channel resistance of the
transmission gate when the output reaches 0.8VDDV. Given that VDD =
3.0V, the devices transconductance = 1.5x10-3S, and the threshold
voltage of the MOSFET are Vtp = |1.0V| and Vtn = 1.0V respectively.
5.4.
- 209 -
5.5.
5.6.
5.7.
5.8.
From the circuit shown below, what is the logic function at output 1 and
output 2?
5.9.
- 211 -
Bibliography
1.
2.
3.
4.
John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and
Simulation, Thomson, 2006.
John P. Uyemura, Introduction to VLSI Circuits and Systems, John
Wiley & Sons, Inc. 2002.
Etienne Sicard and Sonia Delmas Bendhia, Basics of CMOS Cell
Design, TATA McGraw Hill, 2006.
Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits
Analysis and Design, third edition, McGraw Hill, 2005.
- 212 -