This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2472530, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Three-Phase Single-Switch DCM Boost PFC

Converter with Optimum Utilization Control of
Switching Cycles
Kai Yao, Member, IEEE, Qingsai Meng, Yuming Bo, Wenbin Hu
AbstractThree-phase
single-switch
discontinuous
conduction mode (DCM) boost power factor correction (PFC)
converter features zero-current turn-on for the switch, no
reverse recovery in diode, constant switching frequency
operation, simple control and low cost, which is suitable for
low-to-medium power and cost-sensitive applications. Due to
DCM, the energy transfer does not cover the whole switching
cycle, the RMS and peak values of the inductor current are
large, so do that of the switch and diode. This increases not only
the current stress of the power components but also the
conduction and switching turn-off losses, which lower the
efficiency of the converter. An optimum utilization control of
switching cycles is proposed in this paper so as to increase the
critical boost inductance. The root-mean-square (RMS) and
peak current values of the main power components are reduced
and the conduction and switching turn-off losses are therefore
decreased, leading to a higher efficiency. The proposed method
also slightly achieves the output voltage ripple reduction, and
the input current harmonics comply with the standard of IEC
61000-3-2 Class A.
Index TermsPower factor correction, discontinuous
conduction mode (DCM), optimum utilization control of
switching cycles

I. INTRODUCTION

OWER factor correction (PFC) converters have been

widely used in ac-dc power conversions to achieve high
power factor (PF) and low harmonic distortion. The methods
of achieving PFC can be classified into active and passive
types. Compared with passive PFC converter, active one can
achieve a high PF and a small size, which draws nearly
sinusoidal current out of the source and also the output
voltage is adjustable. There are different topologies and
control strategies for implementing active three phase PFC
converters. Compared with that implemented with s single
switch, three-phase PFC converters with two or more active
switches exhibit better PF and THD. These converters adopt
high number of active switches and thus the structure is
relatively complex and expensive. In addition, complex
control is necessary to achieve a good power factor.
Featuring zero-current turning on for the switch, no reverse

Manuscript received February 17, 2015; revised May 22, 2015 and July 7,
2015; accepted July 21, 2015.
Copyright (c) 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
This work was supported by the national natural science foundation of
China (51307085), natural science foundation of Jiangsu province
(BK2012400), China Postdoctoral Science Foundation (2012M521087),
Postdoctoral Science Foundation of Jiangsu province (1202068C), Science
and Technology Support Program of Jiangsu Province (BE2013125), Jiangsu
province joint innovation fund of industry, education, and researchProspective joint research project (BY2013004-03, BY2013004-01,
BY2013004-04).
K. Yao, Q. Meng, Y. Bo, and W. Hu are with the School of Automation,
Nanjing University of Science and Technology, Nanjing 210094, China
(e-mail: yaokai@nuaa.edu.cn, zzmengsai@163.com, byming@njust.edu.cn,
hwb_njust@163.com).

recovery in diode, simple control and drive, less component

count and low cost, three-phase single-switch DCM boost
PFC converter proposed in [1-2], is suitable for medium and
low power, cost-sensitive applications. In these converters,
the input current is pulsating and an additional filter should
be used to eliminate the high frequency ripple component
[1-10].
For three-phase single-switch DCM boost PFC converter,
if the duty cycle is constant in a line cycle, the average value
of the inductor current in a line cycle is not sinusoidal. The
PF is low and the input current contains rich 5th and 7th
harmonics. Increasing the output voltage can reduce the
current harmonics, but the stress of power component and the
cost will also increase. Some methods have been proposed to
reduce input current harmonics without increasing the output
voltage [11-17]. Adding the 5th harmonic trap in the input
side can reduce the 5th harmonic in the input current and
improve the PF. However, the efficiency decreases as high
circulating current flows in the loop consisting of the trap
filter and the ac source [11]. Variable switching frequency
control can reduce the input current harmonic distortion.
However, the inductor and EMI filter design is a little
complicated [12-14]. Injecting 6th harmonic into the duty
cycle is an effective technique [15-17]. The proposed 6th
harmonic injection circuit, which employs a band-pass filter,
has a severe phase-shift problem and the effect is not so ideal
[15]. Ref. [16] offers another solution, where the harmonic
injection is realized with the out voltage ripple. The method
requires complicated and expensive additional circuitry such
as phase-detecting and phase-locking circuits to properly
synchronize the injected signal with the input current. The
solution proposed in [17] is that the duty cycle is modulated
by subtracting a fraction of the ac component of the rectified
input voltage from the error signal of the output voltage
control loop. However, the input current harmonics distortion
can not be achieved at minimum value over the input voltage
range. In addition, the converter needs a relatively big filter
equipment to fulfill the limitation of EMI. Increasing the
switching frequency can decrease the volume of the filter [18],
but the switching loss will increase at the same time which
will lower the efficiency. In [19-20], resonant techniques are
employed to achieve zero-current switching (ZCS) of the
switch, whereas in [21], ZCS is achieved by using an active
snubber. In [22], coupled inductor and buffering capacitors are
applied to reduce the voltage stress on the main switch and
diode, and the efficiency and THD are improved.
Due to DCM, energy transfer does not cover the whole
switching cycle, the peak and RMS values of the inductor
current is large, so do that of the switch and diode. This
increases not only the current stress of the power components
but also the conduction and switching turn-off loss, which
lowers the efficiency of the converter. An optimum utilization
control of switching cycles (OUCSC) is proposed to increase
the critical inductance without adding extra components.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Compared with conventional constant duty cycle control
(CDCC), the proposed control strategy decreases the peak
and RMS current values of the main power components and
increases the efficiency while remaining a little higher PF.
Meanwhile the output voltage ripple or the output
capacitance can be reduced. And the harmonics comply with
IEC 61000-3-2 Class A regulations. The validity of the
proposed strategy was evaluated on a 2kW prototype and the
experimental results agree with the theoretical analysis well.
II. OPERATION PRINCIPLE OF THREE-PHASE SINGLE-SWITCH
DCM BOOST PFC CONVERTER
Fig. 1 shows the main circuit of a three-phase
single-switch boost PFC converter, where La=Lb=Lc=L [1-2].

(a)

(b)

(c)

Fig. 4. Equivalent circuits: (a) Qb conducts; (b) Qb turns off; (c) Qb

turns off and ia =0.

When Qb turns off, the inductor current reaches its peak

value, which is
iap1 = DyTs dia dt = va Dy Ts L
(8(a))
ibp1 = DyTs dib dt = vb DyTs L
(8(b))
icp1 = DyTs dic dt = vc DyTs L
(8(c))
where Dy is the duty cycle and Ts is the switching cycle.
(2) Switching mode 2
When Qb turns off, Db conducts. Fig. 4(b) shows the
equivalent circuit, from which it can be seen that
va vb Vo = L ( dia dt dib dt )
(9(a))
vc vb Vo = L ( dic dt dib dt )
(9(b))
where Vo is the output voltage.
From (4), (5) and (9), the falling rate of the inductor
current is
dia dt = ( va Vo 3) L
(10(a))

Fig. 1. Main circuit of three-phase single-switch boost PFC converter.

dib dt = ( vb + 2Vo 3) L

(10(c))
ia reaches zero first, the duty cycle corresponding to this
falling period is
iap1 1
3va
DR1 =
=
Dy
(11)
dia dt Ts Vo 3va
When ia reaches zero, ib and ic is
V ( v + 2va ) Dy Ts
di
ibp 2 = ibp1 + b DR1Ts = o b
dt
Vo 3va
L

Fig. 3. Inductor current waveform in a switching cycle during [0, /6].

The input voltage is defined as

va = Vm sin t

vb = Vm sin ( t 2 3 )
vc = Vm sin ( t + 2 3 )

(10(b))

dic dt = ( vc Vo 3) L

Fig. 2. Input voltage waveform.

(1)
(2)

(3)
where Vm and are the amplitude and angular frequency of
the input voltage.
It is obvious that
va + vb + vc = 0
(4)
ia + ib + ic = 0
(5)
Three phase input voltage waveform is shown in Fig. 2. A
line cycle of 2 is divided into 12 intervals. In each interval
of /6, the voltage direction and relative size of the three
phase input voltage is same. Fig. 3 gives out the inductor
current waveform in a switching cycle.
(1) Switching mode 1
When Qb turns on, D1D5D4 conducts. Fig. 4(a) shows the
equivalent circuit, from which it can be seen that
va L dia dt = vb L dib dt = vc L dic dt
(6)
From (4) to (6), the rising rate of the inductor current can
be got as follows
dia dt = va L dib dt = vb L dic dt = vc L
(7)

icp 2 = ibp 2 =

Vo ( vb + 2va ) Dy Ts
Vo 3va

(12(a))
(12(b))

(3) Switching mode 3

When ia reaches zero, the equivalent circuit is shown in
Fig. 4(c), from which it can be seen that
vc vb Vo = L ( dic dt dib dt )
(13(a))
ib = ic
(13(b))
From (13), the falling rate of the inductor current is
dib dt = dic dt = (Vo + vb vc ) 2 L
(14)
From (12) and (14), the duty cycle corresponding to this
falling period of ib and ic is
ibp 2 1
2Vo ( vb + 2va )
(15)
DR 2 =
=
Dy
dib dt Ts (Vo + vb vc )( 3va Vo )

(4) Switching mode 4

During this period, the inductor currents of three phase are
all zero, the output capacitor supply the power to the output
load.
From Fig. 3, during [0, /6], the average inductor current
in a switching cycle can be derived as
iap1
sin t
= I0
ia _ ave = ( Dy + DR1 )
(16(a))
2
3M 3sin t

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

1
Dy ibp1 + DR1 ( ibp1 + ibp 2 ) + DR 2 ibp 2

2
sin 2t M sin (t + 3)
= I0
3M 3sin t ( M cos t )

ib _ ave =

ic _ ave

(16(b))

1
= Dy icp1 + DR1 ( icp1 + icp 2 ) + DR 2 icp 2
2
1
M cos (t + 6 ) sin 2t
2
= I0
3M 3sin t ( M cos t )

3Vm

switching frequency.
For other intervals, the operation principle is similar to that
of [0, /6]. Here the average inductor current, i.e., the input
current of phase a during [0, ] is given as follows
iin _ a = ia _ ave = I 0 kn (t )
(17)

where

sin t
k1 (t )=k6 (t )=
3M -3sin t
1
2
M sin t + sin (2t )
2
3
k2 (t )=
2

3M -3sin (t + 3 ) M -sin (t + 6 )

M sin t +sin (2t +

k3 (t )=

3M +3sin (t + 3

(18(a))

(18(b))

) M -sin (t + )
6

(18(c))

k4 (t )=

k5 (t )=

M sin t -sin (2t - )

3

5
3M -3sin (t + ) M +sin (t + )
3
6
1
2
M sin t - sin (2t +
)
2
3

5
3M +3sin (t + ) M +sin (t + )
3
6

(18(d))

Fig. 5. Inductor current waveform of phase a in a half line cycle.

From (1) and (17), the average input power of phase a is

2
0

vaiin _ a dt =

2 I 0Vm h ( M )

2 I 0Vm

n
6
( n 1)

n =1

Vm

I a _ rms

h(M )

j (M )

Vm
2

kn (t ) sin tdt

(19)

2
0

va iin _ a d t

2 2
0 in _ a

d t

2
=

n =1

n
6
( n 1)

n =1

kn (t ) sin td t

6
n
6
( n 1)

kn2 (t ) d t

(20)

where Ia_rms is the RMS value of the current of phase a,

3

j ( M ) = ( n61) kn2 (t ) d t
n =1

According to (20), the PF depends on M. With a given

output voltage Vo, PF is only related to the input voltage.
According to the specifications which will be given in section
V, Vo=750V and the input PF is plotted as shown in Fig. 14.
III. THE OPTIMUM UTILIZATION CONTROL OF SWITCHING
CYCLES
A. The idea of optimum utilization control of switching
cycles
Taking [0, /6] for example, from Fig. 3 it can be seen that
the inductor current of phase a decreases to zero firstly, the
inductor current of phase b and c decrease to zero at the same
time later. To facilitate a further analysis, this paper proposes
a concept of utilization of the switching cycle, which is
represented by .
=Dy + DR1 + DR 2
(21)
Substitution of (11) and (15) into (21) leads to
= Dy M ( M cos t )
(22)
In order to ensure that the convert operates in DCM, the
condition of 1 should be met.
Supposing the efficiency of the converter is 100%, i.e.
Pin_a=Po/3.
With CDCC, the duty cycle can be derived from (19) as

(18(e))

According to the analyses above, the instantaneous

waveform, the peak value envelope and the average value of
ia are shown in Fig. 5. It can be seen that the shape of the
peak inductor current is sinusoidal, however the shape of the
average inductor current is not sinusoidal and there is
distortion in it.

Pin _ a =

Pin _ a
2

(16(c))

, f s = 1 Ts is the

n
n 1

t n = 1, 2," 6

6
6

n =1

Combining (17-19) and according to [23], the PF can be

calculated as
PF =

where I 0 = Dy2Vo ( 2 Lf s ) , M = Vo

where h ( M ) = ( n61) kn (t ) sin tdt .

Dy =

Po Lf s
3VoVm h ( M )

(23)

From (22) and (23), the critical boost inductance with

CDCC is
2

3VoVm M cos t
h(M )
Po f s
M

(24)

It can be seen that the critical inductance varies during [0,

/6] when specifications of converter is certain. L achieves
the minimum value at t=0. So the critical inductance with
CDCC is
2
3V V M 1
L1 = o m
h (M )
(25)
Po f s M
According to the specifications of converter and (25), the
curve of L1 is plotted in Fig. 10. It can be seen the critical
inductance with CDCC is 186H. Substituting L1=186 H
and (23) into (22), the curves of 1 at the input voltages of
176V, 220V, 264V during [0, /6] are plotted as shown in Fig.
6. As can be seen, 1 decreases progressively within [0, /6],
i.e., an decrease from the biggest at 0 when the utilization of
the switching cycle is high and the discontinuous degree of
the inductor current is low to the smallest at /6, when the
utilization of the switching cycle is low and the
discontinuous degree of the inductor current is high.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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1.2

3_264V

3_176V

3_220V

0.6
2_220V

2_176V

2_264V

1.0
0.9

1_264V
1_220V

0.3

1_176V
0

Fig. 6. The curves at different input voltages during [0, /6].

(a) near t=0

(b) near t=/6

Fig. 7. Inductor current waveforms in a switching cycle.

Fig. 7 shows the waveform of three phase inductor current

around the line angle t=0 and t=/6. Assuming that the
critical inductance with the CDCC remains the same,
decrease Dy around 0 slightly, then around 0 is decreased
correspondingly and the discontinuous degree of the inductor
current is increased. Meanwhile, in order to make the output
power remain the same, Dy should be increased slightly
around the line angle /6, i.e., the utilization of the switching
cycle is increased and the discontinuous degree of the
inductor current is decreased. Then by further decreasing and
increasing Dy around 0 and /6, the utilization of the
switching cycle is further decreased and increased at the
certain corresponding angles and the discontinuous degree of
the inductor current is further increased and decreased. In
other words, with the difference of the duty cycle between 0
and /6 becoming bigger, the line angle, at which 1 is close
to 1, i.e., the inductor current is near quasi-critical conduction
in a switching cycle, is changing progressively from 0 to /6.
It can be predicted that in this process, there is a kind of duty
cycle changing according to a certain law, which makes the
utilization of the switching cycle low, i.e., the discontinuous
degree of the inductor current high at any angle during [0,
/6]. So the critical inductance can be increased on the base
of that with CDCC so as to increase the utilization of the
switching cycle and decrease the discontinuous degree of the
inductor current. Thus the peak and RMS values of the
inductor current can be decreased and the efficiency of the
converter will be higher.
According to the above analyses, the duty cycle around
t=0 and t=/6 should decrease and increase respectively.
Similarly, the corresponding change rhythm of the duty cycle
can be got at other angles during [0, 2], i.e., decreasing
around /32/34/35/3 and increasing around /2

5/67/63/211/6. The expression of the rectified

voltage of the three phase input is given out in (26) and its
waveforms are shown in Fig. 8. It can be seen that the change
rhythm of vg is opposite to that of the expected duty cycle.
Therefore, the rectified input voltage can be introduced into
the duty cycle so as to achieve OUCSC. It should be noted
that, in order to simplify the derivation process, Vm, which
affects the amplitude of the rectified input voltage, should be
eliminated, while the variation rule should be remained.
Therefore, the expression of duty cycle is defined as (27),
where vg 3Vm is utilized.

vg =

3Vm cos t
3Vm cos (t 3)
3Vm cos (t 2 3)
3Vm cos (t )
3Vm cos (t + 2 3)
3Vm cos (t + 3)
3Vm cos t

( 0 t 6 )
( 6 t 2 )
( 2 t 5 6 )
( 5 6 t 7 6 )
( 7 6 t 3 2 )
( 3 2 t 11 6 )
(11 6 t 2 )

vg
Dy = D0 1

3Vm

where is an undetermined coefficient, and 1 vg

(26)

(27)
3Vm

determines the variation rule of the duty cycle. For another,

as the value of duty cycle affects the power of the converter,
D0, being constant in a line cycle, is related to several factors
such as the input and output voltage, the output power, the
switching frequency and the inductance.
According to (26), the schematic diagram of the duty cycle
variation is plotted as shown in Fig. 8.

Fig. 8. Schematic diagram of the rectified input voltage and duty cycle
variation.

B. The derivation of maximum critical inductance

During [0, /6], substitution of (27) into (22) leads to
= D0 M (1 cos t ) ( M cos t )

(28)

Define
f ( M , , t ) = M (1 cos t ) ( M cos t )

(29)
Taking the partial derivatives of f (M, , t) with respect
to t
f ( M , , t )
(t )

f ( M , , t )
0
(t )

( 1 M ) sin t
2
( M cos t )

(30)

with 0<1/M, thus f(M,,t) decreases

monotonically and the maximum value occurs at t=0.

f ( M , , t )
> 0 with 1/M<<1, thus f(M,,t) increases
(t )
monotonically and the maximum value occurs at t=/6.
Therefore, the following equation is got
f ( M , ,0 ) = (1 ) (1 1 M ) 0 < 1 M
f max ( M , , t ) =
f ( M , , 6 ) = 1 3 2 1 3 2 M 1 M < < 1

)(

From (17), (19) and (27), it can be derived that

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(31)

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

D0 =

Lf s Po 3VoVm

(1 cos t ) k (t ) sin tdt

2

6
0

(32)

+
n =2

n
6
( n1)
6

1 cos (t 3) kn (t ) sin tdt

2

In order to ensure that the convert operates in DCM, 1

should be met. From (28), (31) and (32), the critical boost
inductance with OUCSC is obtained as

(1 cos t ) k1 (t ) sin td t

3V V 0

n
o m
3
2

cos

3
k

t
sin

td

t
+

(
)
(
)

( n 1)

1
n=2 6

0 <
2

Po f s

1 1 M
L2 =

6
2

(1 cos t ) k1 (t ) sin td t

V
V
3
o m 3 n

+ ( n61) 1 cos (t 3) 2 kn (t ) sin td t

n =2 6
1

< < 1

1 3 2
Po f s

1 3 2 M

Combining the specifications of the converter, from (33),

the critical inductance L2 for OUCSC can be plotted in Fig. 9.
According to Fig. 9 and (33), when >1/M, (33) is a
decreasing function, while when 1/M, (33) is an increasing
function, so L2 gets the maximum value when =1/M.
Substituting =1/M into (27) and (33), the duty cycle and the
critical inductance can be expressed respectively as

1
Dy = D0 1

Fig. 10. Critical inductors over the phase voltage range.

C. The control circuit

vg

1
Vo

Lf s Po 3VoVm

6
0

cos t

1
k1 (t ) sin td t
M

n
6
( n 1)

n=2

+
=

vg

3Vm

L ( H)

(33)

(b)
Fig. 9. Surface and curves of the critical inductance as the function of M
and .

(34)

cos (t 3)
1
k n (t ) sin td t
M

Lf s Po 3VoVm
s (M )

vg
1
V
o

L2 =

where

3VoVm

Po f s

s(M )

(35)

cos t

s ( M ) = 6 1
k1 (t ) sin td t
0
M

n
3
cos (t 3)
+ ( n61) 1
kn (t ) sin td t
M
n=2

6
2

According to the specifications of the converter, from (35),

Fig. 10 is plotted. It can be seen that the critical inductance
with OUCSC is 294H, which is greatly increased, compared
to that with CDCC.

vx v y
vz
Fig. 11. Control circuit for the optimum utilization of switching cycles.

(a)

The control circuit can be implemented as shown in Fig.

11. The input voltage of three phase is sensed through a
differential sampler, and vA=mvg , where m is the voltage
sensor gain. The output voltage signal, sensed through a
voltage divider composed of R8 and R9, can be expressed as
vB=mVo. When R10=R11=R12=R13, the output of the subtractor
vC=vB-vA=m(Vo-vg). The output voltage is regulated through
the error amplifier, and the sensed output voltage through a
voltage divider composed of R14 and R15 is compared with the
reference voltage Vref. vB, vC and vEA, i.e., the error signal
from the compensation network formed by R16 and C1, are
sent to the multiplier whose output vp is compared with the
saw-tooth carrier, and the duty cycle of (34) can be obtained,
where
vP = vEA m (Vo vg ) mVo = vEA (1 vg Vo )
(36)

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IV. PERFORMANCE COMPARISON
A. The utilization of the switching cycle
From (28), (32) and =1/M, with OUCSC is expressed as
Lf s Po 3VoVm
=
(37)
s (M )
In combination with the design parameters of the converter,
the utilization of the switching cycle 2 and 3, with the
inductance L2 for OUCSC of 186 H and 294 H at the input
voltages of 176V, 220V, 264V, can be plotted in Fig. 6,
respectively.
Since the inductor current of phase a decreases to zero firstly
and the inductor current of phase b is negative in a switching
cycle during [0, /6], for the convenience of analysis, the
driving signal of the switch and the waveform of the inductor
current of phase c during [0, /6] under three control situations,
i.e., CDCC, OUCSC (L2 =186 H) and OUCSC (L2 =294 H)
is given out as shown in Fig. 12.
From Fig. 6 and Fig. 12(a), for the CDCC control scheme,
as the sinusoidal AC input voltage changes from the line angle
0 to /6, the utilization of the switching cycle decreases
progressively, while the discontinuous degree of the inductor
current becomes higher. The utilization of the switching cycle
is the highest at 0 and the lowest at /6. A higher input voltage
means a bigger difference between the highest and lowest
utilization. When the input voltage is 264V, the utilization is
1 at 0.

From Fig. 6 and Fig. 12(b), for the OUCSC, when the
critical inductance L2=L1=186 H, compared with Fig. 12(a),
the utilization of the switching cycle is decreased and the
discontinuous degree of the inductor current becomes higher
around the line angle of 0, but around /6, the situation is the
opposite. The utilizations are identical and less than 1 at any
angle within [0, /6]. So the utilization of the switching
cycles can be further increased.
It can be seen from Fig. 6 and Fig. 12(c) that for the
OUCSC with the corresponding critical inductance, the
utilization is the same during [0, /6] and it is 1 at 264V and
close to 1 at 176V and 220V.
B. The PF and input current harmonics
Substituting (23) and (34) into (17), the input current with
CDCC and OUCSC can be expressed respectively as
iin _ a = Po kn ( t ) 6Vm h ( M )
(38)
iin _ a = Po kn ( t ) (1 vg Vo )

( ( n 1)

where

6Vm s ( M )

(39)

6 t n 6 n = 1,2," 6 ) .

From (1) and (39), the PF with OUCSC can be expressed

as
PF =

Pin _ a
Vm
2

I a _ rms

2
0

va iin _ a d t

2 2 2
iin _ a dt
2 0

Vm

cos t
06 1

k1 ( t ) sin td t
M

2
3 n6 cos (t 3)

1
sin
k

td

t
+

(
)

(
1)
n

n=2 6

cos t

2
06 k1 (t ) 1 M dt

(40)
=

s (M )

u (M )

n
3
cos (t 3)
+ ( n61) kn2 ( t ) 1
d t
M
n=2

6
4

.
4
cos ( t 3)
+
k ( t ) 1
dt
M
n=2

According to (40), PF with OUCSC is figured out as

shown in Fig. 13 [31]. It can be seen that PF is a little higher
compared to CDCC.

where
(a) CDCC

cos t
u ( M ) = 6 k12 ( t ) 1
dt
0
M

n
6
( n 1)
6

2
n

1.00

PF

0.99

(b) OUCSC (L2 =186 H)

0.98
CDCC
OUCSC
0.97
176

198

220
Vm / 2

242

264

Fig. 13. Relationship between the input PF and input voltage.

By Fourier analysis, the harmonics of the input current can

be obtained as

a
iin _ a = 0 + an cos ( nt ) + bn sin ( nt )
(41)
2 n =1
where
(c) OUCSC (L2 =294 H)
Fig. 12. The driving signal of the switch and the waveform of the inductor
current during [0, /6].

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

1 2

an = 0 iin _ a cos ( nt )d t ( n = 0,1, 2, )

(42)

b = 1 2 i sin ( nt )d t ( n = 1, 2,3)
n 0 in _ a
Substituting (38) and (39) into (41) respectively, the
harmonics of the input current with CDCC and OUCSC can
be figured out, in which the cosine part, the even and the
triple sinusoidal part are zero, i.e.,
an = 0 ( n = 0,1, 2, ) , b2 n3 n = 0 ( n = 1, 2,3 )
(43)
The normalized amplitudes of the 5th, 7th, 11th and 13th
harmonics to the base of the fundamental component are
shown in Fig. 14. It should be noted that the negative
amplitude means that the corresponding harmonic has an
initial phase of 180. It can be seen that with CDCC the input
current mainly contains the 5th harmonic with an initial phase
of 180o, while the 7th harmonic is dominated with OUCSC.
0.1

1
2
3
4, 5,6

0.0

b5/b1
b7/b1
b11/b1
b13/b1

-0.1
-0.2
-0.3
176

Curves 2, 4, 5, 8: CDCC
Curves 1, 3, 6 ,7: OUCSC
198

220
Vm / 2

7
8
242

respectively, where t1 and t1' are the time instants when pin*
crosses 1 with CDCC and OUCSC, respectively. E1* and
E2* can also be expressed as
2

V 1
V
1
Co Vo + o1 Co Vo o1
6C V V
2
2
2
2

E1* =
= o o o1
Po Tline 6
PoTline
2

(46(a))

V 1
V
1
Co Vo + o 2 Co Vo o 2
6C V V
2
2 2
2
*
E2 =
= o o o2
Po Tline 6
PoTline

(46(b))

where Vo1 and Vo2 are the output voltage ripple with
CDCC and OUCSC, respectively.
From (45) and (46), the expressions of Vo1 and Vo2 are
derived as
t1
Vo1 = 2 Po ( pin* 1 1) dt CoVo
(47(a))
0

t1
Vo 2 = 2 Po (1 pin* 2 ) dt CoVo
(47(b))
0

According to the specifications of the converter, Vo1 and

Vo2 can be figured out as shown in Fig. 16. It can be seen
that with OUCSC, the output voltage ripple is reduced
compared to that with CDCC. In other words, if the
maximum output voltage ripple is kept the same, the storage
capacitor can be reduced.
'

264

Fig. 14. Normalized amplitudes of the harmonics.

C. The reduction of the output voltage ripple

The normalized instantaneous input power is derived as
pin* = ( va iin _ a + vb iin _ b + vc iin _ c ) Po
(44)
The phase difference of a, b, c is 2/3 successively, so
does the phase difference of input current. From (38-39), the
input current of phase b and c namely iin_b and iin_c can be
derived. Then from (44), the normalized instantaneous input
power with CDCC and OUCSC are derived as pin* 1 and

pin

pin* 2 . With 220V input, the curves of pin* 1 and pin* 2 during
[0, /3] are depicted in Fig. 15.

t1'

t2'

Fig. 15. The normalized instantaneous input power.

The storage capacitor Co is charged when pin* >1, and

discharged when pin* <1. The charged and discharged energy
with CDCC and OUCSC are
t1
E1* = 2 ( pin* 1 1) dt (Tline 6 )
(45(a))
0

t1'
E2* = 2 (1 pin* 2 ) dt (Tline 6 )
(45(b))
0

Fig. 16. The output voltage ripple.

V. EXPERIMENTAL VERIFICATION
In order to verify the validity of the proposed optimum
utilization control of switching cycles, a prototype has been
built and tested in the lab. The specifications and components
of the prototype are as follows:
input voltage: vin = 90 ~ 264 VAC / 50 Hz;
output voltage: Vo = 400 VDC;
output power: Po = 120 W;
switching frequency: fs = 100 kHz.
input rectifier diode: STTH12010TV2;
power switch Qb: NGTB20N120IHL-D;
Boost diode Db: DSEI2x61;
boost inductor: L1 = 170 H (CDCC), L2 = 280 H
(OUCSC)
input filter inductor: Lf= 200 H
input filter capacitor: Cf= 0.47 F
output filter capacitor: Co = 102 F
Figs. 17-18 show the experimental waveforms of the input
voltage, input current, boost inductor current and output
voltage ripple with CDCC and OUCSC at 176 VAC, 220
VAC and 264 VAC input respectively. It can be seen that with
both of the control schemes, due to DCM, the input current is
not sinusoidal and the form of distortion is different. A larger
input voltage means more severe distortion.

0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2472530, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Figs. 19-21 show the the measured efficiency, PF, output
voltage ripple.
From Fig. 19 it can be seen that the efficiency is increased
with OUCSC, particularly at low line voltage.
According to Fig. 20, the PF of OUCSC is a little higher
than that of CDCC. A larger input voltage results in a lower
PF. The measured results agree well with that of the
theoretical analysis shown in Fig. 13.
As seen from Fig. 21, the output voltage ripple is reduced
when OUCSC is employed compared to that with CDCC.
The output voltage ripple becomes bigger with the increasing

input voltage. The measured result is in conformity with that

of the theoretical analysis shown in Fig. 16.
Fig. 22 shows the measured 5th, 7th, 11th, 13th harmonics of
the input current at 100%, 50% and 10% loads, respectively,
of which for OUCSC, compared with that of CDCC, the 5th
and 11th harmonic are reduced, while the 7th and 13th
harmonics increase. The harmonics for both CDCC and
OUCSC control schemes meet the IEC 61000-3-2 Class A
standard. The measurement is consistent with the theoretical
analysis as shown in Figs. 14.

(a) 176 VAC

(c) 264 VAC
(b) 220 VAC
Fig. 17. Experimental waveforms of input voltage, input current, inductor current and output voltage with CDCC at 100% load.

(a)176 VAC
(b) 220 VAC
(c) 264 VAC
Fig. 18. Experimental waveforms of input voltage, input current, inductor current and output voltage with OUCSC at 100% load.

Fig. 19. Measured efficiency.

Fig. 20. Measured PF.

Fig. 21. Measured output voltage ripple.

Fig. 22. Measured input current harmonics.

0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2472530, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

VI. CONCLUSIONS
In this paper, an optimum utilization control of switching
cycles is proposed for three-phase single-switch DCM boost
PFC converter. Compared to that with conventional constant
duty cycle control
1. The critical inductance is increased which leads to
decrement of current ripple and higher efficiency;
2. The output voltage ripple or the output storage
capacitance can be reduced also;
3. The PF is a little higher and the input current harmonics
meet the IEC61000-3-2 Class A standard.
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Kai Yao (M'14) was born in Jiangsu Province, China,
in 1980. He received the B.S. degree in industrial
automation from Nantong University, Nantong,
China, the M.S. degree in mechanical design and
theory, and Ph.D. degree in electrical engineering
from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China, in 2002,
2005, and 2010 respectively.
In 2011, he joined the faculty of electrical
engineering, school of automation, Nanjing
University of Science and Technology (NJUST),
where he has been engaged in teaching and research in the field of power
electronics. His research interests include power factor correction converters,
renewable energy generation system and power supplies for LED.
Qingsai Meng was born in Henan Province, China,
in 1991. He received the B.S. degrees in electrical
engineering from Zhengzhou University of Light
Industry (ZZULI), Zhengzhou, China, in 2013.
He is currently pursuing the M.S. degree in power
electronics in Nanjing University of Science and
Technology (NJUST). His research interest is power
factor correction converters.

Yuming Bo was born in Jiangsu Province, China, in

1965. He received the Ph.D. degree in control
science and engineering from Nanjing University of
Science and Technology (NJUST), Nanjing, China,
in 2005.
In 1987, he joined the faculty of automatic control,
school of automation, Nanjing University of Science
and Technology (NJUST). He is a member of the
Chinese Association of Automation and Vice
Chairman of Jiangsu Branch, and a standing council
member of China Command and Control Society. He was granted a
secondary prize of natural science from the ministry of education of China in
2005 and a secondary prize of technology promotion from Shandong
Province in 2012. His research interests include filtering and system
optimization.
Wenbin Hu was born in Jiangsu Province, China, in
1970. He received the Ph.D. degree in electrical
engineering from Nanjing University of Aeronautics
and Astronautics (NUAA), Nanjing, China, in 2003.
In 2004, he joined the faculty of electrical
engineering, school of automation, Nanjing
University of Science and Technology (NJUST), and
he became associate professor in 2010, and he has
been engaged in teaching and research in the field of
power electronics. His research interests include
power factor correction converters, renewable energy
generation system and electric traction system of rail vehicles.

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