EN1802 - Basic Electronics

S7 - Logic Gates and Circuits

By : Dr. S. Thayaparan

Slide contents are extracted from the following source of origin :

1.

Digital Electronics Basics: Combinational Logic, Lecture Notes By Prof. Michael Tse
http://cktse.eie.polyu.edu.hk/eie209

Course Outline
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Introduction
Materials used in Electronics
Diodes, Diode Circuits and Applications
Bipolar Junction Transistors and Circuits
Field Effect Transistors and Circuits
Integrated Circuits and Amplifiers
Logic Gates and Circuits

EN1802 - Basic Electronics

Sequential Logic Circuits

Sequential Logic circuits have some form of inherent memory and they take
their previous inputs and present inputs into account
Output state of a sequential logic circuit is a function of the present input, the
past input and/or the past output
It remembers these conditions until the next clock signal changes its state
In Sequential Logic circuits, the clock signal determines when things will
happen next
Simple sequential logic circuits can be constructed from standard bistable
circuits such as Flip-flops and Latches
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SR NOR latch
NOR Truth Table
X

Out

Symbol for an
SR NOR latch
It is the most fundamental latch
S and R stand for set and reset
R = S = 1 combination is called a restricted
combination or a forbidden state
both NOR gates output zeros, and
breaks Q, relationship
May cause race condition or damped
oscillations
Although this condition is usually
avoided, it can be useful in some
applications
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SR Latch Operation
S

Action

No Change

Q=0

Q=1

Restricted combination

SR NAND Latch
NAND Truth Table

Symbol for an
SR NAND latch

Out

An alternate model of the simple SR

latch
Set and reset now become active low
signals

SR Latch Operation
S

Action

Restricted combination

Q=1

Q=0

No Change

Note: It is forbidden to have both inputs at a logic 0 level at the same time. This
state will force both outputs to a logic 1
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Gated SR NAND Latch

To prevent the system from becoming

unstable:
a. gating the set and reset inputs
using a control input
b. making sure that both set and
reset signals are never active at
the same time
It is called a D latch
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Symbol

Gated SR latch

Gated SR Latch
Operation

SR Latch Operation
S R

Action

0 0

No Change

0 1

Q=0

1 0

Q=1

1 1

Restricted

S R Action

- -

0 0 No Change

0 1 Q=0

1 0 Q=1

1 1 Restricted

No Change

Symbol

Gated D latch

Gated D Latch Operation

E

Action

No Change (Latch)

No Change (Latch)

Q = 0 (reset)

Q = 1 (set)

SR Latch Operation
S R

Action

0 0

No Change

0 1

Q=0

1 0

Q=1

1 1

Restricted

D-Latch

Positive Clock Edge Detection

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Negative Clock Edge Detection

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SR Flip-Flop

Edge detector is attached to the enable input (E) of the Gated SR Latch
SR Latch turns into a SR Flip-Flop since latch operation is done by
detecting the edge of C (Clock) input
Circuit responsive to the S and R inputs only when the clock signal (C) is
transitioning from low to high (positive edge)
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JK Flip-Flop

J-K flip-flop is the most versatile of the basic flip-flops.

It has two inputs, traditionally labeled J and K.
If J and K are different then the output Q takes the value of J at the next clock
edge.
If J and K are both low then no change in outputs occurs.
If J and K are both high at the clock edge then the output will toggle from one
state to the other.
It is a modified version of SR flip-flop with no "invalid" or "illegal" output
state.
It can perform the functions of the SR flip-flop.
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JK Flip-Flop
It has the advantage that there are no ambiguous states.
It can also act as a T flip-flop to accomplish toggling action if J and K are
tied together.
This toggle application finds extensive use in binary counters.

CLK

Q_bar

Pos-edge

No Change

Pos-edge

Pos-edge

Pos-edge

Toggle

Symbol

Truth Table for Basic J-K Flip-flop

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JK Flip-Flop Timing Diagram

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T Flip-Flop

T (toggle) flip-flop changes its output on each clock edge

Output frequency is the half of the input (T) signal frequency
Applications such as binary counters, frequency dividers
T Flip-Flop is made from a J-K flip-flop by tying both of its inputs high
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D Flip-Flop

Symbol

Master-Slave D Flip Flop

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D Flip-Flop with Asynchronous Reset

A D-type flip-flop is the most basic building block in sequential logic circuits
Output must copy the input at either the positive or negative transition of
the clock (rising or falling edge)
If rst = 1, then the output q must be 0 regardless of the status of clk
If rst = 0, then the output must copy the input (q = d) at the positive edge
of clk
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Block Symbols

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Timing Considerations
Setup-Time (tsu) = Minimum time input data must be valid and
before active edge of clock
Hold-Time (th) = Minimum time input date must be held valid
after active edge of clock
Clock-to-output Delay (tco) = Maximum time before output data
is valid with respect to active edge of clock

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