libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

entityd_latch_topis
Port(D:inSTD_LOGIC;
EN:inSTD_LOGIC;
Q:outSTD_LOGIC);
endd_latch_top;

architectureBehavioralofd_latch_topis
signalDATA:STD_LOGIC;
begin

DATA<=Dwhen(EN='1')elseDATA;
Q<=DATA;

endBehavioral;

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

entityd_latch_2_topis
Port(EN:inSTD_LOGIC;
D:inSTD_LOGIC;
Q:outSTD_LOGIC);
endd_latch_2_top;

architectureBehavioralofd_latch_2_topis
begin

process(EN,D)
begin
if(EN='1')then
Q<=D;
endif;
endprocess;

endBehavioral;