Zero-Drift, Single-Supply, Rail-to-Rail

Input/Output Operational Amplifiers

AD8571/AD8572/AD8574
FEATURES PIN CONFIGURATIONS
Low offset voltage: 1 μV NC 1 8 NC
Input offset drift: 0.005 μV/°C –IN A 2 AD8571 7 V+
TOP VIEW
Rail-to-rail input and output swing +IN A 3 6 OUT A
(Not to Scale)
5 V/2.7 V single-supply operation V– 4 5 NC

01104-001
High gain: 145 dB typical NC = NO CONNECT

CMRR: 140 dB typical Figure 1. 8-Lead MSOP (RM Suffix)

PSRR: 130 dB typical
NC 1 8 NC
Ultralow input bias current: 10 pA typical –IN A 2 7 V+
AD8571
Low supply current: 750 μA per op amp +IN A 3 TOP VIEW 6 OUT A
Overload recovery time: 50 μs V– 4 (Not to Scale) 5 NC

01104-004
No external capacitors required NC = NO CONNECT

Figure 2. 8-Lead SOIC (R Suffix)

APPLICATIONS
OUT A 1 8 V+
Temperature sensors AD8572
–IN A 2 7 OUT B
Pressure sensors +IN A
TOP VIEW
–IN B

01104-002
3 6
(Not to Scale)
Precision current sensing V– 4 5 +IN B
Strain gage amplifiers Figure 3. 8-Lead TSSOP (RU Suffix)
Medical instrumentation
OUT A 1 8 V+
Thermocouple amplifiers
–IN A 2 AD8572 7 OUT B
TOP VIEW
+IN A 3 –IN B

01104-005
6
(Not to Scale)
GENERAL DESCRIPTION V– 4 5 +IN B

Figure 4. 8-Lead SOIC (R Suffix)

This family of amplifiers has ultralow offset, drift, and bias
current. The AD8571, AD8572, and AD8574 are single, dual, OUT A 1 14 OUT D

and quad amplifiers, respectively, featuring rail-to-rail input –IN A 2 13 –IN D

+IN A 3 AD8574 12 +IN D
and output swings. All are guaranteed to operate from 2.7 V to
V+ 4 TOP VIEW 11 V–
5 V single supply. +IN B 5 (Not to Scale) 10 +IN C

–IN B 6 9 –IN C
The AD857x family provides benefits previously found only in
01104-003
OUT B 7 8 OUT C
expensive auto-zeroing or chopper-stabilized amplifiers. Using
Analog Devices, Inc., topology, these zero-drift amplifiers Figure 5. 14-Lead TSSOP (RU Suffix)
combine low cost with high accuracy. (No external capacitors
OUT A 1 14 OUT D
are required.) Using a patented spread-spectrum, auto-zero –IN A 2 13 –IN D
technique, the AD857x family eliminates the intermodulation +IN A 3 AD8574 12 +IN D

effects from interaction of the chopping function with the V+ 4 TOP VIEW 11 V–

+IN B 5 (Not to Scale) 10 +IN C

signal frequency in ac applications.
–IN B 6 9 –IN C
01104-006

With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the OUT B 7 8 OUT C

AD857x family is perfectly suited for applications where error
sources cannot be tolerated. Position and pressure sensors,
medical equipment, and strain gage amplifiers benefit greatly
from nearly zero drift over their operating temperature range.
Many more systems require the rail-to-rail input and output
swings provided by the AD857x family.
Figure 6. 14-Lead SOIC (R Suffix)
The AD857x family is specified for the extended industrial/
automotive temperature range (−40°C to +125°C). The AD8571
single amplifier is available in 8-lead MSOP and narrow SOIC
packages. The AD8572 dual amplifier is available in 8-lead narrow
SOIC and surface-mount TSSOP packages. The AD8574 quad
amplifier is available in 14-lead narrow SOIC and TSSOP packages.

Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1999–2008 Analog Devices, Inc. All rights reserved.
AD8571/AD8572/AD8574
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics ...................................................... 3
2.7 V Electrical Characteristics................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description .................................................................. 14
Amplifier Architecture .............................................................. 14
Basic Auto-Zero Amplifier Theory .......................................... 14
Auto-Zero Phase ......................................................................... 15
Amplification Phase ................................................................... 15
High Gain, CMRR, and PSRR .................................................. 16
REVISION HISTORY
6/08—Rev. C to Rev. D
Changes to Figure 19 and Figure 20 ............................................... 8
Changes to Figure 44 ...................................................................... 12
Changes to Figure 38 ...................................................................... 13
Moved Figure 50 and Figure 51 .................................................... 14
Changes to Figure 66, Precision Current Meter Section, Layout,
Figure 67, Equation 24, and Figure 68 ......................................... 21
5/07—Rev. B to Rev. C
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Basic Auto-Zero Amplifier Theory Section ........... 14
Changes to Figure 50 ...................................................................... 15
Changes to Figure 55 ...................................................................... 16
Changes to Figure 66 ...................................................................... 21
Updated Outline Dimensions ....................................................... 22
9/06—Rev. A to Rev. B
Rev. D | Page 2 of 24
Maximizing Performance Through Proper Layout ............... 16
1/f Noise Characteristics ........................................................... 17
Random Auto-Zero Correction Eliminates Intermodulation
Distortion .................................................................................... 17
Broadband and External Resistor Noise Considerations .......... 18
Output Overdrive Recovery...................................................... 18
Input Overvoltage Protection ................................................... 18
Output Phase Reversal ............................................................... 18
Capacitive Load Drive ............................................................... 19
Power-Up Behavior .................................................................... 19
Applications Information .............................................................. 20
5 V Precision Strain Gage Circuit ............................................ 20
3 V Instrumentation Amplifier ................................................ 20
High Accuracy Thermocouple Amplifier ............................... 21
Precision Current Meter ............................................................ 21
Precision Voltage Comparator.................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 23
Updated Format .................................................................. Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Figure 50...................................................................... 14
Changes to Figure 51...................................................................... 15
Changes to Figure 66...................................................................... 21
Deleted Figure 69 and SPICE Macro-Model Section ................ 17
Deleted SPICE Macro-Model for the AD857x Section ............. 18
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
7/03—Rev. 0 to Rev. A
Renumbered Figures .......................................................... Universal
Changes to Ordering Guide .............................................................4
Change to Figure 15. ...................................................................... 16
Updated Outline Dimensions ....................................................... 19
10/99—Revision 0: Initial Version
 AD8571/AD8572/AD8574

SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 5 μV
−40°C ≤ TA ≤ +125°C 10 μV
Input Bias Current IB 10 50 pA
AD8571/AD8574 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C ≤ TA ≤ +85°C 160 300 pA
−40°C ≤ TA ≤ +125°C 2.5 4 nA
Input Offset Current IOS 20 70 pA
AD8571/AD8574 −40°C ≤ TA ≤ +125°C 150 200 pA
AD8572 −40°C ≤ TA ≤ +85°C 30 150 pA
−40°C ≤ TA ≤ +125°C 150 400 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 120 140 dB
−40°C ≤ TA ≤ +125°C 115 130 dB
Large Signal Voltage Gain 1 AVO RL = 10 kΩ, VO = 0.3 V to 4.7 V 125 145 dB
−40°C ≤ TA ≤ +125°C 120 135 dB
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 4.99 4.998 V
RL = 100 kΩ to GND @ −40°C to +125°C 4.99 4.997 V
RL = 10 kΩ to GND 4.95 4.98 V
RL = 10 kΩ to GND @ −40°C to +125°C 4.95 4.975 V
Output Voltage Low VOL RL = 100 kΩ to V+ 1 10 mV
RL = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV

RL = 10 kΩ to V+ 10 30 mV
RL = 10 kΩ to V+ @ −40°C to +125°C 15 30 mV
Short-Circuit Limit ISC ±25 ±50 mA
−40°C to +125°C ±40 mA
Output Current IO ±30 mA
−40°C to +125°C ±15 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB
−40°C ≤ TA ≤ +125°C 115 130 dB
Supply Current per Amplifier ISY VO = 0 V 850 975 μA
−40°C ≤ TA ≤ +125°C 1000 1075 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 0.4 V/μs
Overload Recovery Time 0.05 0.3 ms
Gain Bandwidth Product GBP 1.5 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0 Hz to 10 Hz 1.3 μV p-p
0 Hz to 1 Hz 0.41 μV p-p
Voltage Noise Density en f = 1 kHz 51 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
1
Gain testing is dependent upon test bandwidth.

Rev. D | Page 3 of 24
AD8571/AD8572/AD8574
2.7 V ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.

Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 1 5 μV
−40°C ≤ TA ≤ +125°C 10 μV
Input Bias Current IB 10 50 pA
AD8571/AD8574 −40°C ≤ TA ≤ +125°C 1.0 1.5 nA
AD8572 −40°C ≤ TA ≤ +85°C 160 300 pA
−40°C ≤ TA ≤ +125°C 2.5 4 nA
Input Offset Current IOS 10 50 pA
AD8571/AD8574 −40°C ≤ TA ≤ +125°C 150 200 pA
AD8572 −40°C ≤ TA ≤ +85°C 30 150 pA
−40°C ≤ TA ≤ +125°C 150 400 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 115 130 dB
−40°C ≤ TA ≤ +125°C 110 130 dB
Large Signal Voltage Gain 1 AVO RL = 10 kΩ, VO = 0.3 V to 2.4 V 110 140 dB
−40°C ≤ TA ≤ +125°C 105 130 dB
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.005 0.04 μV/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 2.685 2.697 V
RL = 100 kΩ to GND @ −40°C to +125°C 2.685 2.696 V
RL = 10 kΩ to GND 2.67 2.68 V
RL = 10 kΩ to GND @ −40°C to +125°C 2.67 2.675 V
Output Voltage Low VOL RL = 100 kΩ to V+ 1 10 mV
RL = 100 kΩ to V+ @ −40°C to +125°C 2 10 mV
RL = 10 kΩ to V+ 10 20 mV
RL = 10 kΩ to V+ @ −40°C to +125°C 15 20 mV
Short-Circuit Limit ISC ±10 ±15 mA
−40°C to +125°C ±10 mA
Output Current IO ±10 mA
−40°C to +125°C ±5 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 5.5 V 120 130 dB
−40°C ≤ TA ≤ +125°C 115 130 dB
Supply Current per Amplifier ISY VO = 0 V 750 900 μA
−40°C ≤ TA ≤ +125°C 950 1000 μA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 0.5 V/μs
Overload Recovery Time 0.05 ms
Gain Bandwidth Product GBP 1 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0 Hz to 10 Hz 2.0 μV p-p
Voltage Noise Density en f = 1 kHz 94 nV/√Hz
Current Noise Density in f = 10 Hz 2 fA/√Hz
1
Gain testing is dependent upon test bandwidth.

Rev. D | Page 4 of 24
 AD8571/AD8572/AD8574

ABSOLUTE MAXIMUM RATINGS

Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Parameter Rating
rating only; functional operation of the device at these or any
Supply Voltage 6V
other conditions above those indicated in the operational section of
Input Voltage GND to VS + 0.3 V
this specification is not implied. Exposure to absolute maximum
Differential Input Voltage 1 ±5.0 V
rating conditions for extended periods may affect device reliability.
ESD (Human Body Model) 2000 V
Output Short-Circuit Duration to GND Indefinite THERMAL CHARACTERISTICS
Storage Temperature Range −65°C to +150°C
θJA is specified for the worst-case conditions, that is, θJA is
Operating Temperature Range −40°C to +125°C
specified for a device soldered in a circuit board for SOIC and
Junction Temperature Range −65°C to +150°C
TSSOP packages.
Lead Temperature (Soldering, 60 sec) 300°C
1
Differential input voltage is limited to ±5.0 V or the supply voltage, Table 4. Thermal Resistance
whichever is less. Package Type θJA θJC Unit
8-Lead SOIC (R) 158 43 °C/W
8-Lead MSOP (RM) 190 44 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
14-Lead SOIC (R) 120 36 °C/W
14-Lead TSSOP (RU) 180 36 °C/W

ESD CAUTION

Rev. D | Page 5 of 24
AD8571/AD8572/AD8574

TYPICAL PERFORMANCE CHARACTERISTICS

180 180
VS = 2.7V VS = 5V
160 VCM = 1.35V 160 VCM = 2.5V
TA = 25°C TA = 25°C
140 140

NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS

120 120

100 100

80 80

60 60

40 40

20 20

0 0

01104-010
01104-007
–2.5 –1.5 –0.5 0.5 1.5 2.5 –2.5 –1.5 –0.5 0.5 1.5 2.5
OFFSET VOLTAGE (µV) OFFSET VOLTAGE (µV)

Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage Distribution

50 12
VS = 5V
40 TA = –40°C, +25°C, +85°C VS = 5V
10 VCM = 2.5V
TA = –40°C TO +125°C
INPUT BIAS CURRENT (pA)

30
NUMBER OF AMPLIFIERS

+85°C
8
20

10 6
+25°C
0
4
–10
–40°C
2
–20
01104-008

–30 0

01104-011
0 1 2 3 4 5 0 1 2 3 4 5 6
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET DRIFT (nV/°C)

Figure 8. Input Bias Current vs. Input Common-Mode Voltage Figure 11. Input Offset Voltage Drift Distribution

1500 10k
VS = 5V VS = 5V
TA = 125°C TA = 25°C
1000
1k
INPUT BIAS CURRENT (pA)

OUTPUT VOLTAGE (mV)

500

100
0

SOURCE
–500 10 SINK

–1000
1
–1500

–2000 0.1
01104-012
01104-009

0 1 2 3 4 5 0.0001 0.001 0.01 0.1 1 10 100

COMMON-MODE VOLTAGE (V) LOAD CURRENT (mA)

Figure 9. Input Bias Current vs. Common-Mode Voltage Figure 12. Output Voltage to Supply Rail vs. Load Current

Rev. D | Page 6 of 24
 AD8571/AD8572/AD8574
10k 800
VS = 2.7V TA = 25°C
TA = 25°C

SUPPLY CURRENT PER AMPLIFIER (µA)

700
1k
600
OUTPUT VOLTAGE (mV)

500
100

400
SOURCE SINK
10
300

200
1
100

0.1 0

01104-013

01104-016
0.0001 0.001 0.01 0.1 1 10 100 0 1 2 3 4 5 6
LOAD CURRENT (mA) SUPPLY VOLTAGE (V)

Figure 13. Output Voltage to Supply Rail vs. Load Current Figure 16. Supply Current per Amplifier vs. Supply Voltage

1000 60
VCM = 2.5V VS = 2.7V
VS = 5V 50 CL = 0pF
RL = ∞
40 0
INPUT BIAS CURRENT (pA)

750

PHASE SHIFT (Degrees)

OPEN-LOOP GAIN (dB)
30 45

20 90

500 10 135

0 180

–10 225
250
–20 270

–30

0 –40
01104-014

01104-017
–75 –50 –25 0 25 50 75 100 125 150 10k 100k 1M 10M 100M
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 14. Input Bias Current vs. Temperature Figure 17. Open-Loop Gain and Phase Shift vs. Frequency

1.0 60
VS = 5V
50 CL = 0pF
5V RL = ∞
0.8 40 0
SUPPLY CURRENT (mA)

PHASE SHIFT (Degrees)

OPEN-LOOP GAIN (dB)

2.7V 30 45

0.6 20 90

10 135

0.4 0 180

–10 225

0.2 –20 270

–30

0 –40
01104-015

01104-018

–75 –50 –25 0 25 50 75 100 125 150 10k 100k 1M 10M 100M
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 15. Supply Current vs. Temperature Figure 18. Open-Loop Gain and Phase Shift vs. Frequency

Rev. D | Page 7 of 24
AD8571/AD8572/AD8574
60 300
VS = 2.7V
50 CL = 20pF 270 VS = 5V
RL = 2kΩ
40 240
AV = 100
CLOSED-LOOP GAIN (dB)

OUTPUT IMPEDANCE (Ω)

30 210

20 180
AV = 10
10 150 AV = 100

0 120
AV = 1
–10 90 AV = 10
–20 60

–30 30
AV = 1
–40 0

01104-019

01104-022
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 19. Closed-Loop Gain vs. Frequency Figure 22. Output Impedance vs. Frequency

60
VS = 5V VS = 2.7V
50 CL = 20pF CL = 300pF
RL = 2kΩ RL = 2kΩ
40 AV = 1
AV = 100
CLOSED-LOOP GAIN (dB)

30

20
AV = 10
10

0
AV = 1
–10

–20

01104-023
–30 2µs 500mV

–40
01104-020

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 20. Closed-Loop Gain vs. Frequency Figure 23. Large Signal Transient Response

300
VS = 5V
270 VS = 2.7V CL = 300pF
RL = 2kΩ
240 AV = 1
OUTPUT IMPEDANCE (Ω)

210

180
AV = 100
150

120
AV = 10
90

60
01104-024

30 AV = 1 5µs 1V

0
01104-021

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 21. Output Impedance vs. Frequency Figure 24. Large Signal Transient Response

Rev. D | Page 8 of 24
 AD8571/AD8572/AD8574
45
VS = ±1.35V VS = ±2.5V
CL = 50pF RL = 2kΩ
RL = ∞ 40
TA = 25°C
AV = 1

SMALL SIGNAL OVERSHOOT (%)

35
+OS
30

25

20
–OS
15

10

01104-025
5
5µs 50mV

01104-028
10 100 1k 10k
CAPACITANCE (pF)

Figure 25. Small Signal Transient Response Figure 28. Small Signal Overshoot vs. Load Capacitance

VS = ±2.5V
CL = 50pF 0V
RL = ∞
AV = 1 VS = ±2.5V
VIN VIN = –200mV p-p
(RET TO GND)
CL = 0pF
RL = 10kΩ
AV = –100

VOUT

0V
01104-026

5µs 50mV 20µs 1V

01104-029
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV

Figure 26. Small Signal Transient Response Figure 29. Positive Overvoltage Recovery

50
VS = ±1.35V
45 RL = 2kΩ VIN
TA = 25°C
40
SMALL SIGNAL OVERSHOOT (%)

0V
35 VS = ±2.5V
VIN = 200mV p-p
30 (RET TO GND)
CL = 0pF
+OS RL = 10kΩ
25 AV = –100
0V
–OS
20

15

10 VOUT

5 20µs 1V
01104-030

0
BOTTOM SCALE: 1V/DIV
01104-027

10 100 1k 10k
TOP SCALE: 200mV/DIV
CAPACITANCE (pF)

Figure 27. Small Signal Overshoot vs. Load Capacitance Figure 30. Negative Overvoltage Recovery

Rev. D | Page 9 of 24
AD8571/AD8572/AD8574
140
VS = ±2.5V
RL = 2kΩ VS = ±1.35V
AV = –100 120
VIN = 60mV p-p

100

PSRR (dB)
80

60

40 –PSRR +PSRR

20

01104-031
200µs 1V
0

01104-034
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)

Figure 31. No Phase Reversal Figure 34. PSRR vs. Frequency

140 140
VS = 2.7V VS = ±2.5V
120 120

100 100 +PSRR

PSRR (dB)
CMRR (dB)

80 80

60 60

40 40 –PSRR

20 20

0 0

01104-035
01104-032

100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 32. CMRR vs. Frequency Figure 35. PSRR vs. Frequency

140 3.0
VS = 5V
120
2.5
VS = ±1.35V
RL = 2kΩ
100 AV = 1
OUTPUT SWING (V p-p)

2.0 THD + N < 1%

TA = 25°C
CMRR (dB)

80

1.5
60

1.0
40

20 0.5

0
0
01104-033

100 1k 10k 100k 1M 10M

01104-036

100 1k 10k 100k 1M

FREQUENCY (Hz)
FREQUENCY (Hz)

Figure 33. CMRR vs. Frequency Figure 36. Maximum Output Swing vs. Frequency

Rev. D | Page 10 of 24
 AD8571/AD8572/AD8574
5.5
VS = ±2.5V
5.0 RL = 2kΩ VS = 2.7V
364
AV = 1 RS = 0Ω
4.5 THD + N < 1%
TA = 25°C 312
4.0
OUTPUT SWING (V p-p)

3.5 260

en (nV/ Hz)
3.0
208
2.5
156
2.0

1.5 104
1.0
52
0.5

01104-040
0 0.5 1.0 1.5 2.0 2.5

01104-037
100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (kHz)

Figure 37. Maximum Output Swing vs. Frequency Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz

VS = ±1.35V VS = 2.7V
AV = 120,000 112
RS = 0Ω

96

80

en (nV/ Hz)
0V 64

48

32

16
01104-038

1sec 50mV

01104-041
0 5 10 15 20 25
FREQUENCY (kHz)

Figure 38. 0.1 Hz to 10 Hz Noise Figure 41. Voltage Noise Density from 0 Hz to 25 kHz

VS = ±2.5V VS = 5V
AV = 120,000 182
RS = 0Ω

156

130
en (nV/ Hz)

104

78

52

26
01104-039

1sec 50mV
01104-042

0 0.5 1.0 1.5 2.0 2.5

FREQUENCY (kHz)

Figure 39. 0.1 Hz to 10 Hz Noise Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz

Rev. D | Page 11 of 24
AD8571/AD8572/AD8574
150
VS = 5V VS = 2.7V TO 5.5V
112
RS = 0Ω

POWER SUPPLY REJECTION (dB)

145
96

80
en (nV/ Hz)

140
64

48 135

32
130
16

125

01104-043
0 5 10 15 20 25

01104-045
–75 –50 –25 0 25 50 75 100 125 150
FREQUENCY (kHz) TEMPERATURE (°C)

Figure 43. Voltage Noise Density from 0 Hz to 25 kHz Figure 45. Power Supply Rejection vs. Temperature

50

VS = 5V 40 VS = 2.7V

OUTPUT SHORT-CIRCUIT CURRENT (mA)

210
RS = 0Ω
30
180 ISC–
20
150
en (nV/ Hz)

10

120 0

90 –10

–20 ISC+
60
–30
30
–40

–50
01104-044

0 5 10

01104-046
–75 –50 –25 0 25 50 75 100 125 150
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 44. Voltage Noise Density from 0 Hz to 10 Hz Figure 46. Output Short-Circuit Current vs. Temperature

Rev. D | Page 12 of 24
 AD8571/AD8572/AD8574
100 250

80 VS = 5V 225 VS = 5V
OUTPUT SHORT-CIRCUIT CURRENT (mA)

60 200
ISC–

OUTPUT VOLTAGE (mV)

40 175 RL = 1kΩ
20 150

0 125

–20 100

–40 75
ISC+
–60 50 RL = 10kΩ
RL = 100kΩ
–80 25

–100 0

01104-047

01104-049
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 47. Output Short-Circuit Current vs. Temperature Figure 49. Output Voltage to Supply Rail vs. Temperature

250

225 VS = 2.7V

200
OUTPUT VOLTAGE (mV)

175

150
RL = 1kΩ
125

100

75

50
RL = 10kΩ RL = 100kΩ
25

0
01104-048

–75 –50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 48. Output Voltage to Supply Rail vs. Temperature

Rev. D | Page 13 of 24
AD8571/AD8572/AD8574

FUNCTIONAL DESCRIPTION
The AD8571/AD8572/AD8574 are CMOS amplifiers that
achieve their high degree of precision through random frequency
auto-zero stabilization. The autocorrection topology allows the
AD857x to maintain its low offset voltage over a wide temperature
range, and the randomized auto-zero clock eliminates any inter-
modulation distortion (IMD) errors at the amplifier output.
The AD857x can run from a single-supply voltage as low as 2.7 V.
The extremely low offset voltage of 1 μV and no IMD products
allow the amplifier to be easily configured for high gains without
risk of excessive output voltage errors, which makes the AD857x
an ideal amplifier for applications requiring both dc precision
and low distortion for ac signals. The extremely small temperature
drift of 5 nV/°C ensures a minimum of offset voltage error over
its −40°C to +125°C temperature range. These combined features
make the AD857x an excellent choice for a variety of sensitive
measurement and automotive applications.
AMPLIFIER ARCHITECTURE
Each AD857x op amp consists of two amplifiers: a main amplifier
and a secondary amplifier that is used to correct the offset voltage
of the main amplifier. Both consist of a rail-to-rail input stage,
allowing the input common-mode voltage range to reach both
supply rails. The input stage consists of an NMOS differential
pair operating concurrently with a parallel PMOS differential
pair. The outputs from the differential input stages are combined in
another gain stage whose output is used to drive a rail-to-rail
output stage.
BASIC AUTO-ZERO AMPLIFIER THEORY
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years,
and some improvements have been made over time. The
AD857x design offers a number of significant performance
improvements over older versions while attaining a very
substantial reduction in device cost. This section offers a
simplified explanation of how the AD857x is able to offer
extremely low offset voltages and high open-loop gains.
As noted in the Amplifier Architecture section, each AD857x
op amp contains two internal amplifiers. One is used as the
primary amplifier, and the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figure 50 and Figure 51, these are labeled as
VOSA and VOSB, where A denotes the nulling amplifier and B
denotes the primary amplifier. The open-loop gain for the +IN
and −IN inputs of each amplifier is given as AX. Both amplifiers
also have a third voltage input with an associated open-loop
gain of BX.
VOSB
+
VIN+
AB VOUT
VIN–
BB
ΦB
VOA
CM2
VOSA ΦB
ΦA1
+
AA VNB

The wide voltage swing of the amplifier is achieved by using two –BA ΦA2 CM1
output transistors in a common-source configuration. The output

01104-050
voltage range is limited by the drain-to-source resistance of VNA
these transistors. As the amplifier is required to source or sink Figure 50. Auto-Zero Phase of the Amplifier
more output current, the voltage drop across these transistors
VOSB
increases due to their on resistance (RDS). Simply put, the output +
VIN+
voltage does not swing as close to the rail under heavy output AB VOUT
current conditions as it does with light output current. This is a VIN–
BB
characteristic of all rail-to-rail output amplifiers. Figure 12 and ΦB
VOA
CM2
ΦA VOSA ΦB
Figure 13 show how close the output voltage can get to the rails +
with a given output current. The output of the AD857x is short- AA VNB
circuit protected to approximately 50 mA of current.
–BA ΦA CM1
The AD857x amplifiers have exceptional gain, yielding greater
01104-051

than 120 dB of open-loop gain with a load of 2 kΩ. Because VNA

the output transistors are configured in a common-source
configuration, the gain of the output stage, and thus the open-
loop gain of the amplifier, is dependent on the load resistance.
Open-loop gain decreases with smaller load resistances, which
is another characteristic of rail-to-rail output amplifiers.
Figure 51. Output Phase of the Amplifier
There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.

Rev. D | Page 14 of 24
 AD8571/AD8572/AD8574
AUTO-ZERO PHASE For the sake of simplification, it can be assumed that the auto-
In this phase, all ΦAX switches are closed, and all ΦB switches correction frequency is much faster than any potential change
are open. Here, the nulling amplifier is taken out of the gain in VOSA or VOSB. This is a good assumption because changes in
loop by shorting its two inputs together. Of course, there is a offset voltage are a function of temperature variation or long-
degree of offset voltage, shown as VOSA, inherent in the nulling term wear time, both of which are much slower than the
amplifier, that maintains a potential difference between the +IN auto-zero clock frequency of the AD857x, which effectively
and −IN inputs. The nulling amplifier feedback loop is closed makes the VOS time invariant, and Equation 5 can be rewritten as
through ΦA2, and VOSA appears at the output of the nulling AA (1 + BA )VOSA − AA BAVOSA
VOA [t ] = AAVIN [t ] + (6)
amplifier and on CM1, an internal capacitor in the AD857x. 1 + BA
Mathematically, this can be expressed in the time domain as
VOA[t] = AAVOSA[t] − BAVOA[t] (1) or
⎛ VOSA ⎞⎟
This can also be expressed as VOA [t ] = A A ⎜ V IN [t ] + (7)
⎜ 1 + B A ⎟⎠
A AVOSA [t ] ⎝
VOA [t ] = (2)
1 + BA Here, the auto-zeroing becomes apparent. Note that the VOS
term is reduced by a factor of 1 + BA, which shows how the
The previous equations show that the offset voltage of the nulling
nulling amplifier has greatly reduced its own offset voltage error
amplifier times a gain factor appears at the output of the nulling
even before correcting the primary amplifier. Therefore, the
amplifier and thus on the CM1 capacitor.
primary amplifier output voltage is the voltage at the output of the
AMPLIFICATION PHASE AD857x amplifier. It is equal to
When the ΦB switches close and the ΦAX switches open for VOUT[t] = AB(VIN[t] + VOSB) + BBVNB (8)
the amplification phase, the offset voltage remains on CM1 and
In the amplification phase, VOA = VNB, so this can be rewritten as
essentially corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. The potential difference VOUT [t ] =
between the two inputs to the primary amplifier is designated as ⎡ ⎛ V ⎞⎤ (9)
VIN, or VIN = (VIN+ − VIN−). The output of the nulling amplifier ABVIN [t ] + ABVOSB + BB ⎢ AA ⎜⎜ VIN [t ] + OSA ⎟⎟⎥
can then be expressed as ⎣⎢ ⎝ 1 + B ⎥
A ⎠⎦

VOA[t] = AA(VIN[t] − VOSA[t]) − BAVNA[t] (3) Combining terms yield

Because ΦAX is now open and there is no place for CM1 to VOUT [t ] =

VIN [t ](AB + AA BB ) +
discharge, the voltage (VNA) at the present time (t) is equal to AA B BVOSA (10)
the voltage at the output of the nulling amp (VOA) at the time when + ABVOSB
1 + BA
ΦAX is closed. If the period of the autocorrection switching
frequency is designated as TS, the amplifier switches between The AD857x architecture is optimized in such a way that
phases every 0.5 × TS. Therefore, in the amplification phase AA = AB, BA = BB, and BA >> 1. In addition, the gain product to
AABB is much greater than AB. Therefore, Equation 10 can be
⎡ 1 ⎤
VNA [t ] = VNA ⎢t − TS ⎥ (4) simplified to
⎣ 2 ⎦
VOUT[t] = VIN[t]AABA + AA(VOSA+ VOSB) (11)
and substituting Equation 4 and Equation 2 into Equation 3 yields
Most obvious is the gain product of both the primary and nulling
⎡ 1 ⎤ amplifiers. This AABA term is what gives the AD857x its extremely
A A B AVOSA ⎢t − TS ⎥
VOA [t ] = A AVIN [t ] + A AVOSA [t ] − ⎣ 2 ⎦ (5) high open-loop gain. To understand how VOSA and VOSB relate to
1 + BA the overall effective input offset voltage of the complete amplifier,
set up the generic amplifier equation of
VOUT = k × (VIN + VOS, EFF) (12)

where:
k is the open-loop gain of an amplifier.
VOS, EFF is its effective offset voltage.

Putting Equation 12 into the form of Equation 11 gives

VOUT[t] = VIN[t]AABA + VOS, EFFAABA (13)

Rev. D | Page 15 of 24
AD8571/AD8572/AD8574
V+
Therefore, R1 R2
AD8572 R2 R1
VOSA + VOSB
VOS , EFF ≈ (14) VIN1
BA VIN2

GUARD GUARD
Thus, the offset voltages of both the primary and nulling RING VREF
RING
amplifiers are reduced by the gain factor BA, which takes a typical VREF

01104-053
input offset voltage from several millivolts down to an effective V–

input offset voltage of submicrovolts. This autocorrection scheme
makes the AD857x family of amplifiers extremely precise.
HIGH GAIN, CMRR, AND PSRR
Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in
its input common-mode or power supply voltages. As shown in
the Amplification Phase section, the autocorrection architecture
of the AD857x allows it to effectively minimize offset voltages.
The technique also corrects for offset errors caused by common-
mode voltage swings and power supply variations, which results
in superb CMRR and PSRR figures in excess of 130 dB. Because
the autocorrection occurs continuously, these figures can be
maintained across the temperature range of the device (−40°C
to +125°C).
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around
the amplifier inputs further reduces leakage currents. Figure 52
shows how the guard ring should be configured, and Figure 53
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the junction temperature. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
view of the thermal voltage error sources. When the temperature
of the PCB at one end of the component (TA1) differs from the
temperature at the other end (TA2), the Seebeck voltages are not
equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
that both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on the
circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and also
reduces EMI noise pickup.
COMPONENT
LEAD
SOLDER
VSC1 VSC2
–
+ SURFACE MOUNT +
–
VTS1 COMPONENT VTS2
+ +
– –
PC BOARD

shows the top view of how a surface-mount layout can be TA1 TA2
arranged. The guard ring does not need to be a specific width,

01104-054
COPPER IF TA1 ≠ TA2, THEN
TRACE VTS1 + VSC1 ≠ VTS2 + VSC2
but it should form a continuous loop around both inputs. By
setting the guard ring voltage equal to the voltage at the non- Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
inverting input, parasitic capacitance is minimized as well. For
further reduction of leakage currents, components can be mounted
to the PCB using Teflon® standoff insulators. RF

R1

VOUT
VOUT VIN
VOUT
VIN AD8571/AD8572/
V RS = R1 AD8574
AD8572 IN
AD8572
AV = 1 + (RF /R1)
01104-055

RS SHOULD BE PLACED IN CLOSE PROXIMITY AND

ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
VIN
VOUT Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors

AD8572
01104-052

Figure 52. Guard Ring Layout and Connections to

Reduce PCB Leakage Currents

Rev. D | Page 16 of 24
 AD8571/AD8572/AD8574
0
1/f NOISE CHARACTERISTICS
VS = 5V
Another advantage of auto-zero amplifiers is their ability to –20 AV = 60dB
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices and –40

OUTPUT SIGNAL
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the –60
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher –80
degrees of error for sub-Hertz frequencies or dc precision
applications. –100

01104-057
Because the AD857x amplifiers are self-correcting op amps,
–120
they do not have increasing flicker noise at lower frequencies. In 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (kHz)
essence, low frequency noise is treated as a slowly varying offset
error and is greatly reduced with autocorrection. The correction Figure 57. Spectral Analysis of AD857x Output with 60 dB Gain
becomes more effective as the noise frequency approaches dc,
Figure 58 shows the spectral output of an AD8572 configured in
offsetting the tendency of the noise to increase exponentially as
a high gain (60 dB) with a 1 mV input signal applied. Note the
frequency decreases, which allows the AD857x to have lower
absence of any IMD products in the spectrum. The signal-to-
noise near dc than standard low noise amplifiers that are
noise ratio (SNR) of the output signal is better than 60 dB, or 0.1%.
susceptible to 1/f noise.
0
RANDOM AUTO-ZERO CORRECTION ELIMINATES VS = 5V
INTERMODULATION DISTORTION –20 AV = 60dB

The AD857x can be used as a conventional op amp for gains up

to 1 MHz. The auto-zero correction frequency of the device –40
OUTPUT SIGNAL

continuously varies, based on a pseudorandom generator with a

–60
uniform distribution from 2 kHz to 4 kHz. The randomization
of the autocorrection clock creates a continuous randomization
–80
of IMD products that show up as simple broadband noise at the
output of the amplifier. This broadband noise naturally combines
–100
with the amplifier voltage noise in a root-squared-sum fashion,

01104-058
resulting in an output free IMD. Figure 56 shows the spectral
–120
output of an AD8572 with the amplifier configured for unity 0 1 2 3 4 5 6 7 8 9 10
gain and the input grounded. Figure 57 shows the spectral FREQUENCY (kHz)

output with the amplifier configured for a gain of 60 dB. Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal

–20 VS = 5V
AV = 0dB

–40
OUTPUT SIGNAL

–60

–80

–100

–120

–140
01104-056

–160
1 2 3 4 5 6 7 8 9 10
FREQUENCY (kHz)

Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration

Rev. D | Page 17 of 24
AD8571/AD8572/AD8574
BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS
The total broadband noise output from any amplifier is primarily a
function of three types of noise: input voltage noise from the
amplifier, input current noise from the amplifier, and Johnson
noise from the external resistors used around the amplifier.
Input voltage noise, or en, is strictly a function of the amplifier
used. The Johnson noise from a resistor is a function of the
resistance and the temperature. Input current noise, or in,
creates an equivalent voltage noise proportional to the resistors
used around the amplifier. These noise sources are not correlated
with each other and their combined noise sums in a root-
squared-sum fashion. The full equation is given as
en, TOTAL = [en2 + 4kTrs + (inrs)2]1/2 (15)
where:
en is the input voltage noise of the amplifier.
in is the input current noise of the amplifier.
rs is the source resistance connected to the noninverting
terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (K = 273.15 + °C).
The input voltage noise density, en, of the AD857x is 51 nV/√Hz,
and the input noise, in, is 2 fA/√Hz. The en, TOTAL is dominated by
the input voltage noise provided that the source resistance is less
than 172 kΩ. With source resistance greater than 172 kΩ, the
overall noise of the system is dominated by the Johnson noise of
the resistor itself.
Because the input current noise of the AD857x is very small, in
does not become a dominant term unless rs > 4 GΩ, which is an
impractical value of source resistance.
The total noise, en, TOTAL, is expressed in volts-per-square-root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as
en = en, TOTAL × BW (16)
where BW is the bandwidth of interest in Hertz.
OUTPUT OVERDRIVE RECOVERY
The AD857x amplifiers have an excellent overdrive recovery
of only 200 μs from either supply rail. This characteristic is
particularly difficult for autocorrection amplifiers because the
nulling amplifier requires a substantial amount of time to error
correct the main amplifier back to a valid output. Figure 29 and
Figure 30 show the positive and negative overdrive recovery
times for the AD857x.
Rev. D | Page 18 of 24
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to halfway between the supplies. The time from the input signal
step-down to the output settling to within 100 μV of its final
value is the overdrive recovery time. Many autocorrection
amplifiers require a number of auto-zero clock cycles to recover
from output overdrive, and some can take several milliseconds
for the output to settle properly.
INPUT OVERVOLTAGE PROTECTION
Although the AD857x are rail-to-rail input amplifiers, care
should be taken to ensure that the potential difference between
the inputs does not exceed 5 V. Under normal operating conditions,
the amplifier corrects its output to ensure that the two inputs
are at the same voltage. However, if the device is configured as
a comparator, or is under some unusual operating condition, the
input voltages may be forced to different potentials, which could
cause excessive current to flow through the internal diodes in the
AD857x used to protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V,
large amounts of current begin to flow through the ESD
protection diodes in the amplifier. These diodes are connected
between the inputs and each supply rail to protect the input
transistors against an electrostatic discharge event and are
normally reverse-biased. However, if the input voltage exceeds
the supply voltage, these ESD diodes become forward-biased.
Without current-limiting, excessive amounts of current can
flow through these diodes, causing permanent damage to the
device. If inputs are subject to overvoltage, appropriate series
resistors should be inserted to limit the diode current to less
than 2 mA.
OUTPUT PHASE REVERSAL
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage moves outside the common-mode range, the outputs of
these amplifiers suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair
shutting down, causing a radical shifting of internal voltages
that results in the erratic output behavior.
The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided that both inputs are
maintained within the supply voltages. If one or both inputs
exceed either supply voltage, a resistor should be placed in
series with the input to limit the current to less than 2 mA to
ensure that the output does not reverse its phase.
 AD8571/AD8572/AD8574
CAPACITIVE LOAD DRIVE The optimum value for the resistor and capacitor is a function
The AD857x have excellent capacitive load driving capabilities of the load capacitance and is best determined empirically
and can safely drive up to 10 nF from a single 5 V supply. because actual CL includes stray capacitances and can differ
Although the device is stable, capacitive loading limits the substantially from the nominal capacitive load. Table 5 shows
bandwidth of the amplifier. Capacitive loads also increase the some snubber network values that can be used as starting points.
amount of overshoot and ringing at the output. The RC snubber
network shown in Figure 59 can be used to reduce the capacitive Table 5. Snubber Network Values for Driving Capacitive Loads
load ringing and overshoot. CL (nF) Rx (Ω) Cx
1 200 1 nF
5V
AD8571/ 4.7 60 0.47 μF
AD8572/
– AD8574 10 20 10 μF
VOUT
VIN Rx
+ 60Ω
200mV p-p
Cx
CL
4.7nF
POWER-UP BEHAVIOR
01104-059
0.47µF
At power-up, the AD857x settles to a valid output within 5 μs.
Figure 59. Snubber Network Configuration for Driving Capacitive Loads
Figure 61 shows an oscilloscope photo of the output of the
amplifier along with the power supply voltage. Figure 62 shows
Although the snubber network does not recover the loss of the test circuit. With the amplifier configured for unity gain, the
amplifier bandwidth from the load capacitance, it does allow device takes approximately 5 μs to settle to its final output
the amplifier to drive larger values of capacitance while voltage, hundreds of microseconds faster than many other
maintaining a minimum of overshoot and ringing. Figure 60 autocorrection amplifiers.
shows the output of an AD857x driving a 1 nF capacitor with
and without a snubber network.

10μs VOUT

WITH
SNUBBER 0V

V+

0V
WITHOUT
SNUBBER
5µs 1V

01104-061
BOTTOM TRACE = 2V/DIV
01104-060

VS = 5V TOP TRACE = 1V/DIV

CL = 4.7nF 100mV
Figure 61. AD857x Output Behavior at Power-Up
Figure 60. Overshoot and Ringing Are Substantially Reduced Using
a Snubber Network

VSY = 0V TO 5V
100kΩ

VOUT
100kΩ AD8571/
AD8572/
01104-062

AD8574
Figure 62. AD857x Test Circuit for Power-Up Time

Rev. D | Page 19 of 24
AD8571/AD8572/AD8574

APPLICATIONS INFORMATION
R2
5 V PRECISION STRAIN GAGE CIRCUIT
R1
The extremely low offset voltage of the AD8572 makes it an ideal V2
R3 VOUT
amplifier for any application requiring accuracy with high gains, V1 AD8571/
such as a weigh scale or strain gage. Figure 63 shows a configura- R4 AD8572/
tion for a single-supply, precision strain gage measurement system. AD8574

01104-064
R4 R2 R2
IF = , THEN VOUT = (V1 – V2)
R3 R1 R1
The REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference Figure 64. Using the AD857x as a Difference Amplifier
for the top of the strain gage resistor bridge. Q1 provides the
In an ideal difference amplifier, the ratio of the resistors is set
current drive for the 350 Ω bridge network. A1 is used to amplify
equal to
the output of the bridge with the full-scale output voltage equal to
2 × (R1 + R 2 )
R2 R4
AV = = (19)
(17) R1 R3
RB
Set the output voltage of the system to
where RB is the resistance of the load cell.
VOUT = AV (V1 − V2) (20)
Using the values given in Figure 63, the output voltage linearly
Due to finite component tolerance, the ratio between the four
varies from 0 V with no strain to 4 V under full strain.
resistors is not exactly equal, and any mismatch results in a
5V 2 reduction of common-mode rejection from the system. Referring
2.5V 6 3 to Figure 64, the exact common-mode rejection ratio can be
1kΩ REF192
Q1
2N2222 A2 expressed as
4
OR AD8572-B
EQUIVALENT R1R4 + 2R2R4 + R2R3
4.0V
12kΩ 20kΩ CMRR = (21)
2R1R4 − 2R2R3
R1 R2
17.4kΩ 100Ω
In the 3-op amp instrumentation amplifier configuration shown
in Figure 65, the output difference amplifier is set to unity gain
40mV A1 VOUT
350Ω FULL-SCALE with all four resistors equal in value. If the tolerance of the
0V TO 4V
LOAD AD8572-A resistors used in the circuit is given as δ, the worst-case CMRR
CELL
of the instrumentation amplifier is
R3 R4
01104-063

NOTE: 17.4kΩ 100Ω 1

USE 0.1% TOLERANCE RESISTORS. CMRRMIN = (22)
Figure 63. 5 V Precision Strain Gage Amplifier 2δ

V2
AD8574-A
3 V INSTRUMENTATION AMPLIFIER R

The high common-mode rejection, high open-loop gain, R R

and operation down to 3 V of the supply voltage make the VOUT
RG R R
AD857x family an excellent op amp choice for discrete single-
R AD8574-C
supply instrumentation amplifiers. The common-mode
rejection ratio of the AD857x is greater than 120 dB, but the RTRIM
V1
CMRR of the system is also a function of the external resistor AD8574-B
01104-065

tolerances. The gain of the difference amplifier shown in Figure 64 VOUT = 1 +

2R
(V1 – V2)
RG
is given as
Figure 65. Discrete Instrumentation Amplifier Configuration
⎛ R4 ⎞ ⎛ R1 ⎞ ⎛ R2 ⎞
VOUT = V 1⎜ ⎟ ⎜1 + ⎟ − V 2⎜ ⎟ (18)
⎝ R3 + R 4 ⎠ ⎝ R2 ⎠ ⎝ R1 ⎠ Therefore, using 1% tolerance resistors results in a worst-case
system CMRR of 0.02, or 34 dB. To achieve high common-
mode rejection, either high precision resistors or an additional
trimming resistor, as shown in Figure 65, should be used. The value
of this trimming resistor should be equal to the value of R
multiplied by its tolerance. For example, using 10 kΩ resistors
with 1% tolerance would require a series trimming resistor
equal to 100 Ω.

Rev. D | Page 20 of 24
 AD8571/AD8572/AD8574
HIGH ACCURACY THERMOCOUPLE AMPLIFIER Using the components shown in Figure 67, the monitor output
Figure 66 shows a K-type thermocouple amplifier configuration transfer function is 2.49 V/A.
with cold-junction compensation. Even from a 5 V supply, the RSENSE IL
0.1Ω
AD8571 can provide enough accuracy to achieve a resolution of V+

better than 0.02°C from 0°C to 500°C. D1 is used as a tempera- V+

0.1µF
ture measuring device to correct the cold-junction error from R1
100Ω 3 8 LOAD
the thermocouple and should be placed as close as possible to +
1/2 1
the two terminating junctions. With the thermocouple measuring AD8572
2
–
tip immersed in a 0°C ice bath, R6 should be adjusted until the 4
S G
output is at 0 V. M1
Si9433
D
Using the values shown in Figure 66, the output voltage tracks MONITOR
OUTPUT R2
temperature at 10 mV/°C. For a wider range of temperature

01104-067
2.49kΩ
measurement, R9 can be decreased to 62 kΩ. This creates a
5 mV/°C change at the output, allowing measurements of up Figure 67. High-Side Load Current Monitor
to 1000°C.
Figure 68 shows the low-side monitor equivalent. In this circuit,
REF02EZ 5V
12V 2 6 the input common-mode voltage to the AD8572 is at or near
0.1µF 4 ground. Again, a 0.1 Ω resistor provides a voltage drop propor-
R5
40.2kΩ R9 tional to the return current. The output voltage is given as
R1 124kΩ

Monitor Output = V+ − ⎛⎜ × R SENSE × I L ⎞⎟

10.7kΩ R2
5V (24)
1N4148 10µF ⎝ R1 ⎠
+

D1
0.1µF
R2 R8 For the component values shown in Figure 68, the monitor
2.74kΩ 453Ω 2
K-TYPE
– – 7 output transfer function is V+ − 2.49 V/A.
THERMOCOUPLE 6
+ + R6 3
40.7µV/°C V+
200Ω 4 AD8571
0V TO 5V
R4 R3 R2
(0°C TO 500°C)
01104-066

5.62kΩ 53.6Ω 2.49kΩ

MONITOR
OUTPUT V+
Figure 66. Precision K-Type Thermocouple Amplifier Q1
with Cold-Junction Compensation V+
2 LOAD
PRECISION CURRENT METER
R1 3
Because of its low input bias current and superb offset voltage at 100Ω
1/2 AD8572
RSENSE
single-supply voltages, the AD857x family is an excellent amplifier 0.1Ω

for precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or a low-side current
monitor. Using both amplifiers in the AD8572 provides a simple
method to monitor both current supply and return paths for
load or fault detection.
Figure 67 shows a high-side current monitor configuration.
Here, the input common-mode voltage of the amplifier is at or
near the positive supply voltage. The rail-to-rail input of the
amplifier provides a precise measurement, even with the input
common-mode voltage at the supply voltage. The CMOS input
structure does not draw any input bias current, ensuring a
minimum of measurement error.
01104-068
IL
Figure 68. Low-Side Load Current Monitor
PRECISION VOLTAGE COMPARATOR
The AD857x can be operated open loop and used as a precision
comparator. The AD857x have less than 50 μV of offset voltage
when they run in this configuration. The slight increase of
offset voltage stems from the fact that the autocorrection
architecture operates with the lowest offset in a closed-loop
configuration, that is, one with negative feedback. With 50 mV
of overdrive, the device has a propagation delay of 15 μs on the
rising edge and 8 μs on the falling edge.

The 0.1 Ω resistor creates a voltage drop to the noninverting Care should be taken to ensure that the maximum differential
input of the AD857x. The output of the amplifier is corrected voltage of the device is not exceeded. For more information, see
until this voltage appears at the inverting input, which creates a the Input Overvoltage Protection section.
current through R1 that in turn flows through R2. The monitor
output is given by
Monitor Output = R2 × (RSENSE/R1) × IL (23)
Rev. D | Page 21 of 24
AD8571/AD8572/AD8574

OUTLINE DIMENSIONS
3.20 3.10
3.00 3.00
2.80 2.90

8 5 5.15 8 5
3.20
4.90 4.50
3.00
4.65 4.40 6.40 BSC
2.80 1
4
4.30

1 4
PIN 1
0.65 BSC
PIN 1
0.95
0.65 BSC
0.85 1.10 MAX
0.75 0.15
1.20
0.80 0.05 MAX
0.15 0.38 8° 0.60 8°
0.23
0.00 0.22 0° 0.40 0.30 0° 0.75
0.08 COPLANARITY SEATING 0.20
COPLANARITY SEATING 0.10 0.19 PLANE 0.60
0.09
0.10 PLANE 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 69. 8-Lead Mini Small Outline Package [MSOP] Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RM-8) (RU-8)
Dimensions shown in millimeters Dimensions shown in millimeters

5.00 (0.1968) 5.10

4.80 (0.1890) 5.00
4.90
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284) 14 8
4
4.50
4.40 6.40
BSC
1.27 (0.0500) 0.50 (0.0196) 4.30
BSC 45°
1.75 (0.0688) 0.25 (0.0099)
1.35 (0.0532) 1 7
0.25 (0.0098) 8°
0.10 (0.0040) 0° PIN 1
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500) 1.05 0.65
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157) 1.00 BSC
PLANE 0.17 (0.0067) 0.20
0.80 1.20
MAX 0.09 0.75
COMPLIANT TO JEDEC STANDARDS MS-012-A A
8° 0.60
0.15 0.30 0° 0.45
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.05 SEATING
012407-A

0.19 PLANE COPLANARITY

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0.10
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
Narrow Body (R-8) (RU-14)
Dimensions shown in millimeters and (inches) Dimensions shown in millimeters

Rev. D | Page 22 of 24
 AD8571/AD8572/AD8574
8.75 (0.3445)
8.55 (0.3366)

14 8
4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 7 5.80 (0.2283)

1.27 (0.0500) 0.50 (0.0197)

BSC 45°
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8°
1.35 (0.0531)
0.10 (0.0039) 0°
COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

060606-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 73. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8571AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8571AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8571AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8571ARZ 1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8571ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8571ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8571ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 AJA
AD8571ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AJA
AD8571ARMZ-R21 −40°C to +125°C 8-Lead MSOP RM-8 AJA#
AD8571ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP RM-8 AJA#
AD8572AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8572AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8572AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8572ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8572ARZ-REEL1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8572ARZ-REEL71 −40°C to +125°C 8-Lead SOIC_N R-8
AD8572ARU −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARU-REEL −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARUZ1 −40°C to +125°C 8-Lead TSSOP RU-8
AD8572ARUZ-REEL1 −40°C to +125°C 8-Lead TSSOP RU-8
AD8574AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8574AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8574AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ-REEL1 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARZ-REEL71 −40°C to +125°C 14-Lead SOIC_N R-14
AD8574ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARUZ1 −40°C to +125°C 14-Lead TSSOP RU-14
AD8574ARUZ-REEL1 −40°C to +125°C 14-Lead TSSOP RU-14
1
Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.

Rev. D | Page 23 of 24
AD8571/AD8572/AD8574

NOTES

©1999–2008 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D01104-0-6/08(D)

Rev. D | Page 24 of 24