Documente Academic
Documente Profesional
Documente Cultură
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider
bias and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. andwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requiremen
t
Name
Transistor
[Active]
Resistor
[Passive]
Components
BC 107
61k, 10k,
1k,
4.7k
1
1,1,1,2
Capacitor
[Passive]
10f, 100f
2,1
Signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
6
DESIGN
Quantit
y
Range
8 Accessories
PROCEDURE:
Regulated power
supply
Bread Board
Connecting
Wires
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
The voltage gain is
given by, AV= -hfe
(RC|| RF) / hie h ie
= re
re = 26mV / IE = 26mV / 1.2mA
= 21.6 hie = 150 x 21.6
=3.2K
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Single strand
1
as
required
Where VE = IE RE
(IC= IE)
4.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC
analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from
0Hz to 1MHz in incremental steps and note down the corresponding output
voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB
on y-axis., Bandwidth, BW
= f2-f1
where f1 lower cut-off frequency
a.
ii)
iii)
Set VCC= +10v and measure the voltage drop across the
Resistor VRC, voltage across Collector- Emitter Junction VCE
and Voltage drop across base emitter junction. V BE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1
. VBE :
2
. VRC
3. VCE
(forward bias)
= ____________
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be
handled by the amplifier, so that it amplifies the input signal without
any distortion.
Procedure:
i.
ii.
MSH
MSH
MODEL GRAPH:
= _________ volts
S. NO
FREQU
ENCY
[Hz]
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
With Feedback :
Input voltage (Vin=V
6.
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
RESULT:
log Vo/Vi
INFERENCE:
The Common Emitter Amplifier was constructed and the following results were
determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
MODEL GRAPH:
DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2.
REQUIREMENTS:
S.N
o
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
0-3MHz
0-30MHz
0-30 V
Components
2
Resistor [Passive]
Capacitor [Passive]
Signal Generator
Equipment
CRO
Regulated power
supply
Bread Board
Accessories
8
Connecting Wires
Single strand
as
required
(i)
(ii)
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
ii)
iii)
iv)
To verify dc condition
1
. VBE :
2
. VRC
3. VCE
(forward bias)
= ____________
AC
Procedure:
i.
ii.
5.
TABULATION
Input voltage (Vin=V
MSH /2)
S. NO
FREQU
ENCY
[Hz]
MSH
= _________ volts
=____________ volts
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
The common collector amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c) Gain-Bandwidth product (GBWP) :
MODEL GRAPH:
EXPERIMENT:03
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1k ; hfe = 75 ; hfb =0.987
Single strand
as
required
The Common base amplifier typically has good voltage gain and relatively
high output impedance. But the Common base amplifier unlike CE amplifier has
very low input impedance which makes it unsuitable for most voltage amplifier. It
is typically used used as an active load for a cascode amplifier and also as a
current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor
emitter in a positive direction while the base voltage remains fixed, hence Vbe
reduces. The reduction in VBE results in reduction in VRC, consequently VCE
increases. The rise in collector voltage effectively rises the output voltage. The
positive going pulse at the input produces a positive-going output, hence the
there is no phase shift from input to output in CB circuit. In the same way the
negative-going input produces a negative-going output.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CB amplifier using DC analysis.
To verify dc condition
1
. VBE :
2
. VRC
(forward bias)
3. VCE
= ____________
Procedure:
i.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier
using the
signal generator between base emitter junction of the
transistor. Find the sinusoidal output using CRO across R L.
By increasing the amplitude of the input signal find maximum
input voltage V MSH across VBE at which the sinusoidal signal
gets distorted during the process which can be seen in the
CRO. The amplitude obtained at this point is maximum
voltage that can be applied to the transistor for efficient
operating of transistor.
ii.
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
S. NO
FREQU
ENCY
[Hz]
MSH
/ 2) =____________V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
RESULT:
The Common base amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
MODEL GRAPH:
DARLINGTON AMPLIFIER
EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
Single strand
as
required
DESIGN PROCEDURE:
Given specifications:
VCC= 12V, IC=1.2mA, AV= 30, f1 = 300 HZ, f2 = 500KHZ, hFE= 150
(i) To calculate RC:
Assume R2 = 10K and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier
circuit, we assume equal drops across VCE and load resistance RC. The ICQ
= 1mA is assumed.
This configuration gives a much higher gain than each transistor taken
separately and, in the case of integrated devices, can take less space than two
individual transistors because they can use a shared collector. The Darlington
amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly
high output resistance. Therefore it is generally used to drive medium to high
resistance loads. It is typically used in applications where a small voltage signal
needs to be amplified to a large voltage signal like radio receivers.
4.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington
amplifier using AC analysis.
4. Set the input voltage Vin=V
To verify dc condition
1
. VBE :
2
. VRC
(forward bias)
3. VCE
= ____________
handling capacity :
b. Maximum signal
ii.
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
RESULT:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
Common Source Amplifier Circuit Diagram:
MODEL GRAPH
DATE:
OBJECTIVE:
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BFW10
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Equipment
Bread Board
Accessories
Connecting Wires
Single strand
as
required
DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (V GS)
VGS = ID RS
Assume RS = 3.3K,
VGS = 1.5mA x 3.3K = _____
Bandwidth, BW = f2-f1
where f1 - lower cut-off frequency
f2 - upper cut-off frequency
a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
ii)
iii)
iv)
To verify dc condition
1
. VGS :
2
. VDS
3 ID
= ____________
= ____________
= _______
ii.
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
MODEL GRAPH:
CASCADE AMPLIFIER
EXPERIMENT:06
DATE:
1. OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Bread Board
Accessories
Connecting Wires
Single strand
DESIGN PROCEDURE:
Given specifications:
VCC= 14 V, IC1=1.2mA, RL = 40K hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 VBE = 8V 0.7V = 7.3V
as
required
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC
analysis.
4. Set the input voltage Vin=V
Bandwidth, BW = f2-f1
where f1 - lower cut-off frequency
f2 - upper cut-off frequency
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
v)
vi)
vii)
viii)
To verify dc condition
1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
= _______ (REVERSE BIAS)
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
iv.
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
MSH/2)
=____________ volts
6.RES
The
Cascade
amplifier
was
ULT:
S. NO
FREQU
ENCY
[Hz]
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
constructed and input resistance and gain were determined. The results are
found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
MODEL GRAPH:
CASCODE AMPLIFIER
EXPERIMENT: 07
DATE:
1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
61k, 10k,
1k,
4.7k
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
1,1,1,2
2,1
Equipment
Accessories
8
Connecting Wires
Single strand
DESIGN PROCEDURE:
Given specifications:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90K ;
Transistor Parameters: hFE= 50 , hie = 1.2K and hib= 24
(i) To calculate RC:
Rc = RL / 10 = 90k / 10 = 9K
(ii) To calculate RE:
Assume VCE1 = VCE2 = 3V, and VE = 5V;
The voltage drop across collector resistor is given by,
VRC = VCC - VCE1 - VCE2 VE
as
required
= 20V 3V
3V- 5V VRC = 9V
RE = VE / IE ; Where IE = Ic
= 1.1mA RE = 4.5K
(iii) To Calculate Bias Resistors R1, R2, R3 :
a. R3 = 10 RE = 47K
b. Voltage Across the base of Transistor 1 is given by,
VB1 = VBE + VE
VB1 = 5V + 0.7V = 5.7V
c. Voltage Across the base of Transistor 2 is given by
VB2 = VBE2 + VE + VBE2
= 5V + 3V + 0.7V
= 8.7V
d. Voltage across resistor R2 is given by
VR2 = VB2 - VB1
VR2 = 8.7V 5.7V = 3V
e. The resistor R2 is given by R2 = (VR2 / I3 ) =
(3V / 121A) R2 = 24.8K
f. Resistor R1 = [VCC - VB2 / I3 ]
= [ 20V 8.7V / 121 A]
= 93.4 K
Determination of Capacitor Values:
To Find C1 :
C1 = * 1 / 2f1 (Zi / 10) ]
Where Zi = ( R3 || R2 ) = 1.1K and
f1 = Lower cut-off
frequency= 25HZ =
57.9F
To Find C2 :
C2 = * 1 / 2f1 (hie2 / 10) ] = 53 F
Where hie2= 1.2 K and f1 = Lower cut-off frequency= 25HZ;
To Find C3 :
C3 = * 1 / 2f1hib ]
Where hib= 24 and
f1 = Lower cut-off
frequency= 25HZ =
256F
To Find C4 :
C4 = * 1 / 2f1 ( (RC + RL) / 10) ]
Where RC = 9K; RL = 90K and
f1 = Lower cut-off
frequency= 25HZ = 0.64
F
THEORY:
The cascode configuration has one of two configurations of multistage
amplifier. In each case the collector of the leading transistor is connected to the
emitter of the following transistor. The arrangement of the two transistors is
shown in the circuit diagram. The cascode amplifier consists of CE stage
connected in series with CB stage. The arrangement provides a relatively high
input impedance with low voltage gain for the first stage to ensure the input
miller capacitance is at a minimum, whereas the following CB stage provides an
excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2. It provides high stability and has high output impedance
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC
analysis.
4. Set the input voltage Vin=V
ix)
x)
xi)
Set VCC= +10v and measure the voltage drop across the
Resistor VRC, voltage across Collector- Emitter Junction VCE
and Voltage drop across base emitter junction. V BE
Find the Q-point of the transistor and draw the DC load line.
xii)
To verify dc condition
1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
vi.
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
The Cascode amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
EXPERIMENT: 08
DATE:
DIFFERENTIAL AMPLIFIER
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT and to determine its:
a.
b.
c.
d.
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
2. REQUIREMENTS:
S.No
Requireme
.
nt
1
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
Single strand
as
required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies the
difference
between two voltages but does not amplify the particular voltages. The need for
differential
amplifier arises in many physical measurements where response from D.C to many
MHZ is
required. It is also used in input stage of integrated amplifier.
DESIGN PROCEDURE:
Given specifications:
VCC= 12V, IC=1.2mA, VCE = 5V
Assume Q1 = Q2
Where Q1 = Transistor 1 and Q2 = Transistor 2.
The Collector resistance Rc1 is given by using KVL at the transistor 1
Vcc = IcRc1 VCE Ie1Re1
Rc1 = (Vcc + VCE + Ie1Re1 ) / Ic,
Where VCE = 5V and Ic = 1.2mA, Ie1 = Ic/10 and assume Re1 = 470
Now Rc1 = 1k .
MODEL GRAPH:
Differential amplifier Transfer Characteristics:
ii)
iii)
7. Find the Common mode rejection ratio of differential amplifier using the formula
given
below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
ii)
iii)
iv)
To verify dc condition
1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
= _______ (REVERSE BIAS)
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the operating point of transistor
viii.
V
5.
= _________ volts
TABULATION
a. Transfer Characteristics Calculation:
S.no
Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR
Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
S. NO
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
OUTPUT VOLTAGE
[ VO]
in Volts
6. RESULT:
The Differential amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
Trans-Conductance of Differential amplifier ( in
d) millisiemens) :
Differential mode gain in
e) dB
:
f) Common Mode Gain in dB
g) CMRR in dB