Documente Academic
Documente Profesional
Documente Cultură
I. INTRODUCTION
In ultra-miniature and low power multi-sensor systems,
the level of integration and functional flexibility are essential
considerations for platform design. The sensor interface
circuitry (signal conditioning and processing) is a key
component in the whole system. Low-cost smart sensor
systems increasingly contain multiple sensors of different
types, which require heterogeneous interfaces for preamplification and pre-filtering. Integrating a programmable
processor and an adaptive sensor interface into one systemon-chip (SoC) combines analog and digital processing
capability and permits rapid customization to different
applications using the same integrated circuit. Single-chip
integration of these components enhances performance while
simultaneously reducing size, cost and power consumption.
This paper presents a sensor application SoC that
integrates an 8-channel reconfigurable sensor interface, an 8bit - A/D converter (ADC) and a 16-bit sensor signal
processor (SSP). The sensor interface employs Wheatstone
bridge and switched-capacitor topologies to perform signal
readout for resistive and capacitive sensors, providing a
unified interface for heterogeneous mix of sensors. The
customized SSP executes software to support interface
configuration and calibration, ADC control, and sensor data
processing. This multi-sensor interface can intelligently
adapt to the readout and signal processing needs of many
different sensor applications, providing flexibility that is
crucial for the implementation of low-cost microsystems.
16-bit SSP
RXD
8-bit
- ADC
Universal Sensor
Interface
Sensor array
2006 IEEE
16KB on-chip
Instruction
SRAM
SPI
16KB on-chip
Data
SRAM
16-bit
MAC
1-4244-0376-6/06/$20.00
UART
TXD
MCLK
MOSI
MISO
External
Flash ROM
Interface
8-bit
GPIO
Flash ROM
8-bit
GPIO
8-bit
GPIO
Digital Clock
Management
8-bit
GPIO
8-bit
GPIO
Address Bus Data Bus
50
0xFFE0
GPR
R0
R1
Instruction
Decode Unit
0xE000
..
.
IDU
R15
0x21FF
CU
ctrl2
ctrl3
ALU
0x0200
Hardware MAC
0x0100
0x0010
(16-bit peripherals )
control signals
ctrl6
(8-bit peripherals )
Address Bus
Data Bus
2006 IEEE
ctrl5
Interrupt Vectors
On-Chip Program SRAM
1-4244-0376-6/06/$20.00
ctrl4
0xFFFF
ctrl7
51
Hardware flow
(SystemC)
Software Flow
(ANSI C)
SSP core
Model
Code (C/C++)
Compiler
(TI/GNU)
Bus Model
Peripheral/
Mem Model
Hardware model
Simulation/
Verification
(a)
(b)
2006 IEEE
Application code
SystemC
Model
1-4244-0376-6/06/$20.00
Binary Code
52
Integrator
Comparator
c
o
m
p
Digital
counter
Bi
1 - bit DAC
SSP
MAC + UART +
GPIO
Sensor
Interface
Code SRAM
Data SRAM
S /H
Data SRAM
V in
ADC
ROM
Sensor
Interface
Figure 7 (a) SoC layout with IBM 0.18m CMOS process, (b)
Fabricated SoC die micrograph.
REFERENCES
[1]
[2]
[3]
IV. CONCLUSION
This paper presented a multi-sensor SoC integrating
programmable processor, universal sensor interface and
ADC as well as other on-chip resources. The USI utilizes a
configurable architecture for resistive and capacitive sensors,
and offers 0.33~15 and 0.035~31.75 gain ranges for resistive
and capacitive sensors, respectively. By sharing hardware
resource, the USI achieves a low power consumption of
300A with a 1.8V supply. The on-chip ADC features a
single-stage - architecture and 8-bit resolution with a
power consumption of 2.02mW at a 2.5MHz oversampling
rate. The USI and ADC, along with other functional blocks,
are controlled by the SSP, which executes software to
orchestrate the whole systems operation. With simplified
RISC architectural design, the SSP achieves 209W/MHz
power consumption at 1.8V supply. The SystemC-based
1-4244-0376-6/06/$20.00
2006 IEEE
[4]
[5]
[6]
[7]
[8]
53