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Lab3:TopdownASICDesignwithDFT

Lab3:TopdownASICDesignwithDFT
by:ZhengChen
ModifiedbyLily Li
LastModified22/02/05

INTRODUCTION:
In contemporary design flows, test merges with design much earlier in the process, creating what is called a
designfortest(DFT)processflow.Toensuremaximumdesigntestability,designersmustemployspecialDFT
techniques at specific stages in the development process. Figure 1 shows the basic steps and the Mentor
GraphicstoolsyouwoulduseduringatypicalASICtopdowndesignflowwithastructuredDFTstrategy.As
those steps shown in grey indicate, if your design's format is in VHDL, you can use BISTArchitect to
synthesizeBIST structures into its memory and random logic design blocks. Also at the RTLlevel, you can
insertandverifyboundaryscancircuitryusingBSDArchitect(BSDA).Afteryousynthesizeandoptimizethe
design,youarereadytoinsertinternalscancircuitryintoyourdesignusingDFTAdvisor.Whenyouaresure
the design is functioning as desired, you can use FastScanorFlexTest (depending on your scan strategy) to
generateatestpatternsetviaATPGmethods.Beforehandingthedesignoffformanufactureandtesting,you
shouldverifythatthedesignandpatternsstillfunctioncorrectlywiththepropertiminginformationapplied.

Fig.1
FordetailsaboutDFTconcepts,refertothe.pdfversiondocumentASIC/ICDesignforTestProcessGuide
usingmgcdocscommand.
Thislabwillcover:
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1.UsingDFTAdvisortoinsertfullscan.
2.UsingFastscantogeneratetestvectorsandtestfaultcoverage.

1.Introduction
DFTAdvisor is a utility that allows you to insert scan circuitry into your design. It follows one of two basic
strategies:Thefirstisfullscan.Fullscanconvertseveryflipflopandlatchintoscanableflipflops,whichallows
the use of combinational test pattern generation. After inserting the scan circuitry, you can then generate test
vectorsforyourdesignbyusingFastScan.Theotherstrategyispartialscan.Withpartialscanyouonlyinsert
scan circuitry in some of the memory devices.You can then generate test vectors for your design using
FlexTest.Inthislabexercise,youwillinvokeDFTAdvisoronasimpledesigntoinsertfullscan.Youwilluse
DFTAdvisortowriteascanbasednetlistfileandATPGsetupfiles.ThenyouwillinvokeFastScanusingthe
ATPGsetupfileinformationtocreate,compress,andsavepatterns.Thislabwillgiveyouexperienceusingthe
toolsinatypicalscanandATPGtoolflowutilizingdefaultconfigurations.
ThisVerilogdesigncontainsnoerrors,soyoucanuseitasafuturereferencetohelpyounavigatethrougha
scanandATPGtoolflow.
Understandingandapplyingtheseconceptswillassistyouwhenyoubegintomakecustomizedconfigurations
toenhancetoolperformance.

2.Preparation
1.DFTAdvisorrequiresatestlibrary.Atestlibrarygivesthefunctionsofallthegatesinthedesignandhowto
convertthenonscannableflipflopsintotheirscannableequivalents.Pleasedownloadthelibraryadk.atpg.
Makesuretosavethisfileinthecurrentworkingdirectory.
2.PutyourHDLfileinthecurrentworkingdirectory.Thesourcecodesareinsection4.Pleasedownloadthe
pipe_net_noscan.Makesuretosavethisfileinthecurrentworkingdirectory.

3.InvokingDFTAdvisor
1.ToinvokeDFTAdvisoronyourHDLfileyoumustfirstsetthementorgraphicsworkingdirectorytothe
currentdirectorythathasyourpipe_net_noscanfile.Veryimportant:Theadk.atpgfileshouldbeinthe
samedirectorythatyourHDLfilepipe_net_noscanisin.

2.TostartDFTAdvisor,youneedtoenterthecommandintheformat:
shell>dftadvisor

ThisinvokestheDFTAdvisorInvocationArgumentsdialogbox.Youmustenteradesign,adesignformat,and
anATPGlibrarytoinvoketheGraphicalUserInterface(GUI)asshowninfig.2.

a. Click the Browse button next to the Design field to enter the design. Click the pipe_net_noscan.v design.
NoticethedesignpathisinsertedintotheDesignfield.ClicktheOKbuttoninthedialogbox.

b.SelecttheVerilogdesignformatfromtheFormatdropdownlist,ifnotalreadyselected.

c.ClicktheBrowsebuttonnexttotheATPGLibraryfield.
i.Navigatetothelibrariesdirectory.
ii.Selecttheadk.atpglibraryfile.
iii.ClickOK.

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d.ClicktheBrowsebuttonnexttotheLogFilefield,thennavigatetotheyourdesireddirectorywhereyoucan
saveyourresults.Backoverthe.*.intheFileNameField,andtypedftadvisor.logintothecommandpath.This
will create a log file that logs all of your session, including reading in the library and the nonscan netlist at
invocation.

e.ClickOk.TheFileBrowsercloses.

f.ClickInvokeDFTAdvisor.DFTAdvisorisnowupandrunning.YouhavesuccessfullyinvokedDFTAdvisor
onthepipe_net_noscan.vdesign.BoththeCommandLineandtheControlPanelwindowsshouldnowbeopen.

Fig.2

3.AfterinvokingDFTAdvisor,theDFTAdvisorControlPanelandthecommandlinewillappearasshown
inFig.3.

Fig.3
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Define clocks. Clocks are primary input signals that asynchronously change the state of sequential logic
elements:clocks,sets,resets,andRAMread/writeclocks.

a.ChooseSetup>Clocksmenuitem.OrclickontheClocksbuttonintheCircuitSetupgraphicspane,aSetup
CircuitClocksdialogboxopenasshowninfig.4.
i.ClickontheAutomaticallyIdentify&Addbutton.
ii.ClickontheApplybutton.The/clkcontrolsignalisidentifiedandtheOffStateis0.
iii.ClickOK.

Fig.4

Alternatively,youcanusetheAnalyzeControlSignalsAuto_fixcommandtoautomaticallyidentifyclocksand
controlsignals.

Besidesdefiningscancircuitry,defining(oradding)clocksandpinconstraintsisthekeytosuccessfulDesign
RulesChecking(DRC).
Thesearethemostcriticalstepsyoumustloadscanpatternscorrectlyandyoumustclockcircuitryatthe
propertimetoensurecorrectfaultsimulation.

3.GotoDFTmode.
a.ClickDonewithSetupintheDFTAdvisorcontrolpanelpane.YouarenowintheDFTsystemmode.
WhenyouswitchfromSETUPtoDFTmode,DFTAdvisorandFastScanwill runDRC.
DFTmodeisprimarilyforscanidentificationandinsertion.
TheTestSynthesiswindowisdisplayedinthegraphicpane.Also,TestSynthesisishighlightedinthetaskflow
managerpane.
Note:IfDFTAdvisorencountersDRCviolationsthatareerrors,itwillnotexitSETUPmode.Youmustdebug
andfixtheprobleminSETUPmodebeforeproceeding.Ifnoerrorencountered,thenaninterfaceasshownin
fig.5willshowup.

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Fig.5

4.Choosefullscanmethodology.
ClickSetupIdentificationbuttoninthegraphicpane.TheSetupforScan&
TestPointIdentificationdialogboxopensasshowninfig.6.TheFullScanbuttonisselected(red),whichisthe
defaultsetting.Fullscanmethodologyisthefastestidentificationmethod.
a.ClickOK.

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Fig6
5.Identifyscannableinstances.
a.ClickRunIdentificationinthegraphicpane.
b.Observethedefaultsettings.
c.ClicktheRunwithExistingSettingsbutton.TheDFTAdvisorIdentificationRunStatisticsboxopens.
i.Observetheinformationthatisavailable.
ii.ClicktheViewDetailsbutton.TheScanIdentificationboxopens.
iii.ClicktheClosebuttonforthisdialogbox.
iv.ClicktheReportbutton.TheResults&Analysisboxopens.
v.ClickShowStatistics.
vi.ClickGenerateReport.
Whatinformationisdisplayed?
vii.ClickClose.
ix.ClickDismiss.ThisclosestheDFTAdvisorIdentificationRunStatisticsdialogbox.

d.ClickSetup/RunTestSynthesisinthegraphicpane.ThisopenstheSetup/RunTestSynthesisboxasshown
infig.7.
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e.Thefollowingdefaultsettingsshouldbeselected(redisactive)
SynthesizeScanCircuitryintotheDesign
SynthesizeIdentifiedTestPoints
SynthesizeTestLogictoControlRAMs

Fig.7

f.ClickSetupintheSynthesizeScanCircuitryintotheDesignarea.

i.IntheChainRestrictionsarea,theinsertbuttonisselected(red),andthenumber1isenteredintheChain
entrybox.
ii.IntheScanEnablesarea,theAllowOnlyOneScanEnableSignalto
ControlAllScanChainsisselected(red).

g.ClickDone.
DFTAdvisorcanautomaticallyinsertanumberofdifferentteststructuresintothedesign.Thesestructures
include:scancircuitry,testpoints,testlogictoRAMs,I/Obuffersforaddedtestpins,andbuffertreesfortest
pins.

h.ClickOK.Aboxasshowninfig.8willpopup.

i.ClickRunwithExistingSettings.Youjustinsertedfullscanintothedesignusingthedefaultsettings.

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Fig.8

Ascaninsertednetlisthasnowbeencreated.

6.SaveaVerilognetlistandATPGsetupfiles.
a.ClicktheSaveResultsbuttoninthebuttonpane.ThisopenstheSaveResultsdialogboxshowninfig.9.

b.ClickSavetheNewNetlistbutton.

c.SelecttheVerilogformatfromtheFormatdropdownlist,ifnotalreadyselected.

d.ClicktheBrowsebuttonnexttoPathnameintheNetlistarea.
i.Navigatetotheresultsdirectory.Saveaspipe_scan.vfile.
ii.ClickOK.
iii.ClicktheOverwriteExistingFilebutton.Thisautomaticallyoverwritestheexistingfilewitheachsave.

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Fig.9

e.ClickSaveSetupFilesforATPGbuttonshowninfig.10.

f.ClicktheEnhancedProcedureFilebutton(redwhenactive)intheTimingFileTypearea.TheEnhances
Procedurefiledescribestheorderofeventsforatestpatternsetandintroducestimingtotestvectorsdivided
intocycles.

g.ClicktheBrowsebuttonnexttoBasenameintheSetupforTestPointsarea.
i.Navigatetotheresultsdirectory.Saveaspipe_scan(withoutafileextension).
ii.ClickOK.

h.ClicktheOverwriteExistingFile(s)button.

i.ClicktheViewFilesbutton.ThisactivatestheFileViewerwhenyouhavesavedtheoutputfiles.

j.ClickOK.ThisclosestheSaveResultsdialogbox.

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Fig.10

Youhavewrittenthefollowingthreefiles:
pipe_scan.v,whichistheVerilognetlist
pipe_scan.dofile,whichisadofilefile
pipe_scan.testproc,whichisanEnhancedProcedurefile

k.TheFileViewerisnowopen.
i.Thepipe_scan.dofileisdisplayedasshowninfig.11.Thisfileinputscircuitsetupandscaninformation
neededbyFastScanatinvocation.

Fig.11
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ii.Doubleclickthepipe_scan.testprocintheSelectFiletoViewdisplayarea.Thisdisplaystheshiftand
load_unloadproceduresasshowninfig.12,aswellasthetimingplate(gentp1),whichissharedbyboth
procedures.

Fig.12

l.ClosetheViewer.
Forthisexercise,youwillinvokeFastScanfromDFTAdvisor.Thegoalforthispartoftheexerciseistofollow
atypicalATPGtoolflow.YouwilluseFastScantocreate,compress,andsavepatternsfollowingtheFastScan
toolflow

4.InvokingFastscan

1.RunFastScan.

a.ClickDonewithTestSynthesisbuttoninthegraphicpane.
TheDFTAdvisorTestSynthesisCompletedialogboxopens.ClickRunATPGbutton.TheExitDFTAdvisor
beforestartingFastScanquestionboxopens.
i.ClickNo.

FastScanisnowupandrunning.YouhavesuccessfullyinvokedFastScanonthepipe_scan.vdesign.Boththe
CommandLineandtheControlPanelwindowsareopenasshowninfig.13.The Circuit Setup graphic pane
opens,andSetupishighlightedintheProcessPane.

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Fig.13

FastScancompletedthefollowing:
Compiledthelibrary
ReadintheVerilogNetlist
ReadintheVerilogfile(pipe_scan.v)
Readinthetestprocedurefile(pipe_scan.testproc)
Readinthedofile(pipe_scan.dofile)
Thisisdisplayedinthesessiontranscriptarea.

2.GotoATPG.
a.ClickDonewithSetupintheCircuitSetupgraphicpane.TheFastScanSessionPurposedialogboxopensas
showninfig.14.

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Fig.14

b.ClickthePatternGenerationbutton.TheTestPatternGenerationgraphicpaneopens.Also,Pattern
Generationishighlightedintheprocesspane.Thefollowingprocessesoccurred:
Circuitflattening
Designhierarchyisreduceddowntoitssimulationprimitivesandconnectivity.
Learninganalysis
AnalysisbyFastScantolearncircuitbehavior,usedlaterinfaultsimulationandATPG.
FastScanperformsstaticlearningonlyonceafterflattening.Staticlearninginvolvesgatebygatelocal
simulationtodetermineinformationaboutthedesign.PinandATPGconstraintsarenotconsidered.
DesignRulesChecking(DRC)
ThetoolexitedSETUPmodeandenteredtheATPGmode.Thisisdisplayedinthesessiontranscriptarea.

3.Selectfaultmodelandaddfaults.
a.ClickonFaultUniverseintheTestPatternGenerationgraphicpane.

b.ClicktheTypicalbutton.
TheStuckatFaultmodelischosen,whichaddsallfaultsintothedesign.

4.Generatepatterns.
a.ClickonTestGenerationintheTestPatternGenerationgraphicpane.
UseExistingSettingsorCustomize?dialogboxopens.
b.ClickRunwithExistingSettings.ATPGRunStatisticswindowcomesupasshowninFigure15,clickon
Dismiss.

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Fig.15

YoujustgeneratedtestpatternsfollowingatypicalATPGflowprocess.
Thefollowinginformationisavailable:
Patterns
NumberofEffectivePatterns
NumberofSimulatedPatterns
Faults
Numberofdetected
Numberofaborted(untestable)
NumberofATPGUntestable(AU)
Numberofundetecteduncontrollable(UC)orunobservablefaults(UO)
TestCoveragepercentagepercentageofalltestablefaultsthataredetectedbythepatternset
FaultCoveragepercentagepercentageofallfaultsbothtestableanduntestablethataredetectedbythepattern
set
ATPGeffectivenesspercentageameasureoftheabilityoftheATPGtooltoeitherprovideatesttodetecta
fault,orprovethatatestcannotbecreated
CPUruntime
c.Intherightsideofcontrolpanel,clickonSavePattern,selectSavethePatternSettoaFile,specifythe
pathname,selectASCIIformat,andclickOK.

5.ResultsandAnalysis
a.FromtheTestPatternGenerationclickonResultsandAnalysis,selectReportFaultsonAllTheseDesign
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ObjectsandBothoftheAbove(SA1andSA0),andclickonShowStatistics.
b.ReportStatisticscomesup,clickonEntireDesignoption.ThentheStatisticsreportwillbeshown.Click
ClosetocloseResults&Analysis.
c.WearedonewithATPG.NextstepisFaultSimulationusedthesamepatternthatjustgeneratedbyATPG.In
TestPatternGenerationpanel,clickonDoneWithPatternGeneration,andclickonFault.
6.Faultsimulation
a.InFaultSimulationcontrolpanel,clickonPatternSource.SetupPatternSourcecomesup,select
ExternalPatternsFrom,navigatetothesamepatternfileandsameformatgeneratedbyATPG,andclickOK.
b.IntherightsideofFaultSimulationcontrolpanel,clickonRunbutton.FastScanFaultSimulationRun
Statisticswillbeshown,andclickonDismiss.

Fig.16
c.Results&Analysis
FromtheFaultSimulationclickonResultsandAnalysis,selectReportFaultsonAllTheseDesignObjects
andBothoftheAbove(SA1andSA0),andclickonShowStatistics.
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ReportStatisticscomesup,clickonEntireDesignoption.ThentheStatisticsreportwillbeshown.
=EN-USstyle='color:blue'>http://www.scudc.scu.edu/mentortu

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