Diamond and Related Materials 11 (2002) 12541257

Optimization of 2H, 4H and 6HSiC high speed vertical MESFETs

K. Bertilssona,b,*, H-E. Nilssona
a
Department of Information Technology and Media, Mid-Sweden University, S-851 70 Sundsvall, Sweden

Department of Solid State Electronics, Kungl. Tekniska Hogskolan

(KTH), Electrum, S-164 40 Kista, Sweden

Abstract
Silicon carbide vertical MESFET devices are well suited for high speed and high power electronic devices. In this work we
have optimized the geometry of vertical MESFETs for microwave applications, using iterative two-dimensional simulations.
Relevant parasitics are included in the simulations to investigate the performance of realistic devices. The state of the art device
has f Ts7 GHz and we show that vertical MESFETs fabricated with traditional technology are totally limited by parasitics. Two
different approaches to reduce the parasitics in the vertical MESFET are proposed where f T increases significantly. 2002
Elsevier Science B.V. All rights reserved.
Keywords: MESFET; Device modeling; SiC

1. Introduction
Silicon carbide is a promising material to be used in
high power and high frequency electronics due to the
favorable combination of several material properties.
The large bandgap (f3 eV), high breakdown electrical
field (24 MVycm), and high thermal conductivity
(f5 Wycm 8C), allows operation at high voltages and
consequently high power densities. The high saturation
velocity, f2=107 cmys, and moderately high mobility,
up to 1000 cm2 yVs, allow high-speed operation of SiC
devices. Silicon carbide is known in over 100 polytypes,
from which 3C, 4H and 6HSiC are the most widely
used in electronic devices. 6HSiC has the lowest
mobility and a very high anisotropy due to the long
repetition length in the crystallographic structure. 4H
SiC is the most promising candidate due to a moderate
mobility and small anisotropy. 3CSiC epitaxial layers
can be grown on silicon, which is an advantage in
integration with Si technology and a trade-off in priceperformance. 2HSiC has been grown in laboratories
and is expected to be a suitable material for devices due
to an expected higher mobility compared with 4HSiC.
SiC MESFET devices are promising candidates for
high-power microwave applications and the highest

measured unity current gain frequency, f T, for a SiC

device is 22 GHz, achieved with a lateral MESFET w1x.
A vertical MESFET (SIT), shown in Fig. 1a, shows
better output power capabilities but the unity currentgain frequency is lower compared to a lateral MESFET.
The state of the art 4HSiC vertical MESFETs w2x have
reached f Ts7 GHz making this structure an interesting
device for microwave power applications.
In simulations of ideal devices w3x it has been shown
that the limitation for vertical MESFETs is much higher
compared to the experimentally obtained value. The
reason for the large difference between fabricated
devices and an ideal device is large parasitics in the
form of a large gate-pad capacitance and a large drain
resistance. The gate-pad is normally placed in the gate
layer forming a capacitor between the pad and the highdoped substrate. The capacitance increases as the channel length of the device is decreased, since the capacitor
thickness is reduced. Thus, a minimal channel length
does not give optimal performance. The drain resistance,
RD, formed by resistivity in the bulk material, increases
as the device width decreases, since the resistor width
is reduced as well. The channel width for an optimal
device is determined by a trade-off between the ideal
device performance and the parasitic drain resistance.
2. Simulation

*Corresponding author. Tel.: q46-6014-89-15; fax: q46-6014-8456.

E-mail address: kent.bertilsson@ite.mh.se (K. Bertilsson).

In the device simulations an anisotropic drift-diffusion

model, based on the CaugheyThomas expression for

0925-9635/02/$ - see front matter 2002 Elsevier Science B.V. All rights reserved.
PII: S 0 9 2 5 - 9 6 3 5 0 1 . 0 0 5 5 0 - 7

K. Bertilsson, H.-E. Nilsson / Diamond and Related Materials 11 (2002) 12541257

1255

Fig. 1. The MESFET structures used in the optimization. (a) Vertical MESFET processed in the traditional way. (b) Etched and metallized
trenches from the rear side and gate-pad placed on a field-oxide layer to decrease the drain-resistance. (c) The vertical MESFET realized on a
semi-insulating substrate.

the field dependent mobility in the Medici w4x package

is used. The transport parameters used are based on
measurements w5,6x and Monte Carlo simulations w7
9x. Large effort has been focused to use a simulation
model that gives accurate results w10x. The transport
parameters are selected differently depending on the
orientation of the device, to give the correct properties
in the main transport direction. The parameters for the
anisotropy are set to give the best possible transport in
the directions perpendicular to the current.
In the simulations, contact resistivity is taken into
consideration for the drain and source contacts. For 6H
SiC WSi2 contacts with resistivity, rcs2.1=10y5 V
cm2 w11x are considered and for 4HSiC TiC-contacts
with resistivity, rcs9.3=10y6 V cm2 is used w12x. For
2HSiC no contact measurement is available and therefore the same values as for 4HSiC is used.

3. Optimization
The optimization goal is to achieve highest possible
unity current gain frequency, f T, which is calculated as
fTs

gm
2pCg

(1)

The transconductance, gm, is extracted from simulations and total gate capacitance Cg is calculated as the
sum of the device capacitance, Cdevice, and the pad
capacitance, Cpad.
CgsCdeviceqCpadsCchlzqSiC

Apad
t

(2)

The device capacitance is proportional to the device

width, lz, and the pad capacitance is assumed as a flat
capacitor formed beneath the gate pad. The area for the
gate pad used in the optimization is 75=75 mm. For
the vertical MESFET the depletion depth, wgd, defines
the thickness, t, of the capacitor.
The maximal allowed gate capacitance is designed to
be as large as possible where a simple input matchingnetwork can be achieved. This is realized with a gate
capacitance having equal reactance as for a typical
bonding wire at a specified frequency. The maximal
allowed frequency where the capacitance can be cancelled by the bonding wire inductance, Lbond, is
fmatchs

1
2pyLbondCg

(3)

In the optimization the value used for the bonding

inductance is Lbonds0.5 nH. For optimal device width
f T and f match is set to be equal. In this case the device
width, lz, is calculated from Eqs. (1)(3) by solving a
second order equation.
Fig. 2. The device performance of a 4HSiC vertical MESFET as a
function the design parameters normalized to optimal values.

lzs

Cch"yC2chq4g2mLbond Cpad
2g2mLbond

(4)

K. Bertilsson, H.-E. Nilsson / Diamond and Related Materials 11 (2002) 12541257

1256

Table 1
Geometry of optimized devices

5. Device improvements

Device

Lds (mm)
Lgd (mm)
Wch (mm)
wgate (mm)
ND (cmy3)
lz (mm)
f T (GHz)

2.0
1.6
0.30
0.20
5.0=1015
3.0
7.5

0.56
0.45
0.20
0.20
5.0=1015
0.24
34

0.45
0.33
0.20
0.20
5.0=1015
0.17
43

Dev. 1, vertical MESFET processes with traditional technology.

Dev. 2, vertical MESFET with reduced bulk-thickness (lbulk) to 10
mm and raised gate pad on top of 10-mm oxide (tox). Dev. 3, vertical
MESFET on semi-insulating substrate.

The device is optimized using a gradient search to

find the highest f T as the design parameters are varied.
In Fig. 2 the results from the optimization are shown
for a 4HSiC vertical MESFET as the design parameters
(Fig. 1) are changed from 0.5 to 1.5 times the optimal
value, where the peak values in the center indicate that
the optimization has found an optimal geometry.
To guarantee realistic device dimensions in the optimization process some parameters are set to limiting
values based on silicon carbide specifications w13x and
a lithographic resolution achievable in commercial silicon products. (1) The minimal lithographic resolution
is 0.2 mm, which limits wgate and wch. (2) The epitaxial
layer thickness is set between 0.1 and 10 mm, which
limits lds. (3) The gate-drain spacing is set to be at least
0.1 mm and at most 80% of the total channel length.
(4) The minimal channel doping, Nch allowed is
5=1015 cmy3.

Optimization indicates that the vertical MESFET have

problems reaching f T higher than 7 GHz that has already
been achieved in a state of the art device. To increase
the performance the parasitics from gate pad and drain
resistance must be reduced.
The gate pad capacitance can be reduced in two
different ways: (1) reduce the area of the pad; or (2)
reduce the capacitor thickness. A discrete vertical MESFET must, however, be connected with a bonding wire
and the pad must have a minimum size for the bonding
process (75=75 mm is used in this case). Placing the
gate pad on top of a field oxide layer increasing the
paddrain distance and in this way decreasing the
capacitance.
The resistivity of the bulk is high for SiC substrates
at room temperature due to the carrier freezeout. A
reduction of the bulk thickness or an increment of the
gate and channel width can decrease the drain resistance
of a vertical MESFET. The influence of gate and channel
widths on the device performance is significant and
optimal widths are obtained in the optimization process.
Further improvements will, however, only be achieved
by reducing the bulk thickness. The thickness is, however, limited by the bulk substrate supplied from the
manufacturer. The effective thickness of the drain resistance might be reduced by etching and metallizing a
grid from the rear side of the substrate.
The performance of such a device (Fig. 1b) has been
optimized to give an idea of the possibilities for vertical
MESFETs in hexagonal SiC. The optimization is performed for a device where the gate-pad is placed on a

4. Optimization results
The 2Hy4Hy6HSiC vertical MESFET optimized for
high frequency have reached f T equal to 8.6y7.5y2.2
GHz. The low value for the 6HSiC device is due to
the bad transport properties perpendicular to the surface
in 6HSiC. The best performance is achieved for a 2H
SiC device due to the favorable transport properties in
the direction perpendicular to the surface. In Table 1 the
geometry of the optimized vertical 4HSiC MESFET
realized in a standard technology using a lithographic
resolution limited to 0.2 mm, is shown.
The influence of the lithographic resolution on f T is
studied and presented in Fig. 3. The low influence of
the lithographic resolution is due to the increased parasitic bulk resistance as the channel and gate widths are
reduced.
The state of the art vertical MESFET is manufactured
with a lithographic resolution 0.5 mm w2x, pad-size of
75=75 mm2 w14x, and f Ts7 GHz. The optimization
procedure for high frequency presented here using the
same lithographic resolution is in excellent agreement
and gives f Ts7.1 GHz.

Fig. 3. Unity current gain frequency, f T, as a function of the lithographic resolution for different types of 4HSiC MESFETs. (s) Normal vertical MESFET; (h) vertical MESFET with reduced effective
bulk thickness and increased gate-pad bulk spacing; (e) vertical
MESFET on semi-insulating substrate.

K. Bertilsson, H.-E. Nilsson / Diamond and Related Materials 11 (2002) 12541257

10-mm-thick SiO2 layer and the drain bulk thickness

has been reduced to 10 mm. The performance is significantly improved with f T reaching 41y34y9.2 GHz for
a 2Hy4Hy6HSiC device. The optimal device in this
structure (Table 1) has large differences in the geometry
and doping compared to an optimal device processed
by standard technology. This device can utilize the
reduced lithography in a better way and an optimal
device is shorter and has a smaller channel width
compared to an optimized vertical MESFET processed
in a traditional way. The performance of this structure
is more sensitive to the lithographic resolution compared
to a normal vertical MESFET (Fig. 3) and for a device
manufactured in a 0.5-mm process, f T is increased from
8.6y7.5y2.2 to 33y27y7.3 GHz compared with a device
manufactured in traditional way.
As seen previously, all of the dominant parasitics in
the vertical MESFET are caused by the high-doped
substrate. The parasitics can be reduced significantly by
manufacturing the vertical MESFET on a semi-insulating substrate (Fig. 1c). All three (gate, drain and source)
contacts are placed on the top side of the wafer. This
device is more three-dimensional compared to a normal
vertical MESFET, since the drain current is transported
laterally in a high-doped epitaxial drain layer, towards
the drain pad. Two-dimensional simulators have problems to simulate this device accurately, but the results
give a good hint of the performance that can be achieved
with this technology. For a 2Hy4Hy6HSiC vertical
MESFET on semi-insulating substrate the highest f T
achieved with 0.2-mm lithography is 50y43y12 GHz.
The dimensions for the optimal 4HSiC structure (Table
1) have large similarities with the previous device where
a small device is optimal and the performance decreases
rapidly with increased lithography (Fig. 3). The vertical
MESFET realized on semi-insulating substrates is the
fastest structure considered in this paper.
6. Conclusions
Vertical MESFET is limited by inherent parasitics
such as a high gate pad capacitance and bulk resistance
and the optimization shows that for vertical MESFETs,
using a standard technology, it is difficult to achieve
higher f T than already is achieved in a fabricated state
of the art device. Vertical MESFET is only slightly
dependent on the lithographic resolution, since the drain
resistance is increased as the channel width is decreased.

1257

Vertical MESFET can be improved by reducing the

parasitics in the device. This can be achieved both by
reducing the effective bulk thickness and increase the
gate-pad to bulk spacing. A device like that gives better
performance compared to vertical MESFETs processed
with traditional technology.
Vertical MESFETs can also be realized on semiinsulating substrates and in this case reaching higher
frequencies, and the highest f T obtained in the optimization for a 4HSiC device is 50 GHz. As this device
is completely realized in the epitaxial layers two-dimensional effects are important and the device should be
designed with multiple short channels to minimize the
influence of distributed drain-resistance and phase shift
in the fingers. One more advantage with this structure
over normal vertical MESFETs is the possibility to
integrate multiple devices on the same chip.
The development of 2HSiC substrates would be an
advantage for SiC vertical MESFET performance, which
can be increased by f20%. We have established good
agreement between simulations and measurements and
the reliability in the results is therefore expected to be
good.
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