TH-A5#SML1 Service Manual

TH-A5
SERVICE MANUAL
DVD DIGITAL CINEMA SYSTEM
Area suffix
TH-A5
A ------------------ Australia
US -------------- Singapore
UB ------------- Hong Kong
UW -- Brazil,Mexico,Peru
UY --------------- Argentina
UJ ------------- U.S.Military
UG ------------------ Turkey,
South Africa,Egypt
STANDBY/ON
AUDIO
VCR
TV
VCR
CONTROL
ON
OFF
TOP MENU
MENU
TV CHANNEL
AUDIO/
FM MODE SUBTITLE
DISPLAY RETURN
TV VOLUME
STEP
TV/VIDEO
TUNER PRESET
DOWN
UP
REW
SP-XSA5 2
SP-XCA5
SP-XSA5 2
FF
VCR CHANNEL
TUNING
B.SEARCH
F.SEARCH
ENTER
VOLUME
DVD
FM/AM
AUX
MUTING
COMPACT
DIGITAL VIDEO
STANDBY
AUDIO/FM MODE
STANDBY/ON
D I G I T A L
DSP
VOLUME
SOURCE
SURROUND
DVD DIGITAL CINEMA SYSTEM TH-A5
D I G I T A L
RM-STHA5U
DVD CINEMA SYSTEM
XV-THA5
SP-WA5
Contents
Safety precautions
Important for laser products
Preventing static electricity
Disassembly method
COPYRIGHT
1-2
1-3
1-4
1-5
Wiring connection
Adjustment method
Description of major ICs
2002 VICTOR COMPANY OF JAPAN, LTD.
1-12
1-13
1-15~33
No.21062
Jan. 2002
TH-A5
1. This design of this product contains special hardware and many circuits and components specially for safety
purposes. For continued protection, no changes should be made to the original design unless authorized in
writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services
should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product
should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further
relieve the manufacture of responsibility for personal injury or property damage resulting therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics. These
characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily
be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which
have these special safety characteristics are identified in the Parts List of Service Manual. Electrical
components having such features are identified by shading on the schematics and by ( ) on the Parts List in
the Service Manual. The use of a substitute replacement which does not have the same safety characteristics
as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or
other hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be
separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of
electric shock and fire hazard. When service is required, the original lead routing and dress should be
observed, and it should be confirmed that they have been returned to normal, after re-assembling.
5. Leakage currnet check (Electrical shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts of the product
(antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the
product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage
current from each exposed metal parts of the cabinet, particularly any exposed metal part having a return
path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.).
Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more
sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor
between an exposed metal part and a known good earth ground.
AC VOLTMETER
Measure the AC voltage across the resistor with the AC
(Having 1000
ohms/volts,
voltmeter.
or more sensitivity)
Move the resistor connection to each exposed metal part,
particularly any exposed metal part having a return path to
0.15 F AC TYPE
the chassis, and meausre the AC voltage across the resistor.
Place this
Now, reverse the plug in the AC outlet and repeat each
probe on
measurement. Voltage measured any must not exceed 0.75 V
each exposed
AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).
1500 10W
metal part.
Good earth ground
1. This equipment has been designed and manufactured to meet international safety standards.
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
3. Repairs must be made in accordance with the relevant safety standards.
4. It is essential that safety critical components are replaced by approved parts.
5. If mains voltage selector is provided, check setting for local voltage.
!
Burrs formed during molding may
be left over on some parts of the
chassis. Therefore, pay attention to
such burrs in the case of
preforming repair of this system.
In regard with component parts appearing on the silk-screen printed side (parts side) of the PWB diagrams, the
parts that are printed over with black such as the resistor (
), diode (
) and ICP (
) or identified by the " "
mark nearby are critical for safety.
(This regulation does not correspond to J and C version.)
1-2
TH-A5
Important for laser products

1.CLASS 1 LASER PRODUCT
2.DANGER : Invisible laser radiation when open and inter
lock failed or defeated. Avoid direct exposure to beam.
3.CAUTION : There are no serviceable parts inside the
Laser Unit. Do not disassemble the Laser Unit. Replace
5.CAUTION : If safety switches malfunction, the laser is able

to function.
6.CAUTION : Use of controls, adjustments or performance of
procedures other than those specified herein may result in
hazardous radiation exposure.
the complete Laser Unit if it malfunctions.

4.CAUTION : The compact disc player uses invisible
laserradiation and is equipped with safety switches
whichprevent emission of radiation when the drawer is

open and the safety interlocks have failed or are de
Please use enough caution not to

see the beam directly or touch it
in case of an adjustment or operation
check.
feated. It is dangerous to defeat the safety switches.
REPRODUCTION AND POSITION OF LABELS

CLASS 1
LASER PRODUCT
1-3
TH-A5
Preventing static electricity

1.Grounding to prevent damage by static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.
2.About the earth processing for the destruction prevention by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as CD players.
Be careful to use proper grounding in the area where repairs are being performed.
2-1 Ground the workbench

Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
2-2 Ground yourself

Use an anti-static wrist strap to release any static electricity built up in your body.
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
4.Handling the traverse unit (optical pickup)

1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.
Attention when traverse unit is decomposed

*Please refer to "Disassembly method" in the text for pick-up and how to detach the substrate.
1. Solder is put up before the card
wire is removed from connector
on the pick up board as shown in
Figure.
(When the wire is removed
without putting up solder, the CD
pick-up assembly might destroy.)
2. Please remove solder after
connecting the card wire with
when you install picking up
in the substrate.
DVD mechanism assembly (bottom side)
Short land
DVD loading
mechanism
Connector
Pick up board
Card wire
DVD loader board
1-4
(These two points are

soldered respectively,
and are made to
short-circuit)
TH-A5
Disassembly method
Removing the top cover
Top cover
(See Fig.1)
1. Remove the four screws A attaching the top cover

on the both sides of the body.
2. Remove the two screws B on the back of the body.
Fig.1
3. Remove the top cover from behind in the direction of

the arrow while pulling both sides outward.
Removing the front panel assembly

(See Fig.2A, 2B and 3)
Front panel assembly
Claw1
Prior to performing the following procedure, remove

the top cover.
1. Remove the one screw a and remove the earth wier.
2. Remove the three screws C attaching the front panel
assembly on the bottom of the body.
(bottom side)
Fig.2A
3. Remove the two screws D attaching the front panel

assembly on the both sides of the body.
Front panel
assembly
4. Remove the claw1, claw2 and claw3, and detach the

front panel assembly toward the front.
Claw3
Claw2 (both side)
5. Disconnect the card wire from the connector DW20

on the DSP board.
Removing the power cord
(See Fig.4)

the top cover.
(both side)
1. Disconnect the power cord from the connector CW1

on the main board and pull up the cord stopper
upward.
(fixing the earth wire)
Notes : The power cord is exchangeable.
Fig.2B
Power cord
DSP board
CW1
Tie band
DW20

(Inner side)
Rear panel
Fig.4
Power cord
stopper
Display board
Fig.3
1-5
TH-A5
Removing the DVD mechanism assembly

(See Fig.5 and 6)
DVD mechanism assembly

DVD
MPEG
board

the top cover.
J14
1. Disconnect the card wire from the connector J14 and

J21 on the DVD MPEG board.
E
J21
2. Remove the two screws E attaching the DVD

mechanism assembly and pull up with drawing out.
3. Disconnect the harness from the connector J2 on the
DVD loader board.
Removing the rear panel (See Fig.7 and 8)

the top cover and power cord.
Rear panel
Fig.5
1. Disconnect the harness from the connector NW11 on

the DSP board.
DVD mechanism
assembly
2. Remove the two screws F, four screws G, five

screws I attaching the each boards to the rear panel.
3. Remove the three screws J attaching the rear panel
on the back of the body.
Removing the tuner pack (See Fig.7 and 8)

DVD loader board

the top cover.
J2
Fig.6
1. Disconnect the card wire from the connector CON01

on the tuner pack.
2. Remove the two screws F attaching the tuner pack
to the rear panel.
Rear panel
Fan motor
Removing the jack board (See Fig.7 and 8)

the top cover.
1. Disconnect the card wire from the connector VW2 on
the jack board.
2. Remove the four screws G attaching the jack board
to the rear panel.
Fig.7
DSP board
CON01
3. Disconnect the connector VW1 on the jack board

and pull up the jack board.
Removing the fan motor (See Fig.7 and 8)

VW2
Prior to performing the following procedures, remove

the top cover .
Rear panel
the DSP board .
2. Removing the two screws H attaching the fan motor
on the rear panel.
1-6
NW11
(on the
DSP board)
VW1
Fig.8
Tuner pack
Jack board
TH-A5
Removing the DSP board
(See Fig.9)
DSP board
VW12 Harness band
Main board

the top cover, the front panel assembly and jack
board.
CW2
1. Untied the harness band and disconnect the harness

from the connector CW2 on the main board.
NW11
3. Disconnect the card wire from the connector VW12

on the DSP board.
4. Pull up the DSP board from the front side upwards
disconnecting the connector DW10, DW13, DW14
and DW15.
(Rear panel side)
(Front panel side)

the DSP board.
DW15
DW10
Fig.9
Main board
Removing the main board
DW14 DW13
K1
(See Fig.10)

the top cover, front panel assembly, DVD
mechanism assembly, jack board and DSP board.
1. Disconnect the card wire from the connector CW4
and CW8 on the main board.
Heat sink
(to which
power
transistor
is attached)
CW8
K2
K1
2. Disconnect the harness from the connector CW3 on

the main board.
3. Remove the five screws I attaching the speaker
terminals and jack to the rear panel (see fig.7).
4. Remove the six screws K1 (short) and one screw K2
(long) attaching the main board.
5. When the rear panel is not removed, pull up the
main board from front side.
CW4
CW3 Power ICs
Fig.10
(Each power transistor is fixed)
Solder part Solder part Solder part
Main board
(Reverse side )
Removing the power transistor & power IC

(See Fig.10 and 11)
the top cover, front panel assembly, DVD
mechanism assembly, jack board, DSP board and
main board.
1. After removing the solder part soldered to the main
board, remove each screw and remove the heat sink
from Power transistor.
2. After removing the solder part soldered to the main
board, remove each screw and remove the heat sink
from Power IC.
Solder part
(Power IC is fixed)
Heat sink
(to which power IC is attached)
Fig.11
1-7
TH-A5
Removing the DVD power board
(See Fig.12)
the top cover, front panel assembly and DSP board.
1. Disconnect the harness and card wire from the
connector PW1, PW2 and PW5 on the DVD power
board.
2. Remove the one screw L1 (short) and two screws L2
(long) attaching the DVD power board.
Tie band
L1
PW5
PW2
DVD
power
board
Power
transformer
Removing the power transformer

(See Fig.12)
PW1
L2
Fig.12

the top cover.
1. Cut off the tie band fixing the harness, if needed.
2. Disconnect the harness from the connector CW2 on
the main board (see fig.9) and PW1, PW2 on the
DVD power board.
3. Remove the four screws M attaching the power
transformer.
<Front panel assembly section>

Removing the display board & switch
board
(See Fig.1 and 2)
FW1
Display board

(inner side)
Switch board

the top cover and the front panel assembly.
1. Disconnect the card wire from the connector FW1 on
the display board.
Fig.1
2. Remove the five screws A attaching the display

board on the inner of the front panel assembly.
3. Remove the four screws B attaching the switch
board on the inner of the front panel assembly.
FW2
Switch button
4. Disconnect the harness from connector FW2 on the

display board, if needed.
Removing the front window

(See Fig.2 and 3)
the top cover, front panel assembly, display board
and switch board.
Claw
Fig.2
Front panel assembly (front side)
1. Remove the switch buttons, if needed.

2. Remove the three screws C attaching the front
window on the front panel.
3. Remove the eight claws fixing the front window on
the front panel.
1-8
Front window
Fig.3
TH-A5
(top side)
<DVD mechanism assembly section>

Removing the DVD loader board
(See Fig.1 to 3)
the top cover and DVD mechanism assembly.
1. Disconnect the card wire from the connector J6 on
the DVD MPEG board.
DVD MPEG board

J6
2. Disconnect the harness from the connector on the

motor board.
3. Disconnect the harness from the connector J5 on the
DVD loader board.
4. Remove the four screws A attaching the DVD loader
board to DVD mechanism assembly.
CAUTION!!
Fig.1
(bottom side)
DVD loader board
Motor board
(see fig.3)
Before removing the card wire which

connects the pickup board and DVD loader
board, solder the two soldering parts and
make it short-circuit.
Moreover, while having removed the card
wire, don't remove these solder.
5. Disconnect the card wire from the connector U9 on
the DVD loader board.
U9
Connector
Fig.2
Pick up
board
ONE POINT
How to eject the DVD tray manually
(see fig.2)
The white lever of the
mark is moved in
the direction of the arrow. Then, the tray will
be opened.
Moreover, the tray is separable from a DVD
mechanism assembly by removing two
screws of the mark (see fig.1) and drawing
out the tray.
Soldering parts
Motor board
DVD loading
mechanism
Fig.3
Removing the DVD loading mechanism

(See Fig.4)

the top cover, DVD mechanism assembly and DVD
loader board.
1. Remove the two screws B and remove the bracket.
J5

(bottom side)
Bracket
X
Lever
DVD loading
mechanism
2. Remove the one screw C fixing the DVD loading

mechanism.
3. Move the lever in the direction of the arrow X.
4. Remove the DVD loading mechanism from the DVD
mechanism assembly by moving it in the direction of
the arrow Y.
Y
C
Fig.4
1-9
TH-A5
DVD loading mechanism
(top side)
Removing the DVD traverse mechanism

(See Fig.5)
the top cover, DVD mechanism assembly, DVD
loader board and DVD loading mechanism.
DVD traverse
mechanism
1. Remove the four screws D attaching the DVD

traverse mechanism to DVD loading mechanism.
Fig.5
Removing the holder & DVD MPEG board

(See Fig.6 and 7)
Holder

the top cover, DVD mechanism assembly and DVD
loader board.
1. Remove the two claws1, and remove the holder from
the DVD mechanism assembly as it is pushed down.
Claw1
Note: When removing only the DVD MPEG board, it is not

necessary to remove this holder.
2. Remove the four claws2 and remove the DVD

MPEG board from the holder.
(bottom side)
Fig.6
Holder
DVD MPEG board
Fig.7
Claw2
DVD MPEG board
ONE POINT
When inserting DVD MPEG board in
holder.
(see fig.8)
Holder
Insert in after uniting with a lower claws,

when inserting DVD MPEG board in holder.
Fig.8
1-10
TH-A5
<Speaker section>
[SP-XSA5 / Satellite speaker]
It is exchange in a unit.
Front panel
[SP-XCA5 / Center speaker]

It is exchange in a unit.
[SP-WA5 / Woofer]
Removing the front panel
(See Fig.1 and 2)
The tool with

a flat tip
1. Remove the six bosses and remove the front panel.

Fig.1
Notes: It will be good to use the tool with a flat tip, since it
is hard to remove. Please take care not to damage the
cabinet at this time.
Front panel
(inner side)
2. The packing separates. It removes if needed.

Boss
Removing the speaker unit

(See Fig.3 to 5)
Packing
1. Remove the four bosses and remove the net

assembly.
Fig.2
Notes: It will be good to use the tool with a flat tip, since it
is hard to remove. Please take care not to damage the
cabinet at this time.
Net assembly
2. Remove the eight screws A attaching the speaker

unit to cabinet.
Boss
3. Disconnect the code from the two terminals of the

speaker unit.
Terminals
Fig.3
red
Code
Speaker unit
black
Cabinet
Speaker unit (reverse side)
Fig.5
Fig.4
1-11
TH-A5
3809-001273
JACK BOARD (V-OUT)

VW2
3809-001274
3809-001224
VW1
0
9
NW11
AH39-00291A
J2
J5
AH39-00368A
DW11
DW10
DW23
DW13
DW12
DW14
1 C
9
0
3809-001296
DW20
DW15
VW11
DSP1 BOARD
SWITCH BOARD
CW2
PT1
RE4
8 3 0
9 2 4
0
2
FW2
3809-001283
RE3
FU3
FU4
FU2
FU1
CW1
CW8
DW31
DW32
PW4
6 1
0
AH39-00176A
PW3
PW1
DVD
POWER
BOARD
PW5 PW2
DSP2 BOARD
U9
DVD LOADER BOARD
J4
0
9
3809-001295
AH39-00104A
TUNER PACK
CON01
J3
J21
DVD MPEG
BOARD
J6
J14
2
0
9
0
FW3
CW5
CW6
CW7
CW4
0
4
3
2
8
9
2
AH39-50001K
MAIN BOARD
CW3
FW1
POWER TRANCE
DISPLAY BOARD
1-12
Color codes are shown below.

1
Brown
6
Blue
2
Red
7
Violet
3
Orange 8
Gray
4
Yellow
9
White
5
Green
0
Black
Wiring connection
3809-001294
TH-A5
Adjustment method
1. Tuner
*Adjustment Location of Tuner PCB
ITEM
AM(MW) OSC Adjustment
AM(MW) RF
Adjustment
Received FREQ.
A : 522~1629KHz (9k step)

US/UB/ : 531~1602KHz (9k step)
UW/UJ 530~1600KHz (10k step)
603 KHz
Adjustment
point
MO
MA
Output
1~7.0V
Maximum
Output(Fig1-1)
MAIN
PCB
VT
GND
TESTER
Fig 1-1 OSC Voltage
1-13
TH-A5
FM THD Adjustment
SSG FREQ.
98 MHz
Adjustment
point
(FD)
FM DETECTOR COIL
Output
60 dB
FM
Antenna SET
Te
T
Terminal
Output
GND
FM S.S.G
Oscilloscope
Input
Speaker
T
Te
Terminal
output
Minimum Distortion (0.4% below)

(Figure 1-2)
Input
Distortion Meter
Figure1-2 IF CENTER and THD Adjustment
FM Search Level Adjustment

SSG FREQ.
28 dB
98 MHz
Adjustment
point
(SVR3)
BEACON
SENSITIVITY
SEMI-VR(20K )
Output
28 dB(
FM Antenna
SET
FM S.S.G
GND
FM IN
dB)
Adjust SVR1 so that TUNED of FL T

is lighted (Figure 1-3)
20 k
*Adjust FM S.S.G level to 28dB

Figure1-3 FM Auto Search Level Adjustment
AM(MW) I.F Adjustment

SSG FREQ.
450 kHz
Frequency
522 kHz
Adjustment
point
60cm
AM IF
AM ANT
IN
OUTPUT
AA
Speaker Terminal
AM SSG
450KHZ
Maximum output (Figure 1-4)

OUTPUT
INPUT
VTVM
Oscilloscope
Figure1-4 AM I.F Adjustment
Notes: This set is a non-adjusted set fundamentally. It is adjusted when the tuner pack is exchanged.
1-14
TH-A5
Description of major ICs

BA5983FM (U6) : 4CH driver
1.Block diagram
27
28
25
26
23
24
22
21
20
18
19
17
Vcc
Vcc
16
10k
15
10k
10k
STAND BY
CH4
10k
10k
10k
10k
10k
10k
20k
Level Shift
10k
20k
Level Shift
10k
Level Shift
10k
10k
Level Shift
10k
10k
10k
STAND BY
CH1/2/3
10k
10k
10k
Vcc
10
10k
10k
12
11
10k
13
14
2.Pin function
Pin No.
Symbol
BLAS IN
OPIN1(+)
Function
Pin No.
Symbol
I/O
Input for Bias-amplifier
15
VO4(+)
Non inverted output of CH4
Non inverting input for CH1 OP-AMP
16
VO4(-)
Inverted output of CH4
I/O
Function
OPIN1(-)
Inverting input for CH1 OP-AMP
17
VO3(+)
OPOUT1
Output for CH1 OP-AMP
18
VO3(-)
OPIN2(+)
19
PowVcc2
Vcc for CH3/4 power block
OPIN2(-)
20
STBY2
Input for Ch4 stand by control
OPOUT2
21
GND
Substrate ground
GND
Substrate ground
22
OPOUT3
STBY1
Input for CH1/2/3 stand by control
23
OPIN3(-)
10
PowVcc1
Vcc for CH1/2 power block
24
OPIN3(+)
11
VO2(-)
25
OPOUT4
12
VO2(+)
26
OPIN4(-)
27
OPIN4(+)
28
PreVcc
Vcc for pre block
13
VO1(-)
14
VO1(+)
74VHC574 (DIC16, DIC17) : Flip flop

1. Pin layout
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
2. Pin function
20
19
18
17
16
15
14
13
12
11
Vcc
O0
O1
O2
O3
O4
O5
O6
O7
CP
Symbol
D0-D7
CP
OE
O0-O7
3. Truth table
Function
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Inputs
Dn
H
L
X
CP
Outputs
OE
L
L
H
On
H
L
Z
H:HIGH Voltage Level

L:LOW Voltage Level
X:Immaterial
Z:High Impedance
:HIGH to LOW transition
1-15
TH-A5
ZiVA-5 (U8) : DVD controller
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DA-IEC958
DA-DATA3
DA-DATA2
VSS
VDD_3.3
DA-DATA1
DA-DATA0
DA-BCK
DA-LRCK
DA-XCK
VSS
VDDC
A_VSS1
A_VDD1
A_VDD2
A_VSS2
XVDD
XTAL/VCLK216BP
XTAL
XVSS
VSS_RREF
VDAC_RREF
VDD_RREF
VDAC_DVDD
VDAC_DVSS
VDAC_0
VDAC_VDD0
VDAC_0B
VDAC_1
VDAC_VDD1
VDAC_1B
VDAC_2
VDAC_VDD2
VDAC_2B
VDAC_3
VDAC_VDD3
VDAC_3B
VDAC_4
VDAC_VDD4
VDAC_4B
HSYNC/IRQ2
VDATA0
VDATA1
VDATA2
VSS
VDD_3.3
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7
VCLK
1. Pin layout
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD_3.3
VSS
MDATA31
MDATA30
MDATA29
MDATA28
VDD_3.3
MDQM3
VSS
MDATA27
MDATA26
MDATA25
MDATA24
MDATA23
MDATA22
MDATA21
MDATA20
VDD_3.3
MDQM2
VSS
MDATA19
MDATA18
MDATA17
MDATA16
VDDC
VSS
MDATA15
MDATA14
MDATA13
MDATA12
VDD_3.3
MDQM1
VSS
MDATA11
MDATA10
MDATA9
MDATA8
MDATA7
MDATA6
MDATA5
MDATA4
VDD_3.3
MDQM0
VSS
MDATA3
MDATA2
MDATA1
MDATA0
MCLK
VDD_3.3
VSS
MWE
VDD_3.3
HA1
HAD15
HAD14
HAD13
HAD12
HAD11
HAD10
HAD9
HAD8
HAD7
VDD_3.3
VSS
HAD6
HAD5
HAD4
HAD3
HAD2
HAD1
VDD_3.3
VSS
HAD0
HDTACK/WAIT
HIRQ0
UDS/UWE
LDS/LWE
R/W
IRRX1
VSS
VDDC
VSS
VDD_3.3
MADDR9
MADDR8
MADDR7
MADDR6
MADDR5
MADDR4
MADDR3
MADDR2
MADDR1
MADDR0
VSS
VDD_3.3
MADDR10
MADDR11
BA1
BA0
MCS0
MCS1
MRAS
MCAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DAI-DATA
DAI-BCK/SYSCLKBP
DAI-LRCK/IEC958BP
I2C_CL
I2C_DA
RTS1
RXD1
TXD1
CTS1
VSS
VDD_3.3
SD-DATA7
SD-DATA6
SD-DATA5
SD-DATA4
VSS
VDDC
SD-DATA3
SD-DATA2
SD-DATA1
SD-DATA0
SD-REQ
SD-EN
VSS
VDD_3.3
SD-ERROR
SD-CLK
VSYNC/HIRQ1
RTS2/SPI_CLK
RXD2/SPI_MISO
TXD2/SPI_MOSI
CTS2/SPI_CS
VDD_5
HCS4
HCS3
HCS2
HCS1
HCS0
VSS
VDD_3.3
TRST
TDO
TDI
TMS
TCK
RESET
ALE
VSS
VDDC
HAD3
HAD2
VSS
System Services
2. Pin function
(1/4)
Name
RESET
Pin No.
202
VCLK
XOUT
105
138
XIN/bypass clk_216
139
Type 1 Description
Active Low Reset. Assert for at least 5-milliseconds in the presence of
I
clock to reset the entire chip.
Video clock that outputs 27 MHz.
I/O
Crystal output. When the internal DCXO is used, a 13.5 MHz crystal
O
should be con-nected between this pin and the XIN pin.
Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should
I
be con-nected between this pin and the XOUT pin. When an external
oscillator or VCXO is used, its output should be connected to this pin.
When configured for an external bypass clock, a 216 MHz clock should be
connected to this pin. The frequency of an external VCXO can be either 27
or 13.5 MHz.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-16
TH-A5
2. Pin function
(2/4)
Power and Ground
Name
Pin No.
VNW
189
VDDP
12, 20, 111, 152, 167, 181, 196
VDD25
32, 44, 55, 63, 74, 87, 98, 104
XVDD
140
VDD
30, 80, 145, 173, 205
VDD_VDAC[4:0]
118, 121, 124, 127, 130
VDAC_DVDD
133
A_VDD[2:1]
142, 143
VDAC_REFVDD
134
GNDP
13, 21, 112, 153, 166, 180, 195, 208
GND
29, 79, 146, 172, 204
GND25
31, 43, 54, 61, 72, 85, 96, 103
VDAC_DVSS
132
AVSS[2:1]
141, 144
VDAC_REFVSS
136
XVSS
137
HCS[4:2]/GPIO[41:43]
190-192
SDRAM Interface
Host Interface
HCS[1:0]
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
O
193, 192
HA[3:1]
206, 207, 2
I/O
HA[15:0]
3-11, 14-19, 22
I/O
HDTACK/WAIT
HIRQ0
23
24
I/OD
I/O
HUDS/UWE
25
I/O
HLDS/LWE
26
I/O
HREAD
ALE
MCS[1:0]
MCAS
MRAS
MDQM[3:0]
27
203
50, 49
52
51
97, 86, 73, 62
I/O
I/O
O
O
O
O
46, 45, 33-42

102-99, 95-88, 84-81,
78-75, 71-64, 60-57
53
O
I/O
56
47, 48
116
O
O
I/O
105
I/O
106-110, 113-115
I/O
184
I/O
MA[11:0]
MD[31:0]
MWE
MCLK
BA[1:0]
HSYNC/HIRQ2/
GPIO1[9]
Digital Video Input/Output
Type 1
Power
Power
Power
Power
Power
Power
VCLK
VDATA[7:0]/GPIO[1:7]
VSYNC/HIRQ1/
GPIO36
Description
5-V supply voltage for 5V-tolerant I/O signals.
3.3-V supply voltage for I/O signals
3.3-V supply voltage for SDRAM I/O signals
3.3V Crystal interface power
1.8-V supply voltage for core logic
Analog Video DAC Power
3.3V Digital supply for 5 DACs
3.3-V Analog PLL Power
3.3V Analog Video Reference Voltage
Ground for I/O signals
Ground for core logic
Ground for SDRAM I/O signals
Digital VSS for DACs
Analog PLL Ground
Video Analog Ground
Crystal interface ground
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation. General Purpose I/Os 41, 42, and 43, respectively.
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation.
Host (muxed address) address bus. 3-bit address bus selects one of eight
host inter-face registers. These signals are not muxed in ATAPI master
mode.
HA[15:0] is the 16-bit (muxed address and data) bi-directional host data
bus through which the host writes data to the decoder Code FIFO. MSB of
the 32-bit word is writ-ten first. The host also reads and writes the decoder
internal registers and local SDRAM/ROM via HA[7:0]. These signals are
not muxed for ATAPI master mode.
Host Data Transfer Acknowledge.
Host interrupt. Open drain signal, must be pulled-up via 4.7k to 3.3 volts.
Driven high for 10 ns before tristate.
Host Upper Data Strobe. Host high byte data, HA[15:8], is valid when this
pin is active.
Host Lower Data Strobe. Host low byte data, HA[7:0], is valid when this pin
is active.
Read/write strobe
Address latch enable
Memory chip select.
Active LOW SDRAM Column Address Strobe.
Active LOW SDRAM Row Address Strobe.
These pins are the bytes masks corresponding to MD[7:0], [15:8], [23:16]
and [31:24]. They allow for byte reads/writes to SDRAM.
SDRAM Address
SDRAM Data
SDRAM Write Enable. Specifies transaction to SDRAM: read (=1) or
write (=0)
SDRAM Clock
SDRAM bank select
Horizontal sync. The decoder begins outputting pixel data for a new
horizontal line after the falling (active) edge of HSYNC.
Host Interrupt Request 2
General Purpose I/O 9
Video clock. Clocks out data on input. VDATA[7:0].
Clock is typically 27 MHz.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At
powerup, the decoder does not drive VDATA. During boot-up, the
decoder uses configuration parameters to drive or 3-state VDATA.
General Purpose I/Os [1:7]
Vertical sync. Bi-directional, the decoder outputs the top border of a new
field on the first HSYNC after the falling edge of VSYNC. VSYNC can
accept vertical synchroni-zation or top/bottom field notification from an
external source. (VSYNC HIGH = bot-tom field. VSYNC LOW = Top field)
Active Low Host Interrupt Pin
1-17
TH-A5
Analog Video Output
Parallel DVD/CD or Serial CD Interface
2. Pin function
Pin No.
168
SDDATA6/VDATA2[6]
/HXCVR_EN/GPIO25
169
SDDATA5/VDATA2[5]
HDMACK/GPIO26
170
SDDATA4/VDATA2[4]/
GPIO27
171
SDDATA3/
VDATA2[3]/GPIO28
174
SDDATA2/
VDATA2[2]/GPIO29
175
SDDATA1/
VDATA2[1]/GPIO30
176
SDDATA0/
VDATA2[0]/GPIO31
177
SDCLK
183
SDERROR
182
SDEN/GPIO33
179
SDREQ/GPIO32
178
VDAC_[4B:0B]
VDAC_4
VDAC_3V
DAC_2
VDAC_1
VDAC_0
VDAC_REF
VCLK
Audio Interface
ADATA[3:0]/GPIO[4:1]
Digital Mic In
(3/4)
Name
SDDATA[7]/VDATA2[7]
/HDMARQ/GPIO24
BCK
LRCK
117, 120, 123, 126, 129

119
122
125
128
131
135
105
155, 154, 151, 150

149
XCK
148
147
IEC958/GPIO14
156
DAI_DATA/GPIO15
157
DAI_BCK/
BYPASS_SYSCLK/
GPIO16
DAI_LRCK/
IEC958BP/GPIO17
158
159
Type 1 Description
I
Compressed data from DVD DSP. Bit 7. In parallel mode, bit 7 is the first
(earliest in time) bit in the bitstream, while bit 0 is the last bit.
Video Data Bus 2, Bit 7
Host DMA Request
Compressed data from DVD DSP. Bit 6.
ATAPI Transceiver Enable
Host DMA Acknowledge
In serial mode, bit 0 should be used as the input, with the unused bits
either used as GPIOs or tied to ground.
I
Data clock. The maximum frequency is 25 MHz for parallel mode, and
???? MHz for serial mode. The polarity of this signal is programmable.
I
Error in input data. This signal carries the error bit associated with the
channel data type (if set, the byte is corrupted).
I
Data enable. Assertion indicates that data on SDDATA[7:0] is valid.
The polarity of this signal is programmable.
General Purpose I/O [33]
O
Bitstream request. controller asserts SDREQ to indicate that the bitstream
input buffer has available space.
Analog O Video DAC Bias Bits[4:0]
Analog O DAC video output format: R, V, C, or CVBS. Macrovision encoded.
Analog O DAC video output format: B, U, C, or CVBS. Macrovision encoded.
Analog O DAC video output format: G or Y. Macrovision encoded.
Analog O DAC video output format: C. Macrovision encoded.
Analog O DAC video output format: CVBS or Y. Macrovision encoded.
Analog I Video DACs Reference Resistor. Connecting to pin 136 through
a 1.18K+/- 1% resis-tor is required.
I/O
System clock that drives internal PLLs. ZiVA-5 27-MHz TTL oscillator.
(See descrip-tion of VCLK for Digital Video Output.) Also optional video
clock for internal PLLs or external encoder.
O
PCM Data Out. Eight channels. Serial audio samples relative to BCK
and LRCK. General Purpose I/Os [4:1]
O
PCM Bit Clock. BCK can be either 48 or 32 times the sampling frequency
PCM Left Clock. Identifies the channel for each sample. The polarity is
O
programma-ble.
I/O
Audio External Frequency clock input or output. BCK and LRCK are
derived from this clock.
O
PCM data out (IEC-958 format ) or compressed data out
(IEC-1937 format). General Purpose I/O [14]
I
PCM data input.
I
PCM input bit clock.
BYPASS_SYSCLK: Alternate function TBS.
I
PCM left/right clock.
IEC958 input bypass
1-18
TH-A5
(4/4)
Name
IRRX1/GPIO0
Type 1 Description
IR Remote Receive. This input connects to an integrated (photo diode,
I
band pass, demodulator) IR receiver. General Purpose I/O 0
Serial clock signal for IDC data transfer. It should be pulled up to the
I/O
positive supply voltage, depending on the device) using an external
pull-up resistor. General Purpose I/O [18]
Serial data signal for IDC data transfer. It should be pulled up to the supply
voltage using an external pull-up resistor. General Purpose I/O [19]
Ready to send, UART1
O
Receive data, UART1
I
Transmit data, UART1
O
Clear to send, UART1
I
Ready to send, UART2
O
Serial Peripheral Interface Clock
Receive data, UART2
I
Serial Peripheral Interface - Master Input/Slave Output
Transmit data, UART2
O
Serial Peripheral Interface - Master Output/Slave Input
Clear to send, UART2
I
Serial Peripheral Interface ????
Test reset. BST reset - resets the TAP controller.
I
This signal must be pulled low.
Test data Out. BST serial data output.
O
Test data In. BST serial data chain input.
I
General Purpose Input pin 0.
Test mode select. Controls state of test access port (TAP) controller.
I
General Purpose Input pin 1.
Test clock. Boundary scan test (BST) serial data clock.
I
Pin No.
28
IDC_CL/GPIO18
160
IDC_DA/GPIO19
161
RTS1/GPIO20
162
RXD1/GPIO21
163
TXD1/GPIO22
164
CTS1/GPIO23
165
RTS2/SPI_CLK/
GPIO37
185
RXD2/SPI_MISO/
GPIO38
186
TXD2/SPI_MOSI/
GPIO39
187
CTS2/SPI_CS/
GPIO40
188
TRST
197
TDO
TDI/GPI0
198
199
TMS/GPI1
200
TCK
201
JTAG
UART2
UART1
IDC
IR
2. Pin function
3. Block diagram
32-128Mbit
SDRAM
SDRAM Controller
Parallel/serial
DVD Interface
I2S Stereo In
Track Buffer
Processor
Audio
Input Unit
Decryption
ZiVA
A/V Core
Interlaced/
Progressive
Video
Encoder
Graphics
Engine
Five 10-bit
Video
DACs
CCIR 656
Digital Video
Composite
Y/R
C
Cr/Pr/G
Cb/Pb/B
System Control Bus

SPARC
Microprocessor
Audio
Output
Unit
Bus Interface Unit
ASYNC BUS IR
GPIO SPI
Remote Control
UART1&2 ATAPI IDC
Phase
Lock
Loop
IEC 958/1937
Downmix
Left/right
Center/subwoofer
Left/ right/surround
JTAG Interface
13.5 MHz Crystal
1-19
TH-A5
A1,SCDIN
RD,R/W,EMOE,GPIO11
WR,DS,EMWR,GPIO10
AUDATA3,XMT958
DGND1
VD1
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
CS493292 (DIC11) : Audio decoder

1. Pin layout
6 5 4 3 2 1 44 43 42 41 40
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ,LRCLKN2
CS
SCDIO,SCDOUT,PSEL,GPIO9
ABOOT,INTERQ
EXTMEM,GPIO8
SDATAN1
VD3
DGND3
SCLKN1,STCCLK2
LRCLKN1
CMPDAT,SDATAN2,RCV958
CMPCLK,SCLKN2
A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,ENAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
VD2
DGND2
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
2. Block diagram
SCDIO
RD
WR
DATA7:0
R/W
DS SCDOUT
A0
EMAD7:0
EMOE EMWR PSEL
GPIO7:0 CS GPIO11 GPIO10 GPIO9 SCCLK
CMPDAT
SDATAN2
CMPCLK
SCLKN2
Compressed
Data Input
Interface
CMPREQ
LRCLKN2
Framer
Shifter
SCLKN1
STCCLK2
Input
Buffer
Controller
LRCLKN1
SDATAN1
CLKIN
CLKSEL
Digital
Audio
Input
Interface
PLL
Clock Manager
FILT1 FILT2 VA
1-20
AGND
A1
ABOOT EXTMEM
SCDIN INTERQ GPIO8
Parallel or Serial Host Interface
DC
DD
24-Bit
DPS Processing
MCLK
RAM
Program
Memory
RAM
Data
Memory
ROM
Program
Memory
ROM
Data
Memory
RAM Input
Buffer
STC
DGND[3:1]
VD[3:1]
SCLK
RAM
Output
Buffer
Output
Formatter
RESET
LRCLK
AUDATA[2.0]
XMT958
/AUDATA3
TH-A5
3. Pin function
Pin No.
1,12,23
2,13,24
3
4
Symbol
VD1,VD2,VD3
DGND1,DGND2,DGND3
AUDATA3,XMT958
WR,DS,EMWR,GPIO10
RD,R/W,EMOE,GPIO11
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A1,SCDIN
A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,ENAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
CS
SCDIO,SCDOUT,PSEL,GPIO9
ABOOT,INTERQ
EXTMEM,GPIO8
SDATAN1
SCLKN1,STCCLK2
LRCLKN1
CMPDAT,SDATAN2
CMPCLK,SCLKN2
CMPREQ,LRCLKM2
CLKIN
CLKSEL
FILT1
TILT2
VA
AGND
RESET
DC
DD
AUDATA2
AUDATA1
AUDATA0
LRCLK
SCLK
MCLK
Function
Digital Positive Supply
Digital Supply Ground
SPDIF Transmitter Output, Digital Audio Output 3
Host write strobe or Host data strobe or External Memory write enable or
General purpose input& output Number 10
Host Parallel Output Enable or Host Parallel R/W or External Memory Output
Enable or General Purpose Input & Output Number11
Host Address Bit One or SPI Serial Control Data Input
Host Parallel Address Bit Zero or Serial Control Port Clock
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Host Parallel Chip Select, Host Serial SPI Chip Select
Serial Control Port Data Input and Output, Parallel Port Type Select
Control Port Interrupt Request, Automatic Boot Enable
External Memory Chip Select or General Purpose Input & Output Number 8
PCM Audio Data Input Number One
PCM Audio Input Bit Clock
PCM Audio Input Sample Rata Clock
PCM Audio Data Input Number Tow
PCM Audio Input bit Clock
PCM Audio Input Sample Rate Clock
Master Clock Input
DSP Clock Select
Phase Locked Loop Filter
Phase-Locked Loop Filter
Analog Positive Supply
Analog Supply Ground
Master Reset Input
Reserved
Reserved
Digital Audio Output 2
Audio Output Sample Rate Clock
Audio Output Bit Clock
Audio Master Clock
BA4560 (IC2, IC5, IC6, IC7, CIC11, CIC13, FIC2, FIC4, FIC5, FIC6, FIC11, RIC11, RIC13)
: Dual op amp.
1.Pin layout
OUT1 1
IN1 2
1ch
+ IN1 3
VEE 4
VCC
OUT2
IN2
+ IN2
+
2ch
1-21
TH-A5
SP3721A (U7) : DVD driver
1.Pin layout
64 ~ 49
48
16
33
17
~ 32
2.Pin function
Symbol
1
DVDRFP
2
DVDRFN
3,4 PD1,PD2
5~6
A2,B2
7~ 8
C2,D2
9
CP
Pin No.
10
CN
(1/2)
I/O
Function
I RF Signal Inputs. Differential RF signal attenuator input pins.
I
I
I/O
I/O
11~14 A,B,C,D
15~16
E,F
17
CDTE
18
VCI2
19
NC
20
VNB
21
DVDPD
22
DVDLD
23
CDPD
24
CDLD
25
LDON#
I
I
O
I
O
I
1-22
26
VC
27
28
29
30
VCI
VPB
MIRR
MP
O
-
31
MB
32
FDCHG#
33
MLPF
CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs.
Photo Detector Interface Inputs. AC coupled inputs for the DPD from
the main beam Photo detector matrix outputs.
Differential Phase tracking LPF pin. An external capacitance is
connected between this pin and the CN pin.
Differential Phase tracking LPF pin. An external capacitance is
connected between this pin and the CP pin.
Photo Detector Interface Inputs. Inputs from the main beam Photo
detector matrix outputs.
CD tracking Error Inputs. Inputs from the CD photo detector error outputs.
CD Tracking. E-F Opamp output for feedback.
Reference Voltage input. DC bias voltage input for the servo input reference.
No Connect.
Ground. Ground pin for the servo block.
APC Input. DVD APC input pin from the monitor photo diode.
APC output. DVD APC output pin to control the laser power.
APC Input. DVD APC input pin from the monitor photo diode.
APC output. DVD APC output pin to control the laser power.
APC output. on/off. APC output control pin. A low level activates the
LD output. (open high)
Reference Voltage output. This pin provides the internal DC bias
reference voltage (+2.5+ fix). Output impedance is less than 50 ohms.
Reference Voltage input. DC bias voltage input for the servo input reference.
Power. Power supply pin for the servo block.
Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output.
MIRR signal Peak hold pin. An external capacitance is connected to
between this pin and VPB.
MIRR signal Bottom hold pin. An external capacitance is connected to
Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches.
A low level activates the switches and the falling edge of the internal FDCHG triggers
the fast decay for the NIRR bottom hold circuit. (open high)
MIRR signal LPF pin. An external capacitance is connected between this pin and VPB.
TH-A5
2.Pin function
34
35
Symbol
MEVO
MIN
36
PI
37
DFT
38
39
TPH
MEV
40
41
42
43
44
MEI
TE
FE
CE
LCN
45
LCP
46
SCLK
47
SDATA
48
SDEN
49
HOLD1
50
51
52
53
VNA
FNN
FNP
DIP
54
DIN
55
RX
56
57
58
59
60
61
62
63
64
BYP
SIGO
VPA
AIP
AIN
ATON
ATOP
CDRF
CDRFDC
Pin No.
(2/2)
Function
I/O
O SIGO Bottom Envelope Output. Bottom envelope for Mirror detection.
I RF signal Input for Mirror. AC coupled inputs for the mirror detection
circuit from the pull-in signal output. (PI)
O Pull-in Signal Output. The summing signal output of A,B,C,D or PD1,
PD2 for mirror detection. Reference to VCI.
O Defect Output. Pseudo CMOS output. When a defect is detected, the
DFT output goes high. Also the servo AGC output can be monitored at
this pin, When CAR bits 7-4 are '0011'.
- PI Top Hold pin. An external capacitance is connected between this pin and VPB.
- SIGO Bottom Envelope pin. An external capacitance is connected
I Mirror Envelope Input. The SIGO envelope input pin.
O Tracking Error Signal Output. Tracking error output reference to VCI.
O Focusing Error Signal Output. Focus error output reference to VCI.
O Center Error Signal Output. Center error out put reference to VCI.
- Center Error LPF pin. An external capacitance is connected between
this pin and the LCP pin.
- Center Error LPF pin. An external capacitance is connected between
this pin and the LCN pin.
I Serial Clock. Serial Clock CMOS input. The clock applied to this pin
is synchronized with the data applied to SDATA. (Not to be left open).
I/O Serial Data. Serial data bi-directional CMOS pin. NRZ programming
data for the internal registers is applied to this input. (Not to be left open)
I Serial Data Enable. Serial enable CMOS input. A high level input
enables the serial port. (Not to be left open)
I Hold Control. ATTL compatible control pin which, when pulled high, disables the RF AFC
charge pump and holds the RE AGC amplifier gain at its present value. (open high)
- Ground. Ground pin for the RF block and serial port.
O Differential Normal Output. Filter normal outputs.
O Differential Normal Output. Filter normal outputs.
I Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended
output buffer and full wave rectifier.
I Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended
output buffer and full wave rectifier.
- Reference Resistor Input. An external 8.2 kohm, 1% resistor is
connected from this pin to ground to establish a precise PTAT
(proportional to absolute temperature) reference current for the filter.
I/O The RF AGC integration capacitor CBYP, is connected between BYP and VPA.
O Single Ended Normal Output. SIngle-ended RF output.
- Power. Power supply pin for the RF block and serial port.
I AGC Amplifier Inputs. Differential AGC amplifier input pins.
I AGC Amplifier Inputs. Differential AGC amplifier input pins.
O Differential Attenuator Output. Attenuator outputs.
O Differential Attenuator Output. Attenuator outputs.
I RF Signal Input. Single-ended RF signal attenuator input pin.
O CD RF Signal Output. Single ended CD RF summing output.
1-23
TH-A5
W986432DH (U5) : SDRAM
VSS
44
43
VCC
VSSQ
DQ24
45
42
DQ25
DQ23
46
41
DQ26
VCCQ
47
40
VCCQ
DQ22
48
39
DQ27
DQ21
49
38
50
37
DQ20
VSSQ
VSSQ
DQ28
51
36
DQ29
DQ19
52
35
DQ30
VCCQ
53
34
VCCQ
DQ18
54
33
DQ31
DQ17
55
32
NC
VSSQ
56
31
VSS
DQ16
57
30
DQM3
NC
58
29
A3
VCC
59
28
A4
DQM2
60
27
A5
A2
61
26
A6
A1
62
25
A7
A0
63
24
A8
A10/AP
64
23
A9
BS1
65
22
CKE
BS0
66
21
CLK
NC
67
20
NC
CS
68
19
RAS
NC
18
69
70
17
WE
CAS
VSS
DQM1
71
16
DQM0
NC
15
VCC
72
DQ8
14
73
VCCQ
NC
74
13
DQ9
DQ7
75
12
76
11
DQ6
VSSQ
VSSQ
DQ10
77
10
DQ11
DQ5
78
9
DQ12
VCCQ
79
8
VCCQ
DQ4
80
7
DQ13
DQ3
81
6
QDQ14
VSSQ
82
5
VSS
DQ2
83
4
DQ15
DQ1
84
3
VCCQ
85
2
DQ0
86
1
VCC
Vss
1. Pin layout
2. Block diagram
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
GENERATOR
COMMAND
CAS
DECODER
COLUMN DECODER
A10
MODE
REGISTER
A0
A9
BS0
BS1
CELL ARRAY
BANK #0
COLUMN DECODER
ROW DECODER
ROW DECODER
WE
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ31
COLUMN
COUNTER
DQM0~3
COLUMN DECODER
Symbol
A0-A10
BS0, BS1
DQ0-DQ31
CS
RAS
CAS
WE
DQM0-DQM3
CLK
CKE
VCC
VSS
VCCQ
VSSQ
NC
1-24
Function
Address
Bank Select
Data Input/Output
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Input/output mask
Clock Inputs
Clock Enable
Power(+3.3V)
Ground
Power(+3.3V) for I/O buffer
Ground for I/O buffer
No Connection
ROW DECODER
3. Pin function
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
ROW DECODER
REFRESH
COUNTER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
TH-A5
LC86P6548 (UIC1) : Microcontroller
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
VP
1.Pin layout
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
P16/BUZ
P17/PWM0
P30
P31
P32
P33
P34
P35
P36
P37
P70/INT0
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P71/INT1
P72/INT2/T0I
P72/INT3/T0I
S0/T0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
2.Block diagram
Interrupt Control
IR
Standby Control
RC
A15-A0
D7-D0
TA
CE
OE
DASEC
PROM
Control
Clock
Generator
CF
PLA
PROM(48KB)
X tal
PC
BaseTimer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 3
C Register
Timer 0
Port 7
ALU
Timer 1
Port 8
ADC
PSW
INT0-3
Noise Filt er
RAR
SIO Automatic
transmission
RAM
RAM
128 bytes
Stack Poi nter
Port 0
VFD
Controller
Watchdog Timer
High voltage Output
1-25
TH-A5
M11B416256A (U1) : DRAM
2. Pin function
1. Pin layout
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
Vss
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Symbol
Pin No.
A0~A10
16~19,22~26
RAS
14
CASH
28
CASL
29
WE
13
OE
27
2~5,7~10,31~34,36~39 I/O0~I/O15
Vcc
1,6,20
Vss
21,35,40
NC
11,12,15,30
I/O
I
I
I
I
I
I
I/O
Supply
Ground
-
Function
Address Input
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Input/ Output
Power, 5V
Ground
No Connect
3. Block diagram
WE
CASL
CASH
CAS
CONTROL
LOGIC
DATA-IN BUFFER
16
NO.2 CLOCK
GENERATOR
A0
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
512
A1
A2
REFRESH
CONTROLLER
A3
DATA-OUT
BUFFER
16
SENSE AMPLIFIERS
I/O RATING
A4
A5
512 x 16
A7
A8
RAS
1-26
ROW
ADDRESS
BUFFERS(9)
NO.1 CLOCK
GENERATOR
ROW
DECODER
REFRESH
COUNTER
A6
512
512 x 512 x 16
MEMORY
ARRAY
Vcc
Vss
I/O0
..
I/O15
CE
TH-A5
M6759 (U3) : MTP microcontroller
2. Pin function
24
11
23
22
25
10
21
26
20
27
19
28
18
29
17
30
16
31
15
32
14
33
13
12
Pin No.
Symbol I/O
Description
44
VDD
I Power supply for internal operation, 5V input
22
GND
I Ground
36,37,38,39, P0.7-P0.0 I/O 8 bits bi-directional I/O port
40,41,42,43,
AD7-0
I/O Multiplexed address/data bus
10
RST
I Reset signal
21
XTAL1
I Crystal In
20
XTAL2
O Crystal out
32
/PSEN
O Program Store Enable Output
33
ALE
O Address Latch Enable
9,8,7,6,
P1.7-P1.0 I/O 8 bits bi-directional I/O port
5,4,3,2
T2EX(P1.1) I External timer/counter 2 trigger
T2(P1.0)
I External timer/counter 2.
31,30,29,28,
P2.7
I/O 8 bits bi-directional I/O port
27,26,25,24
A15-A8
O
19,18,17,16, P3.7-P3.0 I/O 8-bit bi-directional I/O port
15,14,13,11 /RD(P3.7) O External data memory read strobe
/WR(P3.6) O External data memory write strobe
T1(P3.5)
I External timer/counter 1
T0(P3.4)
I External timer/counter .
/INT1(P3.3) I External interrupt 1 (Negative Edge Detect)
/INT0(P3.2) I External interrupt 0 (Negative Edge Detect)
TXD(P3.1) O Serial port output
RXD(P3.0) I Serial port input
35
/EAVPP
I
1,12,23,34
NC
-
34
35
36
37
38
39
40
41
42
43
44
1. Pin layout
3. Block diagram
P0.7:0
P2.7:0
P1.7:0
P3.7:0
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
Port Latch
Port Latch
Serial Port
Timer
Interrupt Logic
Port Latch
Data Bus
Data Bus
ACC
B Register
Program Address
Register
Data Bus
ALU REG1
64K bytes
MTP Memory
ALU REG2
PSW
ALU
Program Counter
Incrementer
Stack
Pointer
Data Bus
Buffer
DPTR
512 Bytes
RAM
RAM Addr.
Register
OSC
Instruction
Register
Clock and Control
RST
/EAVPP
ALE
/PSEN
XTAL2
XTAL1
1-27
TH-A5
SST39VF800A (U6) : 8M Flash memory
1. Pin layout
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
Vss
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
2. Block diagram
EEPROM
Cell Array
X-Decoder
Memory Address
Address Buffer & Latches

Y-Decoder
CE#
OE#
WE#
Control Logic
I/O Buffers & Data Latches

DQ15-DQ0
3. Pin function
Symbol
AMS- A0
Pin name
Address Inputs
Vss
NC
Ground
No Connection
Function
To provide memory addresses. During Sector-Erase AMS-A11 address lines will

select the sector. During Block-Erase AMS-A15 address lines will select the block.
DQ15- DQ0 Data Input/Output To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is
high.
To activate the device when CE# is low.
CE#
Chip Enable
OE#
Output Enable To gate the data output buffers.
To control the Write operations.
WE#
Write Enable
VDD
Power Supply To provide power supply voltage: 2.7-3.6V
1-28
Unconnected pins.
TH-A5
LC75725E (UIC10) : VFD driver
1. Pin layout
I
O
61
BLK
63
64
62
CL
DI
CE
2-12
56-14
G1-G11
S1-S43
O
O
S1
LATCH
GRID
CONTROL
DIMMRE
TIMING
GENERATOR
SHIFT REGISTER
TIMING
GENERATOR
DRIVER
ADDRESS
DETECTOR
VDD
CLOCK
GENERATOR
Vss
OSCI
DI
VFL
VDD
Vss
OSCI
OSCO
S2
VFL
Function
I/O
1,13
60
57
59
58
S42
S43
G1
G2
MPX
BLK
OSCO
3. Pin function
Pin No. Symbol
SEGMENT DRIVER
DIGIT
DRIVER
CE
VFL
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
VFL
S43
S42
S41
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
CL
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S8
S7
S6
S5
S4
S3
S2
S1
Vss
OSCO
OSCI
VDD
BLK
CE
CL
DI
G10
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
G11
2. Block diagram
Driver block power supply connection. (Both pins must be connected.)

Logic block power supply connection. Provide a voltage between 4.5 and 5.5V.
Power supply connection. Connect to the ground.
Oscillator connection. An oscillator circuit is formed by connecting an external resistor
and capacitor to these pins.
Display off contort input.
BLK = Low (Vss)...Display off.(S1 toS43 and G1 to G11 at VFL level.)
BLK = High (VDD)...Display on.
Note that serial data can be transferred while the display is turned off.
Serial data transfer inputs. These pins must be connected to the system microcontroller.
CL: Synchronization clock
DI: Transfer data
CE: Chip enable
Digit outputs. These pins are P-channel open drain outputs with pull-down resistors.
Segment outputs for displaying the display data transferred by serial data input. These pin
are P-channel open drain outputs with pull-down resistors.
W27L010 (DIC21) : EPROM

1. Pin layout
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2. Block diagram
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
PGM
CE
OE
CONTROL
3. Pin function
OUTPUT
BUFFER
A0
DECODER
A16
CORE
ARRAY
Q0
Q7
Symbol
A0~A16
Q0~Q7
CE
OE
PGM
VPP
Vcc
GND
NC
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No connection
Vcc
GND
VPP
1-29
TH-A5
74VHCT244A (DIC12) : Buffer/Line driver

1. Pin layout
2. Pin function
OE1 1
20 Vcc
I0 2
19 OE2
O4 3
18 O0
I1 4
17 I4
O5 5
16 O1
I2 6
15 I5
O6 7
14 O2
I3 8
13 I6
O7 9
12 O3
GND10
11 I7
Symbol
OE1,OE2
I0-I7
O0-O7
Function
3-STATE Output Enable Inputs
Inputs
3-STATE Outputs
3. Truth table
Inputs
OE1
L
L
H
Outputs
(Pins12,14,16,18)
In
L
H
X
L
H
Z
Inputs
OE2
L
L
H
Outputs
(Pins3,5,7,9)
In
L
H
X
L
H
Z

L:LOW Voltage Level
I:Immaterial
Z:High Impedance
74LVT573 (U10, U11, U12) : Latch

1. Pin layout
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
2. Pin function
20
19
18
17
16
15
14
13
12
11
Symbol
D0-D7
LE
OE
O0-O7
Vcc
O0
O1
O2
O3
O4
O5
O6
O7
LE
3. Truth table
Function
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
1. Pin layout
2. Truth table
ENABLE
20
G
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
B7
13
12
B8
11
Control
Inputs
G
L
L
H
DIR
L
H
X
H=HIGH Level
L=LOW Level
X=Irrelevant
1-30
DIR
A1
A2
A3
5
A4
6
A5
LE
X
H
H
L
OE
H
L
L
L
Outputs
Dn
X
L
H
X
On
Z
L
H
O0

L:LOW Voltage Level
Z:High Impedance
X:Immaterial
O0:Previous O0 before HIGH to LOW transition of Latch Enable
MM74HCT245 (U15) : Transceiver
Vcc
Inputs
7
A6
10
A7
A8
GND
Operation
245
B data to A bus
A data to B bus
isolation
TH-A5
CS8415A (DIC14) : Digital audio receiver

1. Pin layout
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
RXP1
RXP2
RXP3
2. Pin function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCL/CCLK
AD1/CDIN
RXP6
RXP5
H/S
VD+
DGND
OMCK
U
INT
SDOUT
OLRCK
OSCLK
RXP4
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12,13
14,15
25,26
16
17
18
19
20
21
22
23
24
27
28
Symbol
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
RMCK
RERR
RXP1,RXP2
RXP3,RXP4
RXP5,RXP6
OSCLK
OLRCK
SDOUT
INT
U
OMCK
DGND
VD+
H/S
AD1/CDIN
SCL/CCLK
I/O
I/O
I/O
O
I
Function
Serial Control Data I/O(I2C) / Data Out(SPI)
Address Bit 0(I2C) / Control Port Chip Select(SPI)
Pre-Emphasis
AES3/SPDIF Receiver Power
I
I
O
O
I/O
O
I
Positive Analog Power

Analog Ground
PLL Loop Filter
Reset
Input Section Recovered Master Clock
Receiver Error
Additional AES3/SPDIF Receiver Port
I/O
I/O
O
O
O
I
I
I
I
I
I
Serial Audio Output Bit Clock

Serial Audio Output Left/Right Clock
Serial Audio Output Data
Interrupt
User Data
System Clock
Digital Ground
Positive Digital Power
Hardware/Sofrware Mode Control
Address Bit 1(I2C) / serial Control Data in (SPI)
Control Port Clock
3. Block diagram
VA+ AGND FILT
RSN0
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
RERR
Clock &
Data
Recovery
Receiver
7:1
MUX
RST
AES
S/PDIF
Decoder
DGND
OMCK
Serial
Audio
Output
C&U bit
Data
Buffer
OLRCK
OSCLK
SDOUT
Control
Port &
Registers
Misc.
Control
H/S
VD+
RMCK
EMPH U
SCL/ AD1/
SDA/
CDOUT CCLK CDIN
AD0/
CS
INT
1-31
TH-A5
FAN8082 (U10) : DC motor driver

2. Block diagram
1.Pin layout
GND
VO2
VO1
PVCC
GND
VO1
DRIVER OUT
VO2
PVCC
SVCC
VIN2
PRE DRIVER
VCTL
SVCC
VIN1
VIN2
VCTL
VIN1
TSD
BIAS
LOGIC SWITCH
3. Pin function
Pin No.
Symbol
I/O
Function
GND
VO1
Ground
Output 1
VCTL
Motor speed control
VIN1
Input 1
VIN2
Input 2
SVCC
Supply voltage (Signal)
PVCC
Supply voltage (Power)
VO2
Output 2
KA78R05 (PQ2,PQ6)/ KA78R08 (PQ5)/ KA278R05 (PQ1)/ KA278R33 (PQ4) : Regulator

1. Block diagram
Vin
Q1
THERMAL SHUTDOWN
BANDGAP REFERENCE
OVERVOLTAGE
PROTECTION
+
R1
SOA PROTECTION
HIGH / LOW
Vdis
1.4V
OUTPUT
ON / OFF
SHORT-CIRCUIT
SHORTCIRCUIT
PROTECTION
3
GND
1-32
R2
Vo
TH-A5
CS4228A (DIC15) : D/A converter
1. Pin layout
2. Pin function
Pin No.
SDIN3
SDIN2
SDIN1
SDOUT
SCLK
LRCK
DGND
VD
VL
MCLK
SCL/CCLK
SDA/CDIN
AD0/CS
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SUB
CENTER
SR
SL
FR
FL
AGND
VA
AINL+
AINLFILT
AINRAINR+
MUTEC
1,2,3
4
5
6
7
8
9
10
11
12
13
14
15
16,17
19,20
18
21
22
23,24,25
26,27,28
Symbol
Function
SDIN1
SDIN2
SDIN3
SDOUT
SCLK
LRCK
DGND
VD
VL
MCLK
SCL/CCLK
SDA/CDIN
ADO/CS
RST
MUTEC
AINR+,AINRAINL+,AINLFILT
VA
AGND
FR,FL,SR,SL
SUB,CENTER
Serial Audio Data In

Serial Audio Data Out
Serial Clock
Left/Right Clock
Digital Ground
Digital Power
Digital Interface Power
Master Clock
Serial Control Interface Clock
Serial Control Data I/O
Address Bit 0/ Chip Select
Reset
Mute Control
Differential Analog Inputs
Internal Voltage Filter
Analog Power
Analog Ground
Analog Outputs
74LCX244 (DIC13) : Bus buffer

1. Pin layout
2. Pin function
1G 1
20 Vcc
1A1 2
19 2G
2Y4 3
18 1Y1
1A2 4
17 2A4
2Y3 5
16 1Y2
1A3 6
15 2A3
2Y2 7
14 1Y3
1A4 8
13 2A2
2Y1 9
12 1Y4
GND10
11 2A1
Pin No.
Symbol
1
2,4,6,8
9,7,5,3
11,13,15
17
18,16,14
12
19
10
20
1G
1A1 to 1A4
2Y1 to 2Y4
2A1 to 2A4
Output Enable Input

Data Inputs
Data Outputs
Data Inputs
1Y1 to 1Y4
Data Outputs
2G
GND
Vcc
Function
Outputs Enable Input

Ground(0V)
Positive Supply Voltage
3. Truth table
INPUT
G
L
L
H
An
L
H
X
OUTPUT
Yn
L
H
Z
X:"H"or"L"
Z:High impedance
1-33
TH-A5
VICTOR COMPANY OF JAPAN, LIMITED

AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
(No.21062)
200201(V)

TH-A5#SML1 Service Manual

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TH-A5

DVD DIGITAL CINEMA SYSTEM TH-A5

2002 VICTOR COMPANY OF JAPAN, LTD.

Important for laser products

5.CAUTION : If safety switches malfunction, the laser is able

the complete Laser Unit if it malfunctions.

whichprevent emission of radiation when the drawer is

Please use enough caution not to

feated. It is dangerous to defeat the safety switches.

REPRODUCTION AND POSITION OF LABELS

Preventing static electricity

2-1 Ground the workbench

2-2 Ground yourself

3. Handling the optical pickup

4.Handling the traverse unit (optical pickup)

Attention when traverse unit is decomposed

DVD mechanism assembly (bottom side)

DVD loader board

(These two points are

1. Remove the four screws A attaching the top cover

3. Remove the top cover from behind in the direction of

Removing the front panel assembly

Front panel assembly

Prior to performing the following procedure, remove

3. Remove the two screws D attaching the front panel

4. Remove the claw1, claw2 and claw3, and detach the

Claw2 (both side)

5. Disconnect the card wire from the connector DW20

Removing the power cord

Prior to performing the following procedure, remove

1. Disconnect the power cord from the connector CW1

(fixing the earth wire)

Notes : The power cord is exchangeable.

Front panel assembly

Removing the DVD mechanism assembly

DVD mechanism assembly

Prior to performing the following procedure, remove

1. Disconnect the card wire from the connector J14 and

2. Remove the two screws E attaching the DVD

Removing the rear panel (See Fig.7 and 8)

1. Disconnect the harness from the connector NW11 on

2. Remove the two screws F, four screws G, five

Removing the tuner pack (See Fig.7 and 8)

Prior to performing the following procedure, remove

1. Disconnect the card wire from the connector CON01

Removing the jack board (See Fig.7 and 8)

3. Disconnect the connector VW1 on the jack board

Removing the fan motor (See Fig.7 and 8)

Prior to performing the following procedures, remove

VW12 Harness band

Prior to performing the following procedure, remove

1. Untied the harness band and disconnect the harness

3. Disconnect the card wire from the connector VW12

(Rear panel side)

(Front panel side)

2. Disconnect the harness from the connector NW11 on

Removing the main board

Prior to performing the following procedure, remove

2. Disconnect the harness from the connector CW3 on

CW3 Power ICs

Removing the power transistor & power IC

Removing the power transformer

Prior to performing the following procedure, remove