CS 201

COMPUTER ORGANIZATION
Assignment -4

1. Consider a small and somewhat impractical CPU. It can access 64 bytes of memory, each byte
being 8 bits wide. The CPU does this by outputting a 6-bit address on its output pins A[5..0] and
reading in the 8-bit value from memory on its inputs D[7..0]. This CPU will have only one
programmer-accessible register, an 8-bit accumulator labeled AC. The CPU has a 6-bit address
register, AR, which supplies an address to memory via A[5..0], a 6-bit program counter, PC,
which contains the address of the next instruction to be executed, an 8-bit data register, DR,
which receives instructions and data from memory via D[7..0], a 2-bit instruction register, IR,
which stores the opcode portion of the instruction code fetched from memory. The CPU has the
following instruction set and state diagram. Show the RTL code for the execute cycles for each
instruction.
Table I

Figure 1.

2. Consider the same CPU as in problem 1. Suppose that the CPU has the state diagram as shown in
figure 2 and the following RTL code. Show the instruction set for this CPU. Design a hardwired
control unit for this CPU.

Figure 2.

3. The control unit shown in figure 3 is supposed to have the state diagram as shown in figure 3. But
it is not having. Draw the correct state diagram of the control unit.

Figure 3.

4. Modify the controller design of figure 3 so that it realizes the state diagram of figure 3.

5. Consider the CPU design in problem 1. We wish to introduce a new instruction CLR which clears
the accumulator (i.e. AC
0). The instruction code for CLEAR is 111XXXXX. The new
instruction code for INC is 110X XXXX; all other instruction codes remain unchanged. Show the
new state diagram and RTL code for this CPU. Show the modification needed in the registers.
Show the design of the control unit.