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UEEA2333

Analogue Electronics
Topic 2a

Op-amp

Topics
Determine the effect of finite loop gain, finite input resistance
and non-zero output resistance of an op-amp
Describe the various practical parameters of an op-amp
Determine the effect of an op-amps slew rate on the input
signal
Calculate the unity gain bandwidth, CMRR and PSRR of an
op-amp
Describe the operation of DAC and ADC
[Reference]
Donald A. Neamen, (2007), Microelectronics Circuit
Analysis and Design, 3rd Edition, McGraw-Hill. ISBN10:007-125443-9. Chapter 14.
Muhammad H. Rashid, (1999), Microelectronic Circuits:
Analysis and Design, PWS Publishing Company, ISBN
053495174-0. Chapter 7.

PART 1

Electronics
Electronics

Analog Electronics

Digital Electronics

Op-amps , Transistors , Circuits


- Power supply
- Regulator
- Filter
- Clock
- Oscillator
- Converter

Boolean , Logic , Gates , States


- Microprocessor
- Microcontroller
- Mobile phone
- Calculator
- Digital watch
- CD player

Ideal Op-Amp Equivalent Circuit


1 Inverting terminal
2 Non-inverting terminal
3 Output terminal

Advantages of op-amps :
- Simple linear input-output characteristics (i.e. AO)
- Achieve near perfect operations (see loading effect)
- Isolate input from output (and vice versa).

Observations
1.
2.
3.
4.

Ideally, the open-loop differential gain is infinite, Ao=


The output resistance is zero, Ro = 0
The input resistance is infinite, Ri =
The input current at each input terminal is ii = 0

Amplifier Design Configurations


Op-amp
Open loop

Comparator

Closed loop

Inverting

Summer

Non-inverting

Difference

Buffer
Instrumentation
Voltage follower
amplifier
Isolation amplifier
7

Inverting Op-Amp
Use Virtual Short or Ground to
solve circuit problems

Noninverting Op-Amp
vO = (1 + R2 /R1)vI
(Try it!)

Voltage Follower (loading effect)

RL
vO
vI
RL RS
The output voltage level is
reduced by a ratio related to RS

vO vI
The load voltage is close to the
ideal input source vI. This is so
for noninverting amplifier.
10

Op-Amps Internal Circuit


Real op-amp consists of:
(1) Differential Stage
- High input resistance and voltage gain.
(2) Amplification Stage
- Voltage gain
(3) Output Stage
- Low output resistance
11

JFET Op-Amp
LF411

Cc is designed to
stabilize the opamp (see chapter
on Stability).

12

BJT Op-Amp
LM324

13

Practical Op-Amps Parameters

Parameters of a practical op-amp differ from


the ideal characteristics due to
(1) Biasing currents
(2) Transistor mismatch
(3) Changes in operation points due to dc
supply changes
(4) Temperature effects

14

Typical Op-Amp Parameters and Values

15

PART 2

16

Practical Op-Amp Model

17

Input Voltage Limits, VI(max)


All voltages inside the circuit cannot exceed the
supply voltage ranges limits: [VCC, VEE].
e.g. A741, input voltage = 15V with a supply
voltage = 18V. Then, the differential input voltage,
vd = 30 V.

18

Output Voltage Limits, VO(max)


Op-amps operate linearly over a limited range of
output voltage
Output saturates within 1V or so of the positive and
negative dc supply i.e. maximum output voltage is
less than the dc supply voltage by about 1V.
e.g. an op-amp operating from 15 V supplies will
saturate when the output voltage reaches about +13 V
or -13 V. The rated output voltage VO(max) is said to be
13V.
Clipping of output waveform occurs when the op-amp
tries to output voltages exceeding these limits.
19

Example :

If input signal is 1.5 V peak, output signal should be


15 V peak, but is clipped at 13 V peak because of
output saturation.
20

Output Current Limits, IO(max)


Output current is limited to a specified maximum e.g.
for 741 op-amp is 20 mA
If an op-amp is forced to supply a total output current
(including currents in feedback circuit) of more than
the limit, it may damage/burn up/not keep up
It is better to choose big feedback resistance to reduce
the current sourcing/sinking from/at the op-amps
output. But too big a resistance will induce stray
capacitive effect. Thus, typical range from 1 to 10s
k is desired.
21

Open-Loop Voltage Gain, Ao


The open-loop voltage gain Ao is the differential
voltage gain of the op-amp (without external
components).

Ao vo / vd
For practical op-amps, the openloop gain is finite. Furthermore,
its value depends on the
frequency of operation, f (see
later on Frequency Response).
22

Effects on Closed-loop Gain, ACL


Inverting Amplifier

ACL

ACLO
1
R2
1
(1 )
AOL
R1

(assume Ri , f 0)

Noninverting Amplifier

where ACLO

R2
R for inverting amp
1
R
1 2 for noninverti ng
R1
23

Details of derivation for the inverting amplifier (Ri = , f = 0)


vI v1 v1 vO

R1
R2
1
vI
1 vO

v1
R1
R1 R2 R2
Since v2 0, vO AOLv1
vO 1
vI
1 vO



R1
AOL R1 R2 R2

R2
vO
R1
ACL

vI 1 1 (1 R2 )
AOL
R1
Note: as AOL , ACL ideal value

24

Details of derivation for the noninverting Amplifier (Ri = , f = 0)


v1 v1 vO

R1
R2
1
vO
1

v1
R2
R1 R2
Since vO AOL (v2 v1 ) and vI v2
v1 vI

vO
AOL

R2
1
vO
R1
ACL

vI 1 1 (1 R2 )
AOL
R1
Note: as AOL , ACL ideal value
25

Example:
A pressure transducer produces a maximum dc voltage signal of 2 mV and has an
output resistance of RS = 2 k. The maximum dc current from the transducer is
to be limited to 0.2 A. An inverting amplifier is used in conjunction with the
transducer to produce an output voltage of -0.10 V for a 2-mV transducer signal.
The error in the output voltage cannot be greater than 0.1%. Determine the
minimum open-loop gain of the amplifier to meet this specification.
R2

Rin = R1 + RS = R1 + 2k
R1
Rin(min) = vi / ii(max) = 2m / 0.2 = 10 k
RS
R1 = 8 k (minimize stray capacitive effect)
ACL = vo / vi = -0.10 / 2m = -50 = -R2 / Rin
R2 = 500 k
For voltage gain to be within 0.1%, minimum gain is 49.95 (magnitude).
R2
Rin
50
ACL
49.95
1
R
51
1
(1 2 )
1
AOL
Rin
AOL
AOL(min) 50.949

26

Effects on Input Resistance

Inverting Amplifier (assume f 0) :

R
1 AOL O
RL
1
i1
1
1

Rif v1 Ri R2 RO RO
1

RL R2

Noninverti ng Amplifier (assume RO 0, f 0) :


Rif

vI

iI

Ri (1 AOL ) R2 (1
1

Ri
)
R1

R2
R1
27

Details of derivation for the inverting amplifier (f = 0):


KCL at output node :
vO vO ( AOLv1 ) vO v1

0
RL
RO
R2
AOL 1

v1

R
R
2
O
vO
1
1
1

RL RO R2
KCL at input node :
v v
v
i1 1 1 O
Ri
R2
Combine :

R
1 AOL O
RL
1
i
1
1
1
Rif v1 Ri R2 RO RO
1

RL R2

Note: Rif Ri as AOL


28

Details of derivation for the noninverting amplifier (f = 0):


KCL at output node :
vO vO AOLvd vO v1

0
RL
RO
R2
v1 AOLvd

R2
RO
vO
1
1
1

RL RO R2
KCL at v1 node :
iI

v1 v1 vO

R1
R2

R
1
R
R R
A v
1 R
iI 1 O O v1{ 1 O O O2 OL d }
R2
RL R2
R1 R2 RL R2 R2
Neglect effect of RO

1
1 A v
iI v1 OL d , vd i1 Ri , and v1 vI iI Ri
R2
R1 R2
R
Ri (1 AOL ) R2 (1 i )
v
R1
So, Rif I
Note: Rif as AOL
R2
iI
1
R1

29

Example :
Consider an inverting amplifier with a feedback resistor R2 = 10
k, and an op-amp with parameters AOL = 105 and Ri = 10 k.
Assume the output resistance RO of the op-amp is negligible.
Determine the closed loop input resistance.
Answer :

RO
1 AOL

RL
1
1
1
1 1 105
4

4

10
10
4
Rif Ri R2 RO RO 10
10
1

R
R
L
2

Rif 0.1

30

Effects on Output Resistance

Inverting & Noninverting Amplifiers (assume Ri = , f = 0):

iO
1
1 AOL

Rof vO RO 1 R2 / R1
31

Details of derivation (assume Ri = , f = 0):


Set input voltages to zero, and do KCL at output node:
iO

vO AOLvd
vO

RO
R1 R2

R1
vO vd
v1
R1 R2
Combining :
vO AOL R1
vO

iO

vO

RO RO R1 R2 R1 R2

RO is normally small and AOL is normally large, so

iO
AOL
1
1

vO RO 1 R2 / R1 R1 R2

iO
AOL
1
1

Rof
vO RO 1 R2 / R1
Note: as RO 0 or AOL , Rof 0
32

PART 3

33

Frequency Response, Ao(f)


At high frequency, internal capacitance
causes the output level to decrease.
So, Ao decreases with f. The system can
be approximated by a single pole:

H ( s)

Bode Plot

s p
/p
/p
H ( j )

1 j p 1 j p /f2
which is written compactly as,

AO
AO ( f )
f
1 j f PD
= f3-dB = fb
with fPD = p/2. See right for graph.
The gain-bandwidth product (GBW) for an op amp is the unity gain bandwidth:
fT fPD AO
(set A0(f)=1 and assume fT >> fPD)
34

Effects on Closed-loop Gain, ACL


Since ACL

ACLO
for both inverting and noninverti ng
1
R
1
(1 2 )
AOL
R1

Substituti ng AO ( f ) into AOL above,


ACLO
ACLO
ACL ( f )

R2
f

(
1

)
1 j

f
R2
R1
R2
f PD

j
(
1

)
1
(1 )
AO
AO
f PD AO
R1
R1

ACLO
R

since typically AO (1 2 )
f
R
R1
1 j
(1 2 )
f PD AO
R1

ACLO

f
1 j
1
f PD AO

1 R2 R1

ACLO
f
j
GBW

1 R2 R1

35

So, the 3 - dB frequency of the closed loop system is,


GBW
f 3dB
... for both invertingand noninverti
ng
R2
1 R1
This 3-dB frequency is also related to the time constant () and
the rise time (tr), as derived below:
* Note that inverse transforming H(s) would give the natural or
impulse response e-pt = e-t/, where p and are related as, p = 1/.
p 2f 3dB 1 /
So, f 3dB

1
2

2.2 0.35

2tr
tr

Note, tr = 2.2 for a single-pole system (from the exp. curve).


* Rise time (tr) is the time required for output value to rise from
the 10% to 90% of the final level (i.e. steady-state value).
36

Gain-Bandwidth Product
For the frequency at unity gain,
ACLO

ACL 1

if ACLO

f unity
1

R
f A /(1 2 )
PD O
R1
1 (i.e. R2 R1 ),
f unity

f PD AO /(1
f unity ACLO

R2
)
R1

ACLO

R2
f PD AO /(1 ) f PD AO fT
R1

( R2 R1 )

The GBWs for the closed-loop and the open-loop systems are identical for the
37
same op-amp.

Example :
An audio amplifier is to use an op-amp with an open-loop gain
of AO = 2 x 105 and a dominant pole frequency of 5 Hz. The
bandwidth of the audio system is to be 20 kHz. Determine the
maximum closed loop gain.
Answer :

fT f PD AO 5(2 105 ) 1 MHz


fT f 3 dB ACLO
ACLO

fT
f 3 dB

106

50
3
20 10

38

PART 4

39

Slew Rate, SR
Causes non-linear distortion of large output signals
If a sharp step input voltage is applied to an op-amp, the output
will not rise as quickly as the input (the reason being that there
are internal capacitances which take time to charge up/down
towards their final voltage levels).
Slew rate (SR) is the maximum rate of change possible at the
output of the op-amp, in V/s

dvo
SR
dt

max

The slew rate depends on the voltage gain, but it is normally


specified at unity gain.
40

Take a unity-gain follower

And the output waveform is


distorted giving a linearly rising
output waveform, due to the slew
rate limitation.

Apply a step input

Note that an op-amp is basically a


single-pole system, which would
output an exponential response for
a step input, provided the slew rate
is not exceeded (i.e. V/ SR). 41

With a unity-gain single-pole op-amp, the rising rate of the output


voltage is limited to an exponential waveform, for a step signal VS,

vO VS 1 et

The maximum rise rate (assume no slew rate yet) is,

dvO d
VS t
t

VS 1 e
e
dt
dt

which gives a maximum value of VS/ (at t = 0).

With a slew rate SR, we need to limit the output rising rate to,
VS/ = SR
VS = SR = SR/p = SR/2f3-dB
= SR/6.286f3-dB
42

Full-Power Bandwidth, fM
Op-amp slew rate limiting can cause non-linear distortion in
sinusoidal waveforms
Consider unity-gain follower with a sinusoidal input voltage,
vO = V sint. The slope of the wave is,

dvO
V cos t
dt
which reaches maximum at t = 0 with a value of V. This
value will push the op-amp to the limit at,
SR = V
43

If V > SR, output waveform will be distorted

44

Full power bandwidth fM is the frequency at which an


output sine waveform with amplitude equals to the
rated output voltage of the op-amp begins to show
distortion due to slew rate limiting.

M VO (max) SR
SR
SR
fM

2VO (max) 6.286VO (max)

For signal amplitude smaller than VO(max), slew rate


distortion occurs at frequencies higher than fM. At
frequency higher than M distortion occurs above

V SR / VO(max)M /
45

Example :
Consider an amplifier with fT = 1 MHz and ACLO = 10.
Assume the op-amp slew rate is SR = 1 V/s and the
desired peak output voltage is VPO = 10 V. Determine
the small-signal bandwidth and the full-power
bandwidth.
Answer :

fT
106
f 3dB

100 kHz
A CLO 10

Convert unit
to V/s

SR
106
fM

15.9 kHz
2VPO 2 10
46

Common-Mode Rejection Ratio


Op-amp is differential amplifier, any signal that is common to both
input terminals should (ideally) not be amplified to the output.
CMRR measures the ability to reject common-mode signals:
Ad
CMRR
Ac

vd/2

Ad
20 log
Ac
CMRR

Advd

vd/2

dB

Differential Mode

ideally.
but the typical value is 100 dB.
vc

Acvc

Common Mode 47

Relationships among Ad, Ac, A1, A2

equivalent

Resolve the input voltages v1 (= v+) and v2 (= v) into two


components: differential voltage vd, and common-mode voltage
vc, where:
v1 v2
vd v1 v2
vc
2
48

We may express vo in terms of a linear combination of v1 and v2:


(compare to a difference amplifier)
vo A1v1 A2 v2
But since:

vd
v1 vc
2

Substituti ng :

vd
v2 vc
2

A1v1 A1 vc d
2

A2 v2 A2 vc d
2

v
v

vo A1v1 A2 v2 A1 vc d A2 vc d
2
2

A1 A2

vd A1 A2 vc
2
Ad vd Ac vc
where
Ad A1 A2 2 differenti al voltage gain

Ac A1 A2 common - mode voltage gain

49

Power Supply Rejection Ratio


If the supply of an op amp changes, its output should ideally not change,
however it typically does. This is because as the power supply voltages
change (e.g. line ripples, drift, spikes, etc.), the biasing currents of the
internal transistors change.
PSRR is the ratio of the change in the supply voltage to the change in
output voltage with the input held at zero,

VCC
PSRR
VO
The ratio may be reversed, and/or may refer to the input (i.e. no fixed
standard):

PSRRRTI

VCC
ACL vO


VI
ASUP vI

VO

VCC

50

PART 5

51

Input Offset Voltage, VOS


Output dc offset voltage VOO is the measured open-loop output
voltage when the input voltage is zero.
Input dc offset voltage VOS is the differential input voltage that
must be applied to an open-loop op-amp to produce a zero
output voltage.

52

VOS is quoted as an absolute value, and it may be positive or


negative (the polarity is unpredictable), and varies with
temperature. Data sheet specifies the maximum value of VOS (e.g.
A741C is 6 mV)
VOS is caused by internal mismatching in the input stage. In
practice, the characteristics of the two input transistors will not be
exactly the same; therefore, the collector biasing currents IC1 and
IC2 will differ. As a result, even without any input voltages, there
could be a differential output voltage, which is amplified in
subsequent stages.
To account for the effect of VOS,
use the circuit model for op-amp
shown on right:

53

To analyze an op-amp circuit to determine the effect of input


offset voltage, replace the op-amp with the model and short
circuit the input signal source.
Inverting and non-inverting amplifier results in the same circuit.
We find that the output voltage could sometimes be large.
e.g. if the closed-loop gain is 200 and the op-amp has 5 mV
VOS, then the output voltage is 1 V.
54

Offset Voltage Compensation

When input signal is large compared to the offset voltage VOS,


then the effect of VOS may be neglected.
Otherwise, in order to compensate or null out its effect, we
may use:
a. An externally connected offset compensation network, or
b. An op-amp with offset-null terminals

55

External Offset Compensation Network

With voltage divider formed by R4 and R5, the potentiometer


R3 is adjusted to cancel out VOS.
As VOS is small, in mV range, normally R5 << R4.
56

But, for noninverting amplifier, the compensation network


affects the voltage gain!
Since R5 << R4, the gain is approximately

R2
Av 1
R1 R5
57

Offset-Null Terminals
Many op-amps include a pair of external offset-null terminals
which can be used to compensate for the offset voltage
By varying the potentiometer R,
the output offset voltage can be
adjusted to zero within a certain
input offset voltage adjustment
range (15mV for the A741 opamp).

58

Example :
Consider a compensation network used for an inverting
amplifier, powered by VCC = 15 V and VEE = 15 V,
R5 = 0.1 k
R4 = 100 k
R3 = 100 k (potentiometer)
Determine the voltage range at VY.
Answer :
Assume the potentiometer arm is connected to VCC.
VY

R5
0.1
VCC
(15) 15 mV
R5 R4
0.1 100

So, the adjustable voltage range is from +15 mV to 15 mV.


59

Input Biasing Current, IB


In practical op-amp, the input bias currents are not
zero (bias currents enter or leave the input terminals,
depending on the type of input transistor) and not the
same value.
For bipolar input stages, the input bias current can be
as high as 10 A, and as low as a few nA. For FET
input stages, may be as low as pA.

60

Input biasing current IB is defined as the average of the base


biasing currents IB1 and IB2

I B1 I B2
IB
2

IB1 = dc current flowing into the noninverting input terminal


IB2 = dc current flowing into the inverting input terminal
IB can be either positive or negative, depending on the design and
type of the input stage.

61

Input Offset Current, IOS


In practice, IB1 IB2, i.e., these currents are not equal because
of internal imbalances within the op-amp circuit.
The input offset current IOS is defined by
IOS = |IB1 IB2|
For the A741C op-amp, IOS is quoted as having a maximum
absolute value of 200 nA and a typical value of 30 nA; it can
be either positive or negative.

62

Effect of Input Bias Current


From virtual ground concept,
VX = VY = 0
so, current through R1 is 0.
Current IB1 flows through R2 and produces offset voltage at the
output:

VO I B1R2

In order to minimize the effect of IB, the value of R2 should be


small. However, the ratio R2/R1 determines the voltage gain.
63

Bias Current Compensation


To eliminate/minimize the effect of IB on vo, add resistor R3
between the noninverting terminal and the ground.
With IB2 = 0, VY = VX = 0
VO1 I B1 R2

With IB1 = 0,

VY I B 2 R3 VX
R2
R2
VO 2 (1 )VX I B 2 R3 (1 )
R1
R1
Then, apply superposition theorem for the combined effects of
IB1 and IB2:
R2
VO I B1 R2 I B 2 R3 (1 )
R1
(I )
(I )
B1

B2

(gain)

64

If IB1 = IB2 = IB and adjust resistances to produce zero output:

R2
0 I B R2 R3 (1 )
R1

R1 R2
R3
R1 || R2
R1 R2
If the bias currents are not equal (i.e. IOS 0), and R3 is chosen
as R1||R2, then, a residue error will appear in the output:
VO R2 ( I B1 I B 2 ) R2 I OS

65

Example :
Consider the op-amp circuit with and without bias current
compensation. Let,
R1 = 10 k
R2 = 100 k
IB1 = 1.1 A
IB2 = 1.0 A.
Determine the output offset voltage due to biasing current.
Answer :
Without R3:
vO = IB1R2 = 1.1 (100k) = 0.11 V

With R3 compensation:
Choose R3 = R1||R2 = 10||100 = 9.09 k
vO = R2(IB1IB2) = (100k)(1.11.0) = 0.010 V
66

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