ISPSD 2003, April 14-17, Cambridge, UK

Stacked high voltage switch based on S i c VJFETs

Peter Friedrichs, Heinz Mitlehner, Reinhold Schorner, Karl-Otto Dohnke, Rudolf Elpelt, and
Dietrich Stephani
SiCED Electronics Development GmbH & Co. KG, a Siemens Company
Paul-Gossen-Str. 100, D-91052 Erlangen
Te1.49-9131-734894, e-mail: peterkiedrichs @siemens.com
Abstract. Based on the serial connection of high
voltage S i c VJFETs a stacked solution able to
block very high voltages is presented. By
connecting VJFETs in series, a unipolar high
voltage switch with SkV blocking voltage and an
on-resistance of 2Q was fabricated. The hasic
functions of this stacked switch are analyzed by
discussing the electrical behavior. The static and
dynamic behavior indicate an interesting
perspective for high voltage and high power
applications. Especially the dynamics are carefully
analyzed using a low voltage version of the stacked
solution. Additionally, the potential of S i c
VJFETs as a 4kV single switch is demonstrated.

S i c power MOSFETs are on a good way since

improvements in channel mobility were demonstrated
recently [I]. However, stability and compatibility
problems have to be solved in order to push S i c
MOSFETs into industrial applications.
We have developed several types of normally on S i c
VIFETs, each adjusted to the special demands of
different applications 121. For low loss and high
voltage demands, we have demonstrated a buried gate
VJFET with a specific on-resistance of less than
30mQcmz for a 3,5kV blocking device [3]. Our
latest developments extended the blocking capability
of single chip VJFETs to 4kV with a specific onresistance of around 45mQcmz (see Fig.1).

).

INTRODUCTION
Silicon carbide devices are well known for their
potential to provide an impact on the development of
new and refined solutions for high voltage and high
power switching. Applications can be found in
traction or energy distribution systems like HVDC
e.g. However, large area SIC devices suited for such
high power application (in the range above 100kVA)
are not profitable at the moment due to a although
considerably improved but still not sufficient
substrate quality. In addition, the technology of high
voltage bipolar S i c switches capable of blocking
more than 6,5kV is still at the very beginning.
Challenges are especially a stable and economical
epitaxial growth technology as well as a smart
minority carrier lifetime management in thick
epitaxial layers. In order to vary this lifetime first of
all it is necessary to demonstrate a sufficient high
value (fairly above Ips !) as a reasonable starting
point. Stable and reproducible methods to achieve
such high minority carrier lifetimes in S i c are still
under investigation. Thus, as an intermediate step on
the way to introduce bipolar S i c in high power
electronics, it is worth to evaluate the potential of
well developed unipolar SIC switching devices for
such applications.
UNIPOLAR DEVICE APPROACH
The most mature type of S i c power switching devices
is the vertical junction field effect transistor (VJFET).

........... ....... ..

1
2

~.

Voltage (kV)
Figure I : Blocking behavior of a 4kV VJFET in
cascode configuration
As the drift layer for this device, we used a low
doped epitaxial layer (1,5 .. 2 ~ 1 0 ' ~ c mwith
~ ~ )a
thickness of about 35pm. The controlling head region
of the VJFET was designed identically to the low
voltage configurations [ 6 ] . The conduction behavior
in both directions is shown in figure 2 for a device
with an active area of 1,3mm2 (single VJFET).
Saturation as well as the operation of the reverse
diode can be observed.
Recently, a smart approach of in series connected
VJFETs based on the well known cascode was
introduced. A first version with 4,5kV blocking
voltage and an on-resistance of 1,2 Q was presented
i n 2002 141. The results indicated an interesting

139
u09-7876-8/03/$17.000 2003 IEEE

... ........

potential due to easy paralleling of chips and the

(theoretical) extendibility of such a serial connection
to any desired blocking voltage. This stacked solution
provides low side control by a simple low voltage
MOSFET without the restriction known from
commonly used in series connected MOSFET dies
[SI.
V,=O

2.01

... -2OV,4V/Slep
I
I
I

(which is exactly the pinch off voltage of J2) and DI,

automatically the pinch-off of 52 is initialed. This
continues up to J4 starts to block. 54 will be driven to
its full blocking voltage and is the only switching
device which has to work under avalanche
conditions, if necessary. The condition for the circuit
dimensioning is simply V,,,,O~:) + V ,_~(i+,)4
V,,,i,
with (i) indicating the corresponding index for the
device, V,, is the avalanche voltage of the device
and V, the pinch off voltage of the VJFET.

Drain
J4

J1
D1
J2
D2
J3

3000V
P2OOV
3000V
22oov

D3

moov

J3

D2
J2

D1

J1
Gate
M1
VGS= 0 ... -28V, 4V/Step

Figure 2 : Conduction behavior of a 4kV VJFET

with an active area of 1,3mm*
STACKED HIGH VOLTAGE SWITCH
We used high voltage 3kV VJFETs to fabricate a
four-fold stacked 8kV switch. The corresponding
electrical circuit diagram is shown in figure 3.
The basic function can be described as follows. In
conduction mode, the power MOSFET M1 is turned
on. Between gate and source of the VJFET appears
only a small voltage drop, therefor, 11 is on too. The
same holds for J2 , J3 and 54, respectively. So, we
have a simple MOSFET with resistive elements in
series and a current limiting behavior. If MI is
turned off, the bias starts to increase between gate
and source of JI until the pinch off voltage of J1 is
reached. The further bias increase occurs at the drain
of JI (= source of J2). The gate of J2 is connected via
D1 to ground, basically we have a serial connection
of two pn-diodes, the gate-source diode of 52 and D1.
Thus, if the bias at the source of J2 reaches the sum
of the blocking voltages of the J2-gate-source diode

Source

Figure 3 : Circuit diagram of the stacked high voltage switch

(8kV). the VJFETs are S i c devices, the diodes and
the MOSFET are silicon devices. The table at the
left side shows the single device blocking voltages.
Statically this behavior can be observed by analyzing
the forward blocking behavior (Figure 4).
4

a3
E

g'

Voltage (kV)

Figure 4 : Forward blocking behavior of a 8kV

stacked high voltage switch

140

The pinch off of each stage is accompanied by a

slight increase in reverse current, depending on the
reverse current of the devices used . For the h p e
shown sample this occurs at 2000, 4000 and 6000V
(according to the used diodes) while the upper stage
reaches its full blocking voltage of nearly 2000V,
resulting in an 8kV blocking capability for the full
stack. In figure 4, a sample is shown with a
pronounced reverse current behavior in order to
demonstrate the basic behavior. Generally the reverse
current can be kept in the micro amp regime up to
the full blocking voltage. In the realized samples,
8,2mm2 active S i c area was used in each stage. The
resulting on-resistances ranged between 1,6 and 2R.
The simplicity and potential of the stacked switch are
impressive. There are no demands on the high
voltage diodes except stable avalanche at a certain
blocking voltage since the circuit can be designed in
a manner that they never turn on. The maximum
electric field within the switching devices can be
adjusted by a proper choice of the blocking voltage of
the corresponding diodes. Furthermore, the single
VJFET chips can be placed thermoelectrically
optimized across a module base plate resulting in a
low thermal resistance. Thus, a high current density
can be handled also for very high blocking voltages.
Remarkable is also the inherent reverse diode
behavior of the stack which is governed by the low
voltage silicon power MOSFET. Reverse diodes of
low voltage power MOSFETs show a very low
storage charge and fast reverse recovery behavior.
DYNAMIC BEHAVIOR OF THE HIGH
VOLTAGE STACK
Besides its static blocking and conduction behavior
the dynamic performance of the serial connection of
power devices is decisive for the potential in
applications. Firstly, we have simulated the turn-ff
behavior of a configuration consisting of two V E T S
in series in a chopper circuit (inductance L=4mH,
ideal diode). Especially the potential distribution
across the stack and the sequence of switching of the
single devices was of interest. Figure 5 shows the
results of the device simulation carried out by
DESSIS-ISETM.
Shown are the drain potentials at the first and the
second VJFET as well as the drain potential of the
MOSFET. Evidently, the potential rises at all three
devices simultaneously , This is reasonahle for the
MOSFET and the first VJFET since the MOSFET
drain-potential provides the pinch off potential for
the first VJFET. However, on a first glance the
potential at 52 should be higher than at JI only after
reaching the blocking voltage of the diode D1.
However, this is not the case. The space charge
charging occurs for all devices simultaneously via the
small displacement currents from drain to source of

the whole stack. Consequently, the VJFETs runs into

pinch off and starts to block. Thus, fast switching can
be expected which was already proven for the first
4,5kV samples [4].

Time @SI

Figure 5 : Turn-off behavior of a two stage stack,

simulated
In order to check the dynamics of a multi stage stack,
we have prepared special low voltage samples with a
blocking voltage of 370V for all diodes and a low
voltage VJFET in the last stage. These 4-stage stacks
exhibited maximum blocking voltages up to 18M)V.
Additionally they allowed access to all nodes of
interest within the stacks (e.g. all drain, gate and
source pins, respectively. Thus, we were able to
analyze the switching behavior of all stages together
using a conventional 2kV chopper circuit setup
(L=4mH, Sic freewheeling diodes) for our analysis.
6

1400

12w
1030

MM2
400

2w

0.0

0.1

0.2

Ti-

0.3
(P)

0.4

0
0.5

Figure 6 : Measured Turn off behavior of a

four-stage 15OOV stack in a chopper
circuit

141

Figure 6 shows the turn-off behavior measured in the

chopper circuit. The line voltage was 120OV, thus,
the switching occurred across. the first three stages
and therefor, only the drain potential at JI, J2 and J4
is shown since 13 and 34 are nearly at the same bias.
The results are very close to the simulation. The
small voltage overshot is due to the high gate
resistance of the used VJFET head structure [2].
Especially the simultaneous increase of the bias at all
drains is obvious and in very good agreement with
the simulated behavior.
A similar performance can be observed for turning on
the stack (see figure 7).

1200

1000

m g

E 4

600

400

200

0.0

-s

5
0

.s

ACKNOWLEDGEMENT

41400

7,

-9

was simulated and measured. Both results are in gwd

agreement and prove the ability of fast turn-on and
turn-off. However, the static stability of the blocking
stage is dependent on the existing leakage path
through the diodes in the stacked switch. Further
investigations will show how this can be stabilized by
the introduction of appropriate resistors or other
components.
Since bipolar S i c high voltage switches are still in an
early stage of development, we believe that the
presented solution may facilitate for S i c the access to
the high power market.

0.1

0.2

0.3

0.4

lime

0.5

0.6

0
0.7

(w)

Figure 7 : Measured turn-on behavior of a fourstage 1 SOOV stack in a chopper

circuit
The relatively long period until the drain potentials
fall to their saturation value are believed to be due to
the necessary charging of the space charge
capacitance of the diodes and the VJFETs. Further
analysis will he necessary to get a better inside of this
behavior.
SUMMARY AND CONCLUSION
A unipolar S i c solid state switch was presented that
is able to block 4kV as a single chip. Based on the
already introduced VJFET technology, a normally off
switch with a specific on-resistance of about
4SmRcmz was realized. Based on this technology and
the well known cascode arrangement, a high voltage
switch realized by the serial connection of VJFETs
was fabricated. First samples with SkV blocking
voltage showed on-resistances of 2R with a current
handling capability of around IOA. The switches
provide easy low side control via a SOV power
MOSFET, fast switching and a favorable thermal
behavior due to the distribution of several in series
and parallel connected chips. The dynamic behavior

The authors would like to thank the members of staff

at SiCED for performing an excellent job in realizing
the technological processes. We would also like to
thank SEMIKRON Germany for their encouraging
help and assistance with packaging of the stacked
switches. The work was supported by the Siemens
Corporate Technology.
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Das,
J.W. Palmour, &proved
inversion
channel mobility for 4H-Sic MOSFETs
following high temperature anneals in nitric
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[2] P.Friedrichs, H.Mitlehner, R.Schorner, K.O.
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