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XUP WORKSHOP 1: FPGA design flow using vivado.

This is the summary of workshop series by XUP under which we learn
about the design flow in FPGA using vivado. So without wasting time Ill
summarize the design flow using vivado.
General design flow:

1.

Creating a project:

The first task in the design flow is to

creating a project. While creating a project we give project a name
and type, select the hardware and start designing. After that we
need to add or create the sources. There are generally three types
of sources design sources, design constraints, and simulation
sources. We can add them if we already have written it or create it
ourselves. To create a design sources we use our knowledge of
vhdl/verilog and the ips in the ip catalogue. After creating or adding
the design sources we can check the RTL schematic of the
project.RTL is the level where we can see our project in terms of
logic i.e. see how the signal flows into different registers. We can
also add ips form ip catalog. In most cases we need to customize
the ips to fit it in the project. We need to instantiate these ips in
the top module. We also can make a constraint file according to the
project requirement. There are generally three types of constraints
timing constraints, placement constraints and synthesis constraints.
Generally the constraint files are in .xdc extension which refers to
Xilinx design constraints. Finally we can add or create simulation
source to simulate the design.

by Prasiddha siwakoti

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2.

Simulation: Once the design is completed we need to check the

functionality of the design, monitor different signals etc, to do that
we need to simulate the design by creating or adding the simulation
source. Generally there are three parts in simulation source the DUT
(devices under test) instances, same module functionality as in
design source and the stimuli. There are two ways to create input
stimulus, using an interactive waveform editor or using a testbench.
In vivado there is a freature-rich, multi-language simulator which
support verilog, system-verilog and VHDL language. After
completion of the simulation process generally there are four main
views displayed which is necessary to go through simulation
process. (i) Scopes, where the testbench hierarchy as well as glbl
instances are displayed, (ii) Objects, where top-level signals are
displayed, (iii) the waveform window, and (iv) Tcl Console where the
simulation activities are displayed. The first thing I did in this
process was to change the radix of the signals, I changed it form
binary to hex. There are many similar tools which are very helpful to
simulate your design.

Fig: Simulation process

by Prasiddha siwakoti

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3.

Synthesis:

4.

Implementation: Implementation stage is intended to translate

In fpga design synthesis is the process of converting

different abstraction form of a designed circuit behavior(typically
they are in RTL level of abstraction) to the design implementation in
terms of logic gates. Synthesizing in vivado is easy and may take
different amount of time depending upon the weight of your
design( I recommend to use computer with latest specs for better
synthesis time). After the synthesis is complete you can analyze
different reports including the schematic. If you open the schematic
then you will notice that it is no longer in the RTL level instead the
gates are replaced by the LUTs. Other things you should not forget
to check before moving onto the next step is reports. The most
important reports are timing and the utilization reports. Timing
reports should be checked to assure that there is no any timing
violation and if exists should be taken care. In most cases we deal
with the failing Intra-clock paths where the values of worst negative
slack and total negative slack are invalid. There is a edit timing
option to edit the timing constraints and recalculate all the values.
You can also see how much resource has been utilized in your
project. It generally no or and the percentage of LUTs, Registers, IOs
used in the project. Similarly there is also facility of reporting the
power utilization, which estimates the power consumption by your
project. It provides detailed power consumption report i.e the
percentages of total power consumed by different modules. Vivado
also allows you to write the checkpoints during the design process
just like in video-games so that you can load it later and proceed
from that point.

netlist into the placed and routed fpga design. Vivado generally has
three stages to complete the implementation run: translate, map
and place and route. Translate merges the incoming netlist and
constraints into the Xilinx design file. Similarly mapping fits the
design into the available resources on the target devices. And finally
in place and route stage design is placed and routed to the timing
constraints. After implementation run you can see various kinds of
report as done in the synthesis process. At this stage analyzing the
pin placement is very important. You must ensure that there is no
any routing and placement violation.

by Prasiddha siwakoti

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[note: you can start the project by selecting I/O planning type, in
this type of project you will create the design constraint first. In this
project you can Enter the pin locations and IO standards via Device
view, Package Pins tab, and Tcl commands. You also can create
period, input and output setup delays etc. And finally you can
perform the timing analysis too]
After completing all the procedures in implementing a design you
need to generate a bit file (bitstream) of your project to program it
in hardware. So, at last there is Generate bitstream option which
will create a bit file of your project
.
5.

Verifying functionality in hardware: After the bitstream is

generated a window pops up with different option including open
hardware manager. You need to click on open hardware manager.
Connect your hardware to the host computer and click on the open
new hardware target link. Once you see your device click next to
see server setting and more nexts until you finish. After that by
clicking on program device you can load bit file and program your
device and test your project in real time with real hardware.

[note: if you miss the pop up option window then go to program and
debug to find hardware manager]
There is a lab about hardware debugging, which explains about the use
of ILA(integrated logic analyzer) core from the ip catalog as debugging
tool. Also teaches about mark debug features.

This portion of workshop series by XUP is very useful to understand the

design flow in vivado. I recommend all interested person to go through
these series to have detailed and better understanting.

by Prasiddha siwakoti