Analogue Electronics

TOPIC 3
Unipolar Devices
The current in Unipolar devices is carried only by the free majority carries in the conducting
channel and no essential role is played by the small numbers of minority carriers - hence the
term Unipolar.
Field Effect Transistor (FET): It is a type of Unipolar device in which the number of carriers
available to carry current in the conducting region is controlled by application of an electric field
to the surface (or junction interface) of the semiconductor.
FET is a 3-terminal active device capable of voltage and power amplifications. The three
elements of the device are
Source:
Source of majority carriers
Drain:
termed so because this is where electrons (or holes) are pulled off.
Gate:
named so because of the controlling function, i.e. the electrode to which
voltage is applied to produce the modulating field.
The general cross sectional view of an FET is illustrated in Fig.20.

Fig.20 General Cross Sectional View of an FET Device

Operation: The operation of an FET, in general, is that electrons (or holes) flow from the
source through a conducting channel to the drain. The conductivity of the channel can be
influenced by a charge on the gate which may have either of two forms.
The device has high input impedance in the range of 1010 - 1515 .

FETs are voltage controlled devices, since current control in FET devices resulted from
electrostatic field that is injected into the channel by reverse biasing the junction. Gate-source
used to carryout this. Hence, no current flows in the junction resulting in very high input
impedance. Whereas in bipolar devices, small voltage forward bias the base and a current
flows across the junction, hence a current controlled device. This input impedance of bipolar
devices is low.

Advantages of FET devices in ICs

1.
2.

FET devices are often simpler to fabricate and occupy smaller areas on ICs, thus high
packing density
FET devices do not need additional isolation stages in IC circuitry since they have high
input impedance. This means that they can be used as resistors or capacitors.

The FET family

Junction field effect transistor
(JFET)
Input impedance 1010
Applications
Small signal JFETs are used
at the input stage of amplifiers
to provide high input resistance.
They are also used as switches.
High frequency JFETs are used to
amplify or produce high frequency
signal.

Insulated gate field effect transistor

IGFET or (MOSFET)
Input impedance 1015
Applications
MOSFET has become the
most important transistor.
Most microcomputers and
memory integrated circuits
be arrays of thousands of
MOSFETs on small silicon chips.

Junction Field Effect Transistor (JFET)

The basic operation of JFET is the variation of resistance of a semiconductor "channel" by the
application of an electric field across the gate region. The JFET can be formed with either ntype or p-type channels. Since, in real life terms only n-channel devices have useful and
practical applications, only n-channel JFET devices will be treated here.

N-Channel JFET
A cross-sectional view of n-channel JFET is shown in Fig.21.

Fig.21 Cross-Sectional View of JFET

N-Channel JFET Operation

Current flow of n-channel JFET is primarily by means of excess electrons through the n-type
channel, when the drain region is made positive with respect to source by the application of a
voltage VDS.
The operation of the device relies on the junction formed between the gate (p-type) and the
channel (n-type). If a reverse bias is applied to the junction (i.e. placing a negative voltage at
the gate region) then, this would produce depletion region in the pn junction. Normal current
flow from source to drain is now restricted. If the negative voltage at the gate is increased,
then this will cause depletion spread further into the channel. This reduces the effective area
of cross section of the channel and thus reduces its conductivity and increasing its resistivity.
As the gate is made more and more negative, the effective width of the channel decreases
until the drain current is stopped completely.
Output Characteristics
Output characteristic is a plot of ID against VDS for a set of VGS values, as shown in Fig.22a. At
low drain voltage the channel behaves linearly as the drain current is directly proportional to
the drain voltage. As the drain voltage is increased the size of the depletion layer increases,
eventually the channel becomes pinched off and further rise in the drain voltage does not
provide an increase in the drain current. This is the saturation region.
The pinch off line is the locus of pinch off points VDS = VGS - VP. VP is the pinch off voltage and
it happens when the depletion region has extended almost completely across the channel. Nchannel JFET circuit symbol is shown in Fig.22b.

Fig.22 a - N-Channel JFET Characteristics

b - N-Channel JFET Circuit Symbol

Fig.23 General View of N and P Channel JFETs

Fig.24 Pictorial View of N-JFETs Operation

Insulated Gate Field Transistor (IGFET or MOSFET)

The basic operation of MOSFET is the same as that of the JFET, namely the control of the
resistance of a semi-conducting channel by an applied electric field.
The MOSFET has an oxide insulating layer, of the order of 100nm thick, separating the gate
electrode from the channel material. The result is a capacitor to the oxide in the channel.
Thus a negative gate attracts positive holes from the channel material and for N channel
material increases the resistance by majority electron flow.

The MOSFET can be of ENHANCEMENT or DEPLETION type

1. Enhancement-mode device
The enhancement device allows virtually NO CURRENT to flow when the gate- source
potential (positive for an n- channel device, negative for a p- channel device) attracts opposite
charges into the channel region. These allow conduction, so the channel is enhanced and
drain current increase with increase gate-source potential. Basic construction of the device is
shown in Fig.25.

Fig.25 Cross Sectional View of n-channel Enhancement

Fig. 26 n-channel Enhancement mode output characteristics

N type

P type

Fig.27 n-channel Enhancement-mode Circuit Symbol

Qn.

Explain how enhancement mode MOSFET can be considered as an ON-OFF device.

Qn.

Draw the cross sectional view of a p-channel enhancement MOSFET device. Give
also the device circuit symbol.

Qn.

Draw the output characteristics of a p-channel enhancement mode device.

2. Depletion-mode device
The DEPLETION type has some light doping in the channel between the source and drain,
which allows some enhancement current with zero gate - source potential. Application of both
negative and positive gate voltages control the drain current, but, the device is generally used
only with negative gate voltages in the case of an N-channel. Fig.28 shows a cross sectional
view of depletion MOSFET device. Characteristics of this type are shown in Fig.29 and circuit
symbols are shown in Fig.30.

Fig.28 Cross-Section View of Depletion MOSFET

Fig.30 Depletion-mode Characteristics

N-type

P-type
Fig.31 Depletion-mode Circuit Symbols

Fig.32 Two dimensional cross sectional view of P & N

Channels MOSFETs

Fig.33 Pictorial View of MOSFET Operation

Qn.

Discuss briefly the principal disadvantage of the MOSFET devices.

Transfer Characteristics
FET transfer characteristic is a useful graphic representation of the operating principles of the
FET. It is a plot of ID vs. VGS for some constant value of VDS in the saturation region.

Fig.34 Transfer Characteristics

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gm = transconductance of the channel at low VGS

gm =

ID

IGS

gm is measured in siemens or S

FET Biasing Circuits

Self- Bias Common Source
In an n-channel depletion FET, the gate needs to be negative with respect to the drain and
source.
This can be achieved by making the source more positive than the gate, since all voltage
requirements on the FET are relative to each other. A single, high value resistor from gate to
ground (Rg) will hold that input close to the zero volts potential (since current is negligible) and
resistors on drain and source (Rd and Rs) will control the voltages on these points, due to the
currents flowing through them:

Fig.35
Input Current is negligible; Rg therefore should be large, say 1 M ohm.
We choose a suitable mid range (quiescent, i.e. with no input signal) drain current (which is
also the source current) and the corresponding gate source voltage.
Calculate Rs from these values using Ohms law.
Choose a suitable quiescent output (drain) voltage. This will usually be approximately half way
between the supply rails, or slightly more to allow for the gate-source voltage.

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Select a value of Rd which will give this chosen quiescent voltage, again using Ohms law.

Example
A FET device has a quiescent Voltage-source (Vgs) of 3V and drain current Id of 0.7 mA. The
power supply is 20 volts. Calculate suitable bias resistors for a simple self bias circuit as
shown above. Assume that the quiescent operating
Voltage Vp should be chosen to give maximum voltage swing on the output.
1. Select a nominal value for Rg of 1 M ohm.
2. Calculate Rs = Vgs/Id = 3/0.7 = about 4.2 k ohms.
3. For a maximum voltage swing, Vp needs to be half-way between the extreme values
possible on the output. This is mid way between the 20 volt supply, and the 3 volt vgs.
Calculate Rd with about half the supply voltage less the vgs lost across Rs, i.e. 20-3/2=8.5V
across Rd.
Therefore Rd=8.5/0.7= 12 k ohms.

Practical Bias Circuit

In practice, quiescent drain current at a given drain- source voltage will vary considerably
from device to device.
To overcome this, the following circuit can be used:

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Fig.35
In this example, the voltage is set by the voltage divided by the resistor pair R1 and Rg minus
the voltage dropped across Rs.
This means there can be a greater voltage drop across Rs than in the previous example.
This greater voltage drop causes a greater variation in voltage if the current varies due to
variations in the FET characteristics, i.e. a greater amount of FEEDBACK.

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