DIRECT MEMORY ACCESS CONTROLLER (8237)

The 8237 is a LSI controller IC that is most widely used to implement the DMA
transfer. DMA capability permits devices, such as peripherals, to perform high speed
data transfers between either two section of memory or between memory and an input
output device. DMA mode of operation is most frequently used when blocks or packets
of data are to be transferred for instance disk controllers, Local area network controllers
and communication controllers are devices that normally process data as blocks or
packets.
The following figure shows the 8237A DMA controller. In a microprocessor system
the 8237A can acts as a peripheral device and its operation must be initialized through
software. This is done by reading from or writing to the register of DMA controller.
These data transfer takes place through microprocessor interface .
Whenever 8237A is not in use by a peripheral device for DMA operation, it is in a state
known as idle state. When in this state, the microprocessor can issue commands to the
DMA controller and read from or write to its internal register. Data bus lines DB0
through DB7 are the path over which these data transfers take place. Which register is
accessed is determined by a 4-bit register address that is applied to address inputs A0
through A3.
During the data transfer bus cycle, other bits of the address are decoded external
circuitry to produce a chip select (CS ) input for the 8237A when in the idle state, the
8237A continuously samples this input waiting for it to become active. Logic 0 at this
input enables the microprocessor interface. The microprocessor tells the 8237A whether
an input or output bus cycle is in progress with the signal IOR or IOW .

DMA Interface of the 8237A:

With the above discussion, we have seen how a microprocessor talk to the register of
8237A. Now let us see how peripheral devices initiates DMA service.
The 8237A contains 4 independent DMA channels, channels 0 through channel 3.
Typically, each of these channel is dedicated to a specific device, such as a peripheral.
The following figure shows the DMA interface. (Fig. 5.10)
There are 4 DMA request inputs denoted as DREQ0 through DREQ3. These DREQ
inputs corresponds to channels 0 through 3. In the idle state the 8327A continuously
tests these inputs to see if one is active. When a peripheral device wants to perform
DMA operation, it makes a request for service at its DREQ input by switching it to its
active state.
In response to DMA request, the DMA controller switches the hold request output to
logic 1. Normally this output is supplied to the HOLD input of the 8086 and signals the
microprocessor that the DMA controller needs to take control of the system bus.
When the 8088/8086 is ready to give up control of the bus, it puts its bus signals in to
the high impedance state and signals this fact to the 8237A by switching the HLDA
(Hold acknowledge) output to the logic 1. HLDA of the 8088/86 is applied to the
HLDA input of 8237A and signals that the system bus is now available for use by the
DMA controller.
The 8237A tells the requesting device that it is ready by outputting a DMA acknowledge
(DACK) signal for each of these 4 DMA request inputs, DREQ0 through DREQ3, has
a corresponding DMA acknowledge outputs DACK0 then DACK3. Once this DMA
request/acknowledge handshake sequence is complete, the peripheral device gets direct
access to the system bus and memory under the control 8237A following figure shows
DMA interface.

During DMA bus cycles, the system bus is driven by the DMA controller not the
microprocessor. The 8237A generates all the address and control signals needed to
perform the memory and the input/output data transfers. At the beginning of the all
DMA bus cycles, a 16-bit address is output on lines A0 - A7 and DB0 thru DB7. The
upper 8 bits of the address, which are available on the data bus lines, appear at the
same time that address strobe becomes active. The ADSTB is used to strobe the
MSB of the address in to an external latch.
This 16-bit address gives the 8237A the ability to directly address up to 64k bytes of
storage location. The AEN (address latch enable) output signal is active during the
complete DMA bus cycle and can be used to both enable the address latch and disable

other devices connected to the bus.

Let us assume that an IO device wants to transfer data to memory. i.e., IO device
want to write data to memory. In this case 8237A uses IOR output signal to the IO
device to put the data onto data bus lines DB0 thru DB7. At the same time, it asserts
MEMW to signal that the data available on the bus are to be written into memory. In
this case the data are transferred directly from the IO device to memory and dont go
thru 8327A.
In a similar way DMA transfer of Data can takes place from memory to an IO device.
Now IO device reads data from the memory. For this data transfer the 8237A activates
MEMR and IOW control signals.
5.2.2 Internal Architecture of 8237A:
The following figure shows the internal architecture of 8237A. Here we have the
following blocks.
timing and control.
priority encoder
rotating priority logic.
command control.
12 different types of registers.
Let us consider these functional blocks in detail.

The timing and control part of 8237A generates the timing and control signals needed
by the external bus interface. It accepts input as Ready and CS and produce output
signals like ADSTB and AEN. READY input is used to accommodate for slow memory
of IO devices. READY must go active, logic 1, before the 8237A will complete a
memory or IO bus cycle. As long as READY is at logic 0, wait states are inserted to
extend the duration of the current bus cycle.
If multiple requests for DMA service are received by the 8237A, they are accepted on
priority basis. One of two priority schemes can be selected for the 8237A under software
control. They are called fixed priority and rotating priority. The fixed priority mode
assigns priority to the channels in descending numeric order. That is channel 0 has the
highest priority and channel 3 has the lowest priority. Rotating priority starts with the
priority levels same way as in fixed priority. However, after a DMA request for a
specific level gets services, the priority is rotated so that the previously active channel
is reassigned to the lowest priority level for instance, assuming that channel, which
was initially at priority level was just serviced, then DREQ2 is now at the highest
priority level and DREQ1 rotates to the lowest level.
The command control circuit decodes the register commands applied to 8237 A through
microprocessor interface. In this way it determines which register is to be accessed
and what type of operation is to be performed. However it is used to decode the

programmed operating modes of the device during the DMA operation.

8237 has 12 different types of Internal register.

Each DMA channel has two address register. They are called the base address
register and current address register. The base address register holds the starting
address for the DMA operation. Current address register contains the address of the
next storage location to be accessed. These register must be loaded with appropriate
value prior to initiating a DMA cycle. To load a new 16-bit address into the base
register, we must write two separate byte one after the other to the address of the
register. 8237A has an internal FF called first/last FF. This FF identifies which byte of
the address is being written in to the register. If the FF = 0, then load low byte of
address to the register. If FF = 1 then write high byte of address to the register.
Current Word Register: Each channel has 16-bit current word register that carries
number of data byte transfers to be carried out. The word count is decremented after
each transfer and the new value is again stored back to current word register when a
count becomes zero an EoP (End of Process) signal will be generated.
Base Address and Base Word Count Register: Each channel has a pair of these
register. These contain the original copy of the respective initial current address register
and current word count register (before incrementing or decrementing). These are
automatically written along with the current register. These cant be read by CPU.
The contents of these register are used for auto initialization.
Command Register: This 8 bit register controls the complete operation of 8237. This
can be programmed by the CPU and cleared by resent operation

Mode Register: Each DMA channel (contains) has an 8-bit mode register. This is
written by CPU in programming mode.

Request Register: Each channel has a request bit associated with it in the required
register. These are non-maskable and subject to prioritization by the priority resolving
network of 8237. Each bit is set or reset under programming

Mask Register: Some times it may be required to disable a DMA request of certain
channel. Each of the 4 channels has a mask bit which can be set under program control to disable
the incoming DREQ requesting at the specific channel. This bit is set when the corresponding
channel produces an EOP signal; if the channel is not programmed for autoinitialization. The
register is set to FFH after a reset operation

Temporary Key: The temporary register holds data during memory-to-memory data
transfers. After the completion of the transfer operation, the last word transferred
remains in the temporary register till it is cleared by reset operation.
Status Register: The status register keep track of all the DMA channel pending
requests and status of their terminal counts (TC). Bits D0 D3 are updated every time;
the corresponding channel reaches TC or an external EOP occurs. These are cleared
upon reset and also on each status read operation. Bits D4 D7 are set, if the
corresponding channels require services

Transfer Modes of 8237:

Single Transfer Mode: In this mode the device transfers only one byte per second. The

word count is decremented and address is decremented or incremented after each such
transfer. The terminal count (TC) state is reached when the count becomes zero. For each
transfer, the DREQ must be active until the DACK is activated.
Block Transfer Mode: In this mode 8237 is activated by DREQ to continue the transfer
until TC is reached i.e., block of data is transferred. The transfer cycle may be terminated
due to EOP which forces the TC. The DREQ needs to be activated only till DACK signal is
activated by DMA controller.
Demand Transfer Mode: In this mode the device continuously transfers until a TC is
reached or an external EOP is detected or DREQ signal goes inactive. Thus a transfer may

exhaust the capacity of data transfer of an input/output device. After the IO device is able to
catch up, the service may be reestablished activating, the DREQ signal again.
Cascade Mode: In this mode, more than one 8237 can be connected together to provide
more than 4 DMA channels. The HRQ and HLDA signals from additional 8237s are
connected with DREQ and DACK pins of a channel of the host 8237 respectively. The
priorities of the DMA requests may be preserved at each level. The 1st device is only used
for prioritizing the additional devices and it does not generate any address or control signal of
its own.
Memory to Memory Transfer: To perform the transfer of a block of data from one set of
memory address to another one, this transfer mode to used. Program the corresponding
mode bit in the command word, set the channel 0 and channel 1 to operate as source and
destination channel. This transfer is initialized by setting the DREQ0 using software commands.
The 8237 sends HRQ signal to the CPU as usual and when the HLDA signal is activated by
the CPU; the device starts operating in block transfer mode to read the data from the memory.
The channel 0 (CAR) Current Address Register acts as a source pointer. The byte read
from the memory is stored in an temporary register of 8237. The channel 1 CAR acts as a
destination pointer the pointers are automatically incremented a decremented, depending
upon program. The channel 1 word count register is used as a counter and is decremented
after each transfer.