ISSCC 2010 / SESSION 26 / HIGH-PERFORMANCE & DIGITAL PLLs / 26.

8
26.8

A 1GHz ADPLL with a 1.25ps Minimum-Resolution

Sub-Exponent TDC in 0.18m CMOS

Seon-Kyoo Lee, Young-Hun Seo, Yunjae Suh, Hong-June Park,

Jae-Yoon Sim
Pohang University of Science and Technology, Pohang, Korea
The resolution of multi-bit linear TDC is closely related to process technology
since the minimum resolvable time quantity is proportional to one-inverter
delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3].
Since the time resolution is determined by the difference between two inverter
delays, a large number of inverter stages is required to cover a large detection
range, resulting in long conversion time and high power consumption. Wellestablished data-conversion architectures have also been sought to achieve both
large detection range and high resolution [4,5]. The two-step TDC was proposed
to improve both the resolution and detectable range by amplifying the time
residue after the coarse conversion for the fine conversion [4]. But, the previous
time amplification schemes [4, 6] use metastability and suffer from small input
range and gain uncertainties due to nonlinearity and PVT variations. This paper
presents a power-efficient and wide dynamic range sub-exponent TDC. Based on
a cascaded chain of 2 time amplifiers, the TDC generates the exponent-only
information for the fractional time difference.
Fig 26.8.1 shows the block diagram of the designed all-digital PLL. A first-order
delta-sigma modulator (DSM) improves the resolution of the ring DCO [7]. The
TDC consists of a front-end PFD, an integer TDC, and a sub-exponent TDC. The
front-end PFD is included in our TDC for the function of frequency detection. The
integer TDC is the conventional 5b TDC with one-bit resolution of two inverter
delays (~80ps in 0.18m CMOS). For the fractional time difference, the subexponent TDC generates 1-of-n encoded 7b output with each bit representing a
fraction of 2-1, 2-2, , 2-6, 2-7 of the two inverter delay. Since the 5b output of the
integer TDC and the 7b output of the sub-exponent TDC follow the format of a
binary number, two outputs can be directly merged to form a 12b binary number, which is applied to digital loop filter(DLF). Therefore, this TDC improves the
dynamic range and resolution for smaller input while maintaining linearity,
resulting in a fast lock time and low-jitter performance when used in a PLL.
Fig. 26.8.2 shows the sub-exponent TDC. The output of PFD is applied to the
cascade of six stages of 2 time amplifiers (TAs). The output of each stage is
tested by an integer checker. The integer checker is the 1b TDC and outputs ONE
if the time difference is larger than t which is two inverter delays or the one bit
resolution of the integer TDC. With the chain of XORs, the outputs of the integer
checkers are converted to a 7b 1-of-n code. Since the integer ONE corresponds
to 80ps, D6 to D1 represent 40ps (= 80 2-1) to 1.25ps (= 80 2-6), respectively.
The LSB D0 covers all the cases less than 1.25ps, resulting in a minimum resolution of 1.25ps, which is the same as D1. When the PLL is in lock state, the input
to the TDC is smaller than the resolution of the integer TDC. To reduce the power
consumption, the integer TDC is disabled for a small input difference by using
an extra integer checker at the input stage of the integer TDC, and only the subexponent TDC operates.
Figure 26.8.3 shows a simplified schematic of the 2 time amplifier. The nodes
A and B are initially precharged to VDD when two inputs are low. The output of
the TA is determined by the discharging times of A and B when rising transitions
of the inputs are applied. The discharging is performed by two pull-down
pathsan inverter-based path and a dependent path. The strength of one
dependent path is determined by the discharging status of the counterpart node.
The first transition makes the other transition slower by reducing the strength of
the dependent path, resulting in an amplified time difference. Assuming W/L of
M1-M4 are identical, the first discharging is performed by two identical pulldown paths at the initial phase of transition. But the second discharging is performed by only one pull-down path at the end of the transition. So the gain of TA
becomes roughly two for small input case. In the case of large input, however,
the amount of delay increase becomes saturated, so the output shows an additional delay offset with the gain of one.

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2010 IEEE International Solid-State Circuits Conference

To increase the input range of TA, the inverter-based independent discharging

path shown in Fig. 26.8.3 is modified to play a role of another dependent path
and calibrated as shown in Fig. 26.8.4. Similar to M2 and M4, the strengths of
M1 and M3 are controlled by the other input. But the pull-down level of C and D
is limited to threshold voltage of PMOS to guarantee the minimum discharging
paths of A and B. To achieve a stable gain of two with wide input range, a calibration scheme is used. The size of PMOS diodes is digitally calibrated so that
the replica TA experiences the output difference of 2 at the point of the input difference of . 8 clock cycles are required for the calibration. As shown in the simulation results, this calibration at slightly increases the gain in the small input
region. But, overall, this calibration achieves a high linearity with a gain error of
less than 8% for a wide input range of up to 100ps. Since this scheme does not
require an extra load capacitor, simulation shows that the delay time from the
first input edge to the last output edge is 200ps for zero input difference and
400ps for the largest input difference of 100ps. This fast amplification enables a
high-conversion-rate TDC.
For verification, the DPLL is implemented in a 0.18m CMOS process. For the
test of TDC resolution, time sweeping input is obtained by two clock signals with
a small difference in frequency. Since the measurement of sub-exponent TDC is
heavily affected by the jitter in two input clocks, 40,000 cycles of time-swept
TDC outputs are collected with a logic analyzer. By measuring the cumulative
code count, the transfer curve is obtained with noise averaged out. Figure 26.8.5
shows the measured transfer characteristics of the sub-exponent TDC.
Compared with the ideal transfer curve, the differential error and absolute error
are normalized to corresponding one-bit resolution, representing DNL and INL.
Without missing code, the sub-exponent TDC shows a maximum differential
error of -0.5b and absolute error of -0.7b. The maximum operating frequency is
250MHz.
The DPLL has a lock range of 0.9 to 1.25GHz. Figure 26.8.6 shows the measured
jitter histogram at 960MHz. The rms and peak-to-peak jitters are 5.03ps and
35.6ps, respectively, which are 0.48% and 3.4% of the output clock period. The
TDC consumes 2mA in tracking phase and 1mA in the lock state due to the disabling of the integer TDC.

Acknowledgement:
This work was supported by Korea Research Foundation Grant funded by the
Korean Government (KRF-2009-0063398) and IDEC.
References:
[1] R.B. Staszewski, et al, 1.3 V 20 ps time-to-digital converter for frequency
synthesis in 90-nm CMOS, IEEE Trans. on Circuits and Systems II, vol. 53, no.
3, pp. 220-224 Mar. 2006
[2] P. Dudek, et al., A high-resolution CMOS time-to-digital converter utilizing a
vernier delay line, IEEE J. Solid-State Cir., vol. 35, no. 2, pp. 240-247, Feb. 2000
[3] J. Yu, et al., A 12-bit vernier ring time-to-digital converter in 0.13m CMOS
technology, Symp. on VLSI Circuits, pp. 232-233, Jun. 2009
[4] M. Lee, et al., A 9b, 1.25ps resolution coarse-fine time-to-digital converter
in 90nm CMOS that amplifies a time residue, Symp. on VLSI Circuits, pp. 168169, Jun. 2007
[5] M.Z. Straayer, et al., An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC, Symp. on VLSI Circuits, pp. 82-83, Jun. 2008
[6] A.M. Abas et al., Time difference amplifier, Electronics Letters, Vol. 38, No.
23, pp. 1437-1438, Nov., 2002.
[7] D-H Oh, et al., A 2.8Gb/s all-digital CDR with a 10b monotonic DCO, Int.
Solid-State Circuits Conf., pp. 222-223, Feb. 2007.

978-1-4244-6034-2/10/$26.00 2010 IEEE

ISSCC 2010 / February 10, 2010 / 5:15 PM

Figure 26.8.1: Block diagram of the proposed all-digital PLL.

Figure 26.8.2: Sub-exponent TDC.

Figure 26.8.3: Simplified schematic of 2 time amplifier.

Figure 26.8.4: Calibration of 2 time amplifier.

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Figure 26.8.5: Measured transfer characteristics of the sub-exponent TDC.

Figure 26.8.6: Jitter histogram of DPLL.

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Figure 26.8.7: Micrograph of the test chip.

2010 IEEE International Solid-State Circuits Conference

978-1-4244-6034-2/10/$26.00 2010 IEEE