Documente Academic
Documente Profesional
Documente Cultură
Outline
Low Power Design Flows
Library requirements for Low Power Design
Example of 90nm EDK
RTL Implementation
Logic simulation
Logic Synthesis
Timing Analysis
Formal Verification
Physical Synthesis
Signoff
RTL Implementation
Logic simulation
Choose appropriate
power intent, design styles etc.
Implement power intent
in appropriate format
Power aware simulation
and analysis
Logic Synthesis
Timing Analysis
Formal Verification
Automate synthesis
of LPD techniques
Power-aware verification
needed to reveal power
Related bugs
Physical Synthesis
Signoff
EN
CG
Leakage
FF
Multi-threshold
Delay
Low-Vth Std-Vth High-Vth
Clk
Clock Gate
Automatically
OFF
Power gating
0.9V
0.9V
Automatically
0.9V
Multi Voltage
0.9V
0.7V
0.9V
Specification of
power intent
Interoperable
Can be freely used
among EDA tools
(open standard)
Hardware
Description
Languages
(Verilog, VHDL, etc.)
Vendor Specific
Formats
UPF
0.9V
Periphery
Power Domain
0.9/OFF
iso
LS
LS
OFF
LS
0.7V/1.2V
C
0.9V
LS
Operation Scenario
(OFF, 0.9V, 0.7V)
(0.9V, 0.9V, 1.2V)
Supply Network
VDDA
0.9V
VDDB
VDD
0.9/OFF
RR
VDD
Control
VDDV
OFF
iso
LS
LS
VSS
B
VDDA
0.7V/1.2V
0.9V
LS
VDDB
LS
VSS
VDD
VSS
VSS
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
VDDV
OFF
Power
Domain
Power
State
0.9/OFF
0.7/1.2
0.9
LS
Control
B
VDDA
0.7V/1.2V
LS
VSS
C
0.9V VDD
LS
VDDB
iso
LS
LS
VSS
VSS
VSS
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
Supply
Net
Voltage
Level (V)
Power
Domain
VDD
0.9
VDDA
0.7
VDDB
1.2
VDDV
Virtual 0.9
VSS
Common
Ground
A/B/C
VDDV
OFF
LS
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
0.9V VDD
LS
VDDB
VSS
C
VSS
VSS
UPF: Periphery
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
Required Periphery
VDDV
OFF
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
VSS
C
0.9V VDD
LS
VDDB
VSS
VSS
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
VDDV
Scenario
0.9
0.7
0.9
Allowed
0.9
1.2
0.9
Allowed
OFF
0.7
0.9
Allowed
OFF
1.2
0.9
Not Allowed
OFF
LS
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
VDDB
LS
VSS
C
0.9V VDD
VSS
VSS
Initial UPF
Logic Synthesis
Gate Level
Ex. Synopsys
IC Compiler
Gate Level
UPF
Physical Synthesis
Gate Level
PG Gate Level
Physical
UPF
Modifications to low-power
circuit structures
PD boundary
Block PD primary
power net
Power Switch
ISO location
parentwith
backup power
defined
Retention register
LS strategy
defined in
UPF
Top PD primary
ground net
Placement respects
voltage area
boundary
Special Level Shifter
and Isolation Cells
placement
Special cells
placed closer to
VA boundary
LS cells
ISO cells
Special cells
Special versions of library
Characterization in additional corners
Additional views/files/attributes
Inverters/Buffers
Logic Gates
Flip-Flops
(regular+scan)
Isolation Cells
Level Shifters
Retention
Flip-Flops
Latches
Delay Lines
Physical
(Antenna diode)
Clock gating
Always-on
Buffers
Power Gating
1.2
LS
LS
LS
LS
LS
0.9
0.7
LS
Level Shifters
Level Shifter
VDDL
VDDL
VDDH
VDDH
VSS
VSS
D (0.8V)
Q (1.2V)
D (1.2V)
Q (0.8V)
VDD
H
VDDH
VDDL
VS
S
VS
S
H
VDDL
VDDH
High-to-Low
Low-to-High
Copyright 2011 Synopsys, Inc.
VDDH
Low voltage
area
VDDL
VDDL
High
voltage
areas
VDDH
0.9
0.9
OFF/0.7
Isolation Cells
Isolation Cells
D
Q
ISO
ISO
ISO
Bypass
mode
Output clamped
Copyright 2011 Synopsys, Inc.
ISO
Bypass
mode
0.7 1.08
0.9
OFF/0.7
Always on cells
Always-on Buffer
VDDG
INP
VDD local
(on/off)
VSS
Always on
area
VDD_global
(always-on)
Always on Non-Inverting
Buffer Truth Table
IN
VDDG
VSS
VSS local
(on/off)
0.7
0.9
OFF/0.7
VDDG
VDD VDDG
D
Q
ISO
ISO
VSS
VSS
ISO
Bypass
mode
Output clamped
Copyright 2011 Synopsys, Inc.
ISO
Bypass
mode
Always on area
Enable level
shifters
1.08
0.9
OFF/0.7
VDDH
VDDH
ENB
VDDL
ENB
LSUPEN
D
VSS
VSS
D(0.8V)
ENB
Q(1.2V)
D(1.2V)
ENB
Q(0.8V)
Bypass
mode
Output clamped
Copyright 2011 Synopsys, Inc.
Bypass
mode
VDDH
VDDL
High
voltage
areas
VDDH
RR
RR
CTR
1.08V/OFF
1.08V/OFF
0.7V
sleep
0.9V
Power Gates
RR
RR
RR
CTR
1.08V/OFF
1.08V/OFF
0.7V
sleep
0.9V
Power Gates
Header Cells
VDDG
VDDG
VDD
VDD
SLEEP
SLEEP
SLEEPOUT
SLEEP
VDDG
VDD
SLEEP
VDDG
VDD
SLEEPOUT
hi-z
hi-z
a. Header Cell
Multi-Threshold Libraries
100%
FF
FF
80%
60%
40%
Critical
Path
FF
0%
FF
FF
20%
Low-Vth
Std-Vth
Leakage
Multi-Vth libraries
AL
BL
CL
Low Vth
AS
BS
CS
Std Vth
AH
BH
CH
High Vth
High-Vth
Delay
Characterization
Characterization computes cell parameter (e.g. delay, output
current) depending on input variables: output load, input slew, etc.
Characterization is preformed for various combinations of operating
conditions: process, voltage, temperature (also called PVT corners).
slew
Input Slew
slew
slew
Iout
Cchar
0.7
0.7 0.5
0.7 0.5
0.2
0.5 0.2
0.1
0.2 0.1
0.1
Process: Fast
Temp:
125o
Voltage: 1.32v
Process: Slow
Temp:
-40o
.023 .047 .065 .078 .091 Voltage: 1.08v
output cap
output cap
Copyright 2011 Synopsys, Inc.
TTNT1p20v
SSHT1p08v
FFLT1p32v
Process
(NMOS proc.
PMOS proc.)
Typical - Typical
Slow - Slow
Fast - Fast
FFHT1p32v
Fast - Fast
Corner
Name
SSLT1p32v
SSLT1p08v
TTNT0p80v
SSHT0p70v
FFLT0p90v
Temperature (T)
Notes
25
125
-40
1.2
1.08
1.32
125
1.32
Typical corner
Slow corner
Fast corner
High leakage
corner
Low temperature
corners
-40
Slow - Slow
1.32
-40
Slow - Slow
1.08
Low Voltage Operating Conditions
25
Typical - Typical
0.80
125
Slow - Slow
0.70
-40
Fast - Fast
0.90
FFHT0p90v
Fast - Fast
125
0.90
SSLT0p90v
SSLT0p70v
Slow - Slow
Slow - Slow
-40
-40
0.90
0.70
Typical corner
Slow corner
Fast corner
High leakage
corner
Low temperature
corners
Benefits
pg_pin(VDD) {
std_cell_main_rail : true ;
voltage_name : VDD;
pg_type
: primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type
: primary_ground;
}
module AND2X1(IN1,IN2,Q);
output Q;
input IN1,IN2;
and (Q,IN2,IN1);
endmodule
VDDG
Always on
VDDG
VDD
IN
AOn
SLEEP
VSS
Retention cells
VDD
RETN
VDDG
ISO
Isolation cells
D
ISO
CLK
QN
VDDL
VDDH
LSUP
D
Clock gatings:
11 cells with different loads, edges,
and control (post/pre)
VSS
SE
ENL
HVT Cells
EN
CLK
L
A
T
C
H
OBS
GCLK
0.9V
0.7V 0.9V
OFF
0.9V
0.9V 0.9V
OFF
0.9V
0.7V 0.9V
OFF
S 0.9V
R
0.7V 0.9V
Isolation
Cells
Level Shifters
Retention
Registers
Always On
Logic
Multiple Power
Domains
Single Voltage
Multiple Voltage
(MV)
Domains
Power Gating
(shut down)
Single Voltage
No State
Retention
MV Domains
Power Gating
No State
Retention
MV Domains
Power Gating
State Retention
+
+
Conclusion
Low Power Design requires significant design flow modifications
UPF enables LPD flow automation