// Model 1

// User-defined identifiers
// A user-defined name given to an object with a unique name
Correct Examples:
- data_bus
- _bus3
- n$657
Incorrect Examples
- $data_bus
- 3bus
- *data
// Model 2
// Numbers
Binary: 8'b00001111
Octal: 8'o013
Decimal:
8'd15
Hexadec:
8'h0F

or

15

// Model 3
// 2-to-1 Multiplexer
module 21_mux
input
input
input
ouput
);

(
logic
logic
logic
logic

d0,
d1,
sel,
q

assign q = (d0 & ~sel) | (d1 & sel);

endmodule
// Model 4
// Vectors
logic
logic
logic
logic
logic

a;
//
[3:0] v; // a 4-bit
signed [3:0] sr; //
[-1:4] b; // a 6-bit
[4:0] x, y, z;
//

A scalar variable
vector MS->LS
a 4-bit vector in range -8 to 7
vector
Declares three 5-bit variables in one line

// Model 5
// Example of packed vs unpacked
bit [2:0] [3:0] array [5]; // 3 Columns, 5 rows, 4 bits
array[2][1] == 4'b1011; // Row 3 Col 2 is assigned the value "1011"
Packed
0
0000
0000
0000
0000
0000

Dimensions
1
2
0000
0000
0000
0000
1011
0000
0000
0000
0000
0000

// Model 6
// Constant Data Objects

0
1
2
3
4

| Unpacked Dimensions
|
|
|
|

`define const_name const_val

`define amount_of_eggs 12;
localparam const_name = const_val;
parameter DWIDTH = 128;
// Remember this from the midterm project?
// Model 7
// Full Adder running in parallel
module fulladder (
input logic x,
input logic y,
input logic cin,
output logic sum,
output logic cout
);
logic m1, m2, m4, m7 // Minterms 1, 2, 4, 7 where the SUM = 1
assign m1 = (~x & ~y & cin);
...
assign m7 = (x & y & cin);
assign sum = m1 | m2 | m4 | m7;
assign cout = ...;
// Model 8
// Modeling Styles: Data Flow
module xor_gate(input logic a, input logic b, ouput logic q);
assign q = a ^ b;
endmodule
// Model 9
// Modeling Styles: Structural
module xor_gate(input logic a, input logic b, output logic q);
logic w1, w2, w3, w4;

// Logic Wires

not g1 (w1, a); // (output, inputs ...)

not g2 (w2, b);
and g3 (w3, w1, b);
and g4 (w4, w2, a);
or g5 (q, w3, w4);
endmodule
// Model 10
// Modeling Styles: Behavorial (Sequential)
module xor_gate (input logic a, input logic b, output logic q);
always_comb
if (a == b)
q = 1'b0;
else
q = 1'b1;
endmodule
// Model 11

// Exploring nonblocking vs blocking statements

// nonblocking is used when running in parallel
// it is usually used to assign a value inside an always_ff block
reg FF; // Flip Flop
always_ff @ (posedge clk) begin
FF <= d;
q <= FF;
end
// blocking is used when running sequentially
always_comb
x =
y =
z =
end

begin
a | b;
c & d;
x ^ y;

// Model 12
// Concatenation
x = 5'b01001;
y = {x[2 : 0], 1'b0};
y = {x[4] & x[4] & x[4:2]}
y = {x[2:0] & x[4:3]}

// (x << 2) == (00001)
// (x >>> 2) == (11010) <-- Questionable
// x rotate left twice

// Model 13
// Concatenation with comma and replication
// Assuming y index is 0 to 4
y
y
y
y

=
=
=
=

'b0;
{ 'b0, 1'b1};
{1'b1, { 3 {1'b0 }};
{1'b0, 1'b0, 1'b1, 1'b0};

//
//
//
//

0000
0001
1000
0010

// Model 14
// Purely concurrent statement syntax
// assign
assign out = a & b;
//
//
//
//

?
if (condition), output is after "?"
":" represents else if
"4'bz" is the else statement

mux = (addr == 1'b00) ?

(addr == 1'b01)
(addr == 1'b10)
(addr == 1'b11)

i0 :
? i1 :
? i2 :
? i3 : 4'bz;

// Model 15
// Simple generate code syntax
genvar i;
generate
for (i = 0; i < MAX; i++) begin: label
[statements]

end
endgenerate
// Model 16
// Loop Example
logic [7:0] x;
logic [15:0] y;
logic [7:0] z;
genvar i;
generate
for (i = 0; i <= 7; i++) begin: g
assign z[i] = x[i] + y[i + 8];
end
endgenerate
// Equivalent Example
assign z[0] = x[0] + y[0 + 8];
.
.
.
assign z[7] = x[7] + y[7 + 8];
// Model 17
// Create a XOR Tree
module xor_tree (
input logic [7:0] x,
ouput logic [7:0] y
);
logic [6:0] temp;
assign
assign
assign
.
.
.
assign
assign
endmodule

temp[0] = x[0];
temp[1] = temp[0] ^ x[1]
temp[2] = temp[1] ^ x[2]

temp[6] = temp[5] ^ x[6]

y = temp[6] ^ x[7];

// XOR Tree using "generate"

module xor_tree (
input logic [7:0] x,
input logic [7:0] y
);
logic [6:0] temp;
assign temp[0] = x[0];
genvar i;
generate
for (i = 1; i <= 6; i++) begin: gen
assign temp[i] = temp[i - 1] ^ x[i];
end generate
assign y = temp[6] ^ x[7];

endmodule
// Model 18
// Vertical Shifter
row(0):
row(1):
row(2):
row(3):
row(4):

0
0
0
0
1

0
0
1
1

0
1
1
1

1
1
1
1

0
1
1
1
0

0
1
1
0
0

0
1
0
0
0

1 1 1 1
0
0
0
0

module vshifter (
input logic [3:0] inp,
input logic [3] sel, // Final bit count
output logic [7:0] outp
);
logic [7:0] tempRow [5];
assign
assign
assign
.
.
.
assign
assign
endmodule

tempRow[0] = 4'b0000 & inp[3:0];

tempRow[1] = tempRow[0][6:0] & 1'b0;
tempRow[2] = tempRow[1][6:0] & 1'b0;

tempRow[4] = tempRow[3][6:0] & 1'b0;

outp = tempRow[sel];

// Vertical Shifter using "generate"

module vshifter (
input logic [3:0] inp,
input logic [3] sel,
output logic [7:0] outp
);
logic [7:0] tempRow[5];
assign tempRow[0] = 4'b0000 & inp[3:0];
genvar i;
generate
for (i = 1; i <= 4; i++) begin: gen
assign tempRow[i] = tempRow[i - 1][6:0] & 1'b0;
endgenerate
assign outp = tempRow[4][sel];
endmodule
// Model 19
// Gray to Binary Converter
module gray2bin1 (bin, gray);
parameter SIZE = 8;
output [SIZE-1 : 0] bin;
input [SIZE - 1 : 0] gray;
genvar i;
generate
for (i = 0; i < SIZE; i++) begin: g2b

assign bin[i] = bin[i] ^ gray[SIZE - 1: i];

end
endgenerate
endmodule
// Model 20
// Simple use of "always_comb" procedure
module test (
input logic a,
input logic b,
output logic y
);
always_comb
y = a & b;
endmodule
// Model 21
// Implicit versus explicit instantiation
// Implicit
fulladder f1 (r1[1], r2[1], c1, result[1], c2);
// Explicit
fulladder f1 (
.a(),
.b(),
.cin(),
.sum(),
.cout()
);