Direct Memory Access

(DMA)

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Introduction to DMA
We have seen that to move data from :
Input device to memory
Memory to output device
Memory location to memory location

Requires that the source data be moved to the processor and

then the processor data be moved to the destination

An obvious way to improve the data transfer rate is to remove

the processor from the data transfer path. This is called DMA.

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Principle of DMA
The principle of DMA is to temporarily turn-off the
microprocessor and allow a peripheral device, the DMA
controller, to assume control of the computer bus structure.
The processor can be turned-off by tri-stating all its bus
interface pins. The bus interface connections to the 8085A
microprocessor are in the Hi-z state when the processor is in
the T-hold state.
Once the processor has relinquished control of the system
busses, it is the function of the DMA controller to assume
control of those busses and supervise the direct transfer of data
between an I/O device and memory or between memory
locations.

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DMA System Architecture

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DMA Operational Sequence

I/O - Memory DMA Transfer
The I/O peripheral device makes a request to the DMA
controller device for a data transfer by asserting the
relevant RQ input of the controller.
The DMA controller (DMAC) responds to the request by
asserting the HOLD input control line to the 8085A.
The microprocessor responds by completing its current
machine cycle, entering the T-hold state, tri-stating its
address bus, data bus and control bus pins and asserting
its HLDA output pin.
The DMAC then tells the peripheral device it has been
selected for a DMA transfer by asserting the ACK input to
the peripheral.

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DMA Operational Sequence

The memory and I/O device are now interfaced to the
DMAC as if it were the microprocessor, the fundamental
difference being that the DMA controller now has control of
the system address bus and control bus.
Two classes of DMA transfer are now possible :
Sequential DMA
The DMAC performs a read operation fetching the data
byte from the source (eg the peripheral device in a I/O
to memory DMA transfer) into the DMAC.
The DMAC then performs a write operation which
transfers the data byte to the destination (eg the
memory device in a I/O to memory DMA transfer).
Generally , two to four clock periods are required for
each read or write operation (four to eight clock periods
for the complete data transfer).

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DMA Operational Sequence

Simultaneous DMA
Simultaneous DMA offers higher data transfer rates
Here both the read and write operations are carried out
simultaneously.
This requires IORD* (IO read) and MWR* (memory
write) to be asserted simultaneously in a I/O to memory
DMA transfer.
Similarly MRD* and IOWR* need to be asserted
simultaneously in a memory to I/O DMA transfer.
Note: It is not possible for simultaneous transfer in
memory-to-memory operations as we cannot read and
write to memory at the same time.

By carrying out both read and write operations at the

same times then simultaneous DMA offers a twofold
increase in speed over sequential DMA.

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Notes on DMA
DMA transfers are carried out only by system hardware; the
DMA controller, the I/O devices and the system memory
devices.
The speed of the DMA transfer is only limited by the speed at
which the hardware devices can operate.
Because the microprocessor is not involved in DMA transfers
there is no software overhead in transferring data.
DMA takes precedence over all other bus activities, including
interrupts. In fact no interrupts - maskable or nonmaskable are
recognised during a DMA transfer.

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Modes of DMA - Byte Mode

When ready to transfer a data byte, the

peripheral requests control of the
system busses.

When acknowledged the peripheral

transfers one byte of data.

The peripheral then relinquishes control

of the system busses.

The peripheral then waits until it is

ready for another byte transfer.

When the peripheral is ready the

process is repeated.

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Modes of DMA - Burst Mode

When ready the peripheral requests

control of the system busses.

When acknowledged the peripheral

transfers one data byte.

The peripheral then checks to see if it

is ready to transfer the next data byte.

If it is ready the peripheral keeps

control of the busses and transfers
another byte of data.

This process continues until the

peripheral is not ready for data
transfer upon which it relinquishes
control of the system busses.

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Modes of DMA - Block Mode

After gaining access to the system

busses, the DMA controller does not
relinquish control until a pre-specified
block of data has been transferred.

The DMA maintains control of the bus

structure irrespective whether the
peripheral device is ready or not for
further data transfer.

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