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Hi everyone hope you are all fine.I am new here please help me.I want to implement
1 bit full adder using Nano Cmos BSIM MOdel in LTspice. adder has two outputs Sum and carry out
Sum is equal to X-OR of three inputs A,B and Cin It means i need to implement two Xor i have implement
X-Or Using BSIM model in Ltspice Separate (...)
ASIC Design Methodologies and Tools (Digital) :: 07-03-2014 16:00 :: Fasi477 :: Replies: 0 :: Views: 599
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-06-2012 13:45 :: spider_man :: Replies: 1 :: Views: 1405
expert problem..help......
for a 1-bit full adder, after i combine the sum circuit and carry circuit, i will come out with nmos problems
during checking with LVS. And the LVS shows my GND connection have problems, but i dint see the
problem on GND.
PCB Routing Schematic Layout software and Simulation :: 06-23-2011 01:10 :: liuyying :: Replies: 4 ::
Views: 791
Hi i am having trouble designing a truth table for the 4-bit ALU. The document details the
specifications:53446 My problem is how would i combine the arithmetic table with the logic table into one
table? The only way i can think of is do it in separate tables This is what i have in code:
process(A,B,sel,sCIN,cIN)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-18-2011 21:31 :: Digit0001 :: Replies: 3 :: Views: 1464
Dynamic Power, Leakage power and progation delay for full adder
Hi, I need to calculate dynamic power, leakage power and propagation delay for 1 bit full adder. So It is
having A, B, Cin as input signals and Cout, Sum as output signals. I need to calculate these using ELDO
tool. I need take the measurements for all the corners and for different temparatures. So Some script help
is also needed.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-21-2010 13:37 :: ahmadiit :: Replies: 1 ::
Views: 1505
how to make 4 bit x 4 bit multiplier with couple of 4 bit adders and
gates?
I know how to make it with and gates and 1 bit full adder but how to use 4 bit adders
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-25-2010 15:03 :: moonnightingale :: Replies: 10 :: Views: 10221
Need full verilog code for 16-bit adder with carry save
please send me full verilog code for 16-bit adder with carry save.please send it as fast as you can.I need
it very urgently.
Elementary Electronic Questions :: 03-22-2009 16:21 :: rsharitwal :: Replies: 5 :: Views: 19292
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-15-2009 13:13 :: icaniwill :: Replies: 6 ::
Views: 98123
bit full adder in verilog , and I synthesis with Synopsys DC adn get a verilog netlist . I simulate
verilog code using Synopsys vcs , and get a (...)
Digital Signal Processing :: 09-04-2006 07:34 :: wildwood :: Replies: 0 :: Views: 781
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