CALIFORNIA STATE UNIVERSITY NORTHRIDGE

DESIGN OF A THREE STAGE MICROWAVE LOW NOISE AMPLIFIER AT 10 GHz

A graduate project submitted in partial fulfillment of the requirements.

For the degree of Master of Science in Electrical Engineering
By
Pramod S Reddy A

April 2015

The graduate project of Pramod S Reddy A is approved:

____________________________

____________

Dr. Ruting Jia

Date

____________________________

____________

Dr. Sembiam Rengaranjan

Date

____________________________

____________

Dr. Matthew M. Radmanesh, Chair

Date

California State University, Northridge

ii

Acknowledgement
I couldnt have attended CSUN without the generous and unfailing support of my loving
family. I owe a debt of gratitude to Dr. Matthew M. Radmanesh. This design would not
have been successful without him. I thank him for his guidance through this project. I was
motivated to implement what he had taught me in class for the RF and Microwave Active
Circuit Design course. I would also like to thanks to Dr. Mathis for her help in report. I am
also grateful to Dr. Ruting Jia and Dr Sembiam Rengaranjan for being in committee
member. I also thank Vakati Jagdish for providing me ADS.

iii

Table of Contents
CHAPTER 1: INTRODUCTION

1.1 Multi Stage Amplifier Design

1.2 Design Goal

CHAPTER 2: DESIGN THEORY AND ANALYSIS

2.1 General Theory

2.2 Classes of Amplifier

2.3: RF/ MW Circuit Design

2.4: Selecting Appropriate Transistor

2.5: DC Biasing of FET

2.6 Stability Factor

2.7: Power Gain

2.8: Matching Network Design

10

CHAPTER 3: DESIGN PROCEDURE

11

3.1 DC Biasing of FET

11

3.2: K- Test

11

3.3: Single Stage Amplifier Design

12

3.3.1: Input Matching Network for MNA

iv

14

3.3.2: Output Matching Network for MNA

3.4: Maximum Gain Amplifier Design

16
18

3.4.1: Input Matching Network for MGA

20

3.4.2: Output Matching Network for MGA

22

3.5: Total Power Gain

24

3.6: Noise Figure of Cascade Amplifier

24

CHAPTER 4 AMPLIFIER DESIGN USING ADS SOFTWARE

26

4.1: Analyzing Transistor

26

4.2: Single Stage Amplifier Design

30

4.2.1: Simulation Result for Single Stage MNA

4.3: Design of the Second Stage

30
32

4.3.1: Simulation Result for Two Stage

4.4: MGA Design in ADS Software

33
34

4.4.1: Simulation Result for Maximum Gain Amplifier

36

4.5: Overall Design of Three Stage Amplifier in ADS Software

37

4.6: Simulation Result for Three Stage Amplifier

38

4.7: Optimization of the Circuit

39

4.8: MATLAB program for Overall Calculation

41

CHAPTER 5 CONCLUSION

45

5.1: Design Results

46

REFERENCES

47

APPENDIX

48

vi

List of Figures
Figure 1.1 The Amplifier circuit block diagram

Figure 1.2 Multi Stage Amplifier

Figure 2.1 Flow chart for the design Steps

Figure 2.2 DC Biasing Circuit

Figure 3.1 Input Matching Network (MNA)

14

Figure 3.2 Output Matching Network (MNA)

16

Figure 3.3 Input Matching Network (MGA)

20

Figure 3.4Output Matching Network (MGA)

22

Figure 4.1 Transistor NE4210S01 in ADS

25

Figure 4.2 Verifying S-Parameters

26

Figure 4.3 S-Parameters

27

Figure 4.4 Noise Parameters

27

Figure 4.5 Simulation for K Stability Factor

27

Figure 4.6 Output Result for K in ADS

28

Figure 4.7 Input and Output Stability after Simulation

29

Figure 4.8 Minimum Noise Amplifier in ADS

30

Figure 4.9 Output Result When Simulated (MNA)

31

vii

Fig 4.10 Output Result of Gain, Noise and K

31

Figure 4.11 Two Stage Amplifier

32

Figure 4.12 Noise Figure and Gain Output

33

Figure 4.13 ADS Result of Two Stage

34

Figure 4.14 MGA in ADS

35

Figure 4.15 Noise Figure Output in ADS (MGA)

36

Figure 4.16 Gain Output in ADS (MGA)

36

Figure 4.17 Three Stage Amplifier in ADS

37

Figure 4.18 Three Stage Amplifier Output in ADS

39

Figure 4.19 Setting the Goal

39

Figure 4.20 Optimization Result

40

Figure 4.21 Input VSWR Result

41

viii

ABSTRACT
This Three-Stage Low Noise Amplifier (LNA) project works at 10 GHz (X-band)
frequency. The components used are from NEC and Johanson Technology. Agilents ADS,
and RF calculator software are used for design and simulation.
The Low-Noise Amplifier (LNA) is designed to produce a 30dB gain with a 1.5 dB of
noise figure. However, the actual design provided a 40.6dB gain and a noise figure of
0.455dB, illustrating that we have exceeded the design requirements.
This report provides the overall revision of the amplifier matching networks for all three
stages, i.e. design steps of the amplifier matching networks, DC Basing and isolation

ix

CHAPTER 1 INTRODUCTION
One of the most basic concepts in microwave circuit design is amplification. In the past,
microwave tubes and microwave diodes (biased in the negative resistance region) were
commonly used, however, nowadays use of the microwave transistors (BJT or FET) has
become very popular [2].
An amplifier is an electronic circuit capable of increasing the power level or magnitude
of a signal [3].

Figure 1.1 Amplifier circuit block diagram [2].

1.1: Multi Stage Amplifier Design

Our design consists of three stages. The first and the second stage each consist of a
minimum noise amplifier (MNA) and the third stage is a maximum gain amplifier (MGA)
as shown in figure 1 where n is equal to three.

Figure 1.2 Multi stage Amplifier [2].

1.2: Design Goal

Table 1.1 is summarize the design goal:
Frequency(GHz)

10

Total Gain(dB)

30

Noise Figure(dB)

1.5

Bandwidth(GHz)

9.5 - 10.5

Input VSWR

< 1.5
Table 1.1

CHAPTER 2 DESIGN THEORY AND ANALYSIS

2.1: General Theory
Microwave amplifiers are divided into two categories depending on the signal level as
follows.
Small Signal Amplifier
Large Signal Amplifier
Our design is based on the Small Signal Amplifier.
2.2: Classes of Amplifiers
There are four classes of amplifiers.
Class A: In this type of amplifier, the transistor operates in its active region for the entire
signal cycle [1].
Class B: In this type of amplifier, the transistor operates in half of the signal cycle [1].
Class AB: In this type of amplifier, the transistor operates in the class A for small signals
and class B for large signals [1].
Class C: In this type, the transistor is active in a region for significantly less than half of
the signal cycle [1].
Our design project is a small signal amplifier with three stages, where two of them are
MNAs and the last stage is an MGA. The design of an amplifier consists of DC circuit
design and RF/MW circuit design.

2.3: RF/ MW Circuit Design:

To design an RF/Microwave circuit, we need to do the following steps:
Step 1-Based on the amplifier design specifications we must choose an appropriate
transistor. For example, if the gain (G) is given then choose a transistor with typical
|S21 / S12|>G that is in thedesired frequency range. Or, if the noise figure (Fo), is given
make sure that it is greater than the Fmin of the selected transistor, i.e. Fo > Fmin [1].
Step 2- Bias the transistor in the mid-range of region ID VDS [1].
Step 3- Measure the S-parameters by using the Network analyzer or use the data sheet at a
desirable Q-point.
Step 4- Check stability condition by calculating K and . If the K<1 <1 then the
transistor is conditionally stable. Otherwise, if K>1 and <1 the transistor would be
unconditionally stable [1].
Step 5- If S12= 0 then use the unilateral formulae for gain calculations or else calculate a
unilateral figure of merit (U) and find the error range. If this is small, then use the unilateral
formulae to calculate the gain values. For large error values we need to use bilateral
formulae (This applies only to the MGA stage) [1].
Step 6- The matching network should then be designed based upon the gain and noise
requirements of the amplifier.
These six steps are shown in figure 2.1.

Figure 2.1 Overall view of design Steps [1].

2.4: Selecting Appropriate Transistor
The first step involves the selection of a transistor for the amplifier. Initially, the different
parameters (such as gain, noise figure) were compared for different transistors. The
NE4210S01 Hetro-Junction FET satisfied the requirements for our design. The

NE4210S01 HJ-FET was found to have the best stability for the required frequency of
10GHz, hence the Hetro-Junction FET NE4210S01 was selected.
The design of an amplifier consists of designing two separate circuits.
a) DC circuit design.
b) RF/MW circuit design.
These two circuits can be connected seamlessly as shown in figure 2.2.
2.5: DC Biasing of FET
The DC Q- point of an amplifier must be chosen approximately in the midrange of current
- voltage (ID VDS for FET) characteristic for class A type amplifiers.

Figure 2.2 DC Biasing Circuit [1].

ID-VDS Characteristics
To operate FET properly we need to do the following [3]:
1. First a channel needs to be established by applying a gate voltage larger than Vt .

2. VDS Must be large enough to pinch off the channel at the drain end, resulting in the
gate-to- drain voltage to fall below Vt , i.e. VGD < Vt .
The drain current in the saturation region is given by:
iDsat = k (VGS Vt )2 ,
where:
k=

IDSS
V2t

and IDSS is the drain current when VGS = 0.

It should be noted that VGS must be always greater than Vt , i.e,VGS > Vt .
DC and RF circuit isolation
There is a process to connect the DC biasing circuit to the amplifier. Since we use the same
transistor in each of the three stages then the same DC Biasing scheme can be employed
for each transistor.
The DC circuit needs to be isolated by the following methods:
a) Connect an RF choke (RFC) between the DC source and the RF/MW circuitry
[1].
b) Connect a quarter wave transformer.
c) Connect a high-value capacitor.
These three methods of isolation is shown in figure 2.2.

2.6: Stability Factor

To check the stability condition of the transistor, we have the two parameter test, i.e. K test as given by:
= S11 S22 S21 S12 ,

K=

1+| |2 | S11 |2 |S22 |2

2 |S12 S21 |

If K>1 and <1, the transistor is unconditionally stable, otherwise the transistor is
conditionally stable.
2.7: Power Gain
Gain in an amplifier plays an important role in the design process. If we want to use the
unilateral assumption and unilateral gain equations, we need to determine the error
involved in our analysis by checking the unilateral figure of merit (U).
S12 S21 S11 S22

U=

(1|S11 |2 )(1|S22 |2 )

1
(1+U)2

GT
GTmax

(1U)2 ,

The two types of design are :

a) Unilateral Design.
b) Bilateral Design.

a) Unilateral Design
For unilateral design of an amplifier, G

GT
TUmax

(in dB) must be in a tolerable error range. If it

is in a tolerable error range, then the design formulas simplified in a unilateral fashion. For
maximum gain design, we can write:

S = S11

L = S22

The maximum transducer gain of the amplifier, is given by:

GTU max =

1
1|S11

|2

||S12 | 1|

2
S22 |

b) Bilateral Design
In this case, the equations for conjugately matched conditions are:
S = IN

(2.1)

L = OUT

(2.2)

These two equations provide the following solution :

b1 b1 2 4 |c1 |2
MS =

2c1

b2
ML =

b2 2 4 |c2 |2
2c2

Where,
b1 = 1 + |S11 |2 |S22 |2 ||

b = 1 + |S22 |2 |S11 |2 ||
c1 = S11 S22
c2 = S22 S11

The total transducer gain is given by :

GT,max =

1
1|MS

1|

ML
||S |
|2 12 |1

|2
2

ML S22 |

2.8: Matching Network Design

General Design Rules for Matching Network:
1- Use the ZY- Smith chart at all times for simplicity.
2- Always start from the Load side to Generator side.
3- Move on the Constant R or G circles to reach the center.
4- Moving on R gives a series reactive element.
5- Moving on the G gives shunt reactive element.
6- Moving on upward gives a series or shunt inductor.
7- Moving on downward gives a series or shunt capacitor.

10

CHAPTER 3 DESIGN PROCEDURE

In this chapter the design steps are clearly shown.
3.1: DC Biasing of FET
Saturation region current, iDsat , remains constant for values of VDS (VDS )min, therefore
its value can be found from the triode region by simply substituting (VDS )min for (VDS )
which yields [3].
iDsat = k (VGS Vt )2
Where k =

IDSS
V2t

(3. 1)

and IDSS is drain current when VGS = 0

Thus we can see that in saturation region, equation 3.1 provides a drain current value
which is independent of the drain to source voltage (VDS ) but only dependent upon the
gate- to- source voltage (VGS ).
From the data sheet we find IDSS = 40mA and Vt = 0.7 V thus we can find k as follows:
40

k = 0.72 = 81.63

mA
V2

Solving equation 3.1 gives:

VGS = 0.3 or 1.04 V
Since VGS must be always greater than Vt , then VGS = 0.3 V is the solution of interest.
3.2: K- Test
At 10 GHz the selected FET transistor has the following S-parameters.

11

[S]

[0.538129.7
4.07047.4

0.09410.7 ]
0.27095.5

Now we need to check the transistor stability condition, using K- Test.

= S11 S22 S12 S21
= 0.145134.8 0.3858.1
= 0.37 144.05
And,

K=

1+| |2 | S11 |2 |S22 |2

2 |S12 S21 |

[2]

K=1.02
Therefore the transistor is unconditionally stable.
3.3: Single Stage Amplifier Design
The Minimum Noise Amplifier (MNA) is the special case of the Low-Noise Amplifier
(LNA) design. In the MNA stage, the noise figure is obtained when s = 0pt , which
gives a noise figure equal to the Fmin [1].
s = 0pt = 0.3897
L = 0ut

L = ( S22

S12 S21 0pt

+
)
1 S11 0pt

0.145155.1
L = ( 0.27095.5 +
)
1 (0.2037.7 )

L = 0.245134.30
12

GT can be now calculated as :

GT = |1.1687||16.56||1.055|
GT = 20.06 = 13.15 dB
Using established techniques, the input and output matching can be realized by plotting s
for input matching network and plotting L for the output matching network.

13

3.3.1: Input Matching Network for MNA

Plot s for input matching network as shown in figure 3.1.

Figure 3.1 Input Matching Network (MNA)

14

1
0.7
=
jLp
50

Lp =

50
0.7 x 2 x 3.14 x 10 x 109

Lp = 1.137 nH

jLs = 0.14 x 50

Ls =

0.14 x 50
2 x 3.14 x 10 x 109

Ls = 0.111 nH

15

3.3.2: Output Matching Network for MNA

Plot L for the output matching network as shown in figure 3.2.

Figure 3.2 Output Matching Network (MNA)

16

jLs = 0.14 x 50

Ls =

0.73 x 50
2 x 3.14 x 10 x 109

Ls = 0.58 nH

jCp =

Cp =

0.7
50

0.7
50 x 2 x 3.14 x 1010

Cp = 0.222 pF
The second stage of the amplifier is the same as the first stage with a gain of 13.15dB and a noise
figure equal to 0.43dB.

17

3.4: Maximum Gain Amplifier Design

The Maximum Gain Amplifier (MGA) is the special case of the High-Gain Amplifier
(HGA). The gain circles are reduced to a single point to obtain the maximum gain [1].
L = OUT
S = IN
Check for Unilateral Design
For our design we must calculate the unilateral figure of merit (U) :
S12 S21 S11 S22

U=

(1|S11 |2 )(1|S22 |2 )

(0.094)(4.070)(0.538)(0.270)

U=

(1(0.538)2 )(1(0.270)2 )

U = 0.083
1
(1+U)2

1
(1+0.083)2

0.85

GT

GTmax

(1U)2

GT
GTmax

GT
GTmax

(10.083)2

0.681

s = s11
= 0.538129.7

L = s22
= 0.27095.5

The gain of the amplifier is given by:

GTU max =

1
1|S11 |2

||S12 | 1|

2
S22 |

18

GTU max =

1
1
|16.56|
1 0.289
1 0.0729

GTU max = 25.189 = 14.01dB

If we consider approximately 0.85dB error as acceptable relative to GTU max = 14.01, then
we can use the unilateral assumption.
Now we have to design the matching network for the Maximum Gain Amplifier by plotting

S which is equal to S11

for the input matching network and plotting L which is equal to

S22
for the output matching network.

19

3.4.1: Input Matching Network for MGA

Plot the conjugate of S that is equal to S11

for the input matching network as shown in

figure 3.3.

Figure 3.3 Input Matching Network (MGA)

20

jLs = 0.91 x 50

Ls = 0.724 nH

jCp =

j 1.35
50

Cp = 0.42 pF

21

3.4.2: Output Matching Network for MGA

Plot the conjugate of L that is equal to the S22

for the output matching network as shown
in figure 3.4.

Figure 3.4 Output Matching Network (MGA)

22

1
j x 0.47
=
jLp
50

Lp =

50
0.47 x 2 x 3.14 x 1010

Lp = 1.69 nH

jLs = j x 0.10 x 50

Ls = 0.0796 nH

Now we have to calculate the noise figure of the Maximum Gain Amplifier
From the data sheet of the transistor we have:

rn =

Rn
= 0.11
Zo

Fmin = 0.43dB

F = Fmin +

4rn N
2

|1 + opt |
2

|s opt |
N=
1 |s |2
s = S11
L = S22

N=

|0.29172.95|2
1 0.289

N = 0.118

23

F = 1.104 +

4(0.11)(0.118)
1.04

F = 1.154 = 0.62dB

3.5: Total Power Gain

The Gain of the overall amplifier is the gain of all three stages i.e.
Gain Total = Gain of MNA (first) + Gain of MNA (second) + Gain of MGA (third)
=13.15 + 13.15 + 14.01
= 40.31dB
3.6: Noise Figure of the Cascaded Amplifier
The overall noise figure of an amplifier is the cascade of noise figures of the three stages,
i.e. two MNA stages and one MGA stage.
The noise figure for each of the MNA is Fmin , which is equal to 0.43dB, or 1.104. The
noise figure of the MGA stage is 0.62dB, or 1.153 in ratio, which will provide Ftotal as:
F1 = Noise figure of first stage (MNA) = 1.104 = 0.43dB
F2 = Noise figure of second stage (MNA) = 1.104 = 0.43dB
F3 = Noise figure of third stage (MGA) = 1.154 = 0.62dB

Ftotal = F1 +

F2 1 F3 1
+
G1
G1 G2

Ftotal = 1.104 +

1.104 1 1.153 1
+
20.19
20.192

Ftotal = 1.1095 = 0.4512dB.

24

CHAPTER 4 AMPLIFIER DESIGN USING ADS SOFTWARE

4.1: Analyzing Transistor
Carrying out a complete research of modern transistors, we found a Hetero-Junction FET
from the NEC Corporation (NE4210S01). NE4210S01 is an ultra-low noise FET which
was found to fit our needs. This transistor operated at an optimal Q point (VDS =2V and
IDS = 10 mA). We simulated the transistor and compared the results with the data-sheet to
verify if the device was performing as it was described. Figure 4.1 is the transistor model
in ADS.

Figure 4.1 Transistor NE4210S01 in ADS

25

Figure 4.2 Verifying S-Parameters

In the above figure (see Figure. 4.2) 50 ohms, terminations are connected and simulated to
verify the data from the data-sheet of the transistor. We used the settings tab for Sparameters from the data S2p file, frequency, temperature, etc. The simulation result is
shown in figure (see Figure. 4.3, Figure. 4.4) which was verified by the data sheet as well
as with the s2p file.

26

Figure 4.3 S-Parameters

Figure 4.4 Noise Parameters

Figure 4.5 Simulation for K Stability Factor

27

Figure 4.6 Output Result for K in ADS

After simulation K is found to be 1.019, which is approximately equal to the result that we
calculated earlier (1.02).
The input stability and output stability circles are plotted and are completely outside of the
Smith Chart as shown in figure 4.7. Thus the unconditional stability was confirmed using
ADS by plotting stability circles.

28

Figure 4.7 Input and Output Stability after Simulation

Our design consists of three stages. The first two stages consist of the Minimum Noise
Amplifier (MNA), and the third stage is the Maximum Gain Amplifier (MGA).
4.2: Single Stage Amplifier Design
This is the first stage of the amplifier i.e. the MNA design.

29

Figure 4.8 Minimum Noise Amplifier in ADS

The above is the single-stage Minimum Noise Amplifier in ADS. It is expected that when
we simulate this circuit it must match the values obtained by the hand calculations, i.e.
Noise Figure must be equal to the Fmin. To simulate this design the simulator temperature
must be set to 16.85 .
4.2.1: Simulation Result for Single Stage MNA
After designing the single-stage amplifier we found the noise figure to be 0.43 dB with a
gain of 13.349dB, as shown in figure 4.9.

30

Figure 4.9 Output Result When Simulated (MNA)

Figure 4.10 Output Result of Gain, Noise and K

According to the simulation result the noise figure is 0.43dB for this design, which is very
close to Fmin value of the transistor.

31

4.3: Designing of the Second Stage

In this design, the second stage is also a Minimum Noise Amplifier, which is the same as
the first-stage design. Figure 4.11 shows the design of two cascaded stage in ADS software.

Figure 4.11 Two Stage Amplifier

32

4.3.1: Simulation Result for Two Stages

The figure 4.12 shows the gain and the cascade noise figure of the two stages.

Figure 4.12 Noise Figure and Gain Output

33

Figure 4.13 ADS Result of Two Stage

34

4.4: MGA Design in ADS Software

In the first two stages we concentrated on reducing the noise figure and in the third stage,
we focus on increasing the gain. MGA design is shown in figure 4.14.

Figure 4.14 MGA in ADS

35

4.4.1: Simulation Result for Maximum Gain Amplifier

The figure 4.15 and 4.16 shows the simulation result for the gain and the noise figure values
for the Maximum Gain Amplifier.

Figure 4.15 Noise Figure Output in ADS (MGA)

Figure 4.16 Gain Output in ADS (MGA)

36

4.5: Overall Design of Three Stage Amplifier in ADS Software

This design is the cascade of all three stages with first two MNA stages and the third
stage as an MGA as shown in figure 4.17.

Figure 4.17 Three Stage Amplifier in ADS

37

4.6: Simulation Result of Three Stage Amplifier

The simulation result shows the cascaded noise figure and the gain for the three stages as
shown in figure 4.18.

38

Figure 4.18 Three Stage Amplifier Output in ADS.

4.7: Optimization of the circuit
To achieve the goal, we must optimize the design.
a- Setup the goal to the required VSWR and the Power Gain as shown in figure 4.19.
b- Simulate the circuit.
Setting up the goal.

Figure 4.19 Setting the Goal.

The simulation result for optimization circuit are shown in figure 4.20.

39

Figure 4.20 Optimization Result.

40

Simulation result of the VSWR after optimization of the circuit as shown in figure 4.21.

Figure 4.21 Input VSWR Result.

Note- After optimization the values of the matching network and the temperature
slightly changes.
4.8: MATLAB Program for Overall Calculation
% 3-stage Amplifer Design
% Chair-Matthew Radmanesh
% By Pramod Sangameshwar Reddy Ankatala
% CSUN ID 105892525
% Program for all 41verall41ion
% Initialing S matrix
S =[ 0.538*exp(-1i*pi*129.7/180),0.094*exp(1i*pi*10.7/180);4.07*exp(1i*pi*47.4/180),0.270*exp(1i*pi*95.5/180)];
%computing Delta
Delta = det(S);
disp([The value of Delta num2str(abs(Delta)) , phase value is num2str(angle(Delta)*180/pi)
degrees]);
a = (S(2,1))*(S(1,2));
disp([The value of a num2str(abs(a))]);
k =1.02;

41

disp([The value of K is num2str(k)]);

% k>1,|Delta|<1
% computing u
u =(abs(S(1,2))*abs(S(1,1))*abs(S(2,2))*abs(S(2,1)))/((1-abs(S(1,1))^2)*(1-abs(S(2,2))^2));
disp([The value of u is num2str(abs(u)) ]);
% compute limits of G_T/G_TuMax
lowerLim = 1/(1+u)^2;
disp([The value of lowerLim num2str(lowerLim)]);
upperLim = 1/(1-u)^2;
disp([The value of upperLim num2str(upperLim)]);
%% MGA
B1 = 1+(abs(S(1,1)))^2-(abs(S(2,2)))^2-abs(Delta);
disp([Magnitude of B1 is num2str(abs(B1)) ]);
B2 = 1+abs(S(2,2))^2-abs(S(1,1))^2-abs(Delta);
disp([Magnitude of B2 is num2str(abs(B2)) ]);
C1 = S(1,1)-Delta*conj(S(2,2));
disp([Magnitude of C1 is num2str(abs(C1)) , phase value is num2str(angle(C1)*180/pi) degrees]);
C2 = S(2,2)-Delta*conj(S(1,1));
disp([Magnitude of C2 is num2str(abs(C2)) , phase value is num2str(angle(C2)*180/pi) degrees]);
GammaMS =(B1-sqrt(B1^2-4*abs(C1)^2))/(2*C1);
disp([Magnitude of GammaMS is num2str(abs(GammaMS)) , phase value is
num2str(angle(GammaMS)*180/pi) degrees]);
GammaML =(B2-sqrt(B2^2-4*abs(C2)^2))/(2*C2);
disp([Magnitude of GammaML is num2str(abs(GammaML)) , phase value is
num2str(angle(GammaML)*180/pi) degrees]);
Gtmax1 = (1/(1-abs(GammaMS)))*abs(S(2,1))^2*(1-abs(GammaML)^2)/abs(1-S(2,2)*GammaML)^2;
disp([Magnitude of Gtmax1 is num2str(abs(Gtmax1)) ]);
Gtmax2 = (1/(1-abs(S(1,1))^2))*(abs(S(2,1))^2)*(1/(1-abs(S(2,2))^2));
disp([The value Gtmax2 in unilateral is num2str(abs(Gtmax2)) ]);
Gainmax=10*log10(Gtmax2);
disp([The value of Gainmax= num2str(Gainmax)]);
%% MNA
GammaS=0.38*exp(1i*pi*97/180);
Gammal=(S(2,2))+((S(1,2))*(S(2,1))*(GammaS))/(1-(S(1,1))*(GammaS));
%% The Gammal which we get the output is the conjugate
disp([The value gammal is num2str(abs(Gammal)) , phase value is num2str(angle(Gammal)*180/pi)
degrees]);
disp([This Gammal value must be conjugated in order to calculate gain because Gammal=
conj(GammaOUT)]);
GammaL=0.246*exp(-1i*pi*134.30/180);
disp([The value GammaL is num2str(abs(GammaL)) , phase value is
num2str(angle(GammaL)*180/pi) degrees]);
%% In the Calculation of Gain its take as Conjugate because the Gammal which we found is the conjugate
i.e Gammal= conj(GammaOUT)

42

GmaxT= (1/(1-(abs(GammaS))^2))*(abs(S(2,1))^2)*(1-conj(abs(Gammal))^2)/(abs(1(S(2,2))*conj(Gammal)))^2;
disp([The value of GmaxT is num2str(abs(GmaxT)) ]);
Gainmin=10*log10(GmaxT);
disp([The value of Gainmin= num2str(Gainmin)]);
vswr=1.182;
disp([The value of VSWR = is num2str(vswr) ]);
% The Noise Figure Of the 3 stage Amplifer at 10 Ghz frequency.
S=[0.538*exp(-1i*pi*129.7/180),0.094*exp(1i*pi*10.7/180),4.070*exp(1i*pi*47.4/180),0.270*exp(1i*pi*95.5/180)];
% The above are the s-parameters of the transistor at 10 Ghz frequency.
GammaS=0.538*exp(1i*pi*129.7/180);
% The GammaS is the conjugate of the S11.
GammaOPT=0.38*exp(1i*pi*97/180);
% The GammaOPT is the value taken from the transistor.
FmindB=0.43;
Fmin=((10)^((FmindB)/(10)));
% The Fmin is the value of transistor minimum noise at 10Ghz.
% Actually the value of Fmin is 0.43 db wnen converted its 1.104
disp([minimum noise in Ratio= num2str(Fmin)]);
% The N is the 43verall noise figure calculated.
N =((0.299)^2)/(0.799);
disp([The value of N= num2str(N)]);
% The F is the Noise Figure of the transistor.
% Where rn is equal to 0.11.
a=(Fmin);
b=((4)*(0.11)*(N));
c=((1.02)^2);
F=((a)+((b)/(c)));
disp([The value of F= num2str(F)]);
% The F1 is the noise figure of the 1st stage ie for MNA.
% The GammaS = GammaOPT in MNA design because of that Noise figue of the
% MNA is equal to Fmin.
F1=1.104;
F2=1.104;
F3=F;
% The Ga1, Ga2 is the Gain of the first 2 stages in ratio.
Ga1=GmaxT;
Ga2=GmaxT;
% Ftotal is the noise figure of 3 stage After Cascading.
A= (F1);
disp([The value of A= num2str(A)]);
B=((F2-1)/(GmaxT));
disp([The value of B= num2str(B)]);
C=(F3-1)/((GmaxT)^2);
disp([The value of C= num2str]);
Ftotal=A+B+C;
disp([The value of Ftotal=A+B+C= num2str(Ftotal)]);
Ft=10*log10(Ftotal);
disp([The value of Ft= num2str(Ft)]);
Totalpowergain = (2*Gainmin)+(Gainmax);
disp([The value of Total power gain = num2str(Totalpowergain)]);

43

Output of Simulation
The value of Delta0.37669 , phase value is -143.9413 degrees
The value of a0.38258
The value of K is1.02
The value of u is 0.084361
The value of lowerLim0.85046
The value of upperLim1.1928
Magnitude of B1 is 0.83985
Magnitude of B2 is 0.40676
Magnitude of C1 is 0.53212 , phase value is -140.5894 degrees
Magnitude of C2 is 0.31199 , phase value is -135.4429 degrees
Magnitude of GammaMS is 1 , phase value is 102.6953 degrees
Magnitude of GammaML is 1 , phase value is 86.126 degrees
Magnitude of Gtmax1 is NaN
The value Gtmax2 in unilateral is 25.1457
The value gammal is0.24602 , phase value is -134.5758 degrees
This Gammal value must be conjugated in order to calculate gain because Gammal= conj(GammaOUT)
The value GammaL is0.246 , phase value is -134.3 degrees
The value of GmaxT is 20.181

minimum noise in Ratio=1.1041

The value of N=0.11189
The value of F=1.1514
The value of A=1.104
The value of B=0.0051533
The value of C=0.00037174
The value of Ftotal=A+B+C=1.1095

44

CHAPTER 5: CONCLUSION
We have successfully designed a three-stage low noise amplifier. The amplifier design uses
a NE4210S01 Hetro Junction FET with lumped elements to implement the matching
networks. For simulating the three-stage amplifier, we used the Agilent ADS software. The
ADS provided an efficient method to design and tackle the simulation problem. The Matlab
was also used to write a program for all equations such as gain, noise figure, etc. In this
design, we obtained a power gain of 40.70dB and a noise figure of 0.45dB. The VSWR
was also satisfactory and within limits. This met our design requirements as specified in
chapter 1. We designed a stable amplifier for each stage by insuring that the transistor was
un-conditionally stable.
In conclusion, the time spent on the design process of a microwave amplifier using
the ADS tool proved to be a great experience for future design endeavors.

45

5.1: Design Results

The table 5.1 shows the design results from the simulations, MATLAB.
Parameters

Goal

Hand

Matlab

Simulation

calculation

Results

using ADS

Frequency(GHz)

10

10

10

10

Power Gain(dB)

30

40.31

40.1

40.69

Noise Figure(dB)

1.5

0.45

0.45

0.45

Bandwidth (GHz)

9.5-10.5

9.5-10.5

9.5-10.5

9.5-10.5

Input VSWR

< 1.5

1.19

1.18

1.16

Table 5.1 Results

46

REFERENCES
[1] Radmanesh, M. M. RF & Microwave Design Essentials, AuthorHouse, pp. 357-373,
2007.
[2] Radmanesh, M. M. RF & Microwave Design Essentials, AuthorHouse, pp. 286-356,
2007.
[3] Radmanesh, M. M. RF & Microwave Design Essentials, AuthorHouse, pp. 174-188,
2007.

47

APPINDEX

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