2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design

(SMACD)

Automatic Common-Centroid Layout Generation for

Binary-Weighted Capacitors in Charge-Scaling DAC
Wei-Hao Hsiao1 , Yi-Ting He1 , Mark Po-Hung Lin1 , Rong-Guey Chang2,3, and Shuenn-Yuh Lee1
Department of Electrical Engineering1
Department of Computer Science and Information Engineering2
Advanced Institute of Manufacturing with High-tech Innovations3
National Chung Cheng University
Chiayi 621, Taiwan

AbstractAs the precision of the capacitance ratios among

binary-weighted capacitors is the key to accuracy/performance
of charge-scaling digital-to-analog converters, it is very important
to generate a highly matched common-centroid layout with minimum routing-induced parasitics. However, most of the previous
works only focused on common-centroid placement optimization
with the consideration of random and systematic mismatch.
This paper introduces a novel common-centroid capacitor layout generation approach to minimize the parasitic impact on
circuit accuracy/performance. Experimental results show that,
compared with the manual layout, the layout generated by the
presented approach can achieve even smaller layout area and
better circuit accuracy/performance within much shorter time.




2




2




I. I NTRODUCTION
The binary-weighted charge-scaling digital-to-analog converter (DAC) [6], as seen in Fig. 1(a), is one of the most
widely used data converters in modern system-on-chip (SoC)
applications. As the precision of the capacitance ratios among
binary-weighted capacitors in the DAC is the key to circuit accuracy/performance, it is very important to generate
a highly matched common-centroid layout with minimum
routing-induced parasitic capacitance. However, there has been
no automatic common-centroid capacitor layout generation
tool which consider the routing-induced parasitic capacitance within the binary-weighted capacitors, as shown in
Fig. 1(b). The layout generation process is still a manual,
time-consuming, and error-prone task, especially when the bit
number of the DAC in Fig. 1 is larger than 6 bits.
A. Previous Work
The common-centroid placement approaches have been
extensively studied in the literature [2], [9][11], [13][15],
[20], [21], [24]. To evaluate the matching quality of a commoncentroid placement, the oxide gradient model [20] and the
spacial correlation model [2], [13] were proposed to quantify
systematic and random mismatch, respectively. Most of the
previous works proposed their algorithms to minimize only
systematic mismatch, while the most recent work [10] introduced a more effective placement approach which simultaneously minimizes random and systematic mismatch. Fig. 2(a)
shows the resulting common-centroid placement considering
only systematic mismatch, while Fig. 2(b) shows a more

978-1-4673-0686-7/12/$31.00 2012 IEEE

Fig. 1. (a) A charge-scaling DAC circuit with binary-weighted capacitors.

(b) The equivalent DAC circuit containing parasitic capacitors around the
binary-weighted capacitors after post-layout parasitic extraction.

sophisticated common-centroid placement considering both

random and systematic mismatch.
For common-centroid capacitor routing, although some previous works [7], [17], [20] briefed the routing guidelines, such
as matching the wirelength with respect to the corresponding
capacitor ratio, and avoiding coupling between wires connecting to the top and bottom plates of the ratioed capacitors, none
of the previous works presented any detailed routing algorithm to optimize the routing within a common-centroid unitcapacitor array based on those guidelines. It should be noted
that the routing quality correlates closely with the placement
topology. It is also required to additionally consider the routing
quality during common-centroid placement in addition to the
minimization of random and systematic mismatch [14].
B. Our Contributions
We propose a complete automatic layout design ow and
the corresponding algorithms for binary-weighted capacitors in
charge-scaling DACs. In addition to minimizing random and

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Capacitor netlist &

Process technology file

Simultaneous Placement &

Global Routing
Common-Centroid
Placement

Common-Centroid
Detailed Routing

Common-Centroid
Global Routing

Parasitic
Trimming/Opt.

Cost Evaluation

INL/DNL Analysis

Good enough?

Good enough?

Fig. 2.
Two different unit-capacitor placements of the binary-weighted
capacitors in an 8-bit charge-scaling DAC, where the number on each unitcapacitor corresponds to the bit number in the DAC, and D denotes
a dummy. (a) A simple common-centroid placement for minimization of
systematic mismatch. (b) A sophisticated common-centroid placement for
minimization of both random and systematic mismatch.

systematic mismatch, we further reduce routing-induced parasitics during common-centroid placement optimization. We
optimize the routing-induced parasitics at the detailed-routing
stage to further improve the circuit accuracy/performance.
Experimental results show that, compared with the manual
layout, the layout generated by our approach can achieve even
smaller layout area and better circuit accuracy/performance
within much shorter time.
The remainder of this paper is organized as follows. Section II introduce the ow and algorithms. Section III reports
the experimental results, and Section IV concludes this paper.
II. T HE F LOW

Detailed Routing &

Parasitic Trimming/Opt.

AND

Optimized Common-Centroid
Capacitor Layout
Fig. 3. The proposed binary-weighted capacitors array of charge-scaling
DAC generation ow.


 
 




 
 




A LGORITHMS

Inputting the netlist of binary-weighted capacitors in a

charge-scaling DAC, as seen in Fig. 1(a), and the process
technology le, we propose the common-centroid layout generation ow for the binary-weighted capacitors, as shown in
Fig. 3, which consists of two major steps: (1) simultaneous
placement and global routing, and (2) detailed routing and
parasitic trimming/optimization.

 
 

 
 

Fig. 4. Different placement styles of the unit capacitors of the 4th bit
in the charge-scaling DAC, and the corresponding routing topologies. (a)
Disconnected unit capacitors. (b) Connected unit capacitors. (c) Distributed
connected unit capacitors.

A. Simultaneous Placement and Global Routing

We adopt the pair-sequence representation [10] and the
simulated-annealing algorithm [8] to nd an optimal commoncentroid placement of a unit-capacitor array. During the placement iterations, we additionally perform global routing to
evaluate the routing quality according to the probable routinginduced parasitics, in addition to evaluating the random and
systematic mismatch based on the oxide-gradient model and
the spacial correlation model.
Fig. 4 shows three different placement styles of the unit
capacitors of the 4th bit in the charge-scaling DAC. Although
the placement style in Fig. 4(a) results in better random
and systematic mismatch compared with those in Figs. 4(b)
and (c), it induces much more parasitics. The placement
style in Fig. 4(c) leads to better random and systematic
mismatch while inducing similar parasitics compared with that
in Fig. 4(b). We design our cost function to generate the
placement style in Fig. 4(c).

The cost function, , of a common-centroid placement is

dened in Equation (1), where M and are the oxide-gradient
induced mismatch [20] and overall correlation coefcient [13],
respectively, R is the routing cost, and and are userspecied parameters between 0 and 1. The routing cost is
proportional to the total wirelength and the length of close
parallel wires. We minimize during placement iterations
while maintaining the average value of M , , and R, which
are denoted by Mavg , avg , and Ravg , respectively.
=

M Mavg
avg
R Ravg
+
+(1)
Mavg
avg
Ravg
(1)

B. Detailed Routing and Parasitic Optimization

After obtaining the optimized common-centroid placement
and global routing, we perform detailed routing to connect the

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top (bottom) plate of each unit capacitor to its adjacent unit

capacitors belonging to the same bit in the DAC, or to the
corresponding routing track in the adjacent channel determined
by global routing. Fig. 5(a) shows an example detailed routing
result and the corresponding routing-induced parasitics, where
Ctb denotes the parasitic capacitance between the top and
bottom plates of the unit capacitors, Cbb denotes the parasitic capacitance between the bottom plates of different unit
capacitors, and Ct (Cb ) denotes the parasitic capacitance
between the top (bottom) plate of the unit capacitors and the
substrate, as demonstrated in Fig. 1(b).

 
 
 

DAC bit number &

Process technology file

C++ / Qt
Simultaneous Placement &
Global Routing

Detail Routing & Parasitic

Trimming/Opt.

Common-centroid Cap. P&R

Layout SKILL files (*.il)

Virtuoso

Load SKILL File (*.il)

Run DRC/LVS/PEX

Fig. 5. (a) An example detail routing for a portion of a common-centroid unitcapacitor array and the corresponding parasitic capacitance. (b) The improved
routing after parasitic trimming and optimization

Netlist & PEX files

(*.netlist), (*.pex), (*.pxi)

According to [6], [19], we analyze the accuracy/performance of the DAC in terms of the differential
non-linearity (DNL) and integral non-linearity (INL) with
the consideration of routing-induced parasitics. The parasitic
capacitance of Ctb and Ct has much greater impact on
circuit accuracy/performance than that of Cbb and Cb .
Therefore, we shall further perform parasitic trimming and
optimization for Ctb and Ct .
We apply wire sizing and relocation for the wire segments
connecting adjacent unit-capacitors to adjust Ctb and minimize Ct based on the genetic algorithm (GA) [4]. For each
iteration, we randomly choose a set of common-centroid wire
segment pairs in the unit-capacitor array, resize/relocate the
chosen wire segments, and perform DNL/INL analysis based
on the updated parasitic capacitance. Fig. 5(b) shows the
improved routing after parasitic trimming and optimization.

HSPICE
Combine netlist/parasitics

Perform post-simulation

Simulation output file (*.lis)

MATLAB
Calculate DNL, INL, SNDR

Optimized layout
with verified specifications

III. E XPERIMENTAL R ESULTS

We implemented our ow and algorithms in the C++
programming language and executed on a 2.26GHz Intel Xeon
machine under the Linux operating system. A graphical user
interface (GUI) of our program was also built up using the
Qt library [18]. We externally linked our program with the
commercial layout editor, Virtuoso [1], to perform design rule
checks (DRC), Layout Versus Schematic (LVS) verication,
and parasitic extraction (PEX). We combined the extracted
parasitics with the original DAC netlist and performed the
post-layout simulation using HSPICE [22]. Based on the
simulation results, we calculated the DNL, INL, and SNDR of
the DAC using MATLAB [16]. Fig. 6 demonstrates the whole
experimental ow.

Fig. 6.

The experimental ow.

We experimentally tested our algorithms on the chargescaling DAC, as seen in Fig. 1, ranging from 6 bits to 8 bits
based on the TSMC 0.18m process technology [23]. For each
case, the capacitance value of each unit capacitor is 100fF. The
resulting capacitor layout area, DNL, INL, signal-to-noise ratio
(SNR), signal-to-noise and distortion ratio (SNDR), effective
number of bits (ENOB), and runtime for each case are shown
in Table I. For DNL and INL, the difference between the
maximum and minimum values must be less than 1 least
signicant bit (LSB) [6], [19]. For SNR, SNDR, and ENOB,

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TABLE I
T HE RESULTING CAPACITOR LAYOUT AREA , CIRCUIT ACCURACY / PERFORMANCE , AND RUNTIME FOR THE CHARGE - SCALING DAC RANGING FROM 6 TO
8 BITS BASED ON OUR ALGORITHMS .
Case
DAC 6b
DAC 7b
DAC 8b

Area
(m2 )
13282
27423
53230

DNL / INL(LSB)
|Max Min|

0.110 / 0.102
0.162 / 0.154
0.241 / 0.230

SNR / SNRideal
(dB)
37.83 / 37.88
43.95 / 43.90
49.91 / 49.92

SNDR / SNDRideal
(dB)
37.48 / 37.88
43.59 / 43.90
49.57 / 49.92

ENOB / ENOBideal
(bits)
5.93 / 6
6.95 / 7
7.94 / 8

Time
(s)
1.1
2.2
4.9

TABLE II
C OMPARISON OF THE CAPACITOR LAYOUTS AND CIRCUIT PERFORMANCE OF THE 8- BIT CHARGE - SCALING DAC BASED ON MANUAL LAYOUT DESIGN
AND THE PROPOSED LAYOUT AUTOMATION TOOL .
Case
DAC 8b

Area
(m2 )
58397

Manual Layout
DNL / INL(LSB)
SNR
SNDR
|Max Min|
(dB)
(dB)
0.246 / 0.292
49.71
49.49

ENOB
(bits)
7.93

Time
(hr)
>12

Area
(m2 )
53230

our results in each case are very close to the ideal values [6],
[19]. It takes only 10 seconds to complete the capacitor layout
of the 9-bit DAC.
We further compared our results of the 8-bit charge-scaling
DAC with the results based on the manual design, as seen
in Table II. The results show that the layout generated by
our algorithms can achieve even smaller layout area and
better circuit accuracy/performance within much shorter time.
Figs. 7(a) and (b) shows the 8-bit DAC layouts generated by
manual design and our approach, respectively.

Fig. 7.

The 8-bit DAC layouts. (a) Manual design. (b) Our approach.

IV. C ONCLUSION
In this paper, we have presented and implemented a novel
automatic common-centroid layout generation tool for binaryweighted capacitors in charge-scaling DACs. We have also
proposed common-centroid placement and routing algorithms
with the consideration of both device matching and parasitic
optimization. The experimental results have shown that the
layout generated by our tool can achieve even smaller layout
area and better circuit accuracy/performance within much
shorter time.
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|Max Min|

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Our Tool
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ENOB
(dB)
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Tool Setup Time

(min)
<5

Runtime
(s)
4.9

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