VLSI DESIGN LAB

LAB FILE

RISHAV GUPTA
SID: 13105078
4TH YEAR
ECE
PEC UNIVERSITY OF
TECHNOLOGY

EXPERIMENT NO. 8
AIM: Basic Introduction of VHDL
VHDL (VHSIC Hardware Description Language) is a hardware description
language used
in electronic
design
automation to
describe digital and mixed-signal systems such as field-programmable
gate arrays and integrated circuits. VHDL can also be used as a general
purpose parallel programming language.
VHDL is commonly used to write text models that describe a logic circuit.
Such a model is processed by a synthesis program, only if it is part of the
logic design. A simulation program is used to test the logic design using
simulation models to represent the logic circuits that interface to the
design. This collection of simulation models is commonly called
a testbench.
VHDL has constructs to handle the parallelism inherent in hardware
designs, but these constructs (processes) differ in syntax from the parallel
constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case
sensitive. In order to directly represent operations which are common in
hardware, there are many features of VHDL which are not found in Ada,
such as an extended set of Boolean operators including nand and nor.
VHDL also allows arrays to be indexed in either ascending or descending
direction; both conventions are used in hardware, whereas in Ada and
most programming languages only ascending indexing is available.
The key advantage of VHDL, when used for systems design, is that it
allows the behavior of the required system to be described (modeled) and
verified (simulated) before synthesis tools translate the design into real
hardware (gates and wires). Another benefit is that VHDL allows the
description of a concurrent system. VHDL is a dataflow language, unlike
procedural computing languages such as BASIC, C, and assembly code,
which all run sequentially, one instruction at a time. A VHDL project is
multipurpose. Being created once, a calculation block can be used in
many other projects. However, many formational and functional block
parameters can be tuned (capacity parameters, memory size, element
base, block composition and interconnection structure). A VHDL project is
portable. Being created for one element base, a computing device project

can be ported on another element base, for example VLSI with various
technologies.

EXPERIMENT NO. 9
AIM: Simulate the basic gates in Xilinx.
1. AND Gate
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity and12 is
Port ( a,b : in std_logic;
y : out std_logic);
end and12;
architecture Behavioral of and12 is
begin
y<= a and b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

2. OR Gate

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity or12 is
Port ( a,b : in std_logic;
y : out std_logic);
end or12;
architecture Behavioral of or12 is
begin
y <= a or b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

3. NAND Gate
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity nand12 is
Port ( a,b : in std_logic;
y : out std_logic);
end nand12;
architecture Behavioral of nand12 is
begin
y <= a nand b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

4. NOR Gate
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity nor12 is
Port ( a,b : in std_logic;
y : out std_logic);
end nor12;
architecture Behavioral of nor12 is
begin
y <= a nor b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

5. XOR Gate
CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity xor12 is
Port ( a,b : in std_logic;
y : out std_logic);
end xor12;
architecture Behavioral of xor12 is
begin
y <= a xor b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

6. XNOR Gate
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity xnor12 is
Port ( a,b : in std_logic;
y : out std_logic);
end xnor12;
architecture Behavioral of xnor12 is
begin
y <= a xnor b;
end Behavioral;

OUTPUT 1:

OUTPUT 2:

EXPERIMENT NO. 10
AIM: Simulate Half Adder and Full Adder in Xilinx.

Half Adder

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity half_add_1 is
Port ( x,y : in std_logic;
s,c : out std_logic);
end half_add_1;
architecture Behavioral of half_add_1 is
begin
s <= x xor y;
c <= x and y;
end Behavioral;

OUTPUT:

Full Adder

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_add_1 is
Port ( x,y,z : in std_logic;
s,c : out std_logic;
w,q,r : inout std_logic);
end full_add_1;
architecture Behavioral of full_add_1 is
begin
w <= x xor y;
q <= x and y;
s <= w xor z;
r <= w and z;
c <= q or r;
end Behavioral;

OUTPUT:

EXPERIMENT NO. 11
AIM: Simulate Half Subtractor and Full Subtractor in Xilinx.

Half Subtractor

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity half_sub1 is
Port ( x,y : in std_logic;
b,d : out std_logic);
end half_sub1;
architecture Behavioral of half_sub1 is
begin
d <= x xor y;
b <= (not x) and y;
end Behavioral;

OUTPUT:

Full Subtractor

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_sub1 is
Port ( x,y,z : in std_logic;
b,d : out std_logic);
end full_sub1;
architecture Behavioral of full_sub1 is
begin
d <= x xor y xor z;
b <= ((not x)and z) or ((not x) and y) or (y and z);
end Behavioral;

OUTPUT: