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Technical Publications

A.

P.

Goclse

D.A.Goclse

Punes

Fundamental s of HDL

ISBN 9788184314052

All righ ts reserved with Technica l Publications. No port of this book

reproduced in any form, Electronic, Mechonicol, Photocopy or ony information storage and

retrievol system without prior permis.sion in writing, from Technical Publications, Pvne.

should be

Published by :

Tuchnical Publications rune"

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Printer :

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Sr.no. 10/3,Sinlw51d Ro1d,

l\.nt • 41 1 041

Copyrighted material

Table of Contents

1.1WhyHDL?

1.2 A Brief History of HDL

1-1

1 - 2

 

1.2.1 A Brief History of VHDL

 

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1.2.2 A Brief History of Verilog HDL.

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1 - 3

1.3 Structure of the

HDL Module

 

1 - 3

 

1.3.1 Structure of the

VHDL Module

 

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1 - 3

1.3. 1.1 Package.

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1-4

1.3.1.2

Entity .

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1 -5

1.3. 1.3 Architecture

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1.3.1.4

Configuration

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1.3.2 Structure of the Verilog Module .

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1 - 9

1.4

Operators

1 - 10

1.4.1 Operators in

 

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1 -

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1.4.1.1 Logical Operators

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1.4.1.2 Relational Operators

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1.4.1.3 Arithmeti c

Operators

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1.4. 1.4 Shift and Rotate Operators .

 

1 -14

1.4.1.SOperatorPrecedence .

 

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1.4.2 Operators i n Verilog HDL

 

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1.4.2.1 Boolean Logical Operators.

 

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1.4.2.2 Unary Reduction Logical Operators

1 -1 6

1.4.2.3 Bitwise Logical Operators

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1 -16

1.4.2.4 Relational Operators

1 - 16

1.4.2.5 Binary Arithmetic Operators

1 -

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1.4.2.6 Unary Arithmetic Operators.

1 -

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1.4.2.7 Other Operators

1- 17

1.4.2.8 Operator Precedence.

1 - 18

Copyrighted material

1.5

Data Types

1 - 18

 

1.5.1 VHDL Data Types

 

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1.5.1.1 Scalar Types

 

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1.5.1.2Comoostte Types.

 

1-22

1.5.1.3AccessTypes .

 

1-25

1.5.1.4FileType

 

1-25

1.5.1.50therTypes.

1.5.2 Veri log

Data Type

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1.5.2.1 Nets (Wire) and Registers

 

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1.5.2.2 Abstract Data Types : integer, real time

 

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1.5.2.3 Parameter

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1 - 29

1.6 Styles or Types of Descriptions

 

1 - 29

 

1.6.1 Behavioral Descriptions

 

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1- 30

1.6.2 Dataflow Design Elements

 

1 - 31

1.6.3 Structural Design Elements

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1.6.4 Switch-Level Descriptions

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1.6.5 Mixed-Type Descriptions

 

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1.6.6 Mixed Language Descriptions .

 

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1.7 Simulation and Synthesis

 

1 - 36

 

1.7.1 Synthesi s

 

1 -

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1.7.2 Si mulation

1 - 37

1.8 Brief Comparison of VHDL

 

and Verilog

 

1 -

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1.9 Summary of Operators in VHDL and Verilog

 

1 - 39

Review Questions

 

1 - 4 1

2.1

 

2 .2

High Lights of Data-Flow Descripti on Structure of the Data-Flow Description

 

2 - 1 2 - 1

2.2.1 Signal Declaration and Assignment Statement

 

2 - 2

2.2.2 Execution of Assignment Statement

 

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2 -

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2.2.3 Constant Declaration and Assignment Statement

 

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2 - 4

2.3

Data Type - Vectors

 

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Review Questions

2 - 26

Copyrighted ma erial

3.1 Behavioral Description Highlights

3.2 Structure of the HDL Behavioral Description

3 - 1 3 - 1

3.3 The VHDL Variable Assignment Statement 3 - 4 3.4 Sequential Statements 3 - 4
3.3 The VHDL Variable Assignment Statement
3
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3.4 Sequential Statements
3 - 4
3.4.1 IF
3 - 4
3.4.2 Signal and Variable Assignment
3 - 10
3.4.3 Case Statement
3 -13
3.4.4 Comparison between CASE and IF Statement
3 -
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3.4.4.1
Verilog Casex and Casez
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3- 20
3.4.5 Loop Statement
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3.4.5.1 For-Loop Statement.
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3.4.5.2 While-Loop Statement.
3-23
3.4.5.3Verilog Repeat.
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3.4.5.4 Verilog
Forever
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3.4.5.5 VHDL Next and Exit
3 - 24
Review Questions
3 - 35
4.1 Highlights of Structural Description
4.2 Organization of the Structural Description
4.3 Binding
4 - 1
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4 - 4
4
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4.3.1 Binding between
Entity
and
Architecture in VHDL
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4 -
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4.3.2 Binding
between
Entity
and Component in VHDL
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4.3.3 Binding between Library and Module in
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4.3.4 Binding
between
Two Modules in Verilog
4 - 8
4.4 State Machine
4 - 36
4.4.1 Types of Sequential Circuits
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4.4.1.1
Moore Model
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4 - 37
4.4.1 .2 Mealy Model
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4.4.1.3
Moore Vs Mealy Circuit Modets
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4-40
4.4.2 State Machine Notations
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4 4 2 1 State and State Variable
4-40
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4.4.2.3

State Transition Diagram

4 - 41

4.4.2.4 State Table .

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4 -42

4.4.2.5 Transition Table .

 

4 -43

4.5 Design Equations and Circuit Diagram

4 - 43

4.6 Generate (HDL), Generic (VHDL), and Parameter (Verilog)

4 - 53

Review Questions

4 -

64

5.1 Highlights of Procedures, Tasks and Functions

5.2 Procedures and Tasks

5 - 1 5 - 1

5.2.1 Procedures (VHDL) . · . . 5 - 2 5.2.2Tasks (Verilog) . . .
5.2.1
Procedures (VHDL) .
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5.2.2Tasks (Verilog)
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5.2.3
Examples of Procedures and Tasks
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5.3 Functions
5 - 21
5.3.1 VHDL Functions
5 - 22
5.3.2 Verilog Functions
5 • 22
5.3.3 Function Examples
5 - 23
5.4 Advanced HDL Descriptions : File Processing
5 - 27
5.4.1
VHDL File Processing
5 - 27
5.4.2 Verilog File
5 - 30
5.5 Examples of File Processing
5 - 33
5.5.1 Examples of VHDL File Processing
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5 - 33
5.5.2 Example of Verilog File Processing
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5 · 40
Review Questions
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6.1 Why Mixed-Type Description?
6.2 VHDL
User-Defined Types
6.3 VHDL Package
6 - 1
6 - 1
6 - 2
6.3.1
Implementation of Arrays
6.3.1.1 Single-Dimensional Arrays in VHDL
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6 - 4
6.3.1.2 Single - Dimensional Arrays inVerilog .
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Copyrighted material

6.4 Mixed-Type Description Examples

 

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Review Questions

 

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6 -

24

7.1

Highl ights o f Mixed -Language

 

Description

 

7 - 1

7 .2

How to Invoke One Language

from the

 

Other

 

7 - 1

Invoking

7.2.1 a

VHDL Entity from a Verilog Module

 

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7.

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7.2.2 a Verilog Module from a VHDL Modul e

Invoking

 

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7.3

Mixed-Lang uage Description Examples

 

7 - 4

7.4

Lim ita tions of Mixed Language Description

 

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Review Questions

 

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7 - 17

8.1 High lights

of Synthesis

 

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- 1

8.2 Synthesis Informati on from Entity and Module

 

8 - 3

 

8.2.1 Synthesis Information from Entity (VHDL) .

 

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8.2.2 Verilog Synthesi s Information from Module Inputs/Outputs

 

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8 • 9

8.3 Mapp ing Process a nd a lways in the Hardware Domain

 

8 - 11

 

8.3.1 Mapping the

Signal-Assignment Statement to

 

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8 • 11

8.3.2 Mapping the Variable-Assignment Statement to Gate-Level

 

8 • 15

8.3.3 Mapping Logical Operators

 

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8 · 16

8.3.4 Mapping the IF Statement

 

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8.3.5 Mapping the Case

 

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8 • 31

8.3.6 Mapping

the Loop Statement

 

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8.3.7 Mapping Procedure or Task

 

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8.3.8 Mapping the Function Statement

 

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8 • 40

Review Questions

 

8 - 43

A

1 VHDL Stand ard s

 

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A - 1

A .2 Pred efin ed

Packages

 

A - 2

 

A.2. 1 Standard . A.2.2 TEXTIO A.2.3 STD LOGIC 1164

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A· 2 A •4 A · 5

 

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A.2.4 NUMERIC_BIT A.2.5 NUMERIC STD • • • • A- 8 A-1 1 A.2.6 MATH
A.2.4 NUMERIC_BIT
A.2.5 NUMERIC STD
A- 8
A-1 1
A.2.6
MATH
A-15
A.2.7 MATH_COMPLEX
A - 16
B.1 Decoders in VHDL
B 2 Encoders in
B.3 Three State Devices in VHDL
B - 1
B - 5
B - 9
B.4
B -
12
B.5
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B.6
Multiplexers in
Parity Circuits in
Comparators in VHDL
B 7 Adders and Subtracters in VHDL
B - 15
B - 16
B - 18
B.8
B.9
ALU in VHDL
Multipliers in
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B.1 OVHDL Code for Barrel Shifter
B - 21
B - 22
B - 23
B.10.1 Barrel
Shifter
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Shifter using VHDL
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B • 25
B.11 VHDL Code for Simple Floating - Point Encoder
B - 26
B.1 1.1 Simple Floating-Point
B.1 1.2 Simple Floating-Point
Encoder
Encoder in VHDL .
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B - 26
B • 28
B.12 VHDL Code for Cascadina Comp.:.rators
B - 28
8.12.1
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B.12.2 Cascading Compa1ators in VHDL
Cascading
Comparators
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B - 28
B. 30
B.13
VHDL
Code for Dual Priority Encoder
B
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B.14 VHDL code for Ones Counter
B - 33
B 14 1 Behavioral VHDL Code for a 32-bit Ones Counter
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8.14.2
Structural VHDL Code for a 32-bit Ones Counter
B - 34
B.15 VHDL Code for Binary to Gray Code Converter
B.16 VHDL Code for Gray to Binary Code Converter
B - 38
B.17
VHDL
Code
for
Latch
B.18
VHDL
Code
for
Flip-Flop
B - 40
B - 42
B - 43

B.1 8.1 VHDL Code for a D Flip-Fl op using IF-THEN Statement

B • 43

Copyrighted material

B.18.2 VHDL Code for a D Flip-Flop using WAIT-UNTIL Statement

B - 44

B.18.3 VHDL

Code

for a D Flip-Fl op with Asynchronous ReseliClear

 

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B - 45

B.18.4

VHDL

Code

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a D Fli p-Fl op with Synchronous ReseVClear

 

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8 .18.5 VHDL code for a DFF wi th a negative-edge clock and asynchronous d ear

 

B - 46

8. 18.6 DFF with Positive-Edge Clock and Synchronous Set

 

B - 47

8 .18.7 DFF with Positiv e-Edge Clock and Clock Enable

 

B - 48

B. 18.8 VHDL Code for JK Flip-Fl op

 

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B. 12 VHDL Code for Registers

 

B - 49

8.19.1

VHDL Code for a Four-bit Register

B-49

8.1 9.2 4-bit Register with Posi tive-Edge Clock, Asynchronous Set and Clock Enable

 

B - 50

8. 19.3

VHDL Code

for an N-bit Register

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B - 51

8.1 9.4

VHDL

Code

for a Shift

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8 - 52

B.19.4.1 Using Sequential Statements

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B-52

B.19.4.2 Hi erarchical Code for a 4-bit Shift Register

 

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B-53

B.19.4.3 VHDL

Code for

an n-bit Left-to-Right Shift Register.

 

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B-54

B.19.4.4

VHDL

Code for

a Left-to-Right Shift Register with an

Enable Input.

 

B - 55

8 .19.5 VHDL Code for a 4-bit Parallel Access Shift Register

 

B - 55

 

B.19.5.1 Using Sequential Statement s

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B - 55

B.19.5.2 Hi erarchical Code for a 4-bit Parallel Access Shift Register.

 

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B - 57

8.19.6

8-bit Shift-Left Register with Positive-Edge Clock.

 

Asynch ronous Parall el Load, Seriall N, and Serial OUT

 

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B - 60

B.19.7 8-bit Shift-Left Registe:r with Positive-Edge Clock.

 
 

Synchronous Para llel Load, Seri al IN. and Seria l OUT

 

B - 61

8.19.8

8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial IN, and Parallel OUT

 

B - 62

B.20 VHDL Code for a Counter

B - 62

B.20.1 VHDL Code for a Four-bit Up Counter

 

•.

B - 62

8.20.2

VHDL Code for a 4-bit Up Counter using Integer Signals

B - 63

B. 20.3

VHDL

Code fo r a 4-bit

Down Counter

B - 64

8.20.4

VHDL

Code

for

a 3-bit Asynchronous Counter

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B - 65

B.20.5 VHDL Code for Asynchronous Counter with GLITCH

 

8 - 66

B.20.6 VHDL Code for Synchronous mod-6 Counter

B - 67

B.20.7 4-bit Unsigned Up Counter with Asynchronous Load from P rimary Input . B- 68

B - 69

B - 70

B - 72

B.20.8 4-bit Unsigned Up Counter with Synchronous Load with a Constant

B 21 VHDL Code for State Machines

B.21. 1 VHDL Code for Mealy-type State Machines

Copyrighted material

. B.21.2 VHDL Code for Moore-type State Machines

B.21.1.1 VHDL Code ror a Serial Adder.

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B - 74 B - 78

B.22

VHDL

Code

for

Guessing Game

B - 80

8.23

VHDL Code for Traffic Light Controller

B - 85

B.24

More Examples

B - 89

3.25

VHDL Code to Display Hex Key Input on the LCD Display

B -

107

B.26 VHDL Code to Display Message on the LCD Display B.27 VHDL Code to Display Key Input on the LED Display

B.28 VHDL Code to Display Message on the Multiplexed LED Display B - 122

B.29 VHDL Code for Stepper Motor Interfacing

B - 124

™~<~ ~g-1

B - 114 B - 120

iRPJ'O&It~IY~~fiiw ~~

C.1 Gate

Level Modeling

C -

1

C.2

Data

Behavioral Modeling

Flow Modeling

C - 6

C.3

C - 7

C.4

Description

of D-Latch

C - 8

C.5

Description

of

Flip-Flops

C - 8

C.6

Description

of

Sequential Circuits

C - 11

 

C.6.1 Description

of Mealy Circuit

C -

11

C.6.2 Description of Moore Circuit

 

C - 13

C.7

HDL for Registers and Counters

 

C - 15

C.7.1 Descriptions

or

Regi sters in Verilog HDL

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C - 16

C. 7.2 !::ascri ptions

of Counters

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C - 20

C.8 Verilog

Code

for Generating Waveforms using DAC

 

C - 25

C .9

Verilog

Code

for

Elevator Controller

 

C - 31

Copyrighted material

Programming (using VHDL and Verilog)

I. Write HDL code to realize all the logic ~ates : Refer Section C. l and listing 2. 1

2. Write a HDL program for the following combinational designs.

a. 2 to 4 decoder : Refer Section B. l . C.2 and listing 4. 12.

b. 8 to 3 (encoder without priority and with priority) : Refer Section B.2 and Listing 3.7.

c. 8 to I multiplexer : Refer Se.ction B.4, C. I and li sting. 2.3, 2.4.

d. 4 bit binary to gray

e. Multiplexer, de-multiplexer, comparator. : Refer Section B.4, B.6 . B. 12 and Listing 2.7, 4.2 0.

3 . Write a HDL code to describe the functions of a Full Adder using three modelling styles. :

Refer Section 1.6 and Listing 1.2, 1.3. !.4. 1.5, 1.9 and 1.10.

converter : Refer Section

B. I 5.

4. Write a model for ALU. : Refer Section B.8 and Listing C.6.

5 . Develop the HDL code for the following flip -flops, SR, D , JK, T . : Refer Section B. 18, C.4. C.S and

listing 3.2. 3.3, 3.4, 3 .5. 4. 16, 4 .18 and 4. 19.

6. Design 4-bit binary, BCD counters (Synchronous reset and Asynchronous reset) and "any

sequence" counters. : Refer Section B.20, C.6, C.7 and Listing 3.6, 4.24, 4.26, 6.8. 7.8, 7.9.

7. Write HDL code to display messages on the given seven segment display and LCD and

accepting Hex key pad input data. : Refer Section B.25, B.26, B.27, B.28.

8. Write HDL code to control speed, direction of Stepper motor. : Refer Section B.29.

9. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using

DAC change the frequency and amplitude. : Refer Section C.8 .

I 0. Write HDL code to simulate Elevator operations. : Refer Section C.9.

Copyngh1ed f"'ater al

Listing

1. 1

:

Description of circ uil usi ng basi c gates

 

1

- 9

Listing

1.2

:

Example

of

VHDL behoviorol description

l

- 30

Listing

1.3

:

Example

o f Veri log b ehavio ral descripti on

1 - 31

l

isting ·1.4

:

Exomple

of

VH DL do te-fl ow descri ption

1

-

3 1

Li

st ing

1 . 5

:

Example

of

Veri log dole - flow desc r iption

1

-

3 1

Lisling

1.6

:

VHDL swilch-level d escription

I -

33

Li

sl ing

1 .7:

Veri log switch -l eve l desc ri ptio n

1 -

34

Li

sting

1.8

:

Exomple

Example

of VHDL mixed -type descriplio n

 

1 -

34

Lisl ing

1.9

:

o f Veri log mixed-type descri plion

1 - 35

Lisl ing

1. 10

: Example

of mixed language type descri plion

1 - 35

Listi ng

2 . 1

:

HD L code

for AND -OR circuit -

 

2

-

1

Li

stin g

2 .2

:

HD

L

code

fo r holf-odder-VHDL

VHDL and Veri l og and Veri log

2 • 6

Li

sting

2 . 3

:

HD L code

of

o

2

x

1 mullip lexer

VHDL

ond

Veri log

2 - 7

Li

sting

2.4

:

HD

L

c ode

of

o

4

x

l mvllip lexer - VHDL

and

Veri log

2

- 10

Li

sl ing

2 . 5

:

HD

L

code

fo r o 2 x 2 unsi gned com b inationa l a rray m ult iplier

 
 

VHDL and Veri

 

2

• 13

Lisling

2 .6

:

HDL

code

for a D -lol ch.VHD L and Veri

log .

2

- 15

Lisling

2.7

:

HDL

code

of o 2

x 2 magnit ude com parator - VH D L and Veri log

2

- 19

List ing

2 .8

:

4 -bit

ri ppl e-corry

odder case

slvdy - VHDL ond Veri log

 

2

- 20

Listi ng

2 .9

:

4 -bil

co ny-lookahead odder - VHD L and Verilog

2

-

23

Listi ng

3 . 1

:

Example of on HDL behoviorol description-

VHDL and Veri log

3 - 2

Listing

3.2

:

VHDL code for behavioral description o f D-Lolch using

va riab le - a ssignment

statements - Listing 3 .3 : VHDL code for beha viora l description of D-Lotch using signal -assignment

3 - 10

stotemen l s

.

Listing 3 .4 : Veri l og code for behoviorol descri ption of o D -Lotch

. 3 - 11

3

-

1 1

~~·~twtft~·m fi!m:;nwt~~iih'i&iWli$ii.5W M

Gopyngh' !Cl rr 1 rial

Listing 3 .5 : HDL code for o posi tive edge-triggered JK fl ip -flop using the case

 

stotement-V HDL end Verilog

3 .

16

List ing

3 .6

:

HDL code for a 3 -bi t b inary counter using the cose sta tement

3 . 18

Listing

3 . 7

:

Verilog descri ption for o 4 -bit priority encoder

 

3 • 21

l

isting

3 .8

:

HDL code for

colculot ing the foctorio l of positive i ntegers-VHDL end Verilog

3 · 26

listing

3 .9

:

4x4-bit boot h

algorithm-

VH DL and Verilog

3 - 33

Listing 4 .1 : HDL structurol description-

VHDL ond Verilog

 

4 · 2

Li

sti ng

4.2

:

H DL

code of hell adder-VHDL end Veri log

4 · 3

Listing

4. 3

:

Binding

between

entity ond

architecture

 

4 • 5

Listin g

4.4

:

Binding

between

entity ond

component

4 · 5

li

sting

4 .5

:

Bi nding

between

library and module in

 

4 •

6

Listing

4 .6

:

Binding

Bindi ng

VHDL code fo r inverter, AND,

o library ond

between

between

component in VHDL

4 · 7

List ing

4.7

:

two modules

in Verilog

4 • 8

Listing

4 .8:

OR, NOR, NANO XOR ga tes

4 . 9

li

sting

4 .9:

H DL des cription of o 2x1 mu lt iplexer w ith act ive

low enabl

4

• 11

Listing

4 .10

:

H DL description of o 2x4 decoder with enable

input

4 .

14

Listing

4 . 1 1

:

VHDL behovioro l descriptio n of o t ri -stote buffer

4 .

16

Listing

:

4 • 17

Listing

Listing

4. 12 4 . 13

4.14

:

:

H Dl. description of o 2x4 decoder with tri -stote output VHDL code for the holf

H DL

of

o lull odder -

VHD L ond Verilog

4 .

4

·

19