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Contents lists available at ScienceDirect

Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Effectiveness of a hardware-based approach to detect resistive-open

defects in SRAM cells under process variations
A.F. Gomez a, * , F. Lavratti b , G. Medeiros b , M. Sartori b , L. Bolzani Poehls b , V. Champac a , F. Vargas b
a
b

National Institute for Astrophysics, Optics and Electronics-INAOE, Mexico

Pontical Catholic University of Rio Grande do Sul-PUCRS, Brazil

A R T I C L E

I N F O

Article history:
Received 9 June 2016
Received in revised form 20 October 2016
Accepted 21 October 2016
Available online xxxx
Keywords:
Nano-Scale SRAM
Resistive-open defects
Hardware-based approach
Process variation.

A B S T R A C T
Resistive-open defects in Static Random Access Memories (SRAMs) represent an important challenge for
manufacturing test in submicron technologies as they may be masked by process variations, which in
turn increases the number of test escapes. This paper evaluates the effectiveness of a hardware-based
test approach that compares the current consumption of neighboring SRAM cells to detect resistive-open
defects. The proposed approach is validated and its fault detection capabilities are analyzed for different
defect sizes and taking into account process variations effects. Finally, the paper provides an evaluation
of the minimum detectable resistive-open defect size for the proposed hardware-based approach under
process variations effects.
2016 Elsevier Ltd. All rights reserved.

1. Introduction
Aggressive scaling of CMOS technology has allowed a signicant
increase of transistors integration into a small silicon area, leading to an increase of density and complexity of circuits. Due to the
increasing need to store more and more information, Static Random
Access Memories (SRAMs) has become a major contributor to overall
System-on-Chip (SoC) area [1], [2]. However, technology scaling has
made SRAMs vulnerable to new manufacturing defects. Thus, new
fault models representing physical defects, which differ from the traditional ones usually adopted by memory testing procedures have
emerged [1], [3]. In the last years, Resistive-open defects have become
one of the most important defects in CMOS technology due to the
presence of many interconnection layers and the ever growing number of connections between each layer [4]. A resistive-open defect
is dened as a partial disconnection between two circuit nodes that
should be connected [5]. While strong resistive-open defects cause
logic faults in the SRAM cell, weak resistive-open defects may not
produce logic faults during manufacturing test. Weak resistive-open
defects are hard to be detected and they are an important source
of test escapes [6]. Moreover, these defects could become a reliability issue [7]. Another fact to be mentioned is that a defect may

* Corresponding author.
E-mail addresses: fgomez@inaoep.mx (A. Gomez), leticia@poehls.com (L. Poehls),
champac@inaoep.mx (V. Champac).

cause a dynamic fault, which means that usually a large number of at

speed operations are required to sensitize it [8]. However, the tests
used currently are mostly designed for static faults detection and not
for dynamic faults detection. Most of the standard March algorithms
fail to detect such dynamic faults [6][9]. This poses a signicant
challenge to provide the detection of dynamic faults in memory cells,
and consequently, to guarantee SRAM reliability.
In the last years, different approaches have been proposed in
order to deal with the detection of resistive-open defects in SRAM
cells. These approaches can be categorized as fault - or defectoriented. In a fault-oriented test approach, the faulty behavior needs
to be propagated to the primary outputs in order to be observable.
Strong resistive-open defects can be detected with fault-oriented
test. In a defect-oriented test approach, a parameter of the tested circuit (i.e. current consumption) is monitored to detect the presence of
a defect. One of the main advantages of a defect-oriented test is that
it does not require observability of the logic faulty behavior at main
circuit outputs. This approach is more adequate for detection of weak
resistive-open defects, which are dicult to detect with a test based
on classic logic fault observation. Current-based test is a widely
known defect-oriented approach based on the monitoring of the current consumption (static or dynamic) of the SRAM [10]. Test of SRAM
static current consumption (IDDQ ) has been shown to be effective
for resistive-bridge defects detection [11]. On the other hand, test
of SRAM dynamic current consumption (IDDT ) can be very effective
for resistive-opens defects detection [12]. In [13], the total charge
involved in the SRAM dynamic current consumption is monitored.

http://dx.doi.org/10.1016/j.microrel.2016.10.012
0026-2714/ 2016 Elsevier Ltd. All rights reserved.

Please cite this article as: A. Gomez et al., Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under
process variations, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.10.012

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A circuit for measurement the charge injected to the SRAMs is proposed in [14]. In [15], the current peak amplitude is monitored. A
comparison of the effectiveness of measuring different parameters of
the dynamic SRAM current consumption is made in [12]. It is shown
that charge-based test is more effective than those approaches measuring a single current parameter such as the peak amplitude or the
average value. Current-based test is a challenging task in nanometric
technologies due to process variations effects that make dicult to
distinguish between current deviations caused by process variations
itself or current deviations caused by the presence of a defect. For
example, under process variations, the charge and the peak amplitude of the monitored SRAM current change, which in turn limit the
detection capability of the techniques in [13],[15].
This paper analyzes the effectiveness of an innovative hardwarebased approach [16] able to detect resistive-open defects in SRAM
cells. The proposed hardware-based technique senses and compares
the current that ows through neighboring SRAM cells to provide
the detection of resistive-open defects. The approach is based on
the insertion of On-Chip Current Sensors (OCCSs) and Neighborhood
Comparison Logic (NCL). An in-depth analysis of the components
of the proposed hardware-based test is presented. First, the defect
detection capabilities of the proposed hardware-based approach are
presented. An analysis of the minimum detectable resistive-open
defect size is provided. Then, the detection capabilities of the proposed methodology are evaluated taking in to account the impact
of process parameters variations. The obtained results from Monte
Carlo simulations show that the hardware-based approach is able
to detect resistive-open defects located at different positions in the
SRAM cell, even if no logic fault is sensitized during the testing
execution. Moreover, it is shown that the proposed hardwarebased approach is robust to manufacturing process variations as the
minimum detectable defect size is slightly changed under process
variations.
This paper is structured as follows: Section 2 presents the background related to the proposed analysis, including the description of
the fault model adopted as well as details about the hardware-based
approach. Section 3 presents a detailed description of the proposed
analysis in terms of experimental setup as well as a discussion about
the results obtained during simulations. In Section 4, our proposal is
compared with respect to other approaches in literature. The main
advantages of the proposed hardware are highlighted in this section.
Finally, Section 5 summarizes the conclusions of this work.

2. Resistive-open defects in SRAMs

In this section, details about resistive-open defects and the respective fault model are presented. Furthermore, the proposed hardwarebased approach to detect resistive-open defects is described.
Resistive-open defects can be located between each pair of nodes
that must be connected in an SRAM cell. The six resistive-open faults
model shown in Fig. 1 has been considered to analyze the impact of
these defects on SRAM performance. These open location are a well
representative group because they allow an exhaustive cell analysis
of the resistive opens due to the symmetry of the cell [4]. As shown,
the considered resistive-open defects are located in 6 different places
within the cell, named Df1, Df2, Df3, Df4, Df5 and Df6. In order to simplify the behavior analysis, usually only one defect is considered at a
time in an SRAM cell. The fault model shown in Fig. 1 represents the
set of the following logic faulty behaviors:
Transition Fault (TF): A cell is said to have a TF if it fails to perform
a transition from 0 to 1 or from 1 to 0 when it is written.
Read Destructive Fault (RDF): A cell is said to have an RDF if a
read operation performed in the cell changes its stored data
and returns an incorrect value at the output.

Df5

WL
BL

BLB

Df4
Df2
INV1

Df3

Df1

bitb

bit
Df6
INV2

Fig. 1. SRAM cell with resistive-open defects [4].

dynamic Read Destructive Fault (dRDF): A cell is said to have

an dRDF if a write operation immediately followed by a read
operation performed in the cell changes its logic state and
returns an incorrect value at the output.
Deceptive Read Destructive Fault (DRDF): A cell is said to have
a DRDF if a read operation performed in the cell returns the
correct logic value, and it changes the contents of the cell.
dynamic Deceptive Read Destructive Fault (dDRDF): A cell is said
to have an dDRDF if a write operation immediately followed by
a read operation performed in the cell changes its logic state
and returns a correct value at the output.
Incorrect Read Fault (IRF): A cell is said to have an IRF if a read
operation performed in the cell returns an incorrect logic value,
and the correct value is still stored in the cell.
In order to analyze the impact of resistive-open defects on the
behavior of SRAM cells, the defects previously mentioned have been
modeled considering different defect resistance values. A sequence
of read and write operations have been applied to the SRAM cell and
the values of defect resistance at which a logic fault is presented
have been identied. Fig. 2 shows the obtained relation between
resistance value and the obtained faulty behavior. Note that defects
located at Df4 are not depicted in Fig. 2 as the insertion of Df4 did
not generate any logic fault for the resistance value interval adopted
during the simulations. As can be seen from Fig. 2, the faulty behavior performed by the SRAM cell changes between static or dynamic
fault depending on the defect resistance value. For weak defects
(small resistance values) no logic faults occur. However, the impact
of those weak defects may aggravate during lifetime operation due
to stress [7], and eventually, faulty operations may occur during
lifetime, even if they are not presented during manufacturing test.
2.1. Fundamental principles of the proposed test technique
Resistive-open defects modify the current ow through the defective SRAM cell, and consequently, they cause loss of the circuits
operation speed and decrease the performance of the SRAM inverters.
Fig. 3 shows the current through a defect-free and a defective SRAM
cell (Df 3 = 40kY) while applying a specic sequence of write and read
operations (w0, r0, w1, r1). Fig. 3 shows that depending on the performed operation on the SRAM cell, different distortions of the current
waveform caused by the resistive-open defect are obtained. Specically, in the situation depicted in Fig. 3, it is possible to observe that
during r0 operation, the current that ows through the cell is the same
for both a defect-free and a defective SRAM cell. This occurs because
during this specic operation, the current does not ow through the
defect resistance Df 3. However, for other operations, the impact of the
weak resistive-open at Df 3 on current consumption is evident. From
Fig. 2, it can be observed that the given defect size (Df 3 = 40kY) is
weak and it does not trigger any logic fault, which makes evident that

Please cite this article as: A. Gomez et al., Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under
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Df1
TF(0 to 1)

20

60

40

80

140

160

180

200

120

140

160

180

200

120

140

160

180

200

1200

1400

1600 1800 2000

1200

1400

1600 1800 2000

120

100

Defect Size (k)

Df2
dDRDF (4th read )

20

dDRDF (2nd read )

60

40

80

RDF

100

Defect Size (k)

Df3
dDRDF (2nd read )

20

RDF

60

40

80

100

Defect Size (k)

Df5
TF(0 to 1)

200

TF(1 to 0)

400

600

800

1000

Defect Size (k)

Df6
TF(0 to 1)

200

TF(1 to 0)

400

600

800

1000

Defect Size (k)

Fig. 2. Defect resistance value and the respective faulty behavior [16].

a fault-oriented test technique would not be able to detect this defect.

However, that weak-defect is sucient to signicantly modify the
current that ows through the SRAM cell, which indicates that defect
detection is possible by monitoring the SRAM current consumption.
This example shows the advantages of a defect-oriented test approach
over a fault-oriented test. It is central to note that different distortions
of the SRAM current consumption can be observed depending on the
defect size and position, which results in altered current amplitudes
as well as off-sets.
2.2. Proposed hardware-based approach
The main idea behind the proposed Hardware-based approach
is to compare the current consumption of two or more neighboring cells, while performing simultaneous and parallel read and write
operations in the SRAMs. For identical fault-free SRAM cells the difference between the current consumption waveform should be close
to zero. On the other hand, if a defect exist in one of the cells, the difference of its current consumption with respect to a defect-free cell
should be different from zero.
The architecture of the proposed Hardware-based approach for
resistive-open defects detection in an SRAM array is depicted in
Fig. 4. For simplicity purposes only the rst 8 columns of the SRAM
array are illustrated. The proposed technique introduces On-Chip
Current Sensors (OCCSs) at both VDD and GND nodes of each column

w0

r0

w1

of the SRAM array. For each column only the SRAM cells on a specic
row are tested at a time by performing simultaneous read/write
operations. The currents that ow through each tested SRAM cell
are converted into a Pulse-Width-Modulated (PWM) signal by the
OCCS. This is done because the comparison of digital data requires
considerably lower area and power cost that the comparison of analog signals. A pulse signal that indicates the presence of a defect is
generated if the skew between any pair of the PWM signals, which
represent the dynamic current of the SRAM cells, is large enough to
cause a transition at the output of the XOR gate. This ag signal is
stored in Latch elements that keep test data results until they are reinitialized by the reset control signal. One Latch SR was inserted at
every NCL block (see Fig. 4). The latches are activated by their clock
signal when a write/read operation is carried-out at the SRAM. As
mentioned before, both Ignd and Ivdd currents are measured in parallel, in order to achieve a single output result for each neighborhood,
an OR logic gate is used to launch a ag signal when a defect is
detected by either the NCL block for Ignd (NCL_Gnd) or the NCL for
Ivdd (NCL_V dd).
The OCCS and NCL block are explained with more detail next.
2.2.1. On Chip Current Sensor (OCCS)
Our proposal evaluates the dynamic current of an SRAM cell. The
OCCS block processes the instantaneous current consumption of an
SRAM cell over time. Fig. 5 depicts the schematic of the OCCS, which
is composed by the following stages:
Current-voltage converter (I-V converter): This stage is composed by a single transistor that works as a low value resistor
generating a small voltage change in Vdd and Gnd nodes of the
SRAM columns due to the current consumption of the SRAM
cell.The voltage change is directly proportional to the instantaneous current that ow through an SRAM cell. The size of
the transistor in this stage is settled depending on the desired
sensitivity to the current ow.
Operational voltage signal amplier (Amplier): This stage
amplies the small voltage signal generated in the I-V converter stage to make it adequate for the next functional stage.
Pulse Width Modulated Generator (PWM Generator): This
functional stage consists of two consecutive inverter gates. The
rst inverter is designed to have unbalanced Pull-Up and Pulldown networks to guarantee the fast charging of the value
that corresponds to the current consumption, and discharges
slowly, creating a time modulated analog signal. The second
inverter transforms this modulated analog signal into a digital signal whose pulse-width is related to the amplitude and
duration of the current consumption of the monitored cells.
It is important to note that the OCCS monitors both the Vdd
Current (IVdd) and Gnd Current (IGnd) in order to achieve the
detection of several resistive-open defects sizes located at different
positions in the SRAMs.

r1

60

Defect Free
DF3=40k

Ignd (A)

40
30

-10

Ivdd (A)

50

20
10
0
0

-20
8

time (ns)
Fig. 3. Current consumption: Gnd current (Ignd ) and Vdd current (Ivdd ) for a defect-free
and a defective SRAM cell with a Df3 of 40kY.

2.2.2. Neighborhood Comparison Logic (NCL)

The PWM signal at OCCS output represents the current consumption behavior of the SRAM cell. Then, the detection of a defective
SRAM cells is made by the Neighborhood Comparison Logic (NCL)
block. The NCL connects the OCCSs output of neighboring SRAM cells
in a circular manner. For each SRAM cell N, its corresponding PWM
signal due to IVdd (IGnd) current consumption is compared to its
direct neighbors, N + 1 and N 1. Under the presence of a defect,
the PWM signal of a defective SRAM cell is de-synchronized with
respect to a neighboring defect-free PWM signal. A simple and low
cost XOR gate (see Fig. 4) makes the function to compare the PWM
signals generated for neighbor cells. The XOR gate produces a pulse
(ag signal) indicating the presence of a defect if there exist a large

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PWM_Vdd_6

Out_NCL_Vdd_0 [0]
Reset

PWM_Vdd_4

Out_NCL_Vdd_0 [1]

ClK
PWM_Vdd_2

Vdd

Gnd

Out_NCL_Vdd_0 [2]

PWM_Vdd_0

Out_NCL
_Vdd_0

Out_NCL_Vdd_0 [3]

PWM_Vdd_0

OCCS_0

PWM_Gnd_0

Out_NCL_Vdd_0
PWM_Vdd_1

OCCS_1

NCL_Vdd_0

Latch

PWM_Gnd_1

OCCS_2

PWM_Gnd_2

NCL_Gnd_0

Column 7

Column 0

Out_NCL_Gnd_0

Latch

PWM_Vdd_3

OCCS_3

OR_NCL_0

OR

PWM_Vdd_2

PWM_Gnd_3
PWM_Vdd_4

OCCS_4

PWM_Gnd_4

Out_NCL_Vdd_1
PWM_Vdd_5

OCCS_5

NCL_Vdd_1

OCCS_7

PWM_Gnd_6

OR_NCL_1

OR

PWM_Vdd_6

OCCS_6

Latch

PWM_Gnd_5

Out_NCL_Gnd_1

NCL_Gnd_1

PWM_Vdd_7
PWM_Gnd_7

Latch
4
clk

Fig. 4. Architecture of the hardware-based approach.

enough skew in the compared PWM signals. The detection capability

of the NCL block to discriminate between good and wrong behavior
of the SRAM cells depends on the XOR gate size. The OR gates add
diagnosis capability.
Note that the detection strategy adopted in the proposed NCL
block uses neighborhoods of four cells from different columns to
allow diagnosis of the defective SRAM cell according to the decodication of the output value with the following rules:
0000: defect-free SRAM cell;
1011: SRAM cell 0 as defective;
0111: SRAM cell 1 as defective;

I-V Converter

Amplifier

vdd

2.3. Implementation issues of the proposed hardware-based approach

2.3.1. Layout placement
There are some minor layout modication required to implement
the proposed hardware. The power supply rails (Vdd and Gnd) distribution in the SRAM need to be modied in such way that each SRAM
column takes an individual Vdd and Gnd signal. It is quite important
to make as balanced as possible the length of Vdd and Gnd rails

PWM Generator
Slow PMOS
vdd

L=10x

Vdd
Column

1110: SRAM cell 2 as defective;

1101: SRAM cell 3 as defective;
1111: More than one cell as defective.

L=20x

W=2x

PWM_VDD

Vdd CMOS
Amplifier

W=4x

Weak Voltage
signal

Strong Voltage
signal

vdd
W=4x

Gnd
Column

vdd

vdd

W=2x

vdd

Digital PWM
Output

W=2x

PWM_GND

Gnd CMOS
Amplifier

L=20x

Slow NMOS

W=2x
Dimensions:
L=60nm
Wp=240nm
Wn=120nm

Fig. 5. On-Chip Current Sensor (OCCS).

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proposed test circuitry is less than 1%. The static power consumption overhead has been estimated with respect only to the SRAM cell
array. The data given in Table 1 show that the proposed hardwarebased test allows detection of weak defects at reasonable area and
power consumption overheads.

Table 1
Area and power overhead of the proposed hardware-based approach.
Array size

Rows Columns

Area overhead (%)

Static power overhead (%)

8 kbit
64 kbit
512 kbit

1024 8
2048 32
8192 64

5.46
2.73
0.68

5.21
2.60
0.65

3. Validation of the proposed test technique

Table 2
Minimum detectable defect size for each SRAM operation using the proposed approach.
Operation

Defect size (kY)

Df1

Df2

Df 3

Df4

Df5

Df6

r0
r1
w0
w1
min

6
32
32
6

820
6
6
6
6

5
5
5
5

16300

36000
160000
16300

280
215
110
110
110

65
180
65

In order to show the feasibility of the proposed test technique,

two analysis have been made:

Performance analysis under nominal process: This step aims

to provide information about the detection capability of the
hardware-based approach;
Performance analysis under process variations: The main goal
of this step is to analyze the impact of process variations on the
detection capability of the proposed hardware-based approach.

that feed neighboring SRAM columns in order to mitigate the impact

of different parasitic components of interconnections. This assures
that nearly equal voltage drops and current ow are presented for
non-defective neighboring cells.

A case study considering an SRAM composed of 1024 lines and

8 columns synthesized with a 65 nm technology library of STMicroelectronics has been used for HSPICE simulations. Note that the case
study is also composed of the circuitry required for adequate SRAM
operation such as Sense Ampliers, Read and Write Drivers and PreCharge modules for each column. The resistive-open defects have
been modeled according to the positions presented in Fig. 1.

2.3.2. Area and power overheads

Area and power consumption overheads introduced by the hardware of our proposal have been evaluated for different SRAM array
sizes (See Table 1). The proposed hardware requires a total of 288
transistors occupying an estimated area of 3.29 lm2 , which corresponds to an area of approximately 56 SRAM cells. As shown in
Table 1, the area overhead reduces as the size of the SRAM array
increases. For an SRAM of 512 kbit, the area overhead is only 0.68%.
Power consumption is composed of two components: Dynamic
power consumption and Static power consumption. Dynamic power
consumption occurs when the proposed hardware is activated during the manufacturing test phase. For SRAM memories, static power
consumption is of great interest. During normal SRAM operation, the
proposed hardware is turned off to save energy. As shown in Table 1,
for a 512 kbit memory the static power consumption overhead of the

3.1. Performance analysis under nominal process

The hardware-based approach has been validated through
simulations that aim at demonstrating the distinguished behavior
of the OCCS when monitoring an SRAM cells neighborhood that is
composed by one defective SRAM cell and three defect-free SRAM
cells. First of all, the detection capability of the proposed approach
is evaluated considering that the defective cell presents a resistive
defect at Df 3 position (see Fig. 1) with the value of 40kY. Fig. 6
depicts the signal processing for current consumption comparison
between the defective and the defect-free SRAM cell during a r1

40

1.2
Defect Free
DF3=40k

20
10
0
-10
0

Defect Free
DF3=40k

1
Voltage (V)

Ignd (A)

30

0.8

Amplifier
Output

0.6
0.4

I-V Converter
Output

0.2
2

4
6
time (ns)

(a) GND Current signals

10

0
0

4
6
time (ns)

10

(b) I-V Converter and Amplifiers output signals

1.2
Defect Free
DF3=40k

Voltage (V)

1
0.8
0.6
0.4
0.2
0
0

4
6
time (ns)

10

(c) PWM signals

Fig. 6. Validation of the OCCS: signal processing for defective (Df3 = 40kY) and defect-free SRAM cell.

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w0

r0

w1

w0

r1

w1

r0

r1

bitb

bit
Bitflip does
not occur

Bitflip
occurs
bit

bitb

OR_NCL

OR_NCL

(a) With Logic Fault

(b) Without Logic Fault

Fig. 7. Df2 with the size of 150kY (a) and 100kY (b).

operation. The waveform in Fig. 6a to c correspond to the IGnd

current ow, outputs of the I-V converter, Amplier and PWM generator (see Fig. 5). From Fig. 6 (a), it is possible to observe that, for
the performed operation, the current owing through the defective
cell is smaller than the current owing through the defect-free cell.
This fact makes the detection of defects by the proposed approach
possible. The detection process starts with the IGnd current being
converted into voltage by the Current-Voltage Converter stage. In
Fig. 6 (b), the shape of the voltage of the I-V converter output corresponds to the IGnd current plotted in Fig. 6 (a). The distinguished
voltages related to the defective and defect-free SRAM cell generate
a different value at the ampliers output (see Fig. 6 (b)). Therefore,
the Amplier Output signal differs according to the voltage variation.
When the voltage change at the output of the amplier surpasses the
threshold voltage of the rst inverter in the PWM Generator stage, a
pulse is generated at the PWM output. Fig. 6 (c) shows that the different current ow through the SRAM cells affects the generated pulse
width, and therefore, a time delay (D) difference exist between the
generated PWM signals. This width difference is detected by the NCL,
which turns on the fault ag signal.
The ability of the entire architecture (see Fig. 4) to detect
resistive-open defects has been evaluated at the following conditions: a) The size of the defect inserted in the SRAM cell produces
a logic fault, and b) The defect inserted in the SRAM cell is weak
and do not produce a faulty behavior at logic. The graphs depicted
in Fig. 7 show the situations previously mentioned. Fig. 7a shows
a condition where a defect Df2 = 150 kY produces a read fault in
the memory cell. Due to the bit-ip, the current between the defective and a defect-free cell are very different and the fault signal
OR_NCL (see Fig. 4) is activated. Moreover, Fig. 7b shows a condition
where a defect size Df2 = 100 kY does not produce a faulty behavior.
However, the proposed hardware-based approach is able to detect
the defect presence and activates the fault signal.
The effectivenes of the proposed architecture to detect weak
resistive-open defects is evaluated based on the defect resistance
resolution, which is dened as the minimum defect resistance
value that produces a fault ag signal activation at the output of the
NCL stage. In order to obtain the resolution of the proposed approach,
the resistance value of the defective SRAM cell is initially settled to
zero (no defect) and it is gradually increased until the fault signal is
activated.
Table 2 summarizes the minimum defect resistance that can be
detected while performing each operation in the SRAM. As can be
seen, the minimum defect size that can be detected by the proposed
approach depends on the performed operation in the SRAM cells during test. For example, a defect size as small as 6kY located at Df1

activates the fault signal during a r1 operation, however, this defect

size does not activate the ag signal if the w1 operation is performed
instead of r1. For each defect location, the minimum defect resistance detected for all the operations (w0, r0, w1, r1) is the resolution
of the defect that can be detected by the proposed approach, and it is
given in the last row of Table 2. These results demonstrate that weak
resistive-open defects can be detected by the proposed approach,
even if the defect size is far from inducing a logic fault (see Fig. 2).
3.2. Performance analysis under process variations
Process variations that occur due to the diculty of precise
fabrication process control have become more signicant with each
scaled technology node. Moreover, process variations have been
shown to diminish yield and reliability of chip designs [17]. The
process-induced variations of important device parameters such as
effective channel width, effective channel length, oxide thickness
and threshold voltage have been considered. Variations in such
parameters are caused by process variations such as lithography process, dopant implantation and temperature control. Other sources of
parameters variations can also be taken into account by a detailed
modeling of their impact on the devices parameters.
Large variations in the currents owing through the SRAM cells
may occur due to process variations effects. Because of this, it is
important to analyze the capability of the proposed test methodology to distinguish the presence of a resistive-open defect in spite of
the process variation effects.
w0

r0

w1

r1

Fig. 8. Ignd current waveforms of a defect-free SRAM cell and a defective cell for
consecutive w0, r0, w1 and r1 operations.

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Df1=20k

Defect free
Df1=20k
Defect free

(a) IGND Peak Value

(b) IGND Average Value

Fig. 9. Process variations effect on IGnd current for a read 1 operation of a defect-free and a defective SRAM cells.

An analysis of the impact of process variations on the detection capability of the proposed approach is made next. In this work,
the variations of the device parameters have been assumed as normal distributed random variables due to process variations. For each
process parameter, a 3s deviation of 20% of the nominal parameter value has been assumed. The modeled process variations are:
a) Correlated variations on channel width (W), channel length (L) and
oxide thickness (tox); and b) Independent or Uncorrelated variations
on the devices threshold voltage (Vth) due to Random Dopant Fluctuation (RDF). Variations due to RDF are of great concern in SRAMs
as its effect is pronounced in minimum-geometry devices [18].
Monte-Carlo simulations considering process parameter variations in the SRAM cells have been executed and the following issues
were analyzed:
Differences in current consumption between two defect-free
SRAM cells due to process variations. This differences can
affect the detection capability of the OCCS since depending on
the difference magnitude the fault signal can be erroneously
activated.
Process variations may impact on the minimum detectable
defect size.
Fig. 8 shows the currents waveform for a defect-free SRAM cell
under process variations effects and the current waveform for the
nominal case of a defective SRAM cell with Df3 = 40kY for a given
sequence of write and read operations. As can be seen, for some
operations the impact of the defect on the current ow may be
masked by process variations (i.e. see r0 and w1 operations) while for
other operations (see r1 and w0 operations) the current waveform
are quite different. Therefore, in order to maximize the effectiveness of the proposed approach, all the operations sequence should
be applied to the SRAM cell to assure a reliable test procedure.
The impact of process variations on the current shape and amplitude can be analyzed with the histograms shown in Fig. 9. A defective
and a defect-free SRAM cell for a read 1 operation have been compared. Fig. 9a shows the histogram of the peak current value, and
Fig. 9b shows the histogram of the average current ow through the
cells. It can be observed that the impact of the defect on the current
signal is signicant, and therefore, the histograms for the defective
and the defect-free cells are well separated. These results suggest
that comparing current consumption of the SRAM cells is a reliable
technique for defect detection even under process variations effects.
Since the proposed method generates a PWM signal according to the
current consumption of the SRAMs cells, the differences of shape and
amplitude of the current waveform are mapped to a different pulsewidth duration of the PWM signal. As shown in Fig. 10, the PWM signals generated for the defective and the defect-free cell have a very
different width, which can be effectively processed by the NCL stage

to activate the fault ag signal. If due to process variations, the delay

difference between the defect-free and faulty behavior (See Fig. 10)
is no suciently large, then a pulse at the ag signal is not delivered, and as a consequence the defect is not detected. Hence, process
variations conditions that reduce the delay difference may lower the
resolution of the minimum detectable resistance of the open.
The impact of process variations on the minimum detectable
defect size is next analyzed with Monte Carlo Simulations for different places in the SRAM cell (see Fig. 1). The detection probabilities
of the defects as function of the defect size are shown in Fig. 11.
Fig. 11a shows that the proposed test technique assures the detection of defects larger than 8kY for Df1, Df2 and Df3, detection can
not be assured for defect sizes in the range 2kY 8kY, and defects
are not detected for defect sizes lower than 2kY. The minimum
detectable size of defects Df1, Df 2 and Df 3 is slightly larger than
that obtained at nominal process parameters (see Table 1). Fig. 11b
shows the impact of process variation on the minimum detectable
defect size for Df 5 and Df6. In this case, detection is assured for defect
sizes larger than 300kY, non-assured detection for defect sizes in
the range 10kY 300kY, and defects are not detected for defect
sizes lower than 10kY. Note that defect Df4 is not considered as does
not generate any faulty behavior for the resistance value interval
adopted during the simulations.
It should be noted that despite of the resolution loss due to process variations effects, the minimum assured detectable defect sizes
by the proposed test technique are smaller than those found with
traditional logic test (see Fig. 2). These results show that the proposed architecture allows a reliable test of SRAM memories in very
scaled technologies even under process variations effects.

Df1=20k

Defect Free

Fig. 10. PWM signal under process variations.

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(a) Df1, Df2 and Df3

(b) Df5 and Df6

Fig. 11. Defect detection probability as function of defect size for different location in the SRAM cell.

4. Comparison with other techniques

Table 3 shows a comparison of the main features of the proposed
hardware-based test approach with other approaches in literature.
All the considered approaches use IDDT test to detect defects in SRAM
cells. However, an important difference relies on the specic parameters of the dynamic current consumption that are taken into account
for pass/fail test decision. As shown, in [13] and [14] the charge delivered to the circuit is measured, in [15] the peak current is measured
and in [19] and the proposed in this paper the current waveform is
measured. While charge-based and waveform-based test take into
account most of the current consumption information, techniques
that considers only the peak value may be less accurate.
Another important feature is the IDDT approach used, which can be
based on current measurements on a single cell or based on current
measurements on neighborhood of cells. Under process variations
effects, the rst approach requires to use Tolerance Bands (TB) in the
monitored parameter to determine whether a defect is presented or
not. TBs are dened from the Monte Carlo analysis of a fault-free
SRAM cell [12]. Those SRAM cells exhibiting a behavior of the monitored parameter (i.e. charge) outside the TB can be easily identied
as defective cells. However, due to the increasing impact of process
variations, TBs can be large, which may reduce test effectiveness
for weak defects. Approaches comparing the measured parameters
within neighboring cells exhibit a greater robustness against process
variations since the electrical characteristics of devices placed very
close to each other present correlation [20].
An advantage of the proposed hardware over other approaches
given in Table 3 is that it processes the current signal using both
analog and digital circuitry. As shown before, analog circuitry converts the current signal into a voltage signal and amplies that
voltage. However, comparison of measured currents and test decision is made by digital circuitry, which require less area overhead
and design complexity than other approaches that are based only on
analog circuitry.

Finally, it should be noted that other approaches in literature monitor the current owing from the power supply (VDD) to the SRAM
cells. This current is only presented during write operations. However,
the proposed hardware senses both the current that ows from VDD
to the cell and the current that ow from the cell to ground (GND).
This increases the defection effectiveness of the proposed hardware.
In addition to the features compared in Table 3, it should be mentioned that our proposal provides improved diagnosis capability due
to the de-codication performed by the NCL block, which allows
identication of faulty SRAM cells.

5. Conclusions
The effectiveness of a hardware-based SRAM test approach based
on the comparison of the current consumption between neighboring
cells to detect resistive-open defects in the presence of process variations has been analyzed. An in-depth analysis of the different components of the test methodology has been presented. Under nominal
conditions the proposed hardware-based approach is capable to
detect small resistive-open defects. The minimum defect size that
can be detected depends on the defect location in the SRAM cell and
it has been shown to be much smaller than the defect size required
to observe a faulty logic operation. The effect of process variations
in the effectiveness of the proposed technique has been evaluated.
Under process variations effects, the probability to obtain a false
defective SRAM cell detection is low. The defect resolution reduces
due to process variations effects. However, the minimum assured
detectable defect sizes by the proposed test technique are still small
compared to those values that cause functional faults. Therefore, the
proposed architecture allows a reliable test of SRAM memories in
scaled technologies even under process variations effects.

Table 3
Comparison with other SRAMs testing techniques. TB: Tolerance Band.
Feature

[13]

[15]

[14]

[19]

Our proposal

Monitored parameter
IDDT approach
PV robustness
Signal processing
Measured current

Charge
Single cell
Use TB
Numerical
VDD

Peak current
Single cell
Use TB
Analog
VDD

Charge
Single cell
Use TB
Analog
VDD

Inst. current
Neighborhood

Analog
VDD

Inst. current
Neighborhood
Yes
Analog/digital
VDD and GND

Please cite this article as: A. Gomez et al., Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under
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Acknowledgments
This work was supported by: CONACYT (Mexico) through the PhD
scholarship number 420129/264560 and by CNPq (Science and Technology Foundation, Brazil) under contracts n. 301726/2008-6 and n.
556761/2009-0, FAPERGS/CAPES 014/2012.

References
[1] A. Pavlov, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled
Technologies: Process-Aware SRAM Design and Test, Springer Netherlands,
Dordrecht, 2008.
[2] M. Sachdev, J.P. de Gyvez, Defect-Oriented Testing for Nano-Metric CMOS VLSI
Circuits:, 2nd edition ed., Springer US, Boston, MA, 2007.
[3] A.J.V.D. Goor, Using march tests to test SRAMs, IEEE Des. Test Comput. 10 (1)
(1993) 814. http://dx.doi.org/10.1109/54.199799.
[4] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan,
Resistive-open defects in embedded-SRAM core cells: analysis and march test
solution, Test Symposium, 2004. 13th Asian, 2004, pp. 266271. http://dx.doi.
org/10.1109/ATS.2004.75.
[5] J.C.M. Li, C.-W. Tseng, E.J. McCluskey, Testing for resistive opens and stuck
opens, Test Conference, 2001. Proceedings. International, 2001, pp. 10491058.
http://dx.doi.org/10.1109/TEST.2001.966731.
[6] P. Dubey, A. Garg, S. Mahajan, Study of read recovery dynamic faults in 6T
SRAMS and method to improve test time, J. Electron. Test. 26 (6) (2010) 659666.
http://dx.doi.org/10.1007/s10836-010-5176-5.
[7] H. Villacorta, V. Champac, R. Gomez, C. Hawkins, J. Segura, Reliability analysis
of small-delay defects due to via narrowing in signal paths, vol. 30, 2013,
pp. 7079. http://dx.doi.org/10.1109/MDT.2013.2238578.
[8] S. Borri, M. Hage-Hassan, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel,
Analysis of dynamic faults in embedded-SRAMs: implications for memory test,
J. Electron. Test. 21 (2) 169179, 10.1007/s10836-005-6146-1.
[9] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli,
Y. Wang, B. Zheng, M. Bohr, SRAM design on 65-nm CMOS technology with
dynamic sleep transistor for leakage reduction, IEEE J. Solid State Circuits 40 (4)
(2005) 895901. http://dx.doi.org/10.1109/JSSC.2004.842846.

[10] S.S. Sabade, D.M. Walker, IDDX-based test methods: a survey, ACM Trans.
Des. Autom. Electron. Syst. 9 (2) (2004) 159198. http://dx.doi.org/10.1145/
989995.989997.
[11] D. Arumi, R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, B. Kruseman, M. Lousberg, IDDQ-based diagnosis at very low voltage (VLV) for bridging
defects, vol. 43, 2007, pp. 2526. http://dx.doi.org/10.1049/el:20073573.
[12] G. Gyepes, V. Stopjakov, D. Arbet, L. Majer, J. Brenku, A new {IDDT} test
approach and its eciency in covering resistive opens in {SRAM} arrays, Microprocess. Microsyst. 38 (5) (2014) 359367. http://dx.doi.org/10.1016/j.micpro.
2014.04.006.
[13] B. Alorda, M. Rosales, J. Soden, C. Hawkins, J. Segura, Charge based transient
current testing (CBT) for submicron CMOS SRAMs, Test Conference, 2002.
Proceedings. International, 2002, pp. 947953. http://dx.doi.org/10.1109/TEST.
2002.1041850.
[14] G. Gyepes, D. Arbet, J. Brenkus, V. Stopjakova, J. Mihalov, An on-chip dynamic
supply current monitor for testing of digital circuits, Radioelektronika
(RADIOELEKTRONIKA), 2013 23rd International Conference, 2013, pp. 156161.
http://dx.doi.org/10.1109/RadioElek.2013.6530907.
[15] H.S. Kim, D.H. Yoon, S. Kang, SRAM transparent testing methodology using
dynamic power supply current, IEE Proc. Circuits Devices Syst. 148 (4) (2001)
217222. http://dx.doi.org/10.1049/ip-cds:20010337.
[16] F. Lavratti, L. Bolzani, A. Calimera, F. Vargas, E. Macii, Technique based on
on-chip current sensors and neighbourhood comparison logic to detect
resistive-open defects in SRAMs, 2013 14th Latin American Test Workshop LATW, 2013, pp. 16. http://dx.doi.org/10.1109/LATW.2013.6562688.
[17] M. Onabajo, J. Silva-Martinez, Analog Circuit Design for Process Variation-resilient Systems-on-a-chip, Springer US, Boston, MA, 2012.
[18] S. Mukhopadhyay, H. Mahmoodi, K. Roy, Statistical design and optimization
of SRAM cell for yield enhancement, Computer Aided Design, 2004. ICCAD2004. IEEE/ACM International Conference on, 2004, pp. 1013. http://dx.doi.
org/10.1109/ICCAD.2004.1382534.
[19] K.A. Anumol, N.M.S. Mangai, P.K. Kumar, Built in self test architecture for
testing SRAM using transient current testing, Information Communication
Technologies (ICT), 2013 IEEE Conference on, 2013, pp. 331335. http://dx.doi.
org/10.1109/CICT.2013.6558115.
[20] J. Xiong, V. Zolotov, L. He, Robust Extraction of Spatial Correlation, vol. 26, IEEE
Press, Piscataway, NJ, USA, 2007, pp. 619631. http://dx.doi.org/10.1109/TCAD.
2006.884403.

Please cite this article as: A. Gomez et al., Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under
process variations, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.10.012