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Santa Clara, CA.

95051
THUY TN
Email: ntranthuy@yahoo.com

Objective: IC CMOS AMS Layout Designer

A team collaborator, successfully delivered Analog Mixed Signal custom layout designs,
seeks to contribute the equivalent 7+ years experience in IC CMOS Layout Mask Designs

Advance Tools, Languages, and Technologies:

Cadence VXL/VLE; Mentor CALIBRE Verification (DRC, LVS, ERC, SC, CCC, )
Edited P-Cell, RLC; Created/Managed Libraries attached to technology files
Design Rules of Technology: TSMCN65, TSMCN45
Unix Solaris; SUSE Linux; DesignSynch; MS-Office (PPS, Excel, Word, Project2003)

Work Experience:

Executive Program Officer


NTPEX, San Jose, CA 2008 Present
Successfully delivered the projects for mask layout designs of the Flash Memory,
SRAM SOC w/ interconnect effects Clock Distribution, I/O Power
Distribution, RAZOR Wireless block, Resonated RACON VCO, Analog embedded
core Blocks DAC, RXADC, PLL, DRC and LVS verification
RF Analog Layout Mask Designer, Sr
Qualcomm (CDMA Technologies), San Diego, CA 2007 2008
Accomplished the custom block layout designs and supported Design Engineers the
tape out activities; the layout designs included the Analog Mixed Signal embedded
core Top Blocks for Wireless SOC; DLL_SDRAM , TVDAC, PCDAC, PLL_NT, TXDAC;
placed/connected the I/O ESD devices followed DM guidelines; also generated LEF,
GDSII files.

IC CMOS Layout Engineer


Don Mask Design Consulting Groups, Stanford, CA 2001
2006
With Cadence OPUS VIRTUOSO Layout Editor to layout the devices:
o Wireless RF combined Analog, Inductor.
o Analog, Digital, BiPolar, BiCMOS, PNP, NPN, and DIODE, VCO, Op-Amp, Mirror
o SRAM, Decoder, Sense Amp, Pre-charge, buffer, Adder
o I/O Pad & ESD, Pre-driver, Buffers, Clock Distribution, Clock Drivers,
Pad circuitry
Implemented layout techniques such as Matching, Cross Coupling,
Common Centroid, digitization, Shielding, E-migration Moat, Double Guard-ring,
latch-up prevented. Isolation layers, different voltages
Modified SIPLL chip to create new version as new Schematic, verified
DRC, LVS without errors to correct by architecture design
Attended detailed schematic information, with the design team, for
the specified high performance and constraint area
Used the library of STANDARD cells for time reduced effectivenesses,
while integrated the full custom layout then ran Abstract such as Exclusive OR/NOR,
D Flip Flop, JK Flip Flop, Tri-state buffer, Transmission Gate, MUX, Memories SRAM,
ROM, DRAM, Nor && Nand Flash

Project Manager
PYROTEST DEV LLC, San Jose, CA 2002 2006
Applied the Project PMBOK, CMMI, Tools and Techniques to advance
the business environment, ensured to deliver the matching requirements and
specifications of the devices/ system designs and testing designs for the commercial
and governmental clients, etc
Education:
Computer Engineering Award Certificate in VLSI Design Engineering
University of California Santa Cruz, Santa Cruz, CA
Bachelor Degree of Science in Applied and Computational Mathematics
San Jose State University, San Jose, CA
IC CMOS Layout Design Professional Development
MOS Institute, San Jose, CA