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LCD & DLP Projectors

Programmable Solutions for


the Broadcast Industry

LCD Projector Anatomy


High Intensity
White Light Source
(a Super Backlight!)

Projection
Optics
Mirror

Transmissive
Full Image
Grayscale
LCD Arrays

Mirror

Mirror

Red LCD

Green LCD

Blue LCD

Lens

Lens

Lens

Condenser
Optics

Mirror
Mirror

Dychroic
Mirror
(wavelength
selective)

Dychroic
Mirror
(wavelength
selective)

LCD Projection Pixel Structure


Cross Sectional View
Thin Film
Transistor

Scanning Electrode

Polarizer
Pixel
Electrode

Wavelength Filtered
Glass Substrate
Projection Beam

Polarizer

Liquid Crystal Slurry

How the LCD Projector Pixel Works


Cross Sectional View

Wavelength filtered projection light enters the back of the pixel


(Green case shown)

How the LCD Projector Pixel Works


Cross Sectional View

The light proceeds to the polarizing filter unimpaired.

How the LCD Projector Pixel Works


Cross Sectional View

At the polarizing filter only a portion of the light is able to pass through.
This light is properly aligned for the LCD slurry to affect its transmission.

How the LCD Projector Pixel Works


Cross Sectional View

Light passes through LCD slurry in proportion to twist


imposed on matrix by driver circuit.
In this example no twist is applied and all of the light is able to pass.

How the LCD Projector Pixel Works


Cross Sectional View

Light then proceeds out of LCD and continues along optical projection path.

How the LCD Projector Pixel Works


Cross Sectional View

By controlling the LCD slurry twist through the driver circuit,


intensity of light escaping can be controlled.

How the LCD Projector Pixel Works


Cross Sectional View

By controlling the LCD slurry twist through the driver


circuit the intensity of light escaping can be controlled.

How the LCD Projector Pixel Works


Cross Sectional View

By controlling the LCD slurry twist through the driver


circuit the intensity of light escaping can be controlled.

How the LCD Projector Pixel Works


Cross Sectional View

By controlling the LCD slurry twist through the driver


circuit the intensity of light escaping can be controlled.

How the LCD Projector Pixel Works


Cross Sectional View

No Light at All

Until no light is emitted at all.

DLP & Digital Micromirrors


The Heart of Digital Light Processing
Micro Electro-Mechanical
(MEM) devices
The structure is capable of a
physical motion
Manufactured using
semiconductor technology

Digital Micromirrors feature and


control small aluminum mirrors
16m in size
+/-10 degrees of rotation
Switch in 15s physically,
2s optically

Image courtesy of Texas Instruments

Digital Micromirror Device (DMD)


An array of digital micromirrors packaged in single device
Digital images created by reflecting a light off the device

TI DLP - Single DMD System


Color images can be made by
shining colored light onto
DMD greyscale image
Light from source bulb is
filtered using spinning color
wheel
Combination of red, green or
blue light is then reflected to
optics from DMD

TI DLP - 3 DMD System


Light from source bulb is
diffracted using filtering prism
Each RGB color component
is reflected from its own
dedicated DMD
Reflected R,G and B light
combined (reflected along
same axis) and passed
through optics to display
Reduced mechanics
(no spinning wheel) means
system more reliable
Dedicated mirrors also mean
higher quality pictures

DLP Projector Anatomy


High Intensity
White Light Source

Projection
Optics

Mirror

Mirror

Mirror

Dychroic
Mirror

Red DMD

Selective
Blue
Reflection

Mirror

Dychroic
Mirror

Green DMD

Light Trap

Light Trap

Light Trap

Mirror

Selective
Green
Reflection

Selective
Red
Reflection

Condenser
Optics

Blue DMD

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

B
Mir
ror

Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the


Output
Cross Sectional View

High Intensity
Light Source

Mirror B
Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

B
Mir
ror

Mir
ror
A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Mirror B
Mirror A

Low
High
Intensity Intensity

Intensity is Controlled by Pulsing the Output


Cross Sectional View

High Intensity
Light Source

Projection Display
Systems

Projection System Data Flow


Source File
- RGB

- MPEG,
JPEG, etc.

Decoding

Raw
RGB

(Decompress/decrypt)

Input transport
- External: USB 2.0, IEEE 1394, Home Networking options, etc.
- Internal: IDE, LVDS, AGP, PCI, FLASH, SDRAM, etc.
DCT/IDCT, color space conversion, decryption, etc.

System transport
Display
Technology
Optimization

- HSTL, LVDS, AGP, PCI, etc.


Scaling, gamma/color correction, dithering,
brightness, contrast, sharpness, etc.

(Image adjustment)

Adjusted RGB

Display Driver

Driver transport
- LVDS, AGP, PCI, etc.
XY timing and output waveform generation
XY array driver circuit

LCD/DLP Projector
Digital Image Processing Board (Wireless)
5-GHz
IEEE 802.11a/
HiperLAN2
Video In
Wireless
LAN
Chipset

I/O Control

MPEG
Decoder

Scan
Conversion

Color Space
Conversion

DMD / ILA /
LCD / GLV

Frame
Buffers

Red
Display
Device

SDRAM

Green
Display
Device

SDRAM

Blue
Display
Device

SDRAM

Scaling

Degamma

Memory
Controller

Projection Design Challenges

System and Component Connectivity

Video and Image Processing

Which interface options should you support?


Can you support more options to increase the accessible market?
How do you integrate the best selection of components to address your application?

How do meet the performance challenge?


How do you maintain compatibility with geographically divergent and continuously evolving
formats and standards?

User Interface

System Control

Display Driver circuitry

How do you implement the best possible user interface to your design?

How do you control the system?

How do you best implement the driver circuit to get to market quickly and achieve supplier
flexibility for this high dollar BOM component?

General System Challenges


Integrating different standards
Broadband access
Home networking
System interfaces

Supporting new and evolving


specifications
Supporting different memory
and storage types

EMI signal management


Power management
Competitive pressures to
bring new features rapidly to
market
Supply chain management
Overall cost management

Each can be addressed with Xilinx solutions

Peripheral Interfacing and


System Glue
Ethernet
Ethernet

Memory
Memory
Memory
Memory
Card
Card
Modem
Modem

USB
USB

Main
Main Processor
Processor
or
or
Embedded
Embedded uP
uP

HDD
HDD

Bluetooth
Bluetooth

A/D
A/D

Interface features to the host processor


Quickly add new capabilities to existing products

Component Integration
Design Flexibility
FPGA Logic Integration Resources

SRAM

I/O

FLASH
IDE

Distributed

RAM

PCI-X

I/O I/O
UserSelect
Designed

SDRAM

Block
RAM

Controllers

AGP

PCI

AGP

SDRAM
SRAM
FLASH

I/O

PCI-X

DLL
Clock
DLL
DLL
Mgmt.
DLL

Buffers &
Memories

Controllers

PCI

I/O I/O
UserSelect
Designed

I/O
Standard
A

IDE

Xilinx Select I/OTM Technology


Chip to backplane
PCI 33MHz 3.3V
PCI 33MHz 5.0V
PCI 66MHz 3.3V
GTL, GTL+, AGP

Chip to Memory
HSTL-I, -III, -IV
SSTL3-I, -II
SSTL2-I, -II
CTT

Chip to Chip
LVTTL
LVCMOS

LVDS
LVDS
BLVDS
LVPECL

I/O
Standard
B

Storage Reference Designs


PCMCIA
Card-side (Spartan & CPLD)
Host-side (Spartan only)

CompactFlash+

Memory Stick
PCMCIA

Card-side (Spartan & CPLD)


Host-side (Spartan only)

SD/MMC
Card-side (Spartan & CPLD)
Host-side (Spartan only)

SD Card
Hard Disk Drive

IDE/ATA
Host-side only (Spartan)

Multimedia Card

Compact Flash

Memory Controller
Reference Designs
DRAM reference designs
64-bit DDR DRAM controller
16-bit DDR DRAM controller
SDRAM controller

SRAM reference designs


ZBT SRAM controller
QDR SRAM controller

Flash controller
(FPGAs/CPLDs)
NOR / NAND flash
controller

Embedded memory reference


designs

CAM for ATM applications


CAM using shift registers
CAM using Block SelectRAM
Data-width conversion FIFO
170MHz FIFO for Virtex
High speed FIFO for Spartan-IIE

Download
Downloadfrom
from
xilinx.com/memory
xilinx.com/memory

Experimenting with Tradeoffs


It would be nice to have a fully flexible device to use for
video processing designs
Allows changing of parameters like colour depth, bit accuracy
(truncation)
Allows exploration of new compression techniques or
acceleration of existing algorithms to improve throughput
Supports various frame rates and resolutions
Implements a wide range of new or existing
filters for enhancement or noise reduction

Welcome to Xilinx FPGAs


FPGAs are a key enabling technology for digital video processing
Allow experimentation for prototypes leading to differentiation for
production
And still enable higher level of system integration with support for:
video interfaces, LAN/WAN technologies, other DSP, simple glue, memory
control and state machines, backplane protocols the list is only limited
by the imagination

FIR Filters for Xilinx FPGAS


Most audio, image and video processing can be done
based around finite impulse response (FIR) filters
Programmability allows experimentation with different
coefficients, filter windows etc to get the best quality
256 Tap FIR Filter Example

IP Core or Reference Design


XAPP219 Transposed Form FIR Filters
MAC FIR
Serial Distributed Arithmetic FIR Filter
Parallel Distributed Arithmetic FIR Filter
Distributed Arithmetic FIR Filter

See www.xilinx.com/ipcenter for more details

Why FPGAs for A/V Processing?


High Computational Workloads
Conventional DSP Processor - Serial

1 GHz
256 clock cycles

= 4 MSPS

FPGA-based DSP - Parallelism

500 MHz
1 clock cycle

= 500 MSPS

Xilinx Programmable Solutions


Provide Several Benefits
Accelerating time-to-market
Consumer devices require fast time-to-market
ASICs & ASSPs take 12-18 months to spin out
Immediate production upon design release

Fast design iterations


Rich, IP portfolio and efficient tools for design and synthesis

System integration
Testing and verification
Re-programmable allows risk aversion/reduction
Solutions are built on a proven FPGA technology with preverified silicon and IP that guarantees performance

Time-to-Market Value

Revenue

Fastest
Time-to-Market

Additional
Profit from
Field
Upgrades
1st to Market
Profit
Reduced Profit
for Late Introduction

Longest
Time-in-Market

Time

Quicker time-to-market and reprogrammability provide the best


chance of achieving full product profit potential

Xilinx Programmable Solutions


Provide Several Benefits
Increased flexibility
Product customization to meet customer needs
Accommodate multiple standards & spec updates/changes
Feature upgrades through field upgradability
Remote update of software and hardware
Increased lifetime for a product (time-in-market)
and allows new, interesting applications
Enable product features per end-user needs

Broad product line


Broad IP and tools solutions

Xilinx Projector Solutions


Issues in creating a stand-alone ASIC/ASSP

Which standards and formats will win in which geographies?


Choosing the right solution: over-design, under-design
Product customization
Development cost and amortization
Flexible and customizable solutions possible in reprogrammable logic

System cost management and assured source of supply

Multiple sourcing for key high $ BOM components


Reduced support costs via reconfiguration over networks
Commodity component flexibility
Programmable logic solutions are standard parts

Low cost!

Xilinx in the Broadcast Chain


Gamma Correction
Codecs
Scaling/Resampling
Colour Space
Network Interfacing
Chip Interfacing
Video Filtering
Effects (Wipe/Key)
Memory Control
FEC/Modulation
System Control

Real Time HD/Multichannel DSP


Highest performance on-chip
DSP blocks, multipliers and
memory
Reduce size of DSP farms
Support real time HD
processing
Support multiple channels of
SD processing through
resource sharing
Reduce cost-per-channel for
FEC and modulation

DVB-S2 FEC & Modulation


Mode
Adapt

Stream
Adapt

FEC

BCH

LDPC

Interleave

Mapper

Framing

Medium Access Controller


(PowerPC)
Gigabit Network Interface

Modulator

Cost Effective Connectivity


Significant cost-per-channel
reductions
Portfolio of audio/video
connectivity solutions
SDI, HD-SDI and DVB-ASI
Video-over-IP

Wide range of general


telecom, datacom and
backplane solutions available
Ethernet, PCI Express, ATM,
Fibre Channel, SONET, SPI
RapidIO, HyperTransport

SDI
Equalizer
$10
SDI
Equalizer
$10
SDI
Equalizer
$10

XC3S1000-5
$40

SDI
Equalizer
$10

~70%
~70%cheaper
cheaperthan
than
ASSP
ASSPSDI
SDIsolutions!
solutions!

Flexible Embedded Processing


8-bit Microcontroller
Simple state-machines and
localised on-chip control
Pixel processing & display control

32-bit Microprocessors
Cost/performance tradeoffs
Extensive peripherals, RTOS &
bus structures
Networking & wireless comms,
control & instrumentation

GbE MAC

Buffer

Filter

Remapper

GbE MAC

VxWorks O/S
Data Path Ctrl

LVDS
Backplane I/F

Baseband
Processing

Xilinx in Broadcast
Programmable Solutions for the Broadcast Industry

Interfaces & Connectivity

Codecs

Video & Audio Processing

Transmission & Reception

End Applications

More info on a wide range of applications and technologies


www.xilinx.com/broadcast