Debugger 68k

CPU32 and ColdFire Debugger and Trace
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
CPU32 and ColdFire ................................................................................................................
CPU32 and ColdFire Debugger and Trace .........................................................................
Brief Overview of Documents for New Users .................................................................
Warning ..............................................................................................................................
Quick Start of the BDM Debugger ...................................................................................
Quick Start of the ROM Monitor .......................................................................................
Restrictions ........................................................................................................................
12
Troubleshooting ................................................................................................................
13
FAQ .....................................................................................................................................
14
FAQ 68K
14
FAQ ColdFire
17
ROM Monitor ......................................................................................................................
18
Monitor Features
18
Monitor Files
18
Address Layout
19
Vector Table
20
Configuration
21
Break without Hardware Interrupt
21
CPU specific Implementations .........................................................................................
22
Hardware Breakpoint for MC68360
22
Memory Classes
23
CPU specific SYStem Commands ...................................................................................

SYStem.BdmClock
24
Select CPU type
25
Run-time memory access (intrusive)
25
SYStem.CPU
SYStem.CpuAccess
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode
Lock and tristate the debug port
26
Real-time memory access (non-intrusive)
26
Establish the communication with the CPU
27
1989-2016 Lauterbach GmbH
24
Select BDM-clock
SYStem.CONFIG
Configure debugger according to target topology
28
Daisy-chain Example
30
TapStates
31
SYStem.CONFIG.CORE
Assign core to TRACE32 instance
32
Select peripheral base address
33
SYStem.Option BASE
SYStem.Option CLKDet
Resync after every clock change
33
Compare PC to hook address
33
Disable interrupts while single stepping
34
Disable interrupts while HLL single stepping
34
SYStem.Option MMUSPACES
Enable multiple address spaces support
34
SYStem.Option SLOWRESET
Slow reset enable
35
Detect HALT condition of the CPU
35
Termination of the PSTCLK pin
35
Debugger behavior when RESET is detected
36
Debugger behavior when power is restored
36
Reset target without reset of debug port
37
Trace specific Commands ................................................................................................
38
SYStem.Option HOOK
SYStem.Option IMASKASM
SYStem.Option IMASKHLL
SYStem.Option PST
SYStem.Option PSTCLKTERM
SYStem.Option ResetAction
SYStem.Option StandbyAction
SYStem.RESetOut
SYStem.Option BTB
Change the width of the address information
SYStem.Option DDC
Configure the tracing of data accesses
38
Send the PC to the trace port
38
CPU specific TrOnchip Commands .................................................................................
39
SYStem.Option TSYNC
TrOnchip.ALIGN
38
Enable breakpoint alignment
39
Enable expansion of address range
39
Enable break on SIZE lines
40
Set filter for the trace
40
TrOnchip.TOFF
Switch the sampling to the trace to OFF
40
TrOnchip.TON
Switch the sampling to the trace to ON
41
Set a trigger for the trace
41
TrOnchip.CONVert
TrOnchip.SIZE
TrOnchip.TEnable
TrOnchip.TTrigger
CPU specific MMU Commands ........................................................................................

MMU.DUMP
42
Page wise display of MMU translation table
42
Compact display of MMU translation table
43
Load MMU table from CPU
44
BDM Connector 68K ..........................................................................................................
46
BDM and Trace Connector ColdFire ................................................................................
46
MMU.List
MMU.SCAN
BDM Connectors for ColdFire V1, V2, V3, V4 and ColdFire+
46
BDM Connector 6 pin ColdFire+/V1 CPUs Debugger
47
BDM Connector 26 pin ColdFire V2 or V3 CPUs Debugger and Trace
47
BDM Connector 26 pin ColdFire V2 or V3 CPUs with ALLPST only Debugger
48
BDM Connector 26 pin ColdFire V4 CPUs Debugger and Trace
48
Technical Data BDM 68K ..................................................................................................

Operation Voltage
49
49
Technical Data BDM ColdFire ..........................................................................................
50
Operation Voltage
50
Technical Data Trace ColdFire
50
Operation Frequency
50
Operation Voltage
52
Support ...............................................................................................................................
53
Available Tools 68K
53
Available Tools ColdFire
54
Compilers 68K
57
Compilers ColdFire
58
Compilers HC16
59
Realtime Operation Systems 68K
60
Realtime Operation Systems ColdFire
60
3rd Party Tool Integrations 68K
61
3rd Party Tool Integrations ColdFire
62
Products .............................................................................................................................
63
Product Information
63
Order Information
63

Version 24-May-2016
SP:0017BE
E::w.d.l
addr/line
571
SP:0017BE
572
SP:0017C0
SP:0017C2
SP:0017C4
SP:0017C6
SP:0017C8
\\MCC\mcc\sieve+36
code
........... MIX
label
mnemonic
comment
flags[ k ] = FALSE;
clr.b
(a2)
k += prime;
adda.l d4,a2
; prime,a2
add.l
d4,d3
; prime,k
moveq
#12,d0
; #18,d0
cmp.l
d3,d0
; k,d0
bge
$17BE
4212
D5C4
D684
7012
B083
6CF4
E::w.v.chain %r %m ast ast.left

0x0 (0) (word = 0x0
NULL,
count = 12346,
(word = 0x0, count = 12,
left = 0x5200
right = 0x5600
field1 = 1,
field2 = 2),
NULL,
0x1 (1) (word = 0x0
count = 12,
left = 0x5756
right = 0x5680
EI
E::w.v.ref
flags = (1, 1, 1, 1, 1
k = 3
prime = 3
i = 0
count = 0
vint = 1
Brief Overview of Documents for New Users

Architecture-independent information:
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.
General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
Choose Help menu > Processor Architecture Manual.
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
Brief Overview of Documents for New Users
Warning
NOTE:
To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
Power ON the TRACE32 hardware.
4.
Start the TRACE32 software to load the debugger firmware.
5.
Connect the debug cable to the target.
6.
Switch the target power ON.
7.
Configure your debugger e.g. via a start-up script.
Power down:
1.
Switch off the target power.
2.
Disconnect the debug cable from the target.
3.
Close the TRACE32 software.
4.
Power OFF the TRACE32 hardware.
Warning
Quick Start of the BDM Debugger

Starting up the debugger is done as follows:
5.
Select the device prompt for the ICD Debugger and reset the system.
b:
RESet
On all host systems except of the emulator device B is already selected. The RESet command is only
necessary if you dont start directly after booting.
6.
Specify CPU specific settings.

SYStem.CPU M68360
SYStem.Option Base <addr>
The default values of all other options are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
7.
Map the EPROM simulator if available (optional).

MAP.ROM 0x0--0x1FFFF
This command maps a standard 8 bit wide 27x010 EPROM.

8.
Enter debug mode.

SYStem.Up
This command resets the CPU and enters debug mode. After this command is executed it is possible
to access memory and registers.
Some ColdFire V1 derivatives need a Power On Reset to enter debug mode out of reset without
executing code. Dependent from their actual memory contents these derivatives might stuck in a
reset loop. When you enter SYStem.Up the debugger tries to get the CPU out of such a loop, but if
the time between two resets is too small this attempt might fail. Use SYStem.Mode StandBy in this
case, remove power from the target and switch it on again.
9.
Load the program.

Data.LOAD.I mcc.abs
The format of the Data.LOAD command depends on the file format generated by the compiler. The
corresponding options for all available compilers are listed in the compiler list. A detailed description
of the Data.LOAD command is given in the General Commands Reference.
A typical start sequence without EPROM simulator is shown below. This sequence can be written to an
ASCII file and executed with the command DO <filename>.
B::
; Select the ICD device prompt
WinCLEAR
; Clear all windows
SYStem.Up
; Reset the target and enter debug mode
Data.LOAD.i mccp.x /nil
; Load the application
Register.Set PC main
; Set the PC to function main
Register.Set USP 0FEFF
; Set USP to address FEFF
Register.Set SPP 0FFFF
; Set SSP to address FFFF
Data.List
; Open disassembly window *)
PER.view
; Show clearly arranged peripherals

; in window *)
Register /SpotLight
; Open register window *)
Frame.view /Locals /Caller
; Open the stack frame with

; local variables *)
Var.Watch %SpotLight flags ast
; Open watch window for variables *)
Break.Set 0x1000 /Program
; Set breakpoint to address 1000
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
Quick Start of the ROM Monitor

Starting up the ROM Monitor is done as follows.
1.
Select the device prompt for the ICD Debugger and reset the system.
b:
RESet
On all host systems except of the emulator device B is already selected. The RESet command is only
necessary if you dont start directly after booting.
2.
Specify CPU specific settings.

SYStem.CPU M68020
SYStem.Option Base <addr>
The default values of all other option are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
3.
Map the EPROM simulator.

This command maps a standard 8 bit wide 27x010 EPROM.

4.
Load the monitor program.

Data.LOAD.B rom68.bin /ny
5.
Configure the Monitor program.

Data.Set 0x400 0x9f
; select 68020 CPU
Data.Set 0x402 1
; 16bit EPROM
At least the CPU type and EPROM size must be specified.

6.
Set the polarity of the Reset and NMI signal according to your target.
eXception.RESetPOL eXception.NMIPOL eXception.NMIBREAK ON
7.
Start the ROM Monitor.

SYStem.Up
If the RESET output of the ESI is not connected you have to reset your target after the SYStem.Up
command manually.
8.
Load the application.

Data.LOAD.i mcc.abs
The format of the Data.LOAD command depends on the file format generated by the compiler. The
corresponding options for all available compilers are listed in the compiler list. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
A typical start sequence for a ROM monitor (68332, EPROM 0--1ffff, RAM 40000--5ffff) is shown below. This
sequence can be written to an ASCII file and executed with the command DO <filename>.
B::
; Select the ICD device prompt
WinCLEAR
; Clear all windows
SYStem.CPU M68332
; Set CPU for debugger

; software
Data.LOAD.i mccp.x /nil
; Load the application
; Map the ESI
Data.LOAD rom68.hex /ny
; Load the monitor program
; add patch to disable 332 watchdog

Data.Set sp:0x0 %Long 0x41000
; Initialize the SSP
Data.Set sp:0x4 %Long 0x0ff0
; Initialize the reset vector
Data.Ass sp:0x0ff0 move.b #40,0x0fffa21
; Extra code to disable

; watchdog
Data.Ass, jmp 0x440
; Jump to monitor start
; initialize the monitor configuration table

d.s sp:0x400 %byte 10.
; Set CPU for monitor program
d.s sp:0x402 %byte 0x0
; Set the EPROM bus width
; set the polarity of RESET and NMI

eXception.RESetPOL -
; Negative polarity for Reset
eXception.NMIPOL -
; Negative polarity for NMI

10
eXception.RESBREAK ON
; Enable Reset activation
; start debugging
SYStem.Up
; Start Monitor
Data.LOAD.rof rof 0x4000 0x40000 /col
; Load Application
Register.Set PC main
; Set the PC to function main
Register.Set USP 0x0FEFF
; Set USP to address FEFF
Register.Set SPP 0x0FFFF
; Set SSP to address FFFF
Data.List
; Open disassembly window *)
Register
; Open register window *)
Var.Frame /Locals /Caller
; Open the stack frame with

; local variables *)
Var.Watch <var1> <var2>
; Add variables to watch

; window *)
Break.Set 0x10000 /p
; Set breakpoint to address

; 10000
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
11
Restrictions
Stack Memory
(only ROM Monitor)
All 68000-type ROM debuggers need memory in the supervisor

stack area (SSP) to break correctly. If you get an invalid PC value
after stopping the program, the SSP register may be outside the
memory area. This must be considered especially when debugging
the startup code of an application. The ROM Monitor needs up to
40 bytes space on the stack for step, go and EPROM modification
(Hot Patch). The stack is not required for starting the Monitor and
memory read or modify commands. BDM debuggers need no stack.
Register Setup
The SR register trace flag should not be set to 1.
12
Restrictions
Troubleshooting
No information available.
13
Troubleshooting
FAQ
FAQ 68K
Debugging via
VPN
The debugger is accessed via Internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and
"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state
checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/
Data.dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE
[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a breakpoint or manual
break. "MAP.CONST" will read the specified address range only once per
SYStem.Mode command (e.g. SYStem.Up).
14
FAQ
Setting a
Software
Breakpoint fails
What can be the reasons why setting a software breakpoint fails?

Setting a software breakpoint can fail when the target HW is not able to
implement the wanted breakpoint.
Possible reasons:
The wanted breakpoint needs special features that are only possible to
realize by the trigger unit inside the controller.
Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set
window). Breakpoints with checking in real-time for data-values ("Data").
Breakpoints with special features ("action") like TriggerTrace, TraceEnable,
TraceOn/TraceOFF.
TRACE32 can not change the memory.
Example: ROM and Flash when no preparation with FLASH.Create,
FLASH.TARGET and FLASH.AUTO was made. All type of memory if the
memory device is missing the necessary control signals like WriteEnable or
settings of registers and SpecialFunctionRegisters (SFR).
Contrary settings in TRACE32.
Like: MAP.BOnchip for this memory range. Break.SELect.<breakpoint-type>
Onchip (HARD is only available for ICE and FIRE).
RTOS and MMU:
If the memory can be changed by Data.Set but the breakpoint doesn't work it
might be a problem of using an MMU on target when setting the breakpoint to a
symbolic address that is different than the writable and intended memory
location.
15
FAQ
68360
M68360
QUADS Board
and BDM
What can I do to emulate the M68360 QUADS Board with the BDM
Debugger?
The watchdogs of both QUICCs are active after the execution of the SYStem.Up
command. The master QUICC is immediately after RESET in debug mode, but
the periphery of the slave will continue to run. So you have about 1 s until the
watchdog of the slave will become active. You must use this second to disable
this watchdog. There are two possibilities:
1. If you use the original boot EPROM:
sys.u
g
wait 1.0s
b
2. If you have no boot EPROM
;
;
;
;
683XX
DTACK
ERROR
sys.u
init Master MBAR
d.s cpu:3ff00 %L 20001
init Slave MBAR
d.s cpu:3ff08 %W 0bfff
d.s cpu:3ff04 %W 2
d.s cpu:3ff08 %W 0bfff
d.s cpu:3ff06 %W 2001
d.s sd:23022 %b 37
disable Master WD
d.s sd:21022 %b 37
disable Slave WD
d.s sd:23022 %b 37
Sometimes I receive the error message: "DTACK error reported by CPU"

after the execution of the SYStem.Up command.
After reset the CPU fetches first the stack pointer and the PC. If the fetched PC
value is invalid it is impossibe to enter debug mode in the normal way. In this
case the debugger asserts the BERR line on the BDM connector to enter debug
mode. This special debug mode entry is indicated by the warning
DTACK error reported by CPU

This is only a warning and you can continue to work as usual.
16
FAQ
68K
3.3 V support
for 68K CPU's
Is my 68K ICD Debugger prepared for 3.3 V support?

All CPU specific ICD dongle after 07.98 with a serial number like 9807000xxxx
with xxxx greater than 3000 support 3.3 V CPUs.
The JTAG/BDM input signals to the CPU will be driven with the same voltage
detected on the VCCS pin.
FAQ ColdFire
tbd.
17
FAQ
ROM Monitor
Monitor Features
The monitor requires no stack during startup and memory operations. A valid stack is only required for
modifications in the EPROM while the monitor is running (Hot Patch) and for single step and go commands.
This allows to use the monitor for testing not fully functional hardware, as only the EPROM access must
work correctly to operate the monitor. The position independent code of the monitor allows to relocate the
monitor during debugging. The NMI pin of the EPROM simulator can be used to manually stop the target
program. On serial linked ROM monitors the NMI line can be controlled by the RTS or DTR lines.
Monitor Files
The rom68 monitor is for EPROM simulator solutions, while the rom68e monitor is used as foreground
monitor for emulators. By using a foreground monitor the target program can be single stepped without
stopping the target processors interrupts or DMA transfers.
The monitor rom68s'is the serial line monitor. It requires linking with a serial line driver module. See the
example files in the monitor directory \files\demo\m68k\monitor for details. All monitors have the same
source file rom68.asm. This source file should not be modified, it is only included for reference purposes.
There are two possibilities to include the monitor in the application: loading the .bin by the Eprom Simulator
or linking the .src file together with the application. The .src files contain only the monitor code, a
corresponding configuration table has to be included in the target program.
18
ROM Monitor
Address Layout
The ROM monitor is freely relocatable in the whole address space. The communication area for the EPROM
simulator is located at the fixed address 1000 to 1FFF of the first EPROM. The CPU address depends on
the bus width of the EPROMs. The following table shows the address ranges occupied by the
communication port:
Bus Width
Start Address
End Address
8 bit
EPROM_BASE+1000
EPROM_BASE+1FFF
16 bit
EPROM_BASE+2000
EPROM_BASE+3FFF
32 bit
EPROM_BASE+4000
EPROM_BASE+7FFF
The monitor program consists of three parts:
Vector Table
Configuration Table
Monitor Program Code
The '.bin' and '.asm' files contain all three parts of the monitor. The address layout of the default monitor is as
follows:
0000--03FF
Vector Table
0400--041F
Configuration Table
0420--=FFF
Monitor Code
19
ROM Monitor
Vector Table
For the first tests of a software, the .bin files can be loaded with vector and configuration table. When the
vector table becomes part of the application, it is not loaded with the monitor. Instead the table is setup
according to the application (the table may also reside in RAM). Some vectors must be set up to point into
the monitor program code. The entry points are located at the beginning of the monitor.
vec
offs
ent
Usage
00
000
Reset Stack (optional)
01
004
+20
Reset PC (optional, can also go to application)
02
008
+50
Bus Error (optional, when Bus Errors should enter monitor)
03
00C
+50
Address Error (optional, when they should enter monitor)
04
010
+30
Illegal Instruction (used for breakpoints)
09
024
+30
Trace (used for single step)
NMI
XXX
+30
Manual Break (optional)
+40
Any unused vector may be handled by the monitor
20
ROM Monitor
Configuration
The configuration table of the monitor must always be located directly before the monitor code. The default
location used in the binary files is 400 (hex).
Processor core type (byte at offset 00H):

00 = 6800x, 6830x, 68322, 68356 (default)
03 = 68010, CPU32
9F = 68020, 68030 no MMU
A7 = 68040 no MMU
A3 = 68060 no MMU
01 = 68070, 93Cxx
EPROM Bus Width (byte at offset 02H):

0 = 8 bit (default)
1 = 16 bit
2 = 32 bit
Monitor Interrupt Level (byte at offset 04H)

0 = all interrupts enabled in monitor
7 = all interrupts disabled in monitor (default)
Relative Monitor Location (long at offset 0CH).

This is the offset from the start of the EPROM to the monitor configuration table. It is not the
absolute address of the monitor.
Break without Hardware Interrupt

If no hardware interrupts are free for the implementation of the Break command, it is possible to implement
a software solution. An interrupt of the target program (usually the timer interrupt) polls the address of the
communication area to determine when a break has been entered. If bit zero of the status byte (at location
1400H) is set, the interrupt should enter the monitor through the breakpoint entry point. The stack should be
set in the same way as if an NMI has been executed.
Clock_Interrupt:
btst #0,$1400
; clear hardware bits here, if required
beq Normal_Interrupt
jmp $420+$30
; enter monitor if bit 0 is set
Normal_Interrupt:
; continue with normal interrupt
21
ROM Monitor
CPU specific Implementations
Hardware Breakpoint for MC68360

The built-in hardware breakpoint of the 68360 can be used by the debugger. It can be used to stop the
debugger on a read or write to a variable or a fetch in the ROM area. They are set with the regular breakpoint
command as read or write breakpoints. Note that the MBAR-Register and the SYSTEM.OPTION BASE
value must be equal before setting the breakpoints. When a program breakpoint is set in a read-only
mapped area, it is automatically converted into a hardware read breakpoint.
The behavior of the hardware breakpoints can be controlled with the TrOnchip commands.
22
Memory Classes
Memory Class
Description
FC0
Function-Code 0
FC1
USER-DATA
UD
USER-DATA
FC2
USER-PROGRAM
UP
USER-PROGRAM
FC3
Function-Code 3
FC4
Function-Code 4
FC5
SUPERVISOR-DATA
SD
SUPERVISOR-DATA
FC6
SUPERVISOR-PROGRAM
SP
SUPERVISOR-PROGRAM
FC7
Function-Code 7
CPU
CPU Function-Code
User
Supervisor
Data
Program
Memory access by CPU
Emulation memory access
23
CPU specific SYStem Commands
SYStem.BdmClock
Select BDM-clock
Format:
SYStem.BdmClock <rate>
<rate>:
4 | 8 | <fixed>
<fixed>:
1000. 5000000.
Either the clock frequency divided by 4 or 8 is used as the BDM clock or a fixed clock rate. The fixed clock
rate must be used when the operation frequency is very slow or the clock is turned off or the target clock line
is not connected. The default is a fixed rate of 1 MHz.
There is an additional plug on the debug cable on the debugger side. This plug can be used as an external
clock input. With setting EXT/x the external clock input (divided by x) is used as BDM port frequency.
The ColdFire+/V1 offers two clock sources for the communication between debugger and CPU:
Format:
SYStem.BdmClock BusClock | Async
BusClock
Time base for BDM communication is the bus frequency of the CPU. This
allows a faster download if the data rate is increased by configuring the FLL. On
the other hand moving the communication frequency can cause problems,
because the debugger has to synchronize again after each change of
frequency.
Async
The lower clock of the FLL is fixed time base for BDM communication. The bus
frequency can be modified without affecting the BDM channel. This selection
requires no resynchronization on busclock changes.
This command tells the debugger how to configure the CPU when you start your debug session. If you have
to download big files you can use BusClock to get the highest available bus frequency and as a result the
highest download performance.
24
SYStem.CPU
Select CPU type
Format:
SYStem.CPU <mode>
<mode>:
000 | 010 | 020 | 030 | 040 | 060

302 | LC302 | PM302 | EN302 | 356 | 306 | 307
330 68336 | 340 | 341 | 349 | 360
Selects the processor type.
NOTE:
ROM debuggers require also a modification in the debug monitor for different
processor types.
SYStem.CpuAccess
Format:
Run-time memory access (intrusive)
SYStem.CpuAccess Enable | Denied | Nonstop
Default: Denied.
Enable
Allow intrusive run-time memory access.

In order to perform a memory read or write while the CPU is executing the
program the debugger stops the program execution shortly. Each short stop
takes 1 100 ms depending on the speed of the debug interface and on the
number of the read/write accesses required.
A red S in the state line of the TRACE32 screen indicates this intrusive behavior
of the debugger.
Denied
Lock intrusive run-time memory access.
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
run-time access to memory and variables
trace display
The debugger inhibits the following:
to stop the program execution
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
25
SYStem.LOCK
Format:
Lock and tristate the debug port
SYStem.LOCK [ON | OFF]
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
SYStem.MemAccess
Real-time memory access (non-intrusive)
Format:
SYStem.MemAccess CPU | Denied<cpu_specific>

SYStem.ACCESS (deprecated)
CPU
Real-time memory access during program execution to target is enabled.
Denied
Real-time memory access during program execution to target is disabled.
Default: Denied.
26
SYStem.Mode
Establish the communication with the CPU
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Up
Default: Down.
Selects the target operating mode.
Debug mode is active means the communication channel via debug port (JTAG) is established. The
features of the on-chip debug support (OCDS) are enabled and available.
Down
The CPU is in reset. Debug mode is not active. Default state and state after fatal
errors.
NoDebug
The CPU is running. Debug mode is not active. Debug port is tristate. In this
mode the target should behave as if the debugger is not connected.
Go
The CPU is running. Debug mode is active. After this command the CPU can be
stopped with the break command or if any break condition occurs.
Up
The CPU is not in reset but halted. Debug mode is active. In this mode the CPU
can be started and stopped. This is the most typical way to activate debugging.
Attach
Not supported.
StandBy
Not supported.
If the mode Go is selected, this mode will be entered, but the control button in the SYStem window jumps
to the mode UP.
The Emulate LED on the debug module is ON when the debug mode is active and the CPU is running.
27
SYStem.CONFIG
Configure debugger according to target topology
Format:
SYStem.CONFIG <parameter> <number_or_address>

SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
28
state
Show multicore settings.
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
(default: 0) <number> of TAPs in the JTAG chain between the core of

interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
(default: 0) <number> of instruction register bits in the JTAG chain

between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
IRPOST
(default: 0) <number> of instruction register bits in the JTAG chain

between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
TAPState
(default: 7 = Select-DR-Scan) This is the state of the TAP controller when

the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel
(default: 0) Level of TCK signal when all debuggers are tristated.
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
29
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Below, configuration for core C.

Instruction register length of
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
; Target Core C is Core 0 in Chip 1
30
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
31
SYStem.CONFIG.CORE
Assign core to TRACE32 instance
Format:
SYStem.CONFIG.CORE <coreindex> <chipindex>

SYStem.MultiCore.CORE <coreindex> <chipindex> (deprecated)
<chipindex>:
1i
<coreindex>:
1k
Default coreindex: depends on the CPU, usually 1. for generic chips

Default chipindex: derived from CORE= parameter of the configuration file (config.t32). The CORE
parameter is defined according to the start order of the GUI in T32Start with ascending values.
To provide proper interaction between different parts of the debugger the systems topology must be mapped
to the debuggers topology model. The debugger model abstracts chips and sub-cores of these chips. Every
GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is
selected a generic chip or none generic chip is created at the default chipindex.
None Generic Chips
None generic chips have a fixed amount of sub-cores with a fixed CPU type.
First all cores have successive chip numbers at their GUIs. Therefore you have to assign the coreindex and
the chipindex for every core. Usually the debugger does not need further information to access cores in
none generic chips, once the setup is correct.
Generic Chips
Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information
how to connect to the individual cores e.g. by setting the JTAG chain coordinates.
Start-up Process
The debug system must not have an invalid state where a GUI is connected to a wrong core type of a none
generic chip, two GUI are connected to the same coordinate or a GUI is not connected to a core. The initial
state of the system is value since every new GUI uses a new chipindex according to its CORE= parameter
of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must
be merged by calling SYStem.CONFIG.CORE.
32
SYStem.Option BASE
Format:
Select peripheral base address
SYStem.Option BASE <address>
Defines the base address of the internal IO of some 683xx processors. This should be set to the value used
by the target system.
Format:
Resync after every clock change
Default: OFF.
If enabled, a resynchronisation to the current communication rate of the BDM connection is carried out after
every clock change. To detect clock changes run-time memory accesses have to be performed.
SYStem.Option HOOK
Format:
Compare PC to hook address
SYStem.Option HOOK <address>
The command defines the hook address. After program break the hook address is compared against the
program counter value.
If the values are equal, it is supposed that a hook function was executed. This information is used to
determine the right break address by the debugger.
Defines the location of the PC after a break in the hook function. The hook function allows to insert a piece of
code in the execution of breakpoints. When the option is active (nonzero) the BGND breakpoint command is
replaced by an undefined instruction. The undefined instruction handler should then execute the required
code and then stop with a BGND instruction. After the code after the BGND instruction is executed with the
next Step or Go command. The code in the hook function should not modify the SSP register.
33
SYStem.Option IMASKASM
Format:
Disable interrupts while single stepping
SYStem.Option IMASKASM [ON | OFF]
Default: OFF.
If enabled, the bit responsible for ignoring pending interrupts during assembler single-step operations of the
CPU will be set. The interrupt routine is not executed during single-step operations.
SYStem.Option IMASKHLL
Format:
Disable interrupts while HLL single stepping
SYStem.Option IMASKHLL [ON | OFF]
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
SYStem.Option MMUSPACES
Format:
Enable multiple address spaces support
SYStem.Option MMUSPACES [ON | OFF]

SYStem.Option MMU [ON | OFF] (deprecated)
Default: OFF.
Enables the usage of the MMU to support multiple address spaces. The command should not be used if
only one translation table is used. Enabling the option will extend the address scheme of the debugger by a
16 bit memory space identifier. You should activate the option first, and then load the symbols.
34
SYStem.Option SLOWRESET
Format:
Slow reset enable
SYStem.Option SlowReset [ON | OFF]
Has to be switched ON if the reset line of the debug connector is not(!) connected direct to the CPU reset
pin.
Problem: At system-up the debugger has to enable the CPUs debug mode first. This is done by a certain
sequence of the debug signals. This sequence becomes faulty if the target includes a reset-circuit which
hold the reset line for a unknown period.
If SlowReset is switched ON the debugger accepts a reset-hold period of up to 1 s. A system up needs
about 3 s then!
SYStem.Option PST
Format:
Detect HALT condition of the CPU
SYStem.Option PST [ON | OFF]
Default: OFF.
Setting this option to ON enables the hardware-based check method for the HALT-condition of the CPU. For
this setting to work correctly the signals PST[3..0] (V2 and V3 ColdFire cores), ALLPST (some pin-limited
CPU's) or PSTDDATA[7..0] have to be properly connected to the debug connector.
If these signals are located on pins sharing some other functions, the PST mode of these CPU pins has to
be enabled first. The recommended setting is ON, because otherwise the HALT state of the CPU cannot be
reliably detected.
SYStem.Option PSTCLKTERM
Format:
Termination of the PSTCLK pin
SYStem.Option PSTCLKTERM [ON | OFF]
Default: ON.
Turns the termination of the PSTCLK pin on the debug connector ON/OFF.
Works only with the COLDFIRE-HS whisker.
35
SYStem.Option ResetAction
Format:
Debugger behavior when RESET is detected
SYStem.Option ResetAction [NOTHING | HALT | GO]
Default: HALT.
This setting changes the behavior of the debugger when a RESET is detected on the target board.
NOTHING
Do nothing at all; the CPU keeps running without the debugger influencing
the CPU after a RESET.
HALT
Break immediately after reset.
GO
After setting up basic registers (on-chip breakpoints, etc.), a GO is issued

automatically.
SYStem.Option StandbyAction
Format:
Debugger behavior when power is restored
SYStem.Option StandbyAction [HALT | GO]
Default: GO.
This setting changes the behavior of the debugger when the power is restored on the target board.
HALT
Break immediately after power comes back.
GO
After setting up basic registers (on-chip breakpoints, etc.), a GO is issued

automatically.
36
SYStem.RESetOut
Format:
Reset target without reset of debug port
SYStem.RESetOut
If possible (nRESET is open collector), this command asserts the nRESET line on the debug connector.
This will reset the target including the CPU but not the debug port. The function only works when the system
is in SYStem.Mode.Up.
37
Trace specific Commands
SYStem.Option BTB
Format:
Change the width of the address information
SYStem.Option BTB [16 | 24 | 32 | OFF]
Default without trace: OFF.

Default with trace: 32.
Changes the width of the address information sent to the trace. The default setting of 32 bits gives the best
trace decoding results.
SYStem.Option DDC
Format:
Configure the tracing of data accesses
SYStem.Option DDC [Write | Read | ReadWrite | OFF]
Default: OFF.
Configures the tracing of data accesses. Only accesses that leave the cache can be traced.
SYStem.Option TSYNC
Format:
Send the PC to the trace port
SYStem.Option TSYNC [ON | OFF]
Default: OFF.
Forces the CPU to send the current PC to the trace port every few milliseconds (a) when set to ON and (b) if
the CPU supports the SYNC_PC BDM instruction.
Set to ON when you have long-running code-sequences without any indirect branches, which confuse the
trace display.
38
Trace specific Commands
CPU specific TrOnchip Commands
TrOnchip.ALIGN
Format:
Enable breakpoint alignment
TrOnchip.ALIGN [ON | OFF]
Some 68360 chips cannot set the breakpoint correctly in 8 and 16 bit chip select areas. This option tries to
work around this bug by setting the breakpoint to the next quad aligned address.
TrOnchip.CONVert
Format:
Enable expansion of address range
TrOnchip.CONVert [ON | OFF]
The hardware breakpoints of the 68360 can only cover specific ranges. If a range cannot be programmed
into the breakpoint it will automatically be converted into a single address breakpoint when this option is
active. This is the default. Otherwise an error message is generated.
to.conv on
b.s 0x1000--0x17ff /w
; set breakpoints to range 1000--17ff
b.s 0x1001--0x17ff /w
; set breakpoint to address 1001
to.conv off
b.s 0x1000--0x17ff /w
; set breakpoints to range 1000--17ff
b.s 0x1001--0x17ff /w
; results in an error message
39
TrOnchip.SIZE
Format:
Enable break on SIZE lines
TrOnchip.SIZE [ON | OFF]
If activated, the SIZE lines of the processor are also used as a breakpoint criteria. The debugger will only be
stopped when the SIZE lines match the breakpoint size. Breakpoint ranges can have a size of 1,2,3 or 4
bytes. Breakpoints on a single address have no size. The following example shows the difference.
to.size on
b.s 0x1000 /w
; ignores the SIZE lines
b.s 0x1000--0x1000 /w
; break only on BYTE access
b.s 0x1000--0x1003 /w
; break only on LONG access
TrOnchip.TEnable
Format:
Set filter for the trace
TrOnchip.TEnable <par>
Obsolete command. Refer to the Break.Set command to set trace filters.
TrOnchip.TOFF
Format:
Switch the sampling to the trace to OFF
TrOnchip.TOFF
40
TrOnchip.TON
Format:
Switch the sampling to the trace to ON
TrOnchip.TON EXT | Break
TrOnchip.TTrigger
Format:
Set a trigger for the trace
TrOnchip.TTrigger <par>
Obsolete command. Refer to the Break.Set command to set a trigger for the trace.
41
CPU specific MMU Commands
MMU.DUMP
Page wise display of MMU translation table
Format:
MMU.DUMP <table> [<range> | <addr> | <range> <root> | <addr> <root>]

MMU.<table>.dump (deprecated)
<table>:
PageTable
KernelPageTable
TaskPageTable <task>
and CPU specific tables
Displays the contents of the CPU specific MMU translation table.
If called without parameters, the complete table will be displayed.
If the command is called with either an address range or an explicit address, table entries will
only be displayed, if their logical address matches with the given parameter.
The optional <root> argument can be used to specify a page table base address deviating from the default
page table base address. This allows to display a page table located anywhere in memory.
PageTable
Display the current MMU translation table entries of the CPU.

This command reads all tables the CPU currently used for MMU translation
and displays the table entries.
KernelPageTable
Display the MMU translation table of the kernel.

If specified with the MMU.FORMAT command, this command reads the
MMU translation table of the kernel and displays its table entries.
TaskPageTable
Display the MMU translation table entries of the given process.

In MMU based operating systems, each process uses its own MMU
translation table. This command reads the table of the specified process,
and displays its table entries.
See also the appropriate OS awareness manuals: RTOS Debugger for
<x>.
42
CPU specific tables:
ITLB
Displays the contents of the ITLB translation table.

Deprecated command syntax: MMU.ITLB.
DTLB
Displays the contents of the DTLB translation table.

Deprecated command syntax: MMU.DTLB.
MMU.List
Compact display of MMU translation table
Format:
MMU.List <table> [<range> | <address>]

MMU.<table>.List (deprecated)
<table>:
PageTable
KernelPageTable
Lists the address translation of the CPU specific MMU table. If called without address or range parameters,
the complete table will be displayed.
If called without a table specifier, this command shows the debugger internal translation table.
See TRANSlation.List.
If the command is called with either an address range or an explicit address, table entries will only be
displayed, if their logical address matches with the given parameter.
PageTable
List the current MMU translation of the CPU.

This command reads all tables the CPU currently used for MMU
translation and lists the address translation.
KernelPageTable
List the MMU translation table of the kernel.

MMU translation table of the kernel and lists its address translation.
TaskPageTable
List the MMU translation of the given process.

and lists its address translation.
<x>.
43
MMU.SCAN
Load MMU table from CPU
Format:
MMU.SCAN <table> [<range> <address>]

MMU.<table>.SCAN (deprecated)
<table>:
PageTable
KernelPageTable
ALL
and CPU specific tables
Loads the CPU specific MMU translation table from the CPU to the debugger internal translation table. If
called without parameters the complete page table will be loaded. The loaded address translation can be
viewed with TRANSlation.List.
If the command is called with either an address range or an explicit address, page table entries will only be
loaded if their logical address matches with the given parameter.
PageTable
Load the current MMU address translation of the CPU.

This command reads all tables the CPU currently used for MMU translation,
and copies the address translation into the debugger internal translation
table.
KernelPageTable
Load the MMU translation table of the kernel.

table of the kernel and copies its address translation into the debugger
internal translation table.
TaskPageTable
Load the MMU address translation of the given process.

and copies its address translation into the debugger internal translation
table.
<x>.
ALL
Load all known MMU address translations.

This command reads the OS kernel MMU table and the MMU tables of all
processes and copies the complete address translation into the
debugger internal translation table.
<x>.
44
CPU specific tables:

-- No CPU specific tables --
45
BDM Connector 68K
Signal
DSGND
GND
RESETVCCS
Pin
1
3
5
7
9
Pin
2
4
6
8
10
Signal
BERRBKPTFREEZE
DSI (IFETCH-)
DSO (IPIPE-)
BDM and Trace Connector ColdFire
BDM Connectors for ColdFire V1, V2, V3, V4 and ColdFire+
The signals needed for debugging and tracing are combined in a single connector.
Some of the pins in the schematics below have multiple alternate signal names. Please check
the "BDM Connector Pinout" chapter of the reference manual for the exact CPU you are using
for further details or contact our support team.
46
BDM Connector 68K
BDM Connector 6 pin ColdFire+/V1 CPUs Debugger

Signal
BKGD
N/C
N/C
Pin
1
3
5
Pin
2
4
6
Signal
GND
RESETVCC
BDM Connector 26 pin ColdFire V2 or V3 CPUs Debugger and Trace

Signal
N/C
GND
GND
RESETVDD_IO 1.8...5.0 V
GND
PST2
PST0
DDATA2
DDATA0
N/C
GND
VDD_CPU 1.8-5.0V
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
BKPTDSCLK
N/C
DSI
DSO
PST3
PST1
DDATA3
DDATA1
GND
N/C
PSTCLK/CLKOUT/CPUCLK
TEA-/TA-/DTACK-/BERR-
If the tracing capability is not needed, DDATA3..0 can be connected or pulled down to GND.
47
BDM Connector 26 pin ColdFire V2 or V3 CPUs with ALLPST only Debugger

Signal
N/C
GND
GND
RESETVDD_IO 1.8-5.0V
GND
ALLPST or pull-up resistor
GND or pull-down resistor
N/C
GND
VDD_CPU 1.8...5.0 V
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
BKPTDSCLK
N/C
DSI
DSO
ALLPST
GND
N/C
PSTCLK/CLKOUT/CPUCLK
TEA-/TA-/DTACK-/BERR-
This connector cannot be used for tracing, because the CPU variants with the ALLPST signal
miss the necessary PST3..0 and DDATA3..0 signals.
BDM Connector 26 pin ColdFire V4 CPUs Debugger and Trace

Signal
N/C
GND
GND
RESETVDD_IO 1.8...5.0 V
GND
PSTDDATA6
PSTDDATA4
PSTDDATA2
PSTDDATA0
N/C
GND
VDD_CPU 1.8-5.0V
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
BKPTDSCLK
N/C
DSI
DSO
PSTDDATA7
PSTDDATA5
PSTDDATA3
PSTDDATA1
GND
N/C
PSTCLK
TA-
48
Technical Data BDM 68K
Operation Voltage
Adapter
OrderNo
Voltage Range
BDM Debugger for 68K (ICD)
LA-7710
3.0 .. 5.5 V
49
Technical Data BDM 68K
Technical Data BDM ColdFire
Operation Voltage
Adapter
OrderNo
Voltage Range
BDM Debugger for ColdFire+/V1 (ICD)

BDM Debugger for ColdFire HS (ICD)
LA-3746
LA-3757
3.0 .. 5.5 V
3.0 .. 5.5 V
Technical Data Trace ColdFire
Operation Frequency
Module
CPU
TRACE
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
MCF5202
MCF5203
MCF5204
MCF5206
MCF5206E
MCF5207
MCF5208
MCF52100
MCF5211
MCF52110
MCF5212
MCF5213
MCF5214
MCF5216
MCF52210
MCF52211
MCF52212
MCF52213
MCF52221
MCF52223
MCF52230
MCF52231
MCF52232
50
Module
CPU
TRACE
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
MCF52233
MCF52234
MCF52235
MCF52236
MCF52256
MCF52258
MCF52259
MCF52274
MCF52277
MCF5232
MCF5233
MCF5234
MCF5235
MCF5249
MCF5249L
MCF5270
MCF5271
MCF5272
MCF5274
MCF5274L
MCF5275
MCF5275L
MCF5280
MCF5281
MCF5282
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
MCF5307
MCF5307A
MCF5307B
MCF5327
MCF5328
MCF5329
MCF5372
MCF5372L
MCF5373
MCF5373L
MCF5407
MCF54410
51
Module
CPU
TRACE
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
LA-3759
MCF54415
MCF54416
MCF54417
MCF54418
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
MCF5470
MCF5471
MCF5472
MCF5473
MCF5474
MCF5475
MCF5480
MCF5481
MCF5482
MCF5483
MCF5484
MCF5485
Operation Voltage
Adapter
OrderNo
Voltage Range
Preprocessor for ColdFire family HS
LA-3759
3.0 .. 5.5 V
52
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
DEBUG
ICE
MC68330
MC68331
MC68332
MC68334
MC68336
MC68338
MC68340
MC68341
MC68349
MC68360
MC68376
MC68EN360
MC68F333
MC68MH360
FIRE
CPU
Available Tools 68K
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
53
Support
CFV1CORE_ALTERA
MCF51AC
MCF51AG
MCF51CN
MCF51EM
MCF51JE
MCF51JF
MCF51JG
MCF51JM
MCF51JU
MCF51MM
MCF51QE
MCF51QM
MCF51QU
MCF51QW
MCF5202
MCF5203
MCF5204
MCF5206
MCF5206E
MCF5207
MCF5208
MCF52100
MCF5211
MCF52110
MCF5212
MCF5213
MCF5214
MCF5216
MCF52210
MCF52211
MCF52212
MCF52213
MCF52221
MCF52223
MCF52230
MCF52231
MCF52232
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools ColdFire
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
54
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
MCF52233
MCF52234
MCF52235
MCF52236
MCF52252
MCF52254
MCF52255
MCF52256
MCF52258
MCF52259
MCF52274
MCF52277
MCF5232
MCF5233
MCF5234
MCF5235
MCF5249
MCF5249L
MCF5270
MCF5271
MCF5272
MCF5274
MCF5274L
MCF5275
MCF5275L
MCF5280
MCF5281
MCF5282
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
MCF5307
MCF5307A
MCF5307B
MCF5327
MCF5328
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
55
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
MCF5329
MCF5372
MCF5372L
MCF5373
MCF5373L
MCF5407
MCF54410
MCF54415
MCF54416
MCF54417
MCF54418
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
MCF5470
MCF5471
MCF5472
MCF5473
MCF5474
MCF5475
MCF5480
MCF5481
MCF5482
MCF5483
MCF5484
MCF5485
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
56
Support
Compilers 68K
Language
Compiler
Company
Option
Comment
ADA
ALSYS-ADA
ALSYS
IEEE
ADA
TELESOFT-ADA
Telesoft
IEEE
ASM
RTOS
IEP GmbH
SYM/LOC
ASM
ASM68K
limited support
(IEEE)
limited support
(IEEE)
Source level
debugging
Source level
debugging
symbols only
Source level
debugging
IEEE
ASM
ASM
Mentor Graphics
Corporation
VERSADOS-ASM NXP Semiconductors
OS-9-ASSEMBLER Radisys Inc.
ASM
C
AS68
ORGANON
IEEE
BOUND
C
C
C68K
GNU-C
GNU-C
GNU-C
C
C
C
C
GREEN-HILLS-C
HP-64000-C
ICC68K
MCC
HT-68K
C
C
C
C
C
C
C
C
C
C
C
HICROSS-68K
CC68K
SUN3-CC
ULTRA-C
OS/9-C
CROSSCODE-C
SCC68K
ICC68K
ICC68K
TT-68K
TCC68K
TASKING
CAD-UL
ElectronicServices
GmbH
Cosmic Software
Free Software
Foundation, Inc.
Free Software
Foundation, Inc.
Free Software
Foundation, Inc.
Greenhills Software Inc.
HP
Introl Corporation
Mentor Graphics
Corporation
Microchip Technology
Inc.
NXP Semiconductors
NXP Semiconductors
Oracle Corporation
Radisys Inc.
Radisys Inc.
SDSI
Sierra
TASKING
TASKING
TASKING
TASKING
C
C
C
TEKTRONIX-C
D-CC
D-CC
Tektronix
Wind River Systems
Wind River Systems
COMFOR
IEEE
ELF/DWARF
VERSADOS
ROF
COSMIC
ELF/DWARF
COFF
ELF/DWARF
COFF
HP
ICOFF
IEEE
no type/locals info
HITECH
HICROSS
COFF
DBX
ROF
ROF
SDS
COFF
COFF
IEEE
IEEE
AOUT
OS/9 compilers
only source and

syms
57
Support
Language
Compiler
C++
ORGANON-C++
C++
C++
C++
C++
C++
C++
C++
MODULA
MODULA
MODULA
PASCAL
PEARL
Company
CAD-UL
ElectronicServices
GmbH
GNU-C++
Free Software
Foundation, Inc.
GNU-C++
Free Software
Foundation, Inc.
CCC68K
Mentor Graphics
Corporation
HICROSS-68K
NXP Semiconductors
CODEWARRIOR
NXP Semiconductors
CROSSCODE-C++ SDSI
D-C++
Wind River Systems
MOD68K
Introl Corporation
MCS2
Multichannelsystems
GmbH
MCDS
NXP Semiconductors
MPC
Mentor Graphics
Corporation
RTOS
IEP GmbH
Option
Comment
BOUND
DBX
ELF/DWARF
IEEE
HICROSS
ELF/DWARF
SDS
ELF/DWARF
ICOFF
COFF
MCDS
IEEE
SYM/LOC
no type/locals info
Comment
Compilers ColdFire
Language
Compiler
Company
Option
C
C++
GREENHILLS-C
GNU-C
COFF
ELF/DWARF
C++
MCC
C++
C++
C/C++
CODEWARRIOR
DCC
ICC68K
Greenhills Software Inc.

Free Software
Foundation, Inc.
Mentor Graphics
Corporation
NXP Semiconductors
Wind River Systems
TASKING
IEEE
ELF/DWARF
ELF/DWARF
IEEE
58
Support
Compilers HC16
Language
Compiler
Company
Option
C
C
C
C
CX68HC16
ICC6816
ICC68HC16
HICROSS-68HC16
Cosmic Software
IAR Systems AB
Introl Corporation
NXP Semiconductors
COSMIC
UBROF
ICOFF
HICROSS
Comment
59
Support
Realtime Operation Systems 68K

Name
Company
Comment
AdaWorld ARTK
AMX
ChorusOS
CMX-RTX
MQX
MTOS-UX
Nucleus PLUS
OS-9
OSE Classic
OSE Delta
RealTime Craft
RTXC 3.2
SDT-Cmicro
uCLinux
VRTX32
VRTXmc
VRTXsa
VxWorks
Atego Ldt.
KadakProducts Ltd.
Oracle Corporation
CMX Systems Inc.
Synopsys, Inc
IPI
Mentor Graphics Corporation
Radisys Inc.
Enea OSE Systems
Enea OSE Systems
GSI tecsi
Quadros Systems Inc.
IBM Corp.
Freeware II
Wind River Systems
2.40 and 2.50, 3.6
(OS68)
4.x and 5.x
(XEC68k)
Kernel Version 2.4 and 2.6, 3.x
5.x and 6.x
Realtime Operation Systems ColdFire

Name
Company
Comment
ECOS
Linux
MQX
Nucleus PLUS
OSEK
ProOSEK
RTEMS
RTXC Quadros
Sciopta
SMX
ThreadX
uC/OS-II
uCLinux
eCosCentric Limited
NXP Semiconductors
Elektrobit Automotive GmbH
RTEMS
Quadros Systems Inc.
Sciopta
Micro Digital Inc.
Express Logic Inc.
Micrium Inc.
Freeware II
1.3, 2.0 and 3.0

Kernel Version 2.4 and 2.6, 3.x, 4.x
3.x and 4.x
via ORTI
via ORTI
4.10
3.4 to 4.0
3.0, 4.0, 5.0
2.0 to 2.92
Kernel Version 2.4 and 2.6, 3.x, 4.x
60
Support
3rd Party Tool Integrations 68K

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
68K
68K
68K
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
OS68 DEBUGGER
SDT CMICRO
DIAB RTA SUITE
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
Enea OSE Systems

IBM Corp.
Wind River Systems
Windows
Windows
61
Support
3rd Party Tool Integrations ColdFire

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COLDFIRE
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
DIAB RTA SUITE
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
Wind River Systems
Windows
62
Support
Products
Product Information
OrderNo Code
Text
LA-7710
BDM-68K
supports MC68330..341, 68349, 68360,

includes software for Windows, Linux and MacOSX
requires Power Debug Module
OrderNo Code
Text
LA-3757
BDM-COLDFIRE-HS
supports FREESCALE ColdFire Family

requires Power Debug Module or PowerTrace
debug cable with 26 pin connector
LA-7982
Adapter for ColdFire BDM to Arcturus Board
ADAPTER-CF-ARCTUR
LA-3746
BDM-COLDFIRE-V1
supports FREESCALE ColdFire+/V1 Family

requires Power Debug Module or PowerTrace
debug cable with 6 pin connector
OrderNo Code
Text
LA-3759
PP-COLDFIRE-HS
Preprocessor for ColdFire

adaption to standard FREESCALE connector
requires LA-3757 (BDM Debugger for ColdFire HS)
Order Information
Order No.
Code
Text
LA-7710
BDM-68K
63
Products
Order No.
Code
Text
LA-3757
LA-7982
LA-3746
BDM-COLDFIRE-HS
ADAPTER-CF-ARCTUR
BDM-COLDFIRE-V1

Adapter for ColdFire BDM to Arcturus Board
Additional Options
LA-3759
PP-COLDFIRE-HS
Order No.
Code
Text
LA-3759
PP-COLDFIRE-HS
64
Products

Debugger 68k

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CPU32 and ColdFire Debugger and Trace

TRACE32 Online Help

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

CPU32 and ColdFire ................................................................................................................

CPU32 and ColdFire Debugger and Trace .........................................................................

Brief Overview of Documents for New Users .................................................................

Quick Start of the BDM Debugger ...................................................................................

Quick Start of the ROM Monitor .......................................................................................

ROM Monitor ......................................................................................................................

Break without Hardware Interrupt

CPU specific Implementations .........................................................................................

Hardware Breakpoint for MC68360

CPU specific SYStem Commands ...................................................................................

Select CPU type

Run-time memory access (intrusive)

Lock and tristate the debug port

Real-time memory access (non-intrusive)

Establish the communication with the CPU

1989-2016 Lauterbach GmbH

CPU32 and ColdFire Debugger and Trace

Configure debugger according to target topology

Assign core to TRACE32 instance

Select peripheral base address

Resync after every clock change

Compare PC to hook address

Disable interrupts while single stepping

Disable interrupts while HLL single stepping

Enable multiple address spaces support

Slow reset enable

Detect HALT condition of the CPU

Termination of the PSTCLK pin

Debugger behavior when RESET is detected

Debugger behavior when power is restored

Reset target without reset of debug port

Trace specific Commands ................................................................................................

Change the width of the address information

Configure the tracing of data accesses

Send the PC to the trace port

CPU specific TrOnchip Commands .................................................................................

Enable breakpoint alignment

Enable expansion of address range

Enable break on SIZE lines

Set filter for the trace

Switch the sampling to the trace to OFF

Switch the sampling to the trace to ON

Set a trigger for the trace

CPU specific MMU Commands ........................................................................................

Page wise display of MMU translation table

Compact display of MMU translation table

Load MMU table from CPU

BDM Connector 68K ..........................................................................................................

BDM and Trace Connector ColdFire ................................................................................

BDM Connectors for ColdFire V1, V2, V3, V4 and ColdFire+

BDM Connector 6 pin ColdFire+/V1 CPUs Debugger

BDM Connector 26 pin ColdFire V2 or V3 CPUs Debugger and Trace

BDM Connector 26 pin ColdFire V2 or V3 CPUs with ALLPST only Debugger

BDM Connector 26 pin ColdFire V4 CPUs Debugger and Trace

Technical Data BDM 68K ..................................................................................................

1989-2016 Lauterbach GmbH

CPU32 and ColdFire Debugger and Trace

Technical Data BDM ColdFire ..........................................................................................

Technical Data Trace ColdFire

Available Tools 68K