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M-Core ......................................................................................................................................
Warning ..............................................................................................................................
Breakpoints ........................................................................................................................
Software Breakpoints
On-chip Breakpoints
Breakpoint in ROM
Troubleshooting ................................................................................................................
10
SYStem.Up Errors
10
10
FAQ .....................................................................................................................................
11
Configuration .....................................................................................................................
15
System Overview
15
Runtime Measurement
16
Memory Classes
16
Memory Coherency
16
SYStem.CONFIG
SYStem.CONFIG
17
17
17
17
Daisy-chain Example
20
TapStates
21
SYStem.CONFIG.CORE
SYStem.CPU
1989-2016 Lauterbach GmbH
M-Core Debugger
22
23
SYStem.CpuAccess
24
25
25
26
27
SYStem.JtagClock
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode
28
SYStem.Option DUALPORT
SYStem.Option DE
28
SYStem.Option IMASKASM
28
29
SYStem.Option IMASKHLL
SYStem.Option PC
29
29
30
SYStem.Option TRST
TrOnchip.CYcle
TrOnchip.A.Address
30
31
TrOnchip.CONVert
32
TrOnchip.EXTernal
32
33
34
TrOnchip.Mode
TrOnchip.VarCONVert
TrOnchip.RESet
34
34
35
36
TrOnchip.view
Operation Voltage
36
Support ...............................................................................................................................
Available Tools
37
37
Compilers
37
37
38
Products .............................................................................................................................
39
Product Information
39
Order Information
39
M-Core Debugger
M-Core Debugger
Version 24-May-2016
#
B::Register
R0
81007FC8
R1
28
R2
0B
R3
666666BE
R4
404F6666
R5
66666666
R6
1
R7
81003953
R8
R9
R10
R11
R12
R13
R14
R15
B::SYStem
Mode
Down
NoDebug
Go
Attach
StandBy
Up (Stand
Up
12345678
9999
1
0
2E002524
81002478
0B
81000A94
PSR
80000001 SS0
1958884A
VBR
81000000 SS1
160F1000
EPSR C3008ADC SS2
E0841008
FPSR 33088171 SS3
0428C10C
EPC
FFFFFFFE SS4
A212880F
FPC
212106CA GCR
0
PC
81000AB2 GSR
0
S S TM 0 TC _ MM _ EE _
IC _ IE _ FE _ AF _ C C
R0'
R1'
82DA8EA3
8543E702
R8'
R9'
MemAccess
CPU
Denied
CpuAccess
Enable
Denied
Nonstop
Option
IMASKASM
IMASKHLL
DE
JtagClock
10.0MHz
CPU
MMC2114
C03A0C4C
57631807
B::Data.List
addr/line
source
int anzahl;
682
anzahl = 0;
684
686
688
690
691
692
694
695
)
i + i + 3;
primz;
k <= SIZE )
flags[ k ] = FALSE;
k += primz;
}
anzahl++;
697
}
}
M-Core Debugger
; i++ )
General Note
This documentation describes the processor specific settings and features for
TRACE32-ICD for the following CPU families:
If some of the described functions, options, signals or connections in this Processor Architecture Manual are
only valid for a single CPU or for specific families, the name(s) of the family(ies) is added in brackets.
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
M-Core Debugger
General Note
Warning
NOTE:
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
4.
5.
6.
7.
Power down:
1.
2.
3.
4.
M-Core Debugger
Warning
If you are working with the PODPC card, a Podbus-Ethernet interface or a Podbus-Parallel adapter
device b:: is already selected.
6.
7.
This command resets the CPU (RESET) and enters debug mode. After this command is executed it
is possible to access the CPU registers. Set the chip selects to get access to the target memory.
9.
The option of the Data.LOAD command depends on the file format generated by the compiler. For
information on the compiler options refer to the section Compiler. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
M-Core Debugger
The start up can be automated using the programming language PRACTICE. A typical start sequence is
shown below:
b::
WinCLEAR
MAP.BOnchip
0x00000000++0x0001FFFF
SYStem.CPU MMC2107
SYStem.Up
Data.LOAD.ELF diabc.x
Data.List
Register /SpotLight
PER.view
Break.Set sieve
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
M-Core Debugger
Breakpoints
There are two types of breakpoints available: Software breakpoints and on-chip breakpoints.
Software Breakpoints
Software breakpoints are the default breakpoints for program breakpoints. A software breakpoint is
implemented by patching a break code into the memory.
There is no restriction in the number of software breakpoints.
On-chip Breakpoints
The resources for the on-chip breakpoints are provided by the CPU.
The following list gives an overview of the on-chip breakpoints for the MCORE:
Instruction breakpoints: Number of on-chip breakpoints that can be used to set Program
breakpoints into ROM/FLASH/EEPROM.
Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
MCORE
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoint
M-Core Debugger
Breakpoints
Breakpoint in ROM
By default program breakpoints are implemented as software breakpoints.
With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH,EPROM) on the target. If a breakpoint is set within the specified address range the debugger uses
automatically the available on-chip breakpoints.
; Software Breakpoint 1
; Software Breakpoint 2
; Software Breakpoint 3
On-chip breakpoints:
Break.Set 0x0100 /Program
; On-chip Breakpoint 1
; On-chip Breakpoint 2
; On-chip Breakpoint 1
; On-chip Breakpoint 2
M-Core Debugger
Breakpoints
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
M-Core Debugger
10
Troubleshooting
FAQ
No information available
Connect a
Nexus Probe to
a PowerTrace
Unit
Incorrect
Nexus-POD
CPLD Revision
M-Core Debugger
11
FAQ
Missing
Address
Information on
Top of the
Trace
Is there any reason why symbol addresses and names are not displayed
from the beginning of the trace?
The Nexus protocol defines that a full address is transferred only occasionally,
just in a Branch-Trace-Sync-Message and Data-Trace-Sync-Message. Most of
the time only the significant portion of the current address is generated in the
device and transferred in a Nexus message. Therefore the address can only be
reconstructed and displayed after occurrence of a Sync-Message in the trace
memory. A Sync messages is generated automatically after 255 messages
latest.
A single Nexus message without knowing what had happened before is useless!
Look at the T.L /NEXUS , then one will see the location of the DTSM . After that
location the address information is visible.
A Sync message could be missing on top of the trace in the following cases:
Any time Program is running before trace is in ARM state!
Normally if analyzer is armed manually!
In FIFO mode if trace memory overflows.
Selective trace using Watchpoints
Selective trace using CTU
Some other cases.
Nexus
Connector
Pinout on
Target
I don't know exactly which signals from MCU must be connected to which
signal on the AUX-port connector.
Must certain signals be crossed ?
Not at all. The pin out one can find in the manual and at our home page, fits the
description of Nexus standard from the target point of view.
With other words, you have to connect the signals from the device to the
appropriate signals with the same name on the connector. You
must not take care about signal crossing.
M-Core Debugger
12
FAQ
No or wrong
Data in Nexus
Trace
M-Core Debugger
M-Core Debugger
14
FAQ
Configuration
System Overview
HUB
PC or
Workstation
Target
Debug Cable
PODBUS IN
TRIG
RECEIVE
COLLISION
PODBUS OUT
JTAG
Connector
ETHERNET
CON ERR
DEBUG CABLE
TRIGGER
TRANSMIT
POWER
7-9 V
LAUTERBACH
EMULATE
RECORDING
DEBUG CABLE
SELECT
USB
Ethernet
Cable
POWER
AC/DC Adapter
PC
Target
Debug Cable
PODBUS IN
USB
Cable
POWER
DEBUG CABLE
USB
POWER
7-9 V
LAUTERBACH
SELECT
EMULATE
DEBUG CABLE
TRIG
PODBUS OUT
JTAG
Connector
LAUTERBACH
M-Core Debugger
15
Configuration
Runtime Measurement
The command RunTime allows run time measurement based on polling the CPU run status by software.
Therefore the result will be about few milliseconds higher than the real value.
If the signal DE is available on the JTAG connector, the measurement will automatically be based on this
hardware signal which delivers very exact results. Please do not disable the option SYStem.Option DE.
Memory Classes
The following memory classes are available:
Memory Class
Description
Program
Data
NC
Memory Coherency
Memory coherency on access to following memory classes.
Physical Memory
NC:
Yes
D:
Yes
P:
Yes
M-Core Debugger
16
Configuration
SYStem.BdmClock
SYStem.CONFIG
The SYStem.CONFIG commands are used to configure the behavior of the complete target system for
debugging, e.g., the Debug Interface or the chaining of several CPUs.
This command replaces the SYStem.MultiCore command and uses exactly the same parameters.
SYStem.CONFIG
Format:
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
M-Core Debugger
17
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
M-Core Debugger
18
state
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
IRPOST
TAPState
TCKLevel
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
M-Core Debugger
19
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
M-Core Debugger
20
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
M-Core Debugger
21
SYStem.CONFIG.CORE
Format:
<chipindex>:
1i
<coreindex>:
1k
M-Core Debugger
22
SYStem.CPU
Format:
SYStem.CPU <cpu>
<cpu>:
M-Core Debugger
23
SYStem.CpuAccess
Format:
Default: Denied.
Enable
Denied
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
trace display
The debugger inhibits the following:
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
M-Core Debugger
24
SYStem.JtagClock
Format:
SYStem.JtagClock <rate>
<fixed>:
Buffers, additional loads or high capacities on the JTAG/COP lines can reduce
the debug speed.
SYStem.LOCK
Format:
Default: OFF.
LOCK must be switched on, if several debuggers are used to debug several Cores using the same JTAG
connector. By locking the debug lines for certain cores another debugger can own mastership on the JTAG
interface.
It must be ensured that the state of the MCORE JTAG state machine remains unchanged while the system
is locked.
M-Core Debugger
25
SYStem.MemAccess
Format:
CPU
Denied
Default: Denied.
This option declares if and how a non-intrusive memory access can take place while the CPU is executing
code. Although the CPU is not halted, run-time memory access creates an additional load on the
processors internal bus.
The run-time memory access has to be activated for each window by using the memory class E: (e.g.
Data.dump E:0x100) or by using the format option %E (e.g. Var.View %E var1). It is also possible to activate
this non-intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting
SYStem.Option DUALPORT ON.
M-Core Debugger
26
SYStem.Mode
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Attach
Up
StandBy
NoDebug
Resets the target with debug mode disabled. The CPU acts like no debugger is
connected.
Go
Resets the target with debug mode enabled. Afterwards the CPU starts
executing the code.
The CPU can be stopped with the break command or until any break condition
occurs.
Attach
User program remains running (no reset) and the debug mode is activated.
After this command the user program can be stopped with the break command
or if any break condition occurs.
Up
Resets the target (HRESET line) and sets the CPU to debug mode. The CPU
stops at the reset vector afterwards.
StandBy
Not implemented.
M-Core Debugger
27
SYStem.Option DE
Format:
ON (default)
The debugger stops the CPU via the Debug Enable line.
OFF
The debugger stops the CPU by transferring a special command via the JTAG
interface.
OFF is only recommended if stopping the CPU via the Debug Enable line is not
possible.
SYStem.Option DUALPORT
Format:
Default: OFF.
ON
(NEXUS only)
Switches the run-time memory access to ON for all windows that display
memory. Use this option if you want all windows to be updated while the
processor is running. This setting has no effect if SYStem.Option.MemAccess
is denied.
SYStem.Option IMASKASM
Format:
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The result
is that interrupts are not accepted during single-step operations. After each single step the interrupt mask
bits are restored to the value before the step.
M-Core Debugger
28
SYStem.Option IMASKHLL
Format:
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The result is that
interrupts are not accepted during HLL single-step operations. After each HLL single step the interrupt mask
bits are restored to the value before the step.
SYStem.Option PC
Format:
SYStem.Option PC <addr>
SYStem.Option TRST
Format:
ON (default)
OFF
M-Core Debugger
29
TrOnchip.CYcle
Format:
TrOnchip.A.CYcle <cycle>
TrOnchip.B.CYcle <cycle>
<cycle>:
ANY
Read
Write
Access
Execute
Defines on which cycle the ICE breaker stops the program execution.
ANY
Read
Write
Access
Execute
M-Core Debugger
30
TrOnchip.A.Address
Format:
TrOnchip.A.Address <selector>
TrOnchip.B.Address <selector>
<selector>:
OFF
Alpha
Beta
Charly
The address/range for an address selector can not be defined directly. Set an breakpoint of the type Alpha,
Beta or Charly to the address/range.
OFF
Alpha
Beta
Charly
.
Break.Set 1000 /Alpha
TrOnchip.A.Address Alpha
M-Core Debugger
31
TrOnchip.CONVert
Format:
The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.CONVert OFF
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.EXTernal
Format:
Generates a trigger for the trace on a high pulse (at least 20 ns) on the IN0 or IN1 connector of the NEXUS
adapter. IN0 and IN1 are ORed for the trigger.
OFF
IN0
IN1
M-Core Debugger
32
Example: Stop the sampling to the trace if a high pulse is recognized at IN0.
TrOnchip.EXTernal IN0
Go
TrOnchip.Mode
Format:
TrOnchip.Mode <mode>
<mode>:
AORB
AANDB
BAFTERA
AANDB
BAFTERA
Stop the program execution if first unit A and then unit B match.
M-Core Debugger
33
TrOnchip.VarCONVert
Format:
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.
TrOnchip.RESet
Format:
TrOnchip.RESet
Sets the TrOnchip settings and trigger module to the default settings.
TrOnchip.view
Format:
TrOnchip.view
M-Core Debugger
34
JTAG Connector
Signal
TDI
TDO
TCLK
(GPIO-SI-)
RESETVDD TARGET
(!GPIO-SO)
Pin
1
3
5
7
9
11
13
Pin
2
4
6
8
10
12
14
Signal
GND
GND
GND
N/C
TMS
DETRST-
This is a standard 14 pin double row (two rows of seven pins) connector (pin to pin spacing: 0.100 in.).
(Signals in brackets are not strong necessary for basic debugging, but its recommended to take in
consideration for future designs.)
M-Core Debugger
35
JTAG Connector
Technical Data
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
Adapter
OrderNo
Voltage Range
LA-7745
2.5 .. 5.5 V
M-Core Debugger
36
Technical Data
Support
M310
MMC2001
MMC2107
MMC2112
MMC2113
MMC2114
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
Compilers
Language
Compiler
GNU-C
C
C
Company
Free Software
Foundation, Inc.
HICROSS-MCORE NXP Semiconductors
D-CC
Wind River Systems
Option
Comment
ELF/DWARF
ELF/DWARF
ELF/DWARF
Company
Comment
Nucleus
OSEK
ProOSEK
via ORTI
via ORTI
M-Core Debugger
37
Support
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
M-Core Debugger
38
Support
Products
Product Information
OrderNo Code
Text
LA-7745
ONCE-MCORE
Order Information
Order No.
Code
Text
LA-7745
ONCE-MCORE
M-Core Debugger
39
Products