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Table of Contents
Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embed Test Circuitry in Your IC Design to Test SerDes or PLLs . . . . . . . . . . . . . . . . . . . .
Characterize and Diagnose Silicon Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generate Production Test Patterns for Your IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 2
Step 1: Prepare Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SerDes Suitability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL/DLL Suitability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stable Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Implementation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.0 Create Working Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.1 ETChecker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.2 Indicate TAP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provide Connections for Second TAP, If Necessary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.3 Indicate Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.4 Check Clock Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.5 Check DFT Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.6 Check Default Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.7 ETPlanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.8 Check Default Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.9 CUT Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections for PLLs and DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.10 Collect Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.11 Update .etplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.12 PLL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 1.13 On-chip sampling clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the PLLs reference clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using another PLLs output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 3
Step 2: Embed Test Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.0 Check .etplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.1 Generate LVWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.2 Specify TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.3 Generate & insert RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Add muxes and userDRBit connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.4 Check connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
File hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 2.5 Prepare for simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 4
Step 3: Prepare a Board to Characterize Your IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3.0 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATE Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRS CG635. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMK03000 PLL Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Si550 VCXO Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3.1 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3.2 JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB-Signalyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3.3 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 3.4 .pinmap File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 5
Step 4: Prepare SiliconInsight to Characterize Your IC . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.0 Accessing SiliconInsight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.1 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a complete set of tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.2 Add a Test Step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.3 Choose a Test Controller (ULTRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.4 Choose test type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.5 Set global clock periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.6 Program loadboard PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.7 Set clock periods for single Test Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 4.8 Add Test Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 6
Step 5: Characterize your PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use SiliconInsight to Characterize Your PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.0 Optimize frequency offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Implementing PLL/DLL Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.1 Measure HF jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bit Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.2 Measure LF jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.3 Measure duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.4 Measure clock frequency ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.5 Measure phase delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.6 Measure lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 5.7 Measure lock range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 7
Step 6: Diagnose and Characterize Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.0 Diagnose Basic Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.1 Diagnose Measurement Failures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.2 Diagnose Jitter Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Finer Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Periodic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.3 Check Lock Time Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.4 Measure Repeatability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.5 Calculate Test Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BasicTests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OffsetFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter, DutyCycleDistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JitterFromCDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FunctionalLoopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.6 Optimize Test Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.7 Characterize many devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Saving Your Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 6.8 Creating scripts for characterization and testing. . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 8
Step 7: Generate Production Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 7.0 Generate Generic Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 7.1 Generate WGL, SVF, STIL, Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step 7.2 Write Test Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Formula for RMS from CDF Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Appendix A
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Appendix B
Commands and Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Sequence of EDA commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Primary control files that you create . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix C
Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Simplified PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Appendix D
Jitter Components and Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Appendix E
Document Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Third-Party Information
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List of Figures
Figure 2-1. Master/Slave TAP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2-2. Example .CADSetup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2-3. Example .LVICTech File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2-4. Example .ETDefaults File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2-5. Design Hierarchy for PLL (or DLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-6. Example PLL Interface Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2-7. Controlling a PLL for Lock Time and Lock Range Measurement . . . . . . . . . . . 31
Figure 2-8. Example PLL, and connections when reference clock is the sampling clock . . 32
Figure 2-9. Architecture of LMK03000 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 3-1. File hierarchy for <chip> = CHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-1. Example connections to two LMK03000 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 4-2. SignalyzerH4 USB-JTAG connector, and pin-out . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 5-1. Example default SiliconInsight GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5-2. Example test type selection within a Test Step. . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5-3. Setting clock periods that will be applied to all test steps, for independent clock (left),
an LMK03000 (middle), and for LMK04033 (right). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 5-4. Example test controller options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 6-1. GUI for calculating settings for LF jitter measurement . . . . . . . . . . . . . . . . . . . 95
Figure 7-1. Example of failures reported when no connections to the TAP pins, or TDO pin 102
Figure 7-2. Example failure due to test not completing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 7-3. Console display of jitter histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 7-4. Measuring Repeatability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure D-1. Jitter Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure D-2. Jitter Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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List of Tables
Table 5-1. LMK030xx and LMK040xx Parameters, Default Values, and Ranges . . . . . . .
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Chapter 1
Introduction
Embed Test Circuitry in Your IC Design to Test
SerDes or PLLs
Verify that your SerDes or PLL and its simulation model are suitable for testing by
SerdesTest or PLLTest.
Create an .etplan file with all required parameters and SerdesTest connection directives
for the following:
BIST of single-clock SerDes transceivers
BIST of dual-clock SerDes transceivers
BIST of PLLs and DLLs
Insert SerdesTest RTL into your design, verify connections, simulate, and diagnose any
problems
Create a Mentor Graphics Database (LVDB) with all data necessary for automated test
generation
Design and manufacture board hardware to allow you to connect a PC's USB port to
your IC's JTAG pins
Open the SiliconInsight GUI on your PC, select tests, and run them on your IC
Characterize and diagnose your SerDes or PLL performance on a board or on an ATE
The information in this document only refers to the preferred options for the majority of cases
and focuses on SerdesTest and PLLTest. If you are implementing other BIST IP in your chip,
Introduction
Generate Production Test Patterns for Your IC
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such as ETMemory, ETLogic, or ETBoundary, then the various files described here will have
additional lines of information.
This document is created in the order in which you should proceed, providing only the essential
information for each particular step. Information that is applicable to multiple steps is only
presented for the first relevant step.
For quick learning and results, it is recommended that you perform the action described by each
instruction in this document while reading it. Some instructions refer to files or test names
implemented earlier in the flow, but the instructions can also be interpreted generally.
For more detailed information and more options, refer to the LV Flow Users Manual and the
Reference manuals for each tool.
Note
The embedded test capabilities in the ULTRA family, presently comprising SerdesTest
and PLLTest, use most of the same RTL blocks and software. Despite testing very
different functions, they do not differ a lot in their connections to the circuit-under-test
(CUT), choice of tests, test settings, and test diagnosis. To simplify documentation and
learning, procedures that are identical for SerdesTest and PLLTest are described on the
same pages.
Note
PLLTest is a new set of capabilities, and some features are not fully implemented. In
most cases this is noted in this document, especially, where the procedure is not fully
automated. The degree of automation will increase in later releases of the software.
For the complete list of Mentor Graphics Tessent-specific terms, refer to the Tessent Glossary.
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Chapter 2
Step 1: Prepare Your Design
SerDes Suitability
To be tested by SerdesTest, your SerDes must have at least the following six ports and port
functionality (logic might be inserted manually or automatically to provide the required polarity
to the SerdesTest ports):
1. LockToRef enables receiver to sample its serial input regardless of signal frequency
or phase:
0 must select the receiver/deserializer's normal mode (lock-to-data mode) in which the
receiver samples its serial input synchronously to a clock recovered from the serial data.
1 must select the receiver/deserializer's other mode (lock-to-reference mode) in which
the receiver samples its serial input synchronously to the receiver's reference clock
(RxRef).
2. RxRef receiver reference clock at parallel rate or lower:
Must be offset from its nominal frequency, and, hence, asynchronous to TxRef
3. TxRef parallel-rate transmit word clock:
Must be suitable for clocking parallel data (TxData) into serializer, rising edge active
Must be synchronous to serial output data
4. TxData[ ] parallel word input to serializer:
Supported widths are 8, 10, 16, 20, 32, 40, 60, and 80 bits
Must be the exact data that is transmitted serially (without any coding)
5. RxRec parallel-rate recovered word clock:
Must be suitable for clocking parallel data (RxData) out of deserializer, rising edge
active
Must become synchronous to serial input data when receiver is in
lock-to-data mode and phase-locked
Must be synchronous to RxRef clock when receiver is in lock-to-reference mode and
phase-locked
6. RxData[ ] parallel words output by deserializer:
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PLL/DLL Suitability
To be tested by PLLTest, your PLL or DLL must have at least the following two ports and port
functionality (logic may be inserted manually or automatically to provide the required polarity
to the PLLTest ports):
1. ReferenceClock
The PLLs output is assumed to phase lock to the rising edge of this signal.
2. OutputClock(s)
The frequency of this output must be an integer ratio to the ReferenceClock frequency
during PLLTest testing, where the denominator is 8 or less. For example, 70/3, 5/8, and
72/9 (=8/1) are acceptable integer ratios, but 7/9 is not acceptable.
Other ports and functionality that might be connected to PLLTest to enable more test
capabilities:
LockDetect
PLLTest can measure lock time only if the PLL has a phase-lock indicator output.
DividerValue(s)
PLLTest can measure lock range and lock time if the PLLs divider values can be
changed.
Stable Performance
The circuit-under-test (CUT) characteristics must be stable during testing. If the CUT has
adaptive modes, such as byte alignment (e.g., FIFO), voltage offset cancellation, feed-forward
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equalization (FFE), decision-feedback equalization (FFE), then these must be frozen or disabled
during testing.
You should directly control the settings of these parameters with TAP userDRBits so
that CUT performance for each setting can be tested individually. Alternatively, allow
the circuitry to adapt, and then freeze the settings before performing CUT tests. This is
recommended for testing the quality of the adaptation algorithm.
The circuit is expected to have some settling time, such as a lock time. You must provide
the expected maximum lock time in the .etplan file so all tests can automatically include
a pause for this duration before each measurement.
First, perform the steps for just the CUT, within an otherwise empty chip. Later, you can
repeat the steps when the CUT is placed within your whole chip.
Create a temporary chip design that contains only your CUT and nothing else.
Time resolution in your CUT model should be 100 fs for <1 GHz, 10 fs for 1~10 GHz,
and 1 fs for >10 GHz.
Tie unused inputs to logic values or provide an initialization pattern to load internal
registers.
Debug the simulations until they run successfully to completion with zero jitter, and
then with a little jitter (e.g., 0.01 UI rms).
Optionally, adjust various settings of your SerDes to see their impact on the results.
Consider using a simplified or generic HDL model of your CUT initially. Later, replace
the simplified model with a more representative model of your own SerDes or PLL.
You should finish your IC design's RTL and simulate it functionally with the CUT operating at
full-speed before adding ULTRA.
If you try to insert and verify ULTRA within your whole chip before fully verifying your
original chip design, then it will be much more difficult to diagnose whether failures are due to
your original design or due to ULTRA connections.
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Create a directory structure for running Embedded Test software on your design (a
whole chip with an IEEE 1149.1 TAP or a sub-module with an IEEE 1500 WTAP) in a
way that does not intrude on your normal design flow.
Create a working directory, such as mychip or mymodule. Inside your working directory,
create an ETCHECKER directory, and a DFT directory.
All ETChecker steps are run while the ETCHECKER directory is your working
directory.
All other Embedded Test software (ETPlanner, ETAssemble, etc.) is run while DFT (or
one if its sub-directories) is your working directory.
Check whether the path to the LV Flow tools directory is defined in your UNIX path
with the following command:
which etchecker
This will produce the following three files in your current directory:
<chip>.etchecker
<chip>.etchecker.README
Makefile
You can read the .README file for detailed information or simply proceed to the next
step. <chip> is your module name: the top-level will contain a TAP; a lower-level
block will contain a WTAP.
14
Note
Almost all logic in SerdesTest and PLLTest is clocked by the sampling clock.
ClockDomainBase indicates the port that supplies a clock (the sampling clock, in this
case) so that timing constraints will be generated for it. If logic BIST will be inserted in
the design, then a Burst Clock Controller gate will be inserted automatically in this path.
If the path also supplies a reference clock to a PLL, you should use the optional parameter
-injectPin to identify a port connected to that clock path where gating can be inserted
without interrupting clocking of the PLL. If the logic in SerdesTest or PLLTest is to be
tested by logic BIST, the default choice of clock is the sampling clock (via its
ClockDomainBase label). If you want a different clock to be used for this logic BIST
testing, then it must be declared as a ClockDomainBase, and by a line containing
"LogicTestClockLabel : <ClockDomainBase_label>;" in the EST wrapper of your
<chip>.etplan file.Please see the ETChecker Reference manual for details and other
options.
A chip is only permitted to have one TAP, or only one TAP active at one time. If a design has
many embedded test controllers (e.g., many instances of SerdesTest, PLLTest, ETMemory,
and/or ETLogic), there can be a lot of on-chip interconnections between the TAP and the
embedded test controllers. It might be more efficient (i.e., use less interconnect) to use the IEEE
1500 approach, in which a wrapper TAP (WTAP) is used for each major block of the chip
design, all accessed via one TAP. However, the primary advantage of the WTAP approach is
that it allows you to insert embedded test, synthesize (or layout), and simulate all SerdesTest
tests for a single block (which might be instantiated multiple times), which greatly reduces
design verification time. Test time is unaffected by WTAPs because all embedded test
controllers can be run in parallel, even if some are at the top level, and others are controlled by
WTAPs within lower-level blocks.
If you are embedding SerdesTest (or PLLTest) in a soft module in your chip that will have a
WTAP, use the following lines instead:
lv.Target -type Block -notPhysicalRegion
lv.EmbeddedTest -memory Off -logic Off
lv.BlackBoxModule -name mySerdes
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A block design that will use a WTAP (IEEE 1500 wrapper TAP) does not need any TAP pins
for this step, so you can proceed directly to
Step 1.4 Check Clock Tree.
If you have more than one TAP controller on your chip, and the Mentor Graphics TAP used by
SerdesTest (or PLLTest) is the secondary TAP, then a signalling procedure is needed to control
when the SerdesTest TAP is active. There are several ways to do this, but the simplest way that
does not require any extra pins is to have the SerdesTest TAP as a Slave TAP selected by an IR
bit (preferably, or a DR bit) in your Master TAP, labeled as SelLV, as shown in Figure 2-1 on
page 17. Before proceeding to later steps, perform the following operations:
Add two 2-to-1 multiplexers between the existing Master TAP and the TDO tri-statable
output pad cell (one for TDO, another for tdoEnable), with their Select input connected
to SelLV.
Add two And gates (ensure SelLV is active high), one between the TMS pad cell and the
TMS input to the Master TAP, with SelLV as its other input, inverted, and one between
TMS pad cell and the TMS input to the Slave TAP, with SelLV as its other input. Ensure
that SelLV will exist after synthesis by using the PERSISTENT construct in the .sdc file.
With the combinational logic circuitry shown in Figure 2-1 on page 17, after the Slave TAP is
selected, the Master TAPs TMS signal becomes constant logic 0, which gracefully halts the
Master TAP by parking it in Run-Test/Idle state. The only way to regain control of the Master
TAP is to assert TRST (it is active low, so it must be set to 0). This asynchronously resets the
Master TAPs IR and DR registers, restores SelLV back to 0, and, thus, enables the Master
TAPs TMS as before.
Alternative ways are to drive SelLV with a Compliance Enable pin, or with an internal signal
possibly derived from a CPU bus.
In most cases, SelLV is set via a special instruction, applied with a UserDefinedSequence
before sending data to the Slave TAP as described later in User Defined Sequence.
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If your design contains modules for which you have inserted SerdesTest (or PLLTest) and a
WTAP, also add a line like the following to point to the modules LVDB file, and to point to the
modules design directory:
-lvdbDir \
<path>/DFT/<module>_LVWS/ETSignOff/
<module>.lvdb_preLayout
or, if it exists
-lvdbDir <path>/DFT/finalLVDB/<module>.lvdb
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The referenced pad.library file is a file required to describe I/O pad cells. Similarly, the
cell.library file is a file required to describe core logic cells so that they can be used
automatically and so that logic paths can be checked. For details and to document more
complex I/O pads, consult the manual ETAssemble Tool Reference.
The pad.library file has the following format for example input, output, and tristate output pads
(you can implement as RTL modules in your design directory for simulation, but for layout
these must be hard cells):
PadLibrary (padLibraryFilename) {
Cell (INPADS) {
Pin (A) { Function : padIO; }
Pin (Y) { Function : fromPad; }
}
Cell (OUTPADS) {
Pin (A) { Function: toPad; }
Pin (Y) { Function: padIO; }
}
Cell (OUTPADZ) {
Pin (A) { Function: toPad; }
Pin (Y) { Function: padIO; }
Pin (GZ) { Function: enableLow; }
}
}
The cell.library file has the following format for example multiplexers, combinational logic,
and buffers (you can implement as RTL modules in your design directory for simulation, but for
layout these must be hard cells):
CellLibrary (cellLibraryFilename) {
Buffer (RTLBUF) {
Port (A): Input;
Port (Y): Output;
}
Inverter (RTLINV) {
Port (A): Input;
Port (Y): Output;
}
And2 (RTLAND2) {
Port (A): Input;
Port (B): Input;
Port (Y): Output;
}
Or2 (RTLOR2) {
Port (A): Input;
Port (B): Input;
Port (Y): Output;
}
Multiplexer (RTLMUX21) {
Port (A0): Input0;
Port (A1): Input1;
Port (SEL): Select;
Port (Y): Output;
}
CellsToUseOnFunctionalClockPaths {
ClockMultiplexer (RTLMUX21) {
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(A0): Input0;
(A1): Input1;
(SEL): Select;
(Y): Output;
}
ClockBuffer (RTLBUF) {
Port (A): Input;
Port (Y): Output;
}
ClockInverter (RTLINV) {
Port (A): Input;
Port (Y): Output;
}
ClockGatingORCell (RTLCGOR) {
Port (CLK): Clock;
Port (TE): TestEnable;
Port (FE): FuncEnable;
Port (CLKOUT): ClockGated;
}
}
Note
The make command parameters are case-sensitive.
If you do not use batch mode, the interactive ETChecker GUI will open.
Click on Run/Analysis or its arrow icon to run SpyGlass analysis of your design.
Check the ETChecker console for errors.
To view a block schematic version of your RTL, double-click on your top-level file in
the Design Files (left) sub-window, then click on Tools/ModularSchematic or its nandgate icon. Navigate around your design in the schematic viewer as follows:
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Note
Any module with an internal WTAP (and the LVDB directory) will appear as an empty
shell so that no checks are done inside, since the module was checked before its LVDB
was created.
To zoom in, click in top-left corner of the window you want to zoom and drag the
cursor to bottom-right corner of the zoomed window.
If you are not using batch mode, the same ETChecker GUI will open again. Repeat the
GUI procedure from Step 1.4 Check Clock Tree.
The following output file is also produced and is required to run ETPlanner in the next
step:
etcHandoff/<chip>.etCheckerInfo
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If any of these variables is defined as a file path, then check that the target file is
appropriate for your design because the files will be automatically referenced in the next
step. You can also provide the file locations or contents in the next step.
Caution
should point to a .CADSetup file which describes your CAD
environment, including:
-Default simulator, and simulation commands to use
-Synthesis tool
-Command to create directories and soft links
LV_CADENV_FILE
Caution
should point to an .LVICTech file which lists your IC technology
model directories and files, or any models, including:
-Simulation models
-Embedded Test models and library files
-Synthesis models and library files
LV_ICTECH_FILE
Caution
- LV_ETDEF_FILE should point to an .ETDefaults file which sets other Embedded Test
parameter values.
Figure 2-2 shows an example of the content for a .CADSetup file.
Figure 2-2. Example .CADSetup File
CADEnvironment {
CreateDirectoryCommand
: /bin/mkdir;
CreateSoftLinkCommand
: /bin/ln -s;
DefaultSimulator : Verilog-XL; // Verilog-XL | NC-Verilog | ModelSim | NCVHDL |
// Leapfrog | VCS
// SynthesisTool
: DCTCL | BlastCreate | TalusDesign;
// Default values per Simulator
// --------------------------------------------------------------------------|
// |
Verilog-XL|NC-Verilog|VCS| ModelSim |Leapfrog| NCVHDL |
// |-------------------------------------------------------------------------|
// | Language -->
|
VERILOG
|VERILOG|VHDL|
VHDL
|
// |-------------------------------------------------------------------------|
// |Command
|verilog |ncxlmode | vcs | vlog | - |
|
|
// |CompileCommand
|
|
| - | |vcom| cv
| ncvhdl |
// |SimulateCommand |
|
| - | |vsim| sv
| ncsim
|
// |ElaborateCommand |
|
| - | | - | ev
| ncelab |
// |-------------------------------------------------------------------------|
// You may use the Simulator wrapper below to override the commands shown
// in the table above. Otherwise, the defaults from the table will be used.
// Repeat the Simulator wrapper for each simulator you want to override
//
Note: Simulator Commands are case sensitive.
//
Simulator ( Verilog-XL ) { Command : verilog ; }
Simulator ( NC-Verilog ) { Command : ncverilog; }
Simulator ( ModelSim )
{ Command : vlog;
}
Simulator ( VCS )
{ Command : vcs;
}
}
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If you already have a <chip>.etplan file, the software will try to patch in any updates,
but if it cannot it will report that the patching command failed and rename the previous
file as <chip>.etplan.bak. In this case, delete or rename the <chip>.etplan file, and then
rename <chip>.etplan.bak to <chip>.etplan
For a chip that contains a module for which you have already inserted a WTAP, and the
SerDes or PLL is within that module, append the following options that point to your
modules pre-synthesis LVDB directory (omit this option if you have a post-synthesis or
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March 2016
post-layout final LVDB) and a final LVDB directory (if you only have a preLayout
LVDB, point to an empty directory with name <module>.lvdb):
-preLayoutLVDBDir <PATH>/DFT/
<module>_LVWS/ETSignOff/<module>.lvdb_preLayout
-lvdbdir <PATH>/DFT/finalLVDB/<module>.lvdb
DFT/<chip>.etplan.README contains the complete syntax of the .etplan file for quick
reference.
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}
ModuleOptions (.*) {
LVWSDirectoryName: <chip>_LVWS;
}
ModuleOptions (<chip>) {
TopLVHWParentInstance: <top_for_DFT>;
// TAP location, if not at top level
SimulateLowerLevelcontrollers: On;
// Generate tests for WTAP modules too
}
Module (<module>) { // This appears only for
// WTAP modules
SignedOffLVDBPointer: <PATH>/DFT/finalLVDB/
<module>.lvdb;
}
} // End of EmbeddedTest
// End of ETPlan
For a chip that contains a module for which you have already inserted a WTAP, and the SerDes
or PLL is within that module, skip the rest of these Steps and proceed directly to Step 2: Embed
Test Circuitry.
The next steps will need the following information. These are brief descriptions, for more
details and default values, refer to the manual ETPlanner Tool Reference.
ClockPeriod the nominal clock period, in nanoseconds, for the reference clock port of the
SerDes (parallel rate) or PLL (input to the block) to be tested.
LockTime the phase-lock time, with appropriate units appended. Auto-generated test
patterns will have this pause time inserted whenever the mode of the SerDes or PLL changes, to
allow phase-lock to be achieved.
SerDesWordSize the number of signals that can be monitored for testing. It must be the
parallel port width for SerDes testing but can be any supported width for PLL testing (a width of
8 is usually sufficient). Supported values are 8,10,16,20,32,40,80.
BistClockGating indicates whether clocks to ULTRA should be gated off whenever tests are
not running. This saves power but adds gates in clock paths which might add jitter to phase
delay measurements.
ScanReady indicates whether you want extra gates and ports added to ULTRA in
preparation for scan path insertion.
NumberOfPipeliningStages indicates the number of flip-flops to be added to all inter-block
paths to add path delay tolerance. This is only needed when a circuit-under-test will be placed
24
far enough from the ULTRA block that the worst case path delay may approach one clock
period.
ParentInstance indicates where you want the automation to place the generated RTL
module. It can be placed in any synthesizable module. If you want the RTL placed in a new
module (just for SerdesTest logic, for example), then you must first add that module to your
design - the module may be empty.
MaximumFrequencyOffset_ppm indicates the maximum frequency offset of the
undersampling reference clock, in parts per million. You should use the largest value that your
SerDes model will tolerate (typically 300~3000) in ppm offset between the receiver's reference
clock and the transmitter's reference clock so that you will be warned if you unintentionally
attempt to use a larger frequency offset. If SerdesTest needs to use a smaller value due to other
constraints (in any case, it must always be less than 1956), it will warn you lateryou can
simply note the warning or reduce the value in the <chip>.etplan file to eliminate the warning.
The value does not affect RTL generation or production test pattern generation. Almost any
value can be used for PLL testing, up to 1956, so use that value.
NominalFrequencyOffset_ppm indicates the nominal frequency offset of the undersampling
reference clock, in parts per million. The value will be used to create simulation test benches for
all measurements. Most SerDes jitter tests require this value to be approximately 150 so that the
low frequency cut-off for jitter frequencies will correspond to that of a golden PLL. For PLL
tests, simply choose 1000 to obtain 0.1% clock period resolution. The value does not affect RTL
generation or production test pattern generation. If you try to use a value larger than
MaximumFrequencyOffset_ppm, then a warning will be issued and the maximum value will be
used instead.
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put the auto-generated Sampler module (that you customize) inside your PLL module -PLLTest will omit its own Sampler.
Note
Either all or none of the PLLs within each EST wrapper of your <chip>.etplan file
must have a custom Sampler. ULTRAs in separate EST wrappers can still test PLLs
simultaneously.
Figure 2-5. Design Hierarchy for PLL (or DLL)
26
RMS, this clock should have differential input pins to reduce the effects of I/O switching; if the
expected output jitter is <2 ps RMS, this clock should (but is not required) be routed
differentially and connected to a differential sampling latch in the Sampler module - the output
of the latch must be single-ended for connection to PLLTest. This clock must be asynchronous
to the PLLs input and output clocks.
Caution
Jitter in the undersampling clock will be included in any jitter measurement, so choose
pins, routing, and clock buffers that minimize the total delay of this signal path since this
will also minimize its jitter.
ClockSource(pllReference) IC pin(s), single-ended or differential, that is the source of each
PLLs reference clock; different pins may be listed for each PLL. You may list a default clock
that is to be used by all PLL modules, and you may list a different one for any individual PLL.
The automatically generated simulation test bench provides a positive frequency offset
(typically by 1000 ppm or 0.1%) relative to the nominal frequency.
SamplerInterface Use this option only if you want to customize the PLLTest logics
Sampler module that interfaces to your PLL, to obtain better measurement accuracy. If you use
this option, then your PLL module must contain a Sampler module based on the one that is
automatically generated by the LV Flow. With this option, the PLLTest module will be
generated without an internal Sampler module, and all signals from the PLL will be assumed
to be already sampled. If you use this option for one PLL, then you must use it for all PLLs.
InputClockPort The PLLs input port for its reference clock. The PLLs reference clock will
be sampled. If your PLL multiplies its input frequency by N/R, then its rising (or falling) edges
must be phase-aligned to at least every Rth edge of the PLL output data edges for PLLTest to be
able to sample them.
ClockOutputs The PLL or DLL output clock port (it may be a bus) to be measured. Each
output may have a different post-divider so that each output frequency is different. The postdivider integers indicate the ratio of the VCO frequency to the output clock frequency.
If the SamplerInterface option is used, then the listed port must be that of the
ULTRA_RPA_Sampler module (contained within your PLL module); the signals must then
be sampled versions of the PLLs output clocks.
LockDetect The lock detector output port of the PLL. Logic 1 indicates the PLL output is
phase-locked to its input. If your PLLs lock detector output is active low, you must add an
inverter and provide its output port as the LockDetect signal.
InterceptChangePLL During BIST insertion (described in Step 2.3 Generate & insert
RTL), the signal to this port is intercepted. During the LockTime test (only), PLLTest inverts
the signal; the signal returns to its non-inverted state at the end of the test or instantly if the
BIST is disabled. You may list any number of these ports on your PLL, and they may be any
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bits of a bus port. For example, the port can be least significant bits of a PLL's feedback divider
input value, or a reset signal (active high or low). LockTime is measured as the total time that
the LockDetect signal is logic 0 during the Test Duration in Beat Cycles (described in Step
5.6 Measure lock time).
VcoFrequencyMultiplier This parameter indicates the ratio between the PLLs internal
voltage-controlled oscillators frequency and the PLLs input reference clock frequency.
Miscellaneous These are ports that you wish to control via the JTAG interface, implemented
as userDRBits in the TAP controller, with easy-to-use aliases, so that you can automate
characterization of the PLL. RTL muxes can be inserted by you later using ETAssemble (if
they do not already exist) in these control input paths so that the function-mode controls are
active when PLL is not operating. Typically, these signals control PLL division ratio, loop
filter, delay, etc.
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Note
All hierarchical names refer to instances. If two different hierarchical names refer to the
same module, the module will be modified only once, in a way that is consistent with
both sets of .etplan descriptions. The LV Flow will check that all ULTRA options within
an EST wrapper for a single module are consistent. If you want a module to have
different options for different instances, you should use different EST wrappers.
Note
In the simulation test bench, the auto-generated sampling clock period will be exactly
equal to the ClockPeriod value and the PLL's reference period will be slightly longer. For
simplest simulation sign-off flow, set the PLL's output-to-input frequency ratio to be an
integer, i.e., the VcoFrequencyMultiplier value divided by the first ClockOutputs divider
value. (The ratio for subsequent ClockOutputs divider values can be fractional.) Later,
you will be able to test using fractional ratios whose denominator is between 1 and 8, as
explained for Under Sampling Clock Ratio on page 86.
Here are other ULTRA properties that can be controlled in this file:
CDFSamplesCounterSize: 12;
// default; max = 16
Sets number of counter bits for each histogram bin. A larger value increases the gate count but
permits more than 4096 edges (beat cycles) to be measured.
CDFNumberOfBins: 32;
Sets number of bins in histogram. Recommended values are 32 (default) and 0. A larger value
significantly increases gate count. If set to 0, then no histogram can be generated, which reduces
gate count to ~4K gates per ULTRA (instead of ~10K for default value). One ULTRA per PLL
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type should include histogram capability to aid jitter characterization, but this capability may be
omitted for the others to reduce gate count. No other tests are affected.
NoiseShiftRegisterSize: 32;
Sets the number of samples captured around each edge for RMS jitter measurements.
Recommended value is 32 (default). If the value is larger than CDFNumberOfBins, then
adjacent samples are accumulated in each histogram bin. Increasing the
UnderSamplingClkRatio value, during test, is a simpler way to increase the measurable peak-topeak jitter for a histogram (without affecting gate count).
The highest-numbered bit of the PLLOUTPUTS[ ] input port of the Sampler module must be
used for detecting loss-of-lock, and the signal provided to the port must be logic 1 when the
PLL is locked. The PLL is assumed to lose lock when the signal to the InterceptChangePLL
port is inverted because PLLTest only starts measuring after this event and will stop measuring
30
after Test Duration in Beat Cycles. To force the PLL to lose phase lock, the port identified by
InterceptChangePLL can be used, for example, to invert one or more bits of the PLL's divider
values. This connection also enables you to load in a divider value chosen so that when the bit is
inverted, the PLL is at its maximum or minimum output frequency, which permits lock range to
be tested too.
Alternatively, InterceptChangePLL can force the PLL to lose lock by temporarily connecting a
different reference clock phase or frequency to the PLL input.
Note
To reduce sampling jitter in a custom RPA_SAMPLER, use the falling edge of the
US_CLK for the sampling latches. Almost all activity in the ULTRA module occurs
around the rising edge of the US_CLK.
Figure 2-7. Controlling a PLL for Lock Time and Lock Range Measurement
After you add the interface module, run (again) Step 1.4 Check Clock Tree, and Step 1.5
Check DFT Rules
Proceed to Step 2: Embed Test Circuitry.
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Using the PLLs reference clock is simplest but only allows sufficiently fine resolution when
the PLL has a ten or more bits in its feedback divider. This clocking also prevents PLLTest from
measuring input clock duty cycle, input-to-output phase delay, and separated input and output
jitter. Using a second on-chip PLL is more complex but allows finer measurement resolution for
the same number of bits, and allows measurement of input clock parameters. In either case,
when choosing the sampling clock frequency and the frequency to measure, note that:
A higher sampling frequency permits shorter test times: 2X higher reduces measurement
time by 4X.
A higher PLL output frequency permits finer sampling resolution: 2X higher permits 2X
finer resolution.
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Procedure for calculating the finest sampling resolution possible when using the PLLs
reference clock to sample the PLLs output clock:
1. The objective is to find a reference frequency and dividers for the PLL so that the PLL
effectively multiplies the reference frequency by K(N-1)/N, where K is the nominal
integer ratio of the PLLs output to input frequency, and N is any integer. The PLLs
feedback divider will equal K(N-1).
2. Choose the PLL output frequency at which you wish to measure PLL performance.
3. Choose the largest possible output divider that keeps the VCO frequency in its range.
5. Choose the highest practical reference frequency for test that is equal to fOUTmin divided
by an integer, fREF = fOUTmin / K .
Choose a value that keeps the PFD input frequency within range.
e.g., choose 50 MHz and K=10;
fREF / inputDivmax = 50 / 32 = 1.5 MHz, which is within the PFDs 1~20 MHz
range.
7. If feedbackDivmax is too large for the divider, then choose a smaller input or output
divider so that the resulting feedback divider will be within its range and fREF / inputDiv
will be within the PFDs range.
Recalculate feedbackDivmax.
e.g., feedbackDivmax = 6 16 10 1, eg. 96 10 1 = 959
8. Calculate the exact PLL output frequency to be used, and its period TOUTexact fOUTexact = fREF feedbackDivmax / (outputDivmax inputDivmax)
TOUTexact = 2.00208 ns
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10. If this is finer than you need, then choose a smaller inputDiv and recalculate
feedbackDiv.
To measure jitter, sampling resolution should be 1~0.3X the expected RMS value.
To measure phase delays or duty cycle, resolution should be 0.2~2% of the PLL
output period.
To keep the sampling frequency low enough that timing closure can be easily achieved during
synthesis and layout of PLLTest (its circuitry operates at the sampling rate or at TCK rate), you
can divide one of the two PLL outputs by the smallest integer that produces a low enough
sampling frequency. This will also make the sampling resolution coarser by the same integer.
For example, if the maximum desired PLLTest clocking rate is 400 MHz, then for the above
example, fSAMPLING = fOUT/2 = 251.06 MHz, and the finest sampling resolution is TRES = 1 ps.
The LV_ClockGenerator GUI software (Figure 6-1) is used to find optimal divider values for
two off-chip PLLs (to generate fREF and fSAMPLING), specifically National Semiconductors
LMK03000 family of clock conditioners. That family of PLLs has the architecture shown in
Figure 2, which is different than the PLL architecture shown in Figure 1 and possibly different
than your PLL. The LV_ClockGenerator GUI can be used to find optimal settings for many
PLL architectures, as will be described.
34
Here is the heuristic procedure to find the finest sampling resolution possible when using one
PLLs reference clock to sample the output of another PLLs output clock. The procedure
requires the use of Mentors LV_ClockGenerator GUI software, which is available by special
request to your Mentor Technical Marketing Engineer. (The procedure is relatively complex so
it may be automated in a future release, but it usually needs to be performed only once per
design.)
1. Enter the target PLL reference input frequency (it will be used for both PLLs).
e.g., 50 MHz
2. Enter the target PLL output frequency as DUT input reference clock nominal
frequency (initially, well assume both PLLs will use approximately the same output
frequency).
e.g., 500 MHz
3. Enter a value of 1 for the DUT on-chip PLL frequency multiplier.
4. Use a value of 4, 8, 10, 16, or 20 for the Parallel word width it has no effect.
5. Use a value of 1667 or 2500 for the Golden PLL LF cutoff frequency it has no
effect.
6. Enter a target User-requested sampling resolution.
If the target PLL output frequency is too high as an input to PLLTest logic for you to
easily achieve timing closure of the PLLTest logic, then assume you will later use a
divider integer on the output of one of the PLLs, and divide your target resolution by
this integer to obtain the value to enter.
e.g., if fMAX=400MHz, and 1 ps resolution is required, then enter 0.5 ps
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If it says Operating range error, then try selecting a different PLL Model
(LMK03000, etc.).
If it says The frequencies must be coherent to each other, then choose one of
the OSCin frequencies provided.
If no choice of PLL Model produces an error-free result, then choose a lower DUT
input reference clock frequency.
At any time, you can save the present values or load previous one by clicking on
File.
If you have made changes, when you exit from the GUI, a pop-up window will ask
you to:
o
Save & Exit save the values you entered for the next time you open the GUI
(default filename for saved data is LV_ClockGenerator_LMK030xx.config)
Exit exit without saving values, so next time it will use other saved values.
Caution
The values provided are for the LMK PLL architecture of Figure 2-9, so the equivalent
feedback divider of the PLL in Figure 2-8 equals the GUIs VCO output divider times
Feedback divider, N. The GUI always chooses values that keep the LMKs VCO in its
required range, but you will need to ensure that the result will be within your PLLs
range.
10. The Clock Generator #1 and #2 divider values (blue font) are acceptable for the chosen
input frequency when both Feedback divider N values are low enough for your PLLs
divider and VCO range, and they are locally optimal if the divider values are within 20%
of each other.
o
e.g., The example PLLs VCO frequency is ~3 GHz but the LMK is ~1.5 GHz,
so the GUI-calculated feedback divider must be doubled to use it for the example
PLL. Therefore, the target feedback divider in the GUI will be 512.
Try each of the following iteratively to optimize the Clock Generator divider values.
Choose the OSCin = frequency, if acceptable, that maximizes the PFD input
frequencies
Increment the DUT input reference frequency to see if the Feedback divider
values continue to diverge; try decrementing too.
e.g., Example iterations for 50 MHz in, 500 MHz out, 0.5 ps target resolution, 400 fs
tolerance
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Both numerators are >512, but both input dividers (26, 32) can be divided by 2
to get the 3 GHz VCO output, and both output dividers (3,3) can be multiplied by
2 to maintain same ratio. Resolution is 0.5 ps, but after dividing by 2 to get <400
MHz, it will be 1.0 ps. Try optimizing further by decrementing the output
frequency.
Enter 499 MHz as new DUT input reference clock (with 52 MHz input)
Both numerators are <512, and OSCin is optimal and low, but resolution is 0.86
ps, which is coarser than the 0.5 ps result.
11. When optimal Clock Generator #1 and #2 divider values have been found, calculate the
divider values that meet the requirements of your PLL (since the ClockGenerator
software chooses values for the LMK03000 architecture, not your PLL).
If your PLL uses the architecture of Figure 2-9, and has a similar VCO frequency
range and PFD input frequency range, then you can use the GUI-computed values.
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If your PLL architecture is different, you will need to calculate the equivalent
divider values, and ensure that the VCO frequency is within PLLs VCO range.
The VCO range is ~3 GHz, and the LMKs VCO range is ~1.5 GHz, so two
extra factors of 2 are needed that cancel each other, but drive the VCO to 3 GHz.
The input divider is in the same position as the LMK, so the GUI value can be
used for the example PLL, after dividing by 2 to get the higher VCO frequency.
e.g., PLL1-inputDiv = 13; PLL2-inputDiv = 16
There is only one feedback divider, but the LMK has two dividers in series
multiply the GUIs VCO output divider by the Feedback divider, N to
produce the feedback divider for the example PLL.
e.g., PLL1-feedbackDiv = 3 251 = 753; PLL2-feedbackDiv = 3 309 = 927
The output divider is connected directly to the VCO output, but the LMK output
divider is connected to the VCO output divider multiply the GUIs VCO
output divider value by the Output-specific divider to produce the output
divider for the example PLL, and use a 2X larger output divider because of the
2X higher VCO frequency.
PLL1-outputDiv = 321 = 6; PLL2-outputDiv = 321 = 6
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Outside the PLL, add a divide-by two to obtain a sampling clock below 400
MHz. Therefore, the sampling clock would be 251.06 MHz and TRES = 1 ps.
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Chapter 3
Step 2: Embed Test Circuitry
Step 2.0 Check .etplan
In this Step, perform the following operations:
to check the .etplan file that you created for syntax, valid file pointers, etc.. Results are reported
to the screen and in DFT/outDir/etplanner.log_checkPlan. Correct any errors, and re-run.
Any time that you make changes in the .etplan file, you should begin the flow again from this
step.
If you have made changes to your design and are running this command again, you should
rename the present <chip>_LVWS directory (e.g., add .old suffix) to ensure that old files are
not reused. You can later copy files into it that you created manually
(<chip>.etassemble).
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Configuration (<chip>) {
BoundaryScan {
// information for 1149.1 (JTAG) implementation - ignore for now
Overrides {
*
: Option(NJTAG); // This declares all pins as non-jtag - ignore for now
}
ACMode {
// Information for 1149.6 (AC-JTAG) implementation - ignore for now
}
}
TAP {
InstanceName: LV_TAP;
DeviceIdCode: 16'h0000;
// Delete this line if register not needed
ManufacturersIdCode: 11'b000;
// Delete this line if register not needed
NumberUserBits: 0;
// Instruction Register bits for you to assign later
NumberUserDRBits: 6;
// Data Register bits for you to assign later
UserBitAliases {
Vout: UserDRBit(2:0);// Assign names to bit ranges that will control SerDes/PLL
Equalization: UserDRBit(4:3);
Preemphasis: UserDRBit(5);
}
TestPortConnections {
// Provide this wrapper if you prepared for Master/Slave TAP
TMS
: <hierarchicalOutputPortName_SelLVAndGate> ;
TDO
: <hierarchicalInputPortName_SelLVMux1> ;
TDO_EN(1 | 0) : <hierarchicalInputPortName_SelLVMux1> ;
}
} // End of TAP
CustomObject ( ) {// for adding muxes, userDRBit connects - ignore for now
}
}
// End of Configuration
Example for <module>.etassemble for a module with a WTAP:
Configuration (<module>) {
WTAP {
InstanceName: LV_WTAP1;
NumberUserIRBits: 0;
// Instruction Register bits for you to assign later
} // End of WTAP
CustomObject ( ) {// for adding muxes, userDRBit connects - ignore for now
}
}
// End of Configuration
Caution
You should assign UserBitAliases for all UserDRBits, even single bits, to avoid problems
setting them later in SiliconInsight.
40
Note
If you are working at the top level, and your SerdesTest (or PLLTest) is controlled by a
WTAP in a lower level block that you wish to simulate as RTL, then create a soft link
called <chip>.v that points to your original RTL for the chip, as follows (where .v is
your suffix for synthesized logic, and .vb is your suffix for unsynthesized RTL):
ln -s <path>/RTL/<chip>.vb <chip>.v
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ModuleName may refer to an RTL multiplexer module in your design directory, or to a specific
Custom Connections
To measure lock time for PLLTest, you must connect some signals within ULTRA to the PLL
interface module that you created in Step 1.12 PLL Interface, as follows:
1. Edit the CustomObject wrapper in <chip>.etassemble to add the following
connections, where <instancePath> is the hierarchical name of the instance:
CustomObject (ConnectPortToPort) {
Var(Port1): <instancePath>/<port>;
Var(Port2): <anotherInstancePath>/<port>;
}
}
42
File hierarchy
At this time, your file directories will look like those in Figure 3-1 on page 44 (for initial
working directory named mydesign, and a chip named CHIP).
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44
If you are working at the top level, and your SerdesTest (or PLLTest) was already
signed-off with a WTAP at a lower block-level, then this file will only contain tests for
the top-level TAP and a test to check the reference clocks.
If you are working at a design level that contains SerdesTest (or PLLTest), then the file
will also contain tests for the Serdes (or PLL). Here are selected lines from the file:
etv ( <chip> ) {
IncludeAllPowerPins : Yes; // Yes, (No)
jtagVerify(<chip>) {
PatternName
: tapbistv;
SimulationScript : <chip>_sim.script;
TCKPeriod
: 40.0ns;
TestStep ( Default ) {
RunTest
: TestLogicReset;
RunTest
: InstReg;
...
serdesVerify(<chip>_<prefix>_P1) {
PatternName
: serdesv_P1_<chip>_<prefix>;
ClockPeriod
: 40.0ns;
TckRatio
: 1;
TestStep ( BasicTests ) {
SerdesTest : BasicTests;
Controller ( BP0 ) { // BIST Port 0
...
serdesVerify(<chip>_<prefix>_P2) {
PatternName
: serdesv_P2_<chip>_<prefix>;
...
UseDutLoopBacks : Off;
TestStep ( OffsetFrequency ) {
SerdesTest : OffsetFrequency;
Controller ( BP0 ) {
...
serdesVerify(<chip>_<prefix>_P3_I0_CH0) {
PatternName
: serdesv_P3_I0_CH0_<chip>_<prefix>;
...
UseAsyncClocks : On;
...
UseDutLoopBacks : On;
DutLoopBacks { <RXserialIn> <= <TXserialOut>; }
TestStep ( RmsJitter ) {
Pattern
: P010J;
SerdesTest : Jitter;
Controller ( BP0 ) {
...
DataBitNo : 0;
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...
The file includes tests that verify basic functionality of SerdesTest (or PLLTest) within your
chip's design:
tapbistv
- test TAP logic
serdesv_P1_<chip>_ULTRA_
- test ULTRA logic
serdesv_P2_<chip>_ULTRA_
- measure clock frequency offset
serdesv_P3_I0_CH0_<chip>_ULTRA_
- measure jitter for Channel0,etc.
The clock period is the value from the ETCHECKER/<chip>.etchecker file, and the TCK
period is 4X this value to get the fastest simulation possible. If necessary you can increase the
TCK period by powers of 2, but do not decrease it. All measured values are expected to be zero.
<chip>.etSignOff information can also be entered within SiliconInsight, when creating
tests for real silicon.
Note
If the PLL's output frequency is not an integer multiple of the reference frequency (as
indicated in your .etplan file via VcoFrequencyMultiplier and ClockOutputs dividers),
then you must edit the period of the "offset test clock" for the _P3 test in your .etSignOff
file so that it equals the nominal period of your PLL's output clock. Later, when you use
SiliconInsight, you can instead adjust the value of USCR to allow different output and
sampling frequencies.
46
The following is a simple, example SVF file you could put in the ETAssemble/SVFFiles
directory:
PIOMAP { IN clk(1) IN data(2) IN reset(3) );
PIO (LLH); PIO (LLL); PIO (HLL); PIO (LLL);
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Running the normal simulation with the extra SignalStrobe module will generate an output file
called Data.strobe which will look like this:
1
2
3
4
01xxxx1
00zzzz1
0100001
1100001
With these cyclized vectors, you create PIO commands using the following command (a Tcl
program in ETCreate/bin):
strobe2pio Data.strobe > MyInitSequence.svf
In the output file, add a PIOMAP header to indicate pins are IN or INOUT and their order in
each PIO line. The resulting file will then look like the following:
PIOMAP ( IN cpuClk IN cpuRstn IN cpuData(3) IN cpuData(2)
IN cpuData(1) IN cpuData(0) IN tck );
! comment
PIO (LHZZZZH );
PIO (LLZZZZH );
PIO (LHLLLLH );
PIO (HHLLLLH );
!toggle TCK to bring TAP into RunTestIdle State for 3 TCK cycles
RUNTEST 3 TCK ENDSTATE IDLE;
Note that PIO patterns cannot be applied to TAP pins: you must use other SVF commands (like
RUNTEST) for TAP pins.
A UserDefinedSequence can be applied immediately before or after the Mentor Graphics TAP
is reset/accessed, as follows:
etv (<designName>) {
...
UserDefinedSequence (<sequenceName1>) {
...
}
...
jtagVerify(<chip>) {
...
PreTAPUserDefinedSequence : <sequenceName1>;
}
}
five consecutive 1s on TDI that resets the TAP at the beginning of each test pattern. If
you have a Master/Slave TAP, you will need this type of UDS.
and five consecutive 1s on TDI that resets the TAP at the beginning of each test pattern,
before the test instructions, userDRBits, test parameters, etc. are shifted in.
48
It documents all the test circuitry in your design and is used by SiliconInsight and ETVerify as
the sole source of data for test pattern generation, until you create a finalLVDB in Step 2.15
Generate final LVDB on page 58.
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Caution
If your SerDes (or PLL) model is very simple, the simulation of all five patterns may
require only a few minutes and produce a summary output like that below (along with
warnings about Too few module port connections), but for more complex models and
more chip logic, you should run and diagnose just one test pattern at a time, as
described on the next page.
Log File:
Date
Number
Number
Number
The last Log File message shown (P4) is produced only for SerDes tests, not PLL tests.
View RTL
To check your RTL connections in the ETChecker schematic viewer, use the command:
make schematicView
If it runs without errors, then use the command:
etchecker <chip> -mode loadVdbFile
In the ETChecker GUI, click on the left-hand side Design tab.
50
See Step 1.4 Check Clock Tree for how to use the schematic viewer to explore
your design.
tapbistv
serdesv_P1_<chip>_ULTRA_
serdesv_P2_I0_CH0_<chip>_ULTRA_
serdesv_P3_<chip>_ULTRA_
serdesv_P4_<chip>_ULTRA_
To run just the P1 pattern and save the results in a file to view in a waveform viewer, use a
command that adds VCD, UTVCD, or debussy
make sim cmdOptions=-select
\ serdesv_P1_<chip>_ULTRA_ +define+VCD
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Note
If you make any changes to your design or to <chip>.etplan, you must re-run Steps
2.0 and 2.1 (make checkPlan, genLVWS ) with DFT as your current directory.
Then, with DFT/<chip>_LVWS/ETAssemble as your current directory, you can rerun steps 2.3~2.8 (make embedded_test, designe, config_etSignOff,
lvdb_preLayout, testbench, sim) with a single command: make all
The following two pages describe what to look for in the simulation results to diagnose a failing
test.
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P2 pattern
For the P2 pattern (FrequencyOffset: frequency offset measurement with RxRef sampling
TxRef; 2 beat periods), verify:
this test only measures the frequency offset between the TX parallel-rate reference clock
and the RX parallel-rate reference clock; it does not involve the PLL;
the clock provided to the PLLTest module's RXREF_CLK input is inverted relative to
its RXREC_CLK signal;
your simulation timing resolution is less than or equal to 0.1% of your PLL output
period (default is 100 fs);
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P3 pattern
For the P3 pattern (RmsJitter: on-chip RMS jitter measurement on the first PLL output
identified in the ClockOutputs wrapper of the <chip>.etplan), verify:
54
your PLL initialization and all clock periods are the same as specified above for P2;
the frequency of the PLL output sampled to produce RxWord[2] is an integer multiple
of the PLL's reference clock frequency (if you chose a fractional ratio, then you must
insert a different sampling clock period for this test in the .etSignOff file).
RxWord[2] pulses each have a duration of 500 +/-2 sampling clock periods, divided by
the PLL output to input frequency ratio, after the declared LockTime;
The Embedded Test methodology for STA is to remove all known false and multi-cycle paths
from the complete list of paths, and whatever is left must be single-cycle paths.
Within SerdesTest and PLLTest logic blocks, test data is loaded in and transferred between the
TAP and ULTRA block's TCK_REG at the TCK clock rate, then the tests are run at the parallel
or reference clock rate, and then the results are transferred back to the TAP controller at the
TCK rate. Transfers involving the TCK_REG register should be treated as false paths, because
once the parallel clock is involved, all TCK_REG outputs are constant values.
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To accommodate different character mappings used by synthesis tools when flattening a design,
such as the hierarchy separator / replaced by _, square bracket indexes ([n]) replaced by
_n_, escaped names in paths, etc., you must find the following lines in the
ETAssemble/outDir/chip_etassemble.sta file and change the [ and _
characters appropriately:
proc LV_map_to_verilog {path} {
set path "[string map {"[" "_"} $path]"
set path "[string map {"]" "_"} $path]"
return $path
}
Also, set the Tcl variable LV_hierarchy_separator to be whatever character your synthesis
tool uses (/ is the default character).
Set your current directory to DFT/<chip>_LVWS/ETAssemble
Use the command:
make sta
to run the static timing analysis tool using the automatically generated STA script.
Caution
For small ICs, especially test chips, I/O switching activity can affect the core logic power
rail voltage more significantly than for large ICs, which may cause excessive jitter in the
SAMPLER flip-flops. If the I/O switching is synchronous with a clock period that is an
integer multiple (2~8) of the ULTRA clock rates, then ULTRA can compensate. If not,
then these outputs should be disabled when ULTRA is testing, and circuitry might need
to be added to do this.
Go back to Step 2.8 Simulate on page 49 and run make sim to re-run simulations, using
this gate-level version.
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If you are embedding SerdesTest (or PLLTest) in a module (with a WTAP) to only the RTL
level, and wish to proceed directly to the top-level without synthesizing the module, then do the
following:
<module>.netlist_prelayout
Return to Step 1.0 Create Working Directories to perform DFT for the top-level
design.
Caution
If you are working at the top level, and your SerdesTest (or PLLTest) is controlled by a
WTAP at a lower block-level, then do not proceed to the next step until all the lower
block-levels have been signed-off, i.e. completed at least to Step 2.15 Generate final
LVDB on page 58.
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58
You may proceed to Step 2.17 Simulate post-layout. If that simulation is successful, then
you should use SiliconInsight to create additional tests (with test limits) that are representative
of all those you intend to use on ATE and then simulate them.
To create more tests in SiliconInsight, while the ETSignOff directory is your current directory,
If necessary, include the SiliconInsight software directory that supports SerdesTest and
PLLTest in your search path, with a command like:
setenv PATH /wv/lvs_rls/prod/Tessent/ETAccess/bin:$PATH
Go to Step 4.2 Add a Test Step and implement tests as described in Step 4 and Step
5 (without any hardware);
o
Use values for Test Duration In Beat Cycles between 1 and 10 so that simulation
time is reasonably short (zero jitter will be measured).
Always set ATE Vector Period (which sets TCK Period) to at least 4 times the
RXREF clock period.
Click on OK
Click on File, then click on Save Config As...
and set the file Selection to
DFT/finalLVDB/<chip>.lvdb/<chip>.config_eta
Click on OK
Exit from SiliconInsight.
Note: Next time you enter SiliconInsight, use the normal configFile:
-configFile <chip>.lvdb/<chip>.config_eta
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60
Note
Presently, SVF patterns cannot be generated for the jtagVerify tests because the tests end
in intermediate TAP states. This limitation will be fixed in a future version of etVerify.
So you will need to comment these tests out of the <chip>.etManufacturing file.
Ensure that you save copies of all files listed in Primary control files that you create.
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Chapter 4
Step 3: Prepare a Board to Characterize
Your IC
ULTRA has three requirements for accurate measurements: clean power, clean clocking, and
clean JTAG. The following Steps will help you to design ATE loadboards and/or stand-alone
characterization boards that meet these requirements.
ATE Clocks
Typical ATE clocks have >5 ps rms jitter and are not suitable for most SerDes reference clock
inputs, nor for use as a sampling clock when testing PLLs. Also, most digital ATE does not
have fine enough frequency resolution to provide ~150 ppm offset frequency. To measure LF
jitter, coherent sampling is necessary, and even though mixed-signal ATE supports coherent
sampling it usually doesnt have sufficiently low jitter.
SRS CG635
You may use bench-top equipment to generate the clocks. SiliconInsight can directly control a
Stanford Research Systems Model CG635 clock generator via a USB-to-GPIB cable. This
equipment is capable of generating clock frequencies up to 2 GHz, with millihertz frequency
resolution, so it is well-suited to testing SerDes with SerdesTest.
Caution
This equipment is not recommended for measuring PLL LF jitter because its absolute
frequency accuracy for some frequencies (for which it interpolates between phase-locked
frequencies) is about 100 millihertz, which introduces too much LF jitter to be usable.
Sharing a common 10 MHz back panel reference clock helps, but not sufficiently.
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loop filter, and the choice of phase-frequency detector (PFD) frequency inside the PLL. Choose
the PLL whose VCO frequency can be an integer multiple of your IC's reference frequency. For
example, if your chip's reference frequency is 225 MHz, you must choose the LMK03002
because there is no integer multiple of 225 within the VCO range of the other PLLs. Mentor can
provide to you a Tcl routine or Excel spreadsheet that allows you to explore the frequency
possibilities.
LMK04010:
LMK04001:
LMK04011:
LMK04031:
LMK04002:
LMK04033:
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measurement equipment, but any reference frequency up to 200 MHz is permitted by the
LMK03000 PLLs. The input to the PLL can be differential or single-ended (3.3 volt maximum
swing, AC-coupled). The two sides of a differential signal can drive two PLLs single-endedly
(as shown in Figure 4-1), or a differential clock buffer can be used (especially if splitting to
more than two signals). If you use one PLL instead of two PLLs, choosing a PLL input
frequency above 80 MHz may limit your choice of sampling resolution (e.g., >0.5 ps).
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USB-Signalyzer
The Signalyzer module's minimum output logic 1 depends on the specific model, and it can
connect to two or four groups of signals, with user-assigned positions, and each group with its
own VCC. Generally the latest Signalyzer modules support a voltage swing of 3V - 5V, but
level translator accessories are available to extend the range to 1.15-5.5V. Refer to the Xverve
website at the following URL for details about the modules:
http://www.signalyzer.com
Additionally, see the Tessent SiliconInsight Users Manual for the LV Flow for details about
supported models.
Ensure that a resistive divider is provided if your IC's voltage levels are <1.2 V.
If the Signalyzer will be used to control the LMK03000 frequencies as well as the JTAG
interface, one connector should be provided for controlling the JTAG pins, connected to
the A slot of the Signalyzer, and one should be provided for controlling the PLLs,
connected to the B slot, so that the DUT's VDD can be different than the PLLs' VDD. In
Step 4.5 Set global clock periods you will indicate to SiliconInsight which of the
Signalyzer pins you connected to the PLL microWire interface.
Each connector should be a standard IDC 26-pin header, 2 x 13 pins with 100 mil
spacing, and signals and power assigned as shown in Figure 4-2.
The module can drive only high-impedance inputs having pull-ups >2k ohms and pulldowns >10k ohm.
The DUT's TRST pin should be assigned to a connector pin, but it may be separately
connected to VDD if not needed (all patterns generated by SiliconInsight include
synchronous reset after a TRST reset). If your DUT uses two TAP controllers, in a
master and slave configuration, and TRST is used to revert back to the master TAP, then
you should use the Signalyzer instead of the Amontex so that the TRST can be activated
when needed.
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Note that all Signalyzer GND pins are a single node and could short circuit your boards
power supply if connected incorrectly.
Caution
For the SignalyzerH4 adaptor, Pin 2 (VEXT) and Pin 26 (VEXT) are 5.0V DC supply
pins from the USB port of the computer. These pins, in contrast to older Signalyzer
models, are not for VREF input and could damage the Signalyzer device if you use them
as such.
Another module that is supported is described at
https://www.olimex.com/Products/ARM/JTAG/ARM-USB-OCD-H/ (Olimex ARM-USBOCD-H).
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DUT socket
Offset reference clock PLL (LMK03000/04000 series), if you are not using clock
generation as described in Step 1.13 On-chip sampling clock generation.
10 MHz crystal - optional if PLLs' input reference clock is provided from a crystal or
external source.
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Chapter 5
Step 4: Prepare SiliconInsight to
Characterize Your IC
Step 4.0 Accessing SiliconInsight
To access SiliconInsight Desktop (in Linux), create a shell script like the one below. Other
parameters and files may be specified in the command line or selected within the GUI. You will
need to specify the path to the directory that contains the SiliconInsight software and licenses your system administrator may need to assist you.
Include the ETAccess software directory that supports SerdesTest in your search path,
with a command like:
setenv PATH
<install_path>/current/ETAccess/bin:$PATH
./<chip>.lvdb \
./<chip>.lvdb/my.config_eta \
signalyzerH4 \
./<chip>.pinmap \
./outDir
The lvdb and config files are produced by the make lvdb_final command, described
earlier in Step 2.15 Generate final LVDB.
The cable option allows you to specify that you are using a SignalyzerH4 connector
(Amontec is default).
The pinmap file was created manually by you, as described earlier in Step 3.4 .pinmap
File.
The outdir directory is your choice of directory for all datalog files and error messages.
You may add -sim to allow you to load the SiliconInsight software in simulation mode, which
is useful for checking that SID software loads correctly, for checking that all required files are
accessible and are error-free, or for adding new tests without the Signalyzer connected. Without
the sim option, SiliconInsight will give an error message if the Signalyzer is not detected
(because it's not connected or the USB port has not been properly identified).
Tessent PLLTest Users Manual, v2016.1
March 2016
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You may add -lvtpExtraArgs -t 120 to increase the time that the software will look
for a license to 120 seconds, but only if your system takes longer than a minute to find the
license.
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Right click on the jtagVerify test group G icon, and then click Options.
Type in a new Group Name of your choice (or preferably leave it as jtagVerify). The
new name must obey the naming rules and be unique among all Test Group names for
the device.
Right click on the jtagVerify test group G icon, and then click on Add Steps.
In the Add Steps pop-up window, click on the checkbox to left of Plugin Step.
Click on OK. This will append a new test step, with default name S0.
Click on OK.
Right click on the Test Step, and replace S0 (or S1, S2, etc.) with the Test Step name of
your choice (use 'ultraBlock' for this example). The new name must obey the naming
rules and be unique among all Test Step names for the device.
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Caution
If you change the Step Name, then you must click on Apply before changing any other
Test Step options (eg. Test or Pattern). Similarly, if you change a Test Step option
(including Edit as a Group), then you must click on Apply before changing the Step
name. Otherwise you may see a simple error message (click on its OK), or the sub-menu
may freeze with OK/Apply/Cancel greyed-out (click on File/Save from main menu,
then click on Yes to save your changes to configuration, then Exit, then enter "pkill eta"
to close the sub-menu).
Click on OK.
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Right click on the first test group (jtagVerify) or on the top-level chip icon.
Right click on the new Test Group's icon, and click on Add Steps...
For each parameter in the following list, click on Add Parameter, and enter the
parameter Name (case sensitive) and then a value in the adjacent field. Do this for at
least the first three parameters listed below to assign a clock period to a pin, and at least
the first eight parameters if you plan to program an LMK0xxxx PLL to generate a clock,
then click on OK. One PLL can drive multiple pins at synchronously related
frequencies, but not both the reference clock and the undersampling clock.
OnlySetAsyncClocks set value to 0 if an LMK PLL will be programmed and to set clock
periods for all Test Steps, or set to 1 if none is to be programmed but you still want to set clock
periods for all Test Steps.
OutputClockPeriod Target output period for the LMK PLL. Specify a value in ns (without
'ns' suffix).
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AsyncClockPins List the chip's pins that are used as asynchronous clocks. You may list any
number of pins, each separated by a space.
CLKout<i>_EN Select outputs of the LMK that are to be enabled, from CLKout0_EN to
CLKout7_EN. You can enter more than one of these lines to enable more than one output.
modelNo LMK0xxxx (3000 is default), where xxxx is one of 3000, 3001, 3002, 3033, 4000,
4001, 4002, 4010, 4011, 4031, or 4033.
OSCin_FREQ Input frequency to the LMK device, in MHz.
Pins_CDE A list to specify Clock, Data, and Enable pins of the device used to load the
LMK. Defaults to 'B0 B1 B2' for Clock, Data, and Enable pins, respectively.
ERROR_max_fs Maximum acceptable error on OutputClockPeriod, in fs (defaults to 100).
The following four parameters can directly set the PLLs dividers, unless OutputClockPeriod
is greater than 0 (in which case, these four parameter values will be ignored).
PLL_R Main PLL input divider
VCO_DIV Main PLL VCO output divider
PLL_N Main PLL feedback divider
CLKoutX_DIV Post divider (from output of VCO divider), applied to all outputs.
Table 5-1 below lists all supported parameters, their default values, and their range of allowed
values. Please refer to the devices datasheet for a detailed description of each parameter.
Table 5-1. LMK030xx and LMK040xx Parameters, Default Values, and Ranges
LMK030xx
LMK040xx
Parameter name
Default Range
Default
Range
Notes
OSCin_FREQ
10
[1..200]
100
[1..250]
(1)
CLKoutX_DIV
[1,2,4,6..510]
[1,2,4,6..510]
(3)
CLKout<i>_DIV
[1,2,4,6..510]
[1,2,4,6..510]
(3)
CLKout<i>_DLY
[0,150,300..2250]
[0,150,300..2250]
(6)
CLKout<i>_EN
[0,1]
[0,1]
EN_CLKout_Global
[0,1]
[0,1]
EN_Fout
[0,1]
[0,1]
PLL_CP_GAIN
[0..3]
[0..3]
(2)
PLL_MUX
[0..11]
[0..24]
(5)
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Table 5-1. LMK030xx and LMK040xx Parameters, Default Values, and Ranges
LMK030xx
LMK040xx
Parameter name
Default Range
Default
Range
Notes
PLL_N
760
[1..262143]
[1..262143]
(1)(2)
PLL_R
10
[1..4095]
[1..4095]
(1)(2)
POWERDOWN
[0,1]
[0,1]
Vboost
[0,1]
(n/a)
VCO_C3_C4_LF
10
[0..11]
10
[0..11]
(2)(4)
VCO_DIV
[2,3,4..8]
[2,3,4..8]
(1)(2)
VCO_R3_LF
[0..4]
[0..4]
(2)(4)
VCO_R4_LF
[0..4]
[0..4]
(2)(4)
CLKin_SEL
(n/a)
[0..3]
CLKin0_BUFTYPE
(n/a)
[0,1]
CLKin1_BUFTYPE
(n/a)
[0,1]
CLKout<i>_PECL_LVL
(n/a)
[0,1]
CLKoutXA_STATE
(n/a)
[0..3]
(7)
CLKoutXB_STATE
(n/a)
[0..3]
(7)
EN_PLL_REF2X
(n/a)
[0,1]
(2)
EN_PLL_XTAL
(n/a)
[0,1]
(2)
LOS_TYPE
(n/a)
[1..3]
LOS_TIMEOUT
(n/a)
[0..3]
PLL_CP_TRISTATE
(n/a)
[0,1]
PLL1_CP_GAIN
(n/a)
[2..7]
PLL1_CP_POL
(n/a)
[0,1]
PLL1_CP_TRISTATE
(n/a)
[0,1]
PLL1_N
(n/a)
[1..4095]
PLL1_R
(n/a)
[1..4095]
RC_DLD1_Start
(n/a)
[0,1]
(2)
(8)
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(1) LMK040xx datasheet has a different default value. With the default values above, 100
MHz in produces 100 MHz out.
(2) In the LMK04000 family, which has two PLLs, this parameter applies to the main PLL
(PLL2).
(3) CLKoutX_DIV is the default value to be applied to each CLKout<i>_DIV, where <i> is
in the range of outputs supported by the device. Any CLKout<i>_DIV will override the value of
CLKoutX_DIV. If the value is 1, the divider is bypassed.
(4) A default value is not specified in the LMK040xx family, so the same default is used as
for the LMK030xx family.
(5) For this parameter on LMK040xx, the reserved values cause an error: 8 10 12 13 16 17
18 19 21.
(6) Delay is directly set in ps and must be a multiple of 150. When delay is set to 0, the delay
path is bypassed.
(7) For the LMK040xx family, CLKoutXA_STATE and CLKoutXB_STATE apply only to
outputs 1, 2 and 3.
(8) The default value is different than the spec sheet so that the auxiliary PLL (PLL1) is
not used.
To use an ATE Step as only a convenient way to set asynchronous clocks for all Test Steps,
without programming a PLL, you must define at least the following parameters:
OnlySetAsyncClocks Set value to 1.
OutputClockPeriod Set to value of the clock period (in ns).
AsyncClockPins Set to list of clock pins affected.
You may add a Test Step for each asynchronous clock connected to your chip for
SerdesTest or PLLTest, whether it comes from a crystal or LMK0xxxx.
If you have connected a GPIB-controlled clock generator, or are running on ATE, under the
Tools menu, you will see Clock Setup..., and Shmoo... as additional options.
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Figure 5-3. Setting clock periods that will be applied to all test steps, for
independent clock (left), an LMK03000 (middle), and for LMK04033 (right)
If the displayed value is not what you want, click on ATE Vector Period and enter a
new value. This will be equal to the TCK period if the DUT's reference clock is derived
from an oscillator or PLL on the loadboard as is recommended for low-jitter testing (in
which case, the reference clock and TCK are asynchronous).
If this clock period is not the TCK period, then also select the TCK Ratio, which is the
ratio of TCK period to vector clock period.
Click on OK, to apply the settings and exit the clock period window.
You can set Async Clock Periods for individual Test Steps (it is the period of a clock generator
that runs independently of the ATE).
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Click on Async Clock Periods and enter the reference clock periods.
Click on OK. to apply the settings and exit the Async Clock Periods window.
Click on OK to apply and exit the Test Step Options.
Caution
You should always use the procedure in Step 4.5 Set global clock periods on
page 75 to set the Async Clock Period values, especially when the asynchronous clocks
are the two reference clocks coming from off-chip PLLs. This ensures that all Test Steps
use the same clock periods. Only set Async Clock Period for individual Test Steps when
you intend it to be different than other Test Steps; you will need to change that Test Step's
clock periods after every time you run the top-level clock period setting function.
Caution
In some operating systems, if a sub-window opens where your cursor is located, you will
not be able to enter values - simply move the cursor out of the window and back in. And
sometimes sub-menus open in the top left corner and behind the main menu, so you may
need to move the main menu to the right to see it.
Click on OK.
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In the ReferenceClocks Test Group, add a Test Step with at least one ULTRA
controller, and name the Test Step something like FrequencyOffset.
Right click on the ReferenceClocks Test Group G icon, and then click on Add Steps.
In the Add Steps pop-up window, click on the checkbox to left of Plugin Step.
Click on OK. This will append a new test step, with default name S0.
Right click on the new Test Step and select Options to get the Test Step Options
window of Figure 5-3 on page 80.
Click on the pull-down menu beside SerDes Test or PLL Test, and choose
OffsetFrequency to measure the frequency offset between the TX and RX parallel word
clocks (PLL reference clock and undersampling clock, respectively).
Pause Time
Enter a value if you want a test sequence to pause just before a Test Step is run, for a time
interval that is independent of the clock period, e.g., to allow an tester's DC PMU to settle. This
should not be used for lock time because there is a separate LockTime parameter (in the .etplan
file that you created) and its delay will be automatically inserted after the BIST controller is
loaded (and SerDes TX pattern applied), just before measuring begins. You may use any time
units - the default is ms.
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Pin Settings
Click on Pin Settings to drive steady-state logic values into the selected pins during the test, but
only if the pins are connected to the ATE or Signalyzer.
User Bits
Click on User Bits to set individual bit values in the TAP registers.
Do not click on the check boxes to set individual DR Bits--this might lock the submenu. For this reason, Step 2.2 Specify TAP specified that you should provide
aliases for all UserDRBits in your .etassemble file.
Caution
In some cases a logic 0 might enable (turn on) a function, depending on how you have
connected that User Bit.
Show User Bits From TAP/WTAP - TAP refers to the 1149.1 TAP controller (if
you have a Master/Slave arrangement, then only one is active in SiliconInsight - the
Slave must be selected by a User-Defined Sequence). WTAP refers to the Wrapper
TAP connected to the selected SerdesTest (or PLLTest). If no user bits have been
defined for the TAP or WTAP, then it cannot be selected.
After entering all the applicable values and settings in the User Bits window, click
on OK (or Cancel).
When you finish the preceding settings in the Test Step Options window,
Click on OK, then run the test by clicking on the Diagnose icon.
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Right click on one of the Test Controllers, e.g., BP0, then click on Options.
Alternatively, right click on one of the Test Steps, and in the pop-up menu, click on Edit
as a Group. This allows you to simultaneously edit the Test Controller options for all
controllers within a Test Step.
Caution
If any of the sub-menu settings are opened, such as the Channel Select or Under
Sampling Clock Ratio, then the values in these sub-menus will be applied to all Test
Controllers.
A new GUI window will open like the one in Figure 5-4. The window content will depend on
the chosen test type - the window shown here is for Frequency Offset.
Figure 5-4. Example test controller options
The following Test Controller Options are also applicable to other test types:
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The reference beat period is equal to the reciprocal of the frequency offset between the TX
and RX parallel-rate reference frequencies (or PLL reference and undersampling clocks,
respectively).
Measurement Limits
Provide values for Measurement Lower / Upper Limit if you want a meaningful pass/fail test
result. The units will automatically be appropriate for the Test Type chosen for this Test Step:
kHz for offset frequency; ps for jitter; % for duty cycle distortion; bit errors for
FunctionalLoopback (when Sanity Check is off). The value may be positive or zero, or (for
some delay tests) negative. A test will pass if the measured result is exactly equal to a Limit, or
between the Lower and Upper Limits.
Note
After running a Test Step, its icon becomes:
Green if the Test Step was Executed and the measurement was with test limits, or test
limits were not applicable;
Yellow if the Test Step was Diagnosed and the test ran to completion, regardless of
measured value;
Red if the test failed to complete (DoneStatus fails meaning Done bit = 0, or any other
reason) or the measurement was not within test limits, regardless of whether it was run in
Execute or Diagnose mode. The output text in the console window of SiliconInsight will
indicate the reason for failure.
Caution
During Execute mode, the frequency offset magnitude is estimated based on a phase
delay measurement (1 bit for a SerDes; one half cycle for a PLL), so it is not as accurate
as in Measurement mode. In production tests, only use the frequency offset test as a
sanity check of the clocks, with limits looser than +/-5% of nominal offset. In a future
release, this test will be made as accurate as in Measurement mode.
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another device), the Test Time Multiplier (TTM) can be changed so that a test result is
expected later (larger TTM) or sooner (smaller TTM, to save test time) than the time
automatically calculated.
Note
Each test runs until the required number of beat cycles has been analyzed, and then the
results are held within ULTRA logic on-chip until an instruction is received via the JTAG
port to shift the results out - no indication is transmitted out of the chip to indicate that the
test is complete, so a test pattern simply waits the expected number of TCK clock period
and then sends in the shift instruction. It is this wait time that is adjusted using the Test
Time Multiplier. The wait time with TTM=1 is 10% longer than the calculated
theoretical wait time, to allow for some indeterminacy.
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The peak-to-peak jitter value is larger than the sampling resolution multiplied by the
number of histogram bins (default value is 32 bins). A larger USCR value will
increase the jitter amplitude for which the entire histogram can be captured in 32
bins, which improves the accuracy of the RMS calculation.
There is significant synchronous noise at some integer multiple of the parallel clock
period, so it must be cancelled. Choosing a USCR value of 4 will effectively cancel
any noise at one quarter of the parallel-rate clock frequency.
The sampling clock frequency is approximately 2~8 times higher than the sampled.
Choosing a USCR value of 6 will permit the sampling clock (e.g., Recovered clock)
to be 3 or 6 times higher than the sampled clock (e.g., RX reference clock).
Caution
The time interval between consecutive jitter-free edges of the data signal must be larger
than twice the size of the sampling register (typically equal to the number of histogram
bins, which is 32 by default) multiplied by the sampling resolution (typically equal to the
difference between the two parallel-rate reference clock periods) multiplied by the
USCR. To allow for the maximum measurable peak-to-peak jitter, this time interval
between consecutive edges must be increased by 25%. If you set the USCR too large for
the pattern being tested, you will cause an error to be reported in the GUI (Error: For the
test to work, the beat period must be greater than ) because there will be too few
same-value samples between edges of the sampled signal for the edge detection algorithm
to detect the end of an edge region. In other words, the algorithm cannot tell whether a
rising edge that occurs too few samples after a falling edge is outlier jitter from the
preceding falling edge or from the next rising edge. If you get this error message, then try
reducing the USCR value, or choosing a test pattern that has more bit intervals between
the signal edges, e.g., try P1100 instead of P1010 (if testing a PLL, try setting the PLL
output frequency lower).
Measurement Edge
There are two choices: RISE or FALL. When measuring jitter for a clock or any clock-like data
pattern, the measurement results may be different for each edge due to differences in slew rate,
crosstalk (on-chip or off-chip), or inter-symbol interference (ISI). For frequency offset and most
other tests, use the default value (RISE) unless you are diagnosing whether there is interference
on only one edge, as can occur when on-chip switching is predominantly active after, say, the
rising edge.
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Within the ReferenceClocks Test Group, add another Test Step with at least one
ULTRA controller, and name the Test Step something like ReferenceClockJitter.
Right click on the new Test Step and select Options to get the Test Step Options
window of Figure 5-2 on page 74.
Click on the pull-down menu beside SerDes Test or PLL Test, and choose
JitterFromCDF to capture the jitter histogram, or Jitter to simply measure its RMS
value (assuming it is Gaussian).
Click on OK, then right-click on one of the Test Controllers, and click on Options.
Click on the pull-down menu beside Signal To Measure, and choose pllInputClk if it
is a PLL or TransmitterClock if it is a SerDes (the Data Bit Number will be ignored).
Click on OK, then run the test by clicking on the Diagnose icon.
JitterFromCDF
ULTRA captures the CDF (cumulative distribution function, or cumulative histogram), and
outputs 32 bin-values of 12 bits each (by default - you can change this with the
CDFNumberOfBins parameter in the .etplan file). The differences between the CDF bins are
equal to the bin values of the histogram.
Note
If you would like nicer jitter histogram plots, suitable for reports,
Create a file named .lv_eta.config in your current directory, that has the following
two lines (the first line is a comment):
# Create jitter histogram gnu plot files
configure PDFPlotEnable 1
Formatted plot files will be placed in the outdir directory.
Caution
For this test, no measurement limits are applied within the GUI - this must be done in a
test program, e.g., for the range or RMS value. For small ranges (fewer than 16 bins), the
center bin may be artificially high because the BIST algorithm uses a median-based
algorithm instead of the mean-based algorithm used for a true RMS calculation. Most
SerDes clock-data-recovery (CDR) circuits use a median-based eye-centering algorithm,
so the BIST algorithm may be more representative of their true performance.
Jitter
ULTRA estimates RMS value on-chip by finding the 25% and 75% points on the CDF and
compares to limits derived from an ideal Gaussian CDF. This test is best for production testing
because the ATE need only monitor the shifted-out pass/fail bits, however, the measured value
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may be significantly less than the value calculated for a shifted-out CDF if the true RMS value
is very small (less than twice the sampling resolution).
When testing SerDes reference clocks, the transmitted/received data pattern is not important
except to provide SerDes activity, and when testing PLLs it is not meaningful at all. Beside
Pattern, click on the pull-down menu and select P1010. This causes a 1010 serial data pattern to
be transmitted/received and will cause the least parallel-data-related noise on-chip, so that you
will measure primarily jitter in the reference clocks caused by the clock generation and the
clock paths. You can try other patterns to see their effect on the measurement result.
Right click on one of the Test Controllers and then click on Options, or right click on
one of the Test Steps, and in the pop-up menu, click on Edit as a Group.
Click on Signal To Measure and select Transmitter. This measures jitter in the
transmitter's parallel-rate clock (reference clock), as sampled in the core logic (RPA
block) by the RX reference clock (undersampling clock).
Caution
Any clock jitter test uses one clock to sample another clock, therefore, the measured jitter
histogram is actually the sum of jitter in each of the two signals involved, and the
measured RMS jitter is the RMS sum of jitter in the two signals, i.e., Jrms2 = J1rms2 +
J2rms2. For example, if the Signal To Measure is Transmitter, then the RX reference clock
(undersampling clock) samples the TX reference clock (reference clock), and the result is
the sum of the jitter in both clocks.
Caution
When testing SerDes, if your RX reference clock (undersampling clock) frequency is not
equal to the RX parallel rate frequency, SerdesTest does not presently account for this, so
you must scale the measured result appropriately. If RX reference clock is N times lower
than parallel rate, then measured values for jitter and mean sampling instant must be
multiplied by N to get the correct value. Only these two tests are affected.
See Use SiliconInsight to Characterize Your PLL.
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Chapter 6
Step 5: Characterize your PLL
Use SiliconInsight to Characterize Your PLL
At this stage, if you have implemented all of the preceding instructions, you have added Test
Steps that test the entire JTAG and PLLTest infrastructure, and these tests will typically take
less than 25 ms to run in a production test program. Next, tests for the PLL or DLL will be
described, in the following order, which is recommended for easiest diagnosis:
PLL output
HF jitter
LF jitter
Measure waveform
o
Duty cycle
Frequency
Phase locking
o
Duty cycle of lock detector, for 1 beat period after PLL's divider altered
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For PLLTest, the sampling resolution is the difference between the sampling clock period and
the nearest frequency that is synchronous to the sampled clock frequency:
TRESOLUTION = | N TPLLOUT - TSAMPLING |
For an example PLL with 50 MHz input, 400 MHz output, and ~50 MHz sampling clock:
TRESOLUTION = | 8 2.5ns - 20.001ns | = 1 ps
Click on the pull-down menu beside PLL Test, and choose JitterFromCDF (if it is not
already selected), or Jitter to measure its RMS value.
Right click on the new Test Step and select Options to get the Test Step Options
window.
Note
The results for this test will be affected by the reference frequency offset because the low
frequency cut-off is linearly dependent on the frequency offset (and because the
measurement's resolution is also linearly dependent).
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Right click on one of the Test Controllers and then select Options (or right click on one
of the Test Steps, and in the pop-up menu click on Edit as a Group).
If more than one PLL Sampler module is connected to the ULTRA, then click on the
number beside PLL to Test that corresponds to the PLL you want to test.
Click on Signal To Measure, and select pllOutput or pllInputClk. This measures jitter
as sampled by one of the inputs to ULTRA.
If you chose pllOutput, click on the number beside Data Bit Number and select the
input of your Sampler module that is connected to the PLL output of interest. Dont
select 0 or 1 because 0 samples the PLL input reference clock divided by two, and 1 resamples that value. (If you chose pllInputClk, the Data Bit Number is ignored.)
Click on OK, then run the test by clicking on the Diagnose icon.
Caution
You must choose a PLL output-to-input frequency ratio that is appropriate for the
sampling resolution you choose. For maximum ppm offset permitted according to the
<chip>.etplan file, which is 1956, the maximum PLL out/in frequency ratio is 15. If the
ppm offset is reduced by half, to 1000 (or 0.1%) for example, then the PLL out/in ratio
can be increased to 30. This ensures sufficient samples per output clock period.
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where,
TBase is the period of the base reference frequency, which is the shortest period into
which fits exactly an integer number of Reference clock periods and an integer number
of Sampling clock periods;
txDivider is the integer number of Reference clock periods that exactly fits the Tbase
period;
rxDivider is the integer number of Sampling clock periods that exactly fits the Tbase
period.
Note
To quickly find the correct ClockSource names, click on the Test Step in SiliconInsight,
then click on Async Clock Periods - you will see the two clock names that are relevant.
The choices of Tbase and divider values must be exactly correct for this test, but they are easily
determined using LV_ClockGenerator.exe (the program is also available in Excel), which is
available by special request to your Mentor Technical Marketing Engineer. The GUI calculates
optimal values for the clock frequencies that are input and output by LMK03000/1/2 PLLs or
any other clock generators. The three values required are highlighted in the bottom right corner
of Figure 6-1.
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In the PLLOutput Test Group, click on the Test Step named OutJitter_HF, then
copy it into the same Test Group. Rename the Test Step to something like
OutputJitter_LF.
Right click on the new Test Step and select Options to get the Test Step Options
window.
Click on the pull-down menu beside PLL Test, and choose JitterFromCDF (if it is not
already selected).
Click on OK.
Click on Signal To Measure, and select pllOutput. Then click on the pull-down menu
beside Data Bit Number and select a number corresponding to the PLL output of
interest. Alternatively, click on Signal to Measure and select pllInputClk.
Click on OK, then run the test by clicking on the Diagnose icon.
Right click on one of the Test Controllers and then select Options (or right click on one
of the Test Steps, and in the pop-up menu click on Edit as a Group).
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Caution
You must use the JitterFromCDF test type to measure low frequency jitter. The Jitter
test will only measure HF jitter.
You may edit this file while you are in SiliconInsight. The file will be used any time the test is
run (in Diagnose mode only).
In the PLLOutput Test Group, copy the OutputJitter_HF Test Step, paste it into the
same Test Group, and rename it something like OutputDutyCycle.
Right click on the new Test Step and select Options to get the Test Step Options
window.
Click on the pull-down menu beside PLL Test, and choose DutyCycleDistortion to
measure the duty cycle, relative to 50%.
If more than one PLL Sampler module is connected to the ULTRA, then click on the
number beside PLL to Test that corresponds to the PLL you want to test.
Click on Signal To Measure, and select pllOutput. Then click on the pull-down menu
beside Data Bit Number and select a number corresponding to the PLL output of
interest. Alternatively, click on Signal to Measure and select pllInputClk.
Click on OK, then run the test by clicking on the Diagnose icon.
DCD is reported after subtracting 50% from the measured duty cycle, but you must
provide test limits for the duty cycle without subtracting 50%.
96
In the PLLOutput Test Group, copy the OutputJitter_HF Test Step, paste it into the
same Test Group, and rename it something like FoutDividedByFin.
Tessent PLLTest Users Manual, v2016.1
March 2016
Right click on the new Test Step and select Options to get the Test Step Options
window.
Click on the pull-down menu beside PLL Test, and choose FrequencyMultiplier.
If more than one PLL Sampler module is connected to the ULTRA, then click on the
number beside PLL to Test that corresponds to the PLL you want to test.
Click on the pull-down menu beside Data Bit Number and select a number
corresponding to the PLL output of interest.
Click on OK, then run the test by clicking on the Diagnose icon.
Click on OK.
Right click on one of the Test Controllers and then select Options (or right click on one
of the Test Steps, and in the pop-up menu click on Edit as a Group),
Click on the pull-down menu beside PLL Test, and select Delay.
If more than one PLL Sampler module is connected to the ULTRA, then click on the
number beside PLL to Test that corresponds to the PLL you want to test.
Click on the pull-down menu beside Data Bit Number, and select the number
corresponding to the PLL ouput of interest.
Click on OK, then run the test by clicking on the Diagnose icon.
In the PLLOutput Test Group, copy the OutputJitter_HF Test Step, paste it into the
PLLInToOut Test Group, and rename the Test Step something like PhaseDelay.
Right click on one of the Test Controllers and then select Options, or right click on one
of the Test Steps, and in the pop-up menu, click on Edit as a Group.
Phase delays are measured in picoseconds, from minus one half of the PLLs reference clock
period, to plus one half of the period. Beyond that is ambiguous: for example, if the reference
clock period is 10 ns, an actual phase delay of +7 ns will be reported as -3 ns. Furthermore,
delay will be measured to the nearest edge in that range, so the maximum measurable delay for
a PLL output frequency that is higher than the input frequency is plus or minus one period of the
output frequency.
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98
Right click on the new Test Step and select Options to get the Test Step Options
window.
Click on the pull-down menu beside PLL Test, and choose LockTime.
Click on the pull-down menu beside Data Bit Number and select the number
corresponding to the lock detector output of your PLL it should be the highest
numbered input.
Enter a value for Test Duration in Beat Cycles that is greater than the largest expected
lock time divided by the period of the frequency offset. If the actual lock time is longer
than this duration, only the test duration will be reported.
For example, if your PLLs reference clock period is 100 MHz, and the frequency offset
is 1000 ppm (= 0.1%), then the offset is 100 kHz and its period is 10 s. If maximum
permitted lock time is, for example, 20 s, then you could set Test Duration in Beat
Cycles to twice that duration, which is 4 Beat Cycles.
Optionally enter values for Test Limits, where the duration is in units of microseconds.
Click on OK.
Right click on the appropriate Test Controller and select Options.
If more than one PLL Sampler module is connected to the ULTRA, then click on the
number beside PLL to Test that corresponds to the PLL you want to test.
Click on OK, then run the test by clicking on the Diagnose icon.
Test limits are in entered units of microseconds.
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Chapter 7
Step 6: Diagnose and Characterize Tests
Step 6.0 Diagnose Basic Connectivity
Run the jtagVerify Test Group a few times to test the JTAG connections to the TAP and
ULTRA.
If it passes, all connections to the IC's TAP are good, the TAP functions correctly, and it
communicates with each of the ULTRA Test Controllers that you have included in the Test Step
that runs the BasicTests pattern.
If it fails, click on the + symbol beside the G icon to see which Test Step failed. Here are
possible failures, their cause, and possible fixes:
All Test Steps failed, with many miscompares reported in the Console window, and the
expected values were all '0' as shown in Figure 7-1 on page 102:
Some Test Steps fail, with a few miscompares reported, some are expected '0' and some
are expected '1':
resistive or capacitive loading on the TAP signal - check amplitude and rise times at
IC pins.
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Figure 7-1. Example of failures reported when no connections to the TAP pins,
or TDO pin
102
the actual reference clock frequency or TCK clock frequency is different than expected;
the frequency offset is less than expected;
the sampling clock frequency is synchronous to the sampled frequency;
LVDB Directory:
/home/siuser/Serdes_FPGA_ITC_demo/EST_FPGA.lvdb
LVDB Name:
EST_FPGA.lvdb
Test Config:
serdes_ITCdemo
TestStep: CDF_RandomJitterRMS_P1010 (FAILED)
Execution Time Stamp: 01/18/09 21:11:30
UltraController "BP1" (RXBCLK, 6.4ns)
Port "DoneStatus" failed (DR_STATUS3=0).
====================================================================
use P1100 instead of P1010, to allow more time between jittery edges
use a clock-like pattern instead of P10J / P01J, to eliminate data-dependent jitter.
The measured value was not between the Measurement Upper and Lower Limits (e.g. for
Jitter) - this is usually caused by:
frequency offset measurement is correct in Diagnose mode, but Exec mode test fails
Lower Limit (by a factor of 3 for PLLTest, or N-1 for N-bit SerdesTest);
check the periods of the two clocks relative to the values declared in SiliconInsight
for Async Clock Periods; if the period for the TestClock clock in etplan file is longer
than the period for pllReference clock, then the offset measured in Diagnosis mode
should be positive - if it is negative, then the clock connections might be reversed.
increase the Test Duration in Beat Cycles, to make the result more repeatable;
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examine the shape of the jitter histogram see Step 6.2 Diagnose Jitter
Measurements
Note
The default number of CDF bins is 32, and the resulting number of histogram bins is 32,
but only 31 bins can be displayed. Also, the console omits leading and trailing zero-value
bins to save screen space.
The Jitter test produces an RMS value (derived on-chip from two points in the CDF curve) that
is often less than the RMS value for the CDF captured by the JitterFromCDF test, especially
when:
104
when the Test Duration in Beat Cycles value is too small (insufficient samples)
there are many outliers (the on-chip algorithm counts the number of outliers but not their
values)
When measuring delay variation (jitter), the jitter in the sampling clock may affect the results
and should be measured.
HF jitter in reference clocks
increased by crosstalk
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Periodic Jitter
Periodic jitter at the clock or data frequency, or a sub-multiple (i.e. jitter with a period that is N
times the clock period or UI), the measured jitter histogram may have every Nth bin nearly zero
- if you change the Under Sampling Clock Ratio to equal N then the histogram will look more
Gaussian. This allows you to diagnose the existence of periodic jitter and still measure the
random jitter accurately. Note that the periodic jitter could be in the sampling clock or the
sampled signal.
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If you want to see a trend plot in the +/-3 sigma range (but without hex codes), then also
click on the checkbox beside Display Trend Plot
Click on OK, then run the test by clicking on the Diagnose icon.
Enter the number of times that you want to repeat the measurement (default is 10)
This setting will result in a statistical summary output when Test Step is Diagnosed
If you want to see every measurement (and the hex code for the actual output bits), then
also click on the checkbox beside Display All Measurements
The Trend plot shows an asterisk for each data point, a vertical line for the lower and upper 3
sigma values, and < or > next to the vertical line if a data point is outside the 3 sigma
range.
If you want to see a histogram for the measurements, click on Tools, select Command Line ,
then in the Command Line Dialog window,
write LV::configure RAHistogramEnable 1 ,
then press Enter.
Thereafter, whenever you run repeatability analysis, the histogram will be displayed. To stop
this display,
write LV::configure RAHistogramEnable 0 ,
then press Enter.
If you click on Execute for a test that has Repeatability Analysis enabled, the test will Execute
only once. If the test does not have an Execute mode (e.g., the JitterFromCDF test), and it has
auto-diagnose enabled, then the test will run once in Diagnose mode once (this is a
convenient way to quickly check the jitter histogram before running Repeatability Analysis).
You can set the Repeatability Analysis options for all Test Steps simultaneously as follows:
Click on OK
If some setting was modified, the Console window will indicate the following:
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Successfully updated
BasicTests
Test time = 100 bits / TCKFrequency(Hz)
108
Typical example
Test time = <0.1 ms
OffsetFrequency
Test time = Test Duration in Beat Cycles / FrequencyOffset(Hz)
Typical example
Test time = 500 / 25000 = 20 ms
Jitter, DutyCycleDistortion
Test time = RelativePatternLength Test Duration in Beat Cycles / FrequencyOffset(Hz)
SerdesTest: RelativePatternLength = PatternLength / SerDesWordSize
PLLTest: RelativePatternLength = PLLReferenceFrequency / MeasuredFrequency
Pattern Lengths (in UI)
P1010, P0101 : 2
P1100, P0011 : 4
PHalfOne, PHalfOneC : 10 if SerDesWordSize is a multiple of 10, else 8
PV40, PV60, P01J, P10J : 10 if SerDesWordSize is a multiple of 10, else 8
All others : SerDesWordSize
JitterFromCDF
Test time = Test time for Jitter + histogram analysis time
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FunctionalLoopback
PLL test time = Test Duration in Beat Cycles / Frequency Offset(Hz)
SerDes test time = Loopback in Word Clock Cycles ClockPeriod(ns)
Typical example for 10M serial bits, SerDesWordSize = 20, 250 MHz parallel clock (at 5 Gb/s)
Test time = 500000 4 = 10 ms
Mentor Graphics can provide software that helps you select optimal values
Whereas Jitter measurements require the correct LF cut-off frequency, phase delay
measurements have no such requirement.
110
The external filter's capacitance can be increased, or its resistance can be decreased,
by connecting passive components in parallel with existing passive components
The internal loop filter can be selected via the Test Step that programs the PLL
LF jitter in the PLL output may be reduced if the master reference frequency is
significantly higher or lower (because it allows a better choice of PLL divider
values).
It is possible to use the output from one LMK03000 PLL as a reference for the other
PLL, thus allowing a higher or lower input frequency for the second PLL; in some
cases this may reduce LF jitter.
Use alternative tests that are more repeatable within a given time interval
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Click on Save To File to define the filename and directory for the data log file; the
default filename is <outdir>/eta_console.log.
click on Datalog File to define the filename and directory for the data log file; the
default filename is <outdir>/eta_results.log.
Enter a User Tag value (12 characters maximum), at the top of the Console section to record the
device identification number and/or a test condition. This value will be appear in the Datalog
file as the Output ID value and is very useful when you are characterizing many devices in
sequence.
Preparation
After each Test Step in SiliconInsight has been run successfully, with sufficiently repeatable
results for each measurement on one device or several devices, you can run all tests for one
device by clicking on the packaged device icon at the top of the Test Configuration window,
and then clicking on the Diagnose button. Before doing that,
Delete all unnecessary Test Steps (click on Test Step, then Ctrl X)
Enter text into the User Tag window to indicate which device number you are testing,
e.g. chip_001
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At the top of SiliconInsight GUI, click on Console, then Save To File then enter a
name and directory.
You will need to write a script to extract the test results for statistical analysis.
The first time you run each test, it runs slowly and produces more text in the Console window as
it is compiled, but thereafter it runs much faster. In SiliconInsight, each Test Step typically
requires 100 ms and a suite of SerDes tests usually requires 5~20 seconds. Outside of
SiliconInsight, using the automatically generated test vectors for go/no-go production testing,
the same test vectors may run 10X faster. The next section will show you how to estimate
production test times.
Caution
When running a suite of tests, in Characterize or Execute mode, pass/fail repeatability is
generally poor on a PC due to USB-JTAG handling of large amounts of data. You should
use SiliconInsight on ATE for this procedure.
or enter each command using the following syntax to get or set property values:
getProp <TestStepName> SerdesTest
setProp <TestStepName> SerdesTest <TestType>
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For example:
setProp Step1 SerdesTest Delay
(Note that SerdesTest is used whether it is a SerDes or PLL, but you must use a
TestType that is applicable to the function.)
For example:
getProp Step1 BP0 LocktimePause
setProp Step1 BP0 LocktimePause LocktimePause 10ms
getProp S0 BP0 UnderSamplingClkRatio
setProp S0 BP0 UnderSamplingClkRatio 2
getProp S0 BP0 MeasurementLimits()::UpperLimit
setProp S0 BP0 MeasurementLimits()::UpperLimit 10
setProp S0 BP0 MeasurementLimits()::LowerLimit -10
For example:
ExecuteStep S0
DiagnoseStep S0
4. To select the TPG/RPA that will be enabled for a test, or to find out which will be
enabled, use the following commands in the Command Line Dialog window:
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For example:
setProp TPGChannelEnable S0 BP0 {0 1 3}
setProp RPAChannelEnable S0 BP0 [list 0 1 3]
Note
There are behavior differences between entering a parameter value with a click, and using
setProp. For the EST plugin, when a property is set using setProp in a test step and the
property is valid, the test step is usually marked as dirty and the pattern is usually
regenerated the next time Execute/Diagnose is performed. This is true even if the value of
the property does not change. However, the GUI is not updated (going from green/red
back to gray), and sometimes the pattern is not regenerated. To update the state of the
GUI and to ensure that the pattern is regenerated, the following commands can be added
after a group of set commands:
dirtyStep <TestStepName>
For example:
dirtyStep Step1
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Chapter 8
Step 7: Generate Production Tests
After characterization, and setting test limits that provide optimal quality and yield based on a
representative number of devices, you generate go/no-go test vectors that run on any ATE. Each
pattern has its own name, and is called by the test program that you write.
Generate an etverify output from SiliconInsight. From this file, you can generate test patterns in
generic formats (STIL, WGL, or SVF).
Click on OK
Import this file back into SiliconInsight to check that any changes you made are correct:
Check that any changes you made are correct, then Exit.
In the Export ETV Configuration File window, select the directory <chip>.lvdb/.
and select the file <chip>.etManufacturing
You can read the resulting plain text file - it contains all your tests organized in
serdesVerify wrappers. If necessary, you can edit this file, for example to duplicate test
steps so that the same User Bits setting is used for equalization.
Instead of -wgl, you can specify any one of the following runtime options:
-stil, -svf, -verilog
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Note
Some of the jtagVerify test steps cannot be performed with .svf because those tests end
in intermediate TAP states.
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Appendix A
Getting Help
There are several ways to get help when setting up and using Tessent software tools. Depending
on your need, help is available from documentation, online command help, and Mentor
Graphics Support.
Documentation
The Tessent software tree includes a complete set of documentation in both HTML and PDF
format. PDF file viewing of the documentation on a Linux file server is best suited for Adobe
Reader versions 8 or 9, and you must set one of these versions as the default using the
MGC_PDF_READER variable in your mgc_doc_options.ini file.
For more information, refer to Specifying Documentation System Defaults in the Managing
Mentor Graphics Tessent Software manual.
You can access the documentation in the following ways:
Shell Command On Linux platforms, enter mgcdocs at the shell prompt or invoke a
Tessent tool with the -Manual invocation switch. This option is available only with
Tessent Shell-based tools.
File System Access the PDF Tessent bookcase directly from your file system,
without invoking a Tessent tool. From your product installation, invoke Adobe Reader
on the following file:
$MGC_DFT/doc/pdfdocs/_bk_tessent.pdf
Application Online Help You can get contextual online help within most Tessent
tools by using the help -manual tool command:
> help dofile -manual
This command opens the appropriate reference manual at the dofile command
description.
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Mentor Graphics Support
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Appendix B
Commands and Control Files
Sequence of EDA commands
Current directory:ETCHECKER
Step 1.1: etchecker <chip> ...
Step 1.4: make <chip>.clockInfo
Step 1.5: make <chip>.ruleCheck
Current directory:DFT
Step 1.7: etplanner <chip> ...
Step 2.0: make checkPlan
Step 2.1: make genLVWS
==> <chip>.etchecker
==> <chip>.etplan
==> <chip>.etassemble
Current directory:DFT/<chip>_LVWS/ETAssemble
Step 2.3: make embedded_test --+
Step 2.4: make designe
|
Step 2.5: make config_etSignOff | ==> <chip>.etSignOff
Step 2.6: make lvdb_preLayout
+-- make all
Step 2.7: make testbench
|
Step 2.8: make sim
--+
Step 2.10: make synth
Step 2.13: make concatenated_netlist => <chip>.vb_postLV
Current directory:DFT/<chip>_LVWS/ETSignOff
Step 2.14: make config_etManufacturing
Step 2.15: make lvdb_final
==> <chip>.lvdb/
Step 2.16: make testbench
Step 2.17: make <chip>_sim
Step 2.18: make patterns
Step 2.19: make archive_config
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ETCHECKER/<chip>.etchecker
ETCHECKER/Makefile
DFT/<chip>.etplan
DFT/<chip>_LVWS/ETAssemble/<chip>.etassemble
DFT/<chip>_LVWS/ETAssemble/<chip>.etSignOff ->
DFT/<chip>_LVWS/ETSignOff/<chip>.lvdb_prelayout/<chip>.etSignOff
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High-level parameters describing the minimum suite of test patterns for simulation and
verifying basic operation of SerdesTest or PLLTest (with jitter-free signals)
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Appendix C
Models
Simplified PLL model
To try the design flow described in this document using an example jitter-free PLL, you may
use the following RTL model to quickly simulate (less than a minute) the test bench
automatically generated by the Make Testbench command.
`celldefine
`timescale 1 ns
// Parameters:
REF clock
/ 1 fs
// Input:
Multiplier integer>0 (not checked); I/O delay (ns); Locktime (us), >1 cycle of
// Outputs
//
//
I/O delay is applied modulo the full period of the output frequency. Within that modulo
delay,
//
//
//
Goes to 1 when PLL has locked. Minimum is 2 full cycles of REF. Otherwise, elapsed time is
checked on
//
every falling edge of REF and the PLL is then enabled. The LOCKED signal goes high on the
2nd rising
//
edge of REF following the time when the specified locktime has elapsed. CKM outputs are
generated in
//
the REF cycle that precedes the LOCKED signal being asserted.
REF;
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Simplified PLL model
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initial begin
MM = 0;
iodelay = 0.0;
edge1Time = 0.0;
firstEdgeTime = 0.0;
lockTime = 0.0;
refLockTime = 1000.0 * LOCKTIME_US;
VCO_CPL = 1'b0;
VCO4 = 1'b0;
EN = 1'b0;
@(posedge REF) firstEdgeTime = $realtime;
@(vcohp);
@(negedge REF);
@(posedge REF);
if (refLockTime <= 0.0) begin
EN = 1'b1;
lockTime = $realtime - firstEdgeTime;
end
end
always @ ( posedge REF ) begin
period = $realtime - edge1Time;
vcohp = 0.125 * period / M;
edge1Time = $realtime;
if (EN) begin
if (vcohp > 0.0) begin
MU = $rtoi(1.0 * IODELAY_NS / vcohp);
iodelay = IODELAY_NS - $itor(MU) * vcohp;
if ((MU % 2) == 0) begin
VCO_CPL = 1'b0;
end else begin
VCO_CPL = 1'b1;
end
end else begin
iodelay = 0.0;
end
VCO4 = 1'b1;
for (MM = 4*M - 1; MM > 0; MM = MM - 1) begin
#(vcohp) VCO4 = ~VCO4;
#(vcohp) VCO4 = ~VCO4;
end
#(vcohp) VCO4 = ~VCO4;
end else begin
VCO4 = 1'b0;
@(negedge REF);
if (refLockTime > 0.0) begin
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Simplified
PLL
model
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lockTime = $realtime - firstEdgeTime;
if (lockTime - refLockTime > 0.0) begin
EN = 1'b1;
end
end
end
end
initial begin
C0 = 2'b11;
C1 = 2'b10;
C2 = 2'b01;
C3 = 2'b00;
CKMD = 4'b0000;
LOCKED = 1'b0;
end
always @(posedge C3[1]) CKMD[3] = EN;
always @(posedge C2[1]) CKMD[2] = EN;
always @(posedge C1[1]) CKMD[1] = EN;
always @(posedge C0[1]) CKMD[0] = EN;
always @(posedge REF) LOCKED <= CKMD[3];
assign CKM = { CKMD[3] & C3[1], CKMD[2] & C2[1], CKMD[1] & C1[1], CKMD[0] & C0[1] };
always @(VCO4 or VCO_CPL) begin
#(iodelay) VCO4D = EN & (VCO4 ^ VCO_CPL);
end
always @(posedge VCO4D) begin
C0 <= C0 - 2'b01;
C1 <= C1 - 2'b01;
C2 <= C2 - 2'b01;
C3 <= C3 - 2'b01;
end
`endif
endmodule
`endcelldefin
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Simplified PLL model
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Appendix D
Jitter Components and Frequencies
Figure D-1 illustrates the source of and relationships between different jitter components.
Figure D-1. Jitter Components
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Appendix E
Document Updates
This is a living document. As improvements are found for the recommended practices
documented herein, they will be added.
Approximately in order of priority, highest at top of list.
How to test Transmitter-only SerDes, by adding a sampling latch to its output so that it
becomes a transceiver - some tests are not applicable
Session Setup...
Debug Toolkit...
How to adjust VDD via SiliconInsight when a power supply is connected via USBJTAG (or in ATE).
Add a note somewhere that each test step presently generates a pattern, and each has its
own reset (and lock time).
Eventually, an option will be provided so that instead of each Test Step having a reset,
only each Test Group would have a reset, to save test time. This also means that Test
Step order would be more significant.
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Third-Party Information
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For information about third-party software included with this release of Tessent products, refer to the Third-Party Software for
Tessent Products.
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The latest version of the End-User License Agreement is available on-line at:
www.mentor.com/eula
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perfecting such security interest. Mentor Graphics delivery of Software by electronic means is subject to Customers provision
of both a primary and an alternate e-mail address.
GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement, including any
updates, modifications, revisions, copies, documentation, setup files and design data (Software) are copyrighted, trade secret and
confidential information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retain all rights not
expressly granted by this Agreement. Except for Software that is embeddable (Embedded Software), which is licensed pursuant to
separate embedded software terms or an embedded software supplement, Mentor Graphics grants to Customer, subject to payment of
applicable license fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form
(except as provided in Subsection 4.2); (b) for Customers internal business purposes; (c) for the term of the license; and (d) on the
computer hardware and at the site authorized by Mentor Graphics. A site is restricted to a one-half mile (800 meter) radius. Customer
may have Software temporarily used by an employee for telecommuting purposes from locations other than a Customer office, such as
the employees residence, an airport or hotel, provided that such employees primary place of employment is the site where the
Software is authorized for use. Mentor Graphics standard policies and programs, which vary depending on Software, license fees paid
or services purchased, apply to the following: (a) relocation of Software; (b) use of Software, which may be limited, for example, to
execution of a single session by a single user on the authorized hardware or for a restricted period of time (such limitations may be
technically implemented through the use of authorization codes or similar devices); and (c) support services provided, including
eligibility to receive telephone support, updates, modifications, and revisions. For the avoidance of doubt, if Customer provides any
feedback or requests any change or enhancement to Products, whether in the course of receiving support or consulting services,
evaluating Products, performing beta testing or otherwise, any inventions, product improvements, modifications or developments made
by Mentor Graphics (at Mentor Graphics sole discretion) will be the exclusive property of Mentor Graphics.
3.
4.
BETA CODE.
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3.1.
Portions or all of certain Software may contain code for experimental testing and evaluation (which may be either alpha or beta,
collectively Beta Code), which may not be used without Mentor Graphics explicit authorization. Upon Mentor Graphics
authorization, Mentor Graphics grants to Customer a temporary, nontransferable, nonexclusive license for experimental use to
test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. Mentor Graphics may
choose, at its sole discretion, not to release Beta Code commercially in any form.
3.2.
If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code under normal
conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customers use of the
Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customers evaluation and testing,
Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and
recommended improvements.
3.3.
Customer agrees to maintain Beta Code in confidence and shall restrict access to the Beta Code, including the methods and
concepts utilized therein, solely to those employees and Customer location(s) authorized by Mentor Graphics to perform beta
testing. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments
that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on
Customers feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and
interest in all such property. The provisions of this Subsection 3.3 shall survive termination of this Agreement.
RESTRICTIONS ON USE.
4.1.
Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices
and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall
remain the property of Mentor Graphics or its licensors. Except for Embedded Software that has been embedded in executable
code form in Customers product(s), Customer shall maintain a record of the number and primary location of all copies of
Software, including copies merged with other software, and shall make those records available to Mentor Graphics upon
request. Customer shall not make Products available in any form to any person other than Customers employees and on-site
contractors, excluding Mentor Graphics competitors, whose job performance requires access and who are under obligations of
confidentiality. Customer shall take appropriate action to protect the confidentiality of Products and ensure that any person
permitted access does not disclose or use Products except as permitted by this Agreement. Customer shall give Mentor Graphics
written notice of any unauthorized disclosure or use of the Products as soon as Customer becomes aware of such unauthorized
disclosure or use. Customer acknowledges that Software provided hereunder may contain source code which is proprietary and
its confidentiality is of the highest importance and value to Mentor Graphics. Customer acknowledges that Mentor Graphics
may be seriously harmed if such source code is disclosed in violation of this Agreement. Except as otherwise permitted for
purposes of interoperability as specified by applicable and mandatory local law, Customer shall not reverse-assemble,
disassemble, reverse-compile, or reverse-engineer any Product, or in any way derive any source code from Software that is not
provided to Customer in source code form. Log files, data files, rule files and script files generated by or for the Software
(collectively Files), including without limitation files containing Standard Verification Rule Format (SVRF) and Tcl
Verification Format (TVF) which are Mentor Graphics trade secret and proprietary syntaxes for expressing process rules,
constitute or include confidential information of Mentor Graphics. Customer may share Files with third parties, excluding
Mentor Graphics competitors, provided that the confidentiality of such Files is protected by written agreement at least as well as
Customer protects other information of a similar nature or importance, but in any case with at least reasonable care. Customer
may use Files containing SVRF or TVF only with Mentor Graphics products. Under no circumstances shall Customer use
Products or Files or allow their use for the purpose of developing, enhancing or marketing any product that is in any way
competitive with Products, or disclose to any third party the results of, or information pertaining to, any benchmark.
4.2.
If any Software or portions thereof are provided in source code form, Customer will use the source code only to correct software
errors and enhance or modify the Software for the authorized use, or as permitted for Embedded Software under separate
embedded software terms or an embedded software supplement. Customer shall not disclose or permit disclosure of source
code, in whole or in part, including any of its methods or concepts, to anyone except Customers employees or on-site
contractors, excluding Mentor Graphics competitors, with a need to know. Customer shall not copy or compile source code in
any manner except to support this authorized use.
4.3.
Customer agrees that it will not subject any Product to any open source software (OSS) license that conflicts with this
Agreement or that does not otherwise apply to such Product.
4.4.
Customer may not assign this Agreement or the rights and duties under it, or relocate, sublicense, or otherwise transfer the
Products, whether by operation of law or otherwise (Attempted Transfer), without Mentor Graphics prior written consent and
payment of Mentor Graphics then-current applicable relocation and/or transfer fees. Any Attempted Transfer without Mentor
Graphics prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics option, result in the
immediate termination of the Agreement and/or the licenses granted under this Agreement. The terms of this Agreement,
including without limitation the licensing and assignment provisions, shall be binding upon Customers permitted successors in
interest and assigns.
4.5.
The provisions of this Section 4 shall survive the termination of this Agreement.
5.
SUPPORT SERVICES. To the extent Customer purchases support services, Mentor Graphics will provide Customer with updates and
technical support for the Products, at the Customer site(s) for which support is purchased, in accordance with Mentor Graphics then
current End-User Support Terms located at http://supportnet.mentor.com/supportterms.
6.
OPEN SOURCE SOFTWARE. Products may contain OSS or code distributed under a proprietary third party license agreement, to
which additional rights or obligations (Third Party Terms) may apply. Please see the applicable Product documentation (including
license files, header files, read-me files or source code) for details. In the event of conflict between the terms of this Agreement
(including any addenda) and the Third Party Terms, the Third Party Terms will control solely with respect toSearch
the OSShere...
or third party
code. The provisions of this Section 6 shall survive the termination of this Agreement.
7.
LIMITED WARRANTY.
7.1.
Mentor Graphics warrants that during the warranty period its standard, generally supported Products, when properly installed,
will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not
warrant that Products will meet Customers requirements or that operation of Products will be uninterrupted or error free. The
warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. Customer must
notify Mentor Graphics in writing of any nonconformity within the warranty period. For the avoidance of doubt, this warranty
applies only to the initial shipment of Software under an Order and does not renew or reset, for example, with the delivery of (a)
Software updates or (b) authorization codes or alternate Software under a transaction involving Software re-mix. This warranty
shall not be valid if Products have been subject to misuse, unauthorized modification, improper installation or Customer is not
in compliance with this Agreement. MENTOR GRAPHICS ENTIRE LIABILITY AND CUSTOMERS EXCLUSIVE
REMEDY SHALL BE, AT MENTOR GRAPHICS OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON
RETURN OF THE PRODUCTS TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF THE
PRODUCTS THAT DO NOT MEET THIS LIMITED WARRANTY. MENTOR GRAPHICS MAKES NO WARRANTIES
WITH RESPECT TO: (A) SERVICES; (B) PRODUCTS PROVIDED AT NO CHARGE; OR (C) BETA CODE; ALL OF
WHICH ARE PROVIDED AS IS.
7.2.
THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS
LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO
PRODUCTS PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY
DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.
8.
LIMITATION OF LIABILITY. TO THE EXTENT PERMITTED UNDER APPLICABLE LAW, IN NO EVENT SHALL
MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER
LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS
AGREEMENT EXCEED THE AMOUNT RECEIVED FROM CUSTOMER FOR THE HARDWARE, SOFTWARE LICENSE OR
SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS
LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8
SHALL SURVIVE THE TERMINATION OF THIS AGREEMENT.
9.
Customer acknowledges that Mentor Graphics has no control over the testing of Customers products, or the specific
applications and use of Products. Mentor Graphics and its licensors shall not be liable for any claim or demand made against
Customer by any third party, except to the extent such claim is covered under Section 10.
9.2.
In the event that a third party makes a claim against Mentor Graphics arising out of the use of Customers products, Mentor
Graphics will give Customer prompt notice of such claim. At Customers option and expense, Customer may take sole control
of the defense and any settlement of such claim. Customer WILL reimburse and hold harmless Mentor Graphics for any
LIABILITY, damages, settlement amounts, costs and expenses, including reasonable attorneys fees, incurred by or awarded
against Mentor Graphics or its licensors in connection with such claims.
9.3.
The provisions of this Section 9 shall survive any expiration or termination of this Agreement.
10. INFRINGEMENT.
10.1.
Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,
Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Product acquired
by Customer hereunder infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics
will pay costs and damages finally awarded against Customer that are attributable to such action. Customer understands and
agrees that as conditions to Mentor Graphics obligations under this section Customer must: (a) notify Mentor Graphics
promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend the
action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.
10.2.
If a claim is made under Subsection 10.1 Mentor Graphics may, at its option and expense: (a) replace or modify the Product so
that it becomes noninfringing; (b) procure for Customer the right to continue using the Product; or (c) require the return of the
Product and refund to Customer any purchase price or license fee paid, less a reasonable allowance for use.
10.3.
Mentor Graphics has no liability to Customer if the action is based upon: (a) the combination of Software or hardware with any
product not furnished by Mentor Graphics; (b) the modification of the Product other than by Mentor Graphics; (c) the use of
other than a current unaltered release of Software; (d) the use of the Product as part of an infringing process; (e) a product that
Customer makes, uses, or sells; (f) any Beta Code or Product provided at no charge; (g) any software provided by Mentor
Graphics licensors who do not provide such indemnification to Mentor Graphics customers; (h) OSS, except to the extent that
the infringement is directly caused by Mentor Graphics modifications to such OSS; or (i) infringement by Customer that is
deemed willful. In the case of (i), Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs
related to the action.
10.4.
THIS SECTION 10 IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR
GRAPHICS AND ITS LICENSORS, AND CUSTOMERS SOLE AND EXCLUSIVE REMEDY, FOR DEFENSE,
SETTLEMENT AND DAMAGES, WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT
OR TRADE SECRET MISAPPROPRIATION BY ANY PRODUCT PROVIDED UNDER THIS AGREEMENT.
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11.1.
If a Software license was provided for limited term use, such license will automatically terminate at the end of the authorized
term. Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement immediately upon
written notice if Customer: (a) exceeds the scope of the license or otherwise fails to comply with the licensing or confidentiality
provisions of this Agreement, or (b) becomes insolvent, files a bankruptcy petition, institutes proceedings for liquidation or
winding up or enters into an agreement to assign its assets for the benefit of creditors. For any other material breach of any
provision of this Agreement, Mentor Graphics may terminate this Agreement and/or any license granted under this Agreement
upon 30 days written notice if Customer fails to cure the breach within the 30 day notice period. Termination of this Agreement
or any license granted hereunder will not affect Customers obligation to pay for Products shipped or licenses granted prior to
the termination, which amounts shall be payable immediately upon the date of termination.
11.2.
Upon termination of this Agreement, the rights and obligations of the parties shall cease except as expressly set forth in this
Agreement. Upon termination of this Agreement and/or any license granted under this Agreement, Customer shall ensure that
all use of the affected Products ceases, and shall return hardware and either return to Mentor Graphics or destroy Software in
Customers possession, including all copies and documentation, and certify in writing to Mentor Graphics within ten business
days of the termination date that Customer no longer possesses any of the affected Products or copies of Software in any form.
12. EXPORT. The Products provided hereunder are subject to regulation by local laws and European Union (E.U.) and United States
(U.S.) government agencies, which prohibit export, re-export or diversion of certain products, information about the products, and
direct or indirect products thereof, to certain countries and certain persons. Customer agrees that it will not export or re-export Products
in any manner without first obtaining all necessary approval from appropriate local, E.U. and U.S. government agencies. If Customer
wishes to disclose any information to Mentor Graphics that is subject to any E.U., U.S. or other applicable export restrictions, including
without limitation the U.S. International Traffic in Arms Regulations (ITAR) or special controls under the Export Administration
Regulations (EAR), Customer will notify Mentor Graphics personnel, in advance of each instance of disclosure, that such information
is subject to such export restrictions.
13. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. The parties agree that all Software is
commercial computer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to U.S. FAR 48
CFR 12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. government or a U.S.
government subcontractor is subject solely to the terms and conditions set forth in this Agreement, which shall supersede any
conflicting terms or conditions in any government order document, except for provisions which are contrary to applicable mandatory
federal laws.
14. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporation and
other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.
15. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice and during
Customers normal business hours, Mentor Graphics may engage an internationally recognized accounting firm to review Customers
software monitoring system and records deemed relevant by the internationally recognized accounting firm to confirm Customers
compliance with the terms of this Agreement or U.S. or other local export laws. Such review may include FlexNet (or successor
product) report log files that Customer shall capture and provide at Mentor Graphics request. Customer shall make records available in
electronic format and shall fully cooperate with data gathering to support the license review. Mentor Graphics shall bear the expense of
any such review unless a material non-compliance is revealed. Mentor Graphics shall treat as confidential information all information
gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights
under this Agreement. The provisions of this Section 15 shall survive the termination of this Agreement.
16. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of certain Mentor Graphics intellectual
property licensed under this Agreement are located in Ireland and the U.S. To promote consistency around the world, disputes shall be
resolved as follows: excluding conflict of laws rules, this Agreement shall be governed by and construed under the laws of the State of
Oregon, U.S., if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of North or
South America or Japan, and the laws of Japan if Customer is located in Japan. All disputes arising out of or in relation to this
Agreement shall be submitted to the exclusive jurisdiction of the courts of Portland, Oregon when the laws of Oregon apply, or Dublin,
Ireland when the laws of Ireland apply, or the Tokyo District Court when the laws of Japan apply. Notwithstanding the foregoing, all
disputes in Asia (excluding Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a
single arbitrator to be appointed by the chairman of the Singapore International Arbitration Centre (SIAC) to be conducted in the
English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to
be incorporated by reference in this section. Nothing in this section shall restrict Mentor Graphics right to bring an action (including
for example a motion for injunctive relief) against Customer in the jurisdiction where Customers place of business is located. The
United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement.
17. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or
illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect.
18. MISCELLANEOUS. This Agreement contains the parties entire understanding relating to its subject matter and supersedes all prior
or contemporaneous agreements. Any translation of this Agreement is provided to comply with local legal requirements only. In the
event of a dispute between the English and any non-English versions, the English version of this Agreement shall govern to the extent
not prohibited by local law in the applicable jurisdiction. This Agreement may only be modified in writing, signed by an authorized
representative of each party. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver
or excuse.
Rev. 151102, Part No. 265968