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WWW.TESTBENCH.IN - SystemVerilog Constructs
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TUTORIALS
SystemVerilog
INDEX
Verification
............INTRODUCTION
Constructs
............DATA TYPES
..................... Signed And Unsigned
..................... Void
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
............LITERALS
..................... Integer And Logic Literals
..................... Time Literals
..................... Array Literals
..................... Structure Literals
............STRINGS
..................... String Methods
..................... String Pattren Match
..................... String Operators
..................... Equality
..................... Inequality.
..................... Comparison.
..................... Concatenation.
..................... Replication.
..................... Indexing.
............USERDEFINED DATATYPES
............ENUMARATIONS
..................... Enumarated Methods
..................... Enum Numerical Expressions
............STRUCTURES AND UNIOUNS
..................... Structure
..................... Assignments To Struct Members
..................... Union
..................... Packed Structures
............TYPEDEF
..................... Advantages Of Using Typedef
Switch TB
............ARRAYS
..................... Fixed Arrays
RVM Ethernet sample ..................... Operations On Arrays
..................... Accessing Individual Elements Of Multidimensional Arrays
RVM Switch TB
Specman E
Interview Questions
............ARRAY METHODS
..................... Array Methods
..................... Array Querying Functions
..................... Array Locator Methods
..................... Array Ordering Methods
..................... Array Reduction Methods
..................... Iterator Index Querying
............DYNAMIC ARRAYS
..................... Declaration Of Dynmic Array
..................... Allocating Elements
..................... Initializing Dynamic Arrays
..................... Resizing Dynamic Arrays
http://testbench.in/SV_00_INDEX.html[9/26/2012 1:55:53 PM]
Index
Introduction
Data Types
Literals
Strings
Userdefined Datatypes
Enumarations
Structures And Uniouns
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Comparison Of Arrays
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
Report a Bug or Comment
on This section - Your
input is what keeps
Testbench.in improving
with time!
..................... Copying Elements

............ASSOCIATIVE ARRAYS
..................... Associative Array Methods
............QUEUES
..................... Queue Operators
..................... Queue Methods
..................... Dynamic Array Of Queues Queues Of Queues
............COMPARISON OF ARRAYS
..................... Static Array
..................... Associative Array
..................... Dynamic Array
..................... Queues
............LINKED LIST
..................... List Definitions
..................... Procedure To Create And Use List
..................... List_iterator Methods
..................... List Methods
............CASTING
..................... Static Casting
..................... Dynamic Casting
..................... Cast Errors
............DATA DECLARATION
..................... Scope And Lifetime
..................... Global
..................... Local
..................... Alias
..................... Data Types On Ports
..................... Parameterized Data Types
..................... Declaration And Initialization
............REG AND LOGIC
............OPERATORS 1
..................... Operators In Systemverilog
..................... Assignment Operators
..................... Assignments In Expression
..................... Concatenation
..................... Arithmetic
..................... Relational
..................... Equality
............OPERATORS 2
..................... Logical
..................... Bitwise
..................... Reduction
..................... Shift
..................... Increment And Decrement
..................... Set
..................... Streaming Operator
..................... Re-Ordering Of The Generic Stream
..................... Packing Using Streaming Operator
..................... Unpacking Using Streaming Operator
..................... Streaming Dynamically Sized Data

............OPERATOR PRECEDENCY
............EVENTS
..................... Triggered
..................... Wait()
..................... Race Condition
..................... Nonblocking Event Trigger
..................... Merging Events
..................... Null Events
..................... Wait Sequence
..................... Events Comparison
............CONTROL STATEMENTS
..................... Sequential Control
..................... Enhanced For Loop
..................... Unique
..................... Priority
............PROGRAM BLOCK
............PROCEDURAL BLOCKS
..................... Final
..................... Jump Statements
..................... Event Control
..................... Always
............FORK JOIN
..................... Fork Join None
..................... Fork Join Any
..................... For Join All
............FORK CONTROL
..................... Wait Fork Statement
..................... Disable Fork Statement
............SUBROUTINES
..................... Begin End
..................... Tasks
..................... Return In Tasks
..................... Functions
..................... Return Values And Void Functions:
..................... Pass By Reference
..................... Default Values To Arguments
..................... Argument Binding By Name
..................... Optional Argument List
............SEMAPHORE
............MAILBOX
............FINE GRAIN PROCESS CONTROL
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WWW.TESTBENCH.IN - Systemverilog Interface
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TUTORIALS
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DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
INDEX
............INTERFACE
..................... Advantages Of Using Inteface
............PORTS
..................... Interface Ports
..................... Modports
..................... Modport Selection Duing Module Definition.
..................... Modport Selection Duing Module Instance.
............INTERFACE METHODS
..................... Methods In Interfaces
............CLOCKING BLOCK
..................... Clocking Blocks
..................... Skew
..................... Cycle Delay
............VIRTUAL INTERFACE
..................... Virtual Interfaces
..................... Advantages Of Virtual Interface
..................... Multi Bus Interface
............SVTB N VERILOG DUT

..................... Working With Verilog Dut
VMM Ethernet sample ..................... Connecting In Top
..................... Connecting Using A Wrapper
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/IF_00_INDEX.html[9/26/2012 1:56:01 PM]
Index
Interface
Ports
Interface Methods
Clocking Block
Virtual Interface
Svtb N Verilog Dut
input is what keeps
with time!
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WWW.TESTBENCH.IN - Systemverilog OOPS
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TUTORIALS
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Verification
Constructs
Interface
OOPS
Randomization
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Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
INDEX
..................... Brief Introduction To Oop
..................... Class
..................... Object
..................... Methods
..................... Inheritance
..................... Abstraction
..................... Encapsulation
..................... Polymorphism
............CLASS
..................... Class Properties
............OBJECT
..................... Creating Objects
..................... Declaration
..................... Instantiating A Class
..................... Initializing An Object
..................... Constructor
............THIS
..................... Using The This Keyword
AVM Switch TB
............INHERITANCE
VMM Ethernet sample ..................... What You Can Do In A Subclass
..................... Overriding
..................... Super
..................... Is Only Method
Verilog
..................... Is First Method
Verification
..................... Is Also Method
Verilog Switch TB
..................... Overriding Constraints.
..................... Overriding Datamembers
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
............ENCAPSULATION
..................... Access Specifiers
............POLYMORPHISM
............ABSTRACT CLASSES
RVM Ethernet sample ............PARAMETERISED CLASS

..................... Type Parameterised Class
..................... Value Parameterised Class
..................... Generic Parameterised Class
Specman E
..................... Extending Parameterised Class
Interview Questions
............NESTED CLASSES
..................... Why Use Nested Classes
............CONSTANT
..................... Constant Class
..................... Global Constant
..................... Instance Constants
............STATIC
..................... Static Class Properties
http://testbench.in/CL_00_INDEX.html[9/26/2012 1:56:09 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
External Declaration
Classes And Structures
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
..................... Static Methods

..................... Static Lifetime Method.
............CASTING
............COPY
..................... Shallow Copy
..................... Deep Copy
..................... Clone
............SCOPE RESOLUTION OPERATOR
............NULL
............EXTERNAL DECLARATION
............CLASSES AND STRUCTURES
............TYPEDEF CLASS
..................... Forward Reference
..................... Circular Dependency
............PURE
............OTHER OOPS FEATURES
..................... Multiple Inheritence
..................... Method Overloading
............MISC
..................... Always Block In Classes
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WWW.TESTBENCH.IN - Systemverilog Randomization
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TUTORIALS
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Randomization
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
INDEX
............CONSTRAINED RANDOM VERIFICATION
..................... Introduction
............VERILOG CRV
..................... Constrained Random Stimulus Generation In Verilog
............SYSTEMVERILOG CRV
..................... Systemverilog Constraint Random Stmulus Generaion
..................... Random Number Generator System Functions
..................... $Urandom_range
..................... Scope Randomize Function
..................... Randomizing Objects
..................... Random Unpacked Structs
..................... Rand Case
..................... Rand Sequence
............RANDOMIZING OBJECTS
..................... Generating Random Stimulus Within Class
............RANDOM VARIABLES
..................... Random Varible Declaration
..................... Rand Modifier
..................... Randc Modifier
VMM Ethernet sample ............RANDOMIZATION METHODS

..................... Randomization Built-In Methods
..................... Randomize()
..................... Pre_randomize And Post_randomize
Verilog
..................... Disabling Random Variable
Verification
..................... Random Static Variable
Verilog Switch TB
..................... Randomizing Nonrand Varible
Basic Constructs
............CHECKER
OpenVera
Constructs
Switch TB
RVM Switch TB
............CONSTRAINT BLOCK
..................... Inheritance
..................... Overrighting Constraints
............INLINE CONSTRAINT
RVM Ethernet sample ............GLOBAL CONSTRAINT
Specman E
Interview Questions
............CONSTRAINT MODE
..................... Disabling Constraint Block
............EXTERNAL CONSTRAINTS
..................... Constraint Hiding
............RANDOMIZATION CONTROLABILITY
..................... Controlability
............STATIC CONSTRAINT
............CONSTRAINT EXPRESSION
..................... Set Membership
..................... Weighted Distribution
http://testbench.in/CR_00_INDEX.html[9/26/2012 1:56:18 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Randomization Methods
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
External Constraints
Randomization
Controlability
Static Constraint
Constraint Expression
Variable Ordering
Constraint Solver Speed
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
..................... Implication
..................... If..Else
............VARIABLE ORDERING
..................... Functions
..................... Iterative Constraints
............CONSTRAINT SOLVER SPEED
............RANDCASE
............RANDSEQUENCE
..................... Random Productions
..................... Random Production Weights
..................... If..Else
..................... Case
..................... Repeat Production Statements
..................... Rand Join
..................... Break
..................... Return
..................... Value Passing Between Productions
............RANDOM STABILITY
..................... Srandom
............ARRAY RANDOMIZATION
............CONSTRAINT GUARDS
............TITBITS
..................... Constraining Non Integral Data Types
..................... Saving Memory
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WWW.TESTBENCH.IN - SystemVerilog Functional Coverage
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TUTORIALS
SystemVerilog
Verification
Constructs
INDEX
..................... Systemverilog Functional Coverage Features
Interface
............COVER GROUP
OOPS
............SAMPLE
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
............COVER POINTS
..................... Commands To Simulate And Get The Coverage Report
............COVERPOINT EXPRESSION
..................... Coverpoint Expression
..................... Coverage Filter
............GENERIC COVERAGE GROUPS
............COVERAGE BINS
..................... Implicit Bins
............EXPLICIT BIN CREATION
..................... Array Of Bins
..................... Default Bin
AVM Switch TB
............TRANSITION BINS
VMM Ethernet sample ..................... Single Value Transition
..................... Sequence Of Transitions
..................... Set Of Transitions
..................... Consecutive Repetitions
Verilog
..................... Range Of Repetition
Verification
..................... Goto Repetition
Verilog Switch TB
..................... Non Consecutive Repetition
Basic Constructs
............WILDCARD BINS
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
............IGNORE BINS
............ILLEGAL BINS
............CROSS COVERAGE
..................... User-Defined Cross Bins
............COVERAGE OPTIONS
..................... Weight
..................... Goal
..................... Name
..................... Comment
..................... At_least
..................... Detect_overlap
..................... Auto_bin_max
..................... Cross_num_print_missing
..................... Per_instance
..................... Get_inst_coverage
............COVERAGE METHODS
............SYSTEM TASKS
http://testbench.in/CO_00_INDEX.html[9/26/2012 1:56:27 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverpoint Expression
Generic Coverage Groups
Coverage Bins
Explicit Bin Creation
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
............COVER PROPERTY
..................... Cover Property Results
..................... Cover Sequence Results
..................... Comparison Of Cover Property And Cover Group.
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WWW.TESTBENCH.IN - System Verilog Assertion - SVA
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INDEX
..................... Advantages Of Assertion
..................... What Assertions Can Verify
............EVENT SIMULATION
............ASSERTION TYPES
............ASSERTION SYSTEM TASKS
..................... Assertion Control System Tasks
..................... Boolean System Function
............CONCURRENT ASSERTION LAYERS
..................... Boolean Expressions
OVM Tutorial
............SEQUENCES
..................... Fixed Delay
Easy Labs : SV
..................... Zero Delay
Easy Labs : UVM
..................... Constant Range Delay
..................... Unbounded Delay Range
Easy Labs : OVM
..................... Repetation Operators
Easy Labs : VMM
..................... Consecutive Repetition
..................... Goto Repetition
AVM Switch TB
..................... Nonconsecutive Repetition
VMM Ethernet sample ..................... Sequence And
..................... Sequence Or
..................... Sequence Intersect
..................... Sequence Within
Verilog
..................... Sequence First_match
Verification
..................... Sequence Throughout
Verilog Switch TB
..................... Sequence Ended
..................... Operator Precedence Associativy
Basic Constructs
OpenVera
Constructs
............PROPERTIES
..................... Overlap Implication
..................... Non Overlapping Implication
............VERIFICATION DIRECTIVE
..................... Assert
RVM Switch TB
..................... Assume
RVM Ethernet sample ..................... Cover Statement
..................... Expect Statement
..................... Binding
Switch TB
Specman E
Interview Questions
http://testbench.in/AS_00_INDEX.html[9/26/2012 1:56:34 PM]
Index
Introduction
Event Simulation
Assertion Types
Assertion System Tasks
Concurrent Assertion
Layers
Sequences
Properties
Verification Directive
input is what keeps
with time!
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WWW.TESTBENCH.IN - Systemverilog DPI
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
INDEX
............INTRODUCTIONS
..................... What Is Dpi-C ?
............LAYERS
..................... Two Layers Of Dpi-C
..................... Dpi-C Systemverilog Layer
..................... Dpi-C Foreign Language Layer
............IMPORT
..................... Import Methods
..................... Steps To Write Import Metyhods
..................... Standard C Functions
............NAMING
..................... Global Name
..................... Local Name
..................... Sv Keyword As Linkage Name
............EXPORT
..................... Export Methods
..................... Steps To Write Export Methods
..................... Blocking Export Dpi Task
AVM Switch TB
............PURE AND CONTEXT

VMM Ethernet sample ..................... Pure Function
..................... Context Function
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
..................... Passing Logic Datatype
............ARRAYS
..................... Open Arrays
..................... Packed Arrays
..................... Linearized And Normalized
............PASSING STRUCTS AND UNIONS
..................... Passing Structure Example
..................... Passing Openarray Structs
..................... Passing Union Example
............ARGUMENTS TYPE
..................... What You Specify Is What You Get
..................... Pass By Ref
..................... Pass By Value
..................... Passing String
..................... Example Passing String From Sv To C
..................... Example Passing String From C To Sv
............DISABLIE
..................... Disable Dpi-C Tasks And Functions
..................... Include Files
http://testbench.in/DP_00_INDEX.html[9/26/2012 1:56:42 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
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WWW.TESTBENCH.IN
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TUTORIALS
VMM Ethernet
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
This testbench is developed in VMM (Systemverilog) for the Ethernet core available from opencores.org. My
intension here is to explore the VMM methodology but not to verify the Ethernet core, as a result there are many
bugs in the environment. I dont remember the versions of VMM but I developed these in the third quarter of 2007.
To simulate this testbench some dependencies on libraries has to be removed from RTL files. It takes bit time for
these changes in RTL.
Feauters:
Full support of automatic random, constrained random, and directed testcase creation.
Supports injuction of random errored packets.
Supports 1G Fullduplex modeled both in RX and TX paths.
Protocol Checker/Monitor for self checking.
Built in function coverage support for packets.
Developed in Systemverilog using Synopsys VMM base classes.
NOTE: All trademarks are the property of their respective owners.
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Download vmm.tar
Browse the code in vmm_eth.tar
BLOCK DIAGRAM OF ETHERNET VERIFICATION ENVIRONMENT
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/ethernet_vmm.html[9/26/2012 1:56:49 PM]
WWW.TESTBENCH.IN
http://testbench.in/ethernet_vmm.html[9/26/2012 1:56:49 PM]
WWW.TESTBENCH.IN - Systemverilog for Verification
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Verification
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Interface
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Randomization
Functional Coverage
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DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
INDEX
............ASIC DESIGN
..................... Mrd
..................... Architecture Specification
..................... Design Specification
..................... Verification Plan
..................... Rtl Design
..................... Functional Verification
..................... Synthesis
..................... Physical Design
..................... Timing Analysis
..................... Tapeout
............BOTTLE NECK IN ASIC FLOW
............FUNCTIONAL VERIFICATION NEED
Easy Labs : SV
............TESTBENCH
Easy Labs : UVM
............LINEAR TESTBENCH
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
............LINEAR RANDOM TESTBENCH

............HOW TO CHECK THE RESULTS
VMM Ethernet sample ............SELF CHECKING TESTBENCHS
Verilog
Verification
Verilog Switch TB
Basic Constructs
............HOW TO GET SCENARIOS WHICH WE NEVER THOUGHT

............HOW TO CHECK WHETHER THE TESTBENCH HAS SATISFACTORILY EXERCISED
THE DESIGN
............TYPES OF CODE COVERAGE

............STATEMENT COVERAGE
OpenVera
Constructs
............BLOCK COVERAGE
Switch TB
............CONDITIONAL COVERAGE
RVM Switch TB
............BRANCH COVERAGE
RVM Ethernet sample
Specman E
Interview Questions
............PATH COVERAGE
............TOGGLE COVERAGE
............FSM COVERAGE
..................... State Coverage
..................... Transition Coverage
............MAKE YOUR GOAL 100 PERCENT CODE COVERAGE NOTHING LESS
..................... Dont Be Fooled By The Code Coverage Report
..................... When To Stop Testing?
............FUNCTIONAL COVERAGE
..................... Introduction To Functional Coverage
..................... Item
http://testbench.in/TS_00_INDEX.html[9/26/2012 1:56:57 PM]
Index
Asic Design
Bottle Neck In Asic Flow
Functional Verification
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
Self Checking Testbenchs
How To Get Scenarios
Which We Never Thought
How To Check Whether
The Testbench Has
Satisfactorily Exercised
The Design
Types Of Code Coverage
Statement Coverage
Block Coverage
Conditional Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Percent Code Coverage
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Architecture
Phases Of Verification
Ones Counter Example
Verification Plan
input is what keeps
with time!
..................... Cross
..................... Transitional
..................... Assertion Coverage
............COVERAGE DRIVEN CONSTRAINT RANDOM VERIFICATION ARCHITECTURE
..................... Verification Components Required For Cdcrv
..................... Stimulus
..................... Stimulus Generator
..................... Transactor
..................... Driver
..................... Monitor
..................... Assertion Based Monitor
..................... Data Checker
..................... Scoreboard
..................... Coverage
..................... Utilities
..................... Environment
..................... Tests
............PHASES OF VERIFICATION
..................... Building Testbench
..................... Writing Tests
..................... Integrating Code Coverage
..................... Analyze Coverage
............ONES COUNTER EXAMPLE
..................... Specification
..................... Test Plan
..................... Block Diagram
..................... Verification Environment Hierarchy
..................... Testbench Components
..................... Stimulus
..................... Driver
..................... Monitor
..................... Scoreboard
..................... Environment
..................... Top
..................... Tests
............VERIFICATION PLAN
..................... Verification Plan Contains The Following
..................... Overview
..................... Feature Extraction
..................... Resources, Budget And Schedule
..................... Verification Environment
..................... System Verilog Verification Flow
..................... Stimulus Generation Plan
..................... Checker Plan
..................... Coverage Plan
..................... Details Of Reusable Components
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WWW.TESTBENCH.IN - UVM Tutorial
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TUTORIALS
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
INDEX
..................... Installing Uvm Library
............UVM TESTBENCH
..................... Uvm_env
..................... Verification Components
..................... About Uvm_component Class
..................... Uvm_test
..................... Top Module
............UVM REPORTING
..................... Reporting Methods
..................... Actions
..................... Configuration
............UVM TRANSACTION
..................... Core Utilities
..................... User Defined Implementations
..................... Shorthand Macros
Easy Labs : OVM
............UVM CONFIGURATION
..................... Set_config_* Methods
..................... Automatic Configuration
AVM Switch TB
..................... Manual Configurations
VMM Ethernet sample ..................... Configuration Setting Members
Easy Labs : VMM
Verilog
Verification
Verilog Switch TB
............UVM FACTORY
..................... Registration
..................... Construction
..................... Overriding
............UVM SEQUENCE 1
..................... Introduction
..................... Sequence And Driver Communication
..................... Simple Example
OpenVera
..................... Sequence Item
Constructs
..................... Sequence
..................... Sequencer
Switch TB
..................... Driver
RVM Switch TB
..................... Driver And Sequencer Connectivity
RVM Ethernet sample ..................... Testcase
Basic Constructs
Specman E
Interview Questions
..................... Pre Defined Sequences
..................... Sequence Action Macro
..................... Example Of Pre_do,Mid_do And Post_do
..................... List Of Sequence Action Macros
..................... Examples With Sequence Action Macros
..................... Body Callbacks
..................... Hierarchical Sequences
..................... Sequential Sequences
..................... Parallel Sequences
http://testbench.in/UT_00_INDEX.html[9/26/2012 1:57:04 PM]
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
..................... Sequencer Arbitration

..................... Setting The Sequence Priority
..................... Sequencer Registration Macros
..................... Setting Sequence Members
..................... Exclusive Access
..................... Lock-Unlock
..................... Grab-Ungrab
............UVM TLM 1
..................... Port Based Data Transfer
..................... Task Based Data Transfer
..................... Operation Supported By Tlm Interface
..................... Methods
..................... Tlm Terminology
..................... Tlm Interface Compilation Models
..................... Interfaces
..................... Direction
..................... All Interfaces In Uvm
............UVM TLM 2
..................... Analysis
..................... Tlm Fifo
..................... Example
............UVM CALLBACK
..................... Driver And Driver Callback Class Source Code
..................... Testcase Source Code
..................... Testcase 2 Source Code
..................... Methods
..................... Macros
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WWW.TESTBENCH.IN - VMM Tutorial
Search
TUTORIALS
SystemVerilog
INDEX
Verification
Constructs
............VMM LOG
..................... Vmm Message Type
..................... Message Severity
..................... Vmm Log Macros
..................... Message Handling
..................... Counting Number Of Messages Based Of Message Severity
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
............VMM ENV
............VMM DATA
..................... Complete Packet Class
..................... Vmm_data Methods
............VMM CHANNEL
..................... Complete Example
..................... Vmm Channel Methods.
............VMM ATOMIC GENERATOR
..................... Completed Example
............VMM XACTOR
..................... Complete Vmm_xactor Example
VMM Ethernet sample ..................... Vmm_xactor Members
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
............VMM CALLBACK
..................... Complete Source Code
............VMM TEST
..................... Writing A Testcase
..................... Example Of Using Vmm_test
............VMM CHANNEL RECORD AND PLAYBACK
..................... Recording
..................... Playing Back
............VMM SCENARIO GENERATOR
..................... Example
..................... Scenario Code
..................... Testcase
............VMM OPTS
http://testbench.in/VM_00_INDEX.html[9/26/2012 1:57:13 PM]
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Atomic Generator
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Scenario Generator
Vmm Opts
input is what keeps
with time!
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WWW.TESTBENCH.IN - OVM Tutorial
Search
TUTORIALS
SystemVerilog
INDEX
Verification
Constructs
............OVM TESTBENCH
..................... Ovm_env
..................... About Ovm_component Class
..................... Ovm_test
..................... Top Module
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
............OVM REPORTING
..................... Actions
..................... Configuration
............OVM TRANSACTION
..................... Core Utilities
............OVM FACTORY
..................... Registration
..................... Construction
..................... Overriding
VMM Ethernet sample ............OVM SEQUENCE 1

..................... Introduction
..................... Simple Example
Verilog
..................... Sequence Item
Verification
..................... Sequence
Verilog Switch TB
..................... Sequencer
..................... Driver
Basic Constructs
..................... Testcase
OpenVera
............OVM SEQUENCE 2
Switch TB
RVM Switch TB
RVM Ethernet sample ..................... Examples With Sequence Action Macros
Constructs
Specman E
Interview Questions
..................... Body Callbacks
http://testbench.in/OT_00_INDEX.html[9/26/2012 1:57:21 PM]
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
..................... Lock-Unlock
..................... Grab-Ungrab
............OVM CONFIGURATION
..................... Configuration Setting Members
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WWW.TESTBENCH.IN - Easy Labs : SV
Search
TUTORIALS
SystemVerilog
INDEX
Verification
Constructs
............SPECIFICATION
..................... Switch Specification
..................... Packet Format
..................... Packet Header
..................... Configuration
..................... Interface Specification
..................... Memory Interface
..................... Input Port
..................... Output Port
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
..................... Overview
..................... Coverage Plan
............PHASE 1 TOP
..................... Interfaces
..................... Testcase
..................... Top Module
..................... Top Module Source Code
Verification
............PHASE 2 ENVIRONMENT
..................... Environment Class
..................... Run
..................... Environment Class Source Code
Verilog Switch TB
............PHASE 3 RESET
Verilog
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
............PHASE 4 PACKET
..................... Packet Class Source Code
..................... Program Block Source Code
............PHASE 5 DRIVER
..................... Driver Class Source Code
RVM Ethernet sample ............PHASE 6 RECEIVER

..................... Receiver Class Source Code
Specman E
Interview Questions
............PHASE 7 SCOREBOARD
..................... Scoreboard Class Source Code
..................... Source Code Of The Environment Class
............PHASE 8 COVERAGE
..................... Source Code Of Coverage Class
..................... Source Code Of The Scoreboard Class
............PHASE 9 TESTCASE
..................... Source Code Of Constraint Testcase
http://testbench.in/SL_00_INDEX.html[9/26/2012 1:57:28 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Driver
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
input is what keeps
with time!
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WWW.TESTBENCH.IN - Easy Labs : UVM
Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
INDEX
..................... Packet Format
..................... Configuration
..................... Overview
............PHASE 1 TOP
..................... Interface
..................... Top Module
............PHASE 2 CONFIGURATION
..................... Configuration
..................... Updates To Top Module
AVM Switch TB
............PHASE 3 ENVIRONMENT N TESTCASE

VMM Ethernet sample ..................... Environment
..................... Testcase
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
..................... Packet
..................... Test The Transaction Implementation
............PHASE 5 SEQUENCER N SEQUENCE
..................... Sequencer
..................... Sequence
..................... Driver
..................... Environment Updates
..................... Testcase Updates
RVM Ethernet sample ............PHASE 7 RECEIVER

..................... Receiver
..................... Environment Class Updates
Specman E
Interview Questions
..................... Scoreboard
http://testbench.in/UL_00_INDEX.html[9/26/2012 1:57:36 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Configuration
Phase 3 Environment N
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
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WWW.TESTBENCH.IN - Easy Labs : OVM
Search
TUTORIALS
SystemVerilog
INDEX
Verification
Constructs
..................... Packet Format
..................... Configuration
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
..................... Overview
............PHASE 1 TOP
..................... Interface
..................... Top Module
............PHASE 2 CONFIGURATION
..................... Configuration
............PHASE 3 ENVIRONMENT N TESTCASE

..................... Environment
VMM Ethernet sample ..................... Testcase
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
..................... Packet
............PHASE 5 SEQUENCER N SEQUENCE
..................... Sequencer
..................... Sequence
..................... Driver
RVM Switch TB
............PHASE 7 RECEIVER
RVM Ethernet sample ..................... Receiver
Specman E
Interview Questions
..................... Scoreboard
http://testbench.in/CM_00_INDEX.html[9/26/2012 1:57:46 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
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WWW.TESTBENCH.IN - Easy Labs : VMM
Search
TUTORIALS
SystemVerilog
INDEX
Verification
Constructs
..................... Packet Format
..................... Configuration
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
..................... Overview
..................... Coverage Plan
............PHASE 1 TOP
..................... Interfaces
..................... Testcase
..................... Top Module
Easy Labs : VMM
............PHASE 2 ENVIRONMENT
..................... Run
VMM Ethernet sample ..................... Environment Class Source Code
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
............PHASE 3 RESET
............PHASE 5 GENERATOR
RVM Switch TB
............PHASE 7 RECEIVER
RVM Ethernet sample ..................... Receiver Class Source Code
Specman E
Interview Questions
............PHASE 9 COVERAGE
http://testbench.in/VL_00_INDEX.html[9/26/2012 1:57:53 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
input is what keeps
with time!
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WWW.TESTBENCH.IN - AVM Switch TB
Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
INDEX
............AVM INTRODUCTION
..................... Tlm
..................... Building Blocks
..................... Avm_transactors
..................... Avm_env
..................... Avm_messaging
............DUT SPECIFICATION
..................... Configuration
..................... Input Interface
..................... Output Interface
............RTL
............TOP
..................... Verilog Top
Easy Labs : OVM
Easy Labs : VMM
............ENVIRONMENT
AVM Switch TB
VMM Ethernet sample
............PACKET
............PACKET GENERATOR
Verilog
Verification
Verilog Switch TB
Basic Constructs
............CONFIGURATION
............DRIVER
............RECIEVER
............SCOREBOARD
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/AV_00_INDEX.html[9/26/2012 1:58:01 PM]
Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard
input is what keeps
with time!
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WWW.TESTBENCH.IN - Verilog for Verification
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
INDEX
..................... Test Bench Overview
............LINEAR TB
..................... Linear Testbench
............FILE IO TB
..................... File I/O Based Testbench
............STATE MACHINE BASED TB
............TASK BASED TB
..................... Task And Function Based Tb
VMM Tutorial
............SELF CHECKING TESTBENCH

..................... Bus Functional Models
Easy Labs : SV
..................... Driver
Easy Labs : UVM
..................... Reciver
..................... Protocol Monitor
Easy Labs : OVM
..................... Scoreboard
Easy Labs : VMM
..................... Checker
..................... Coverage
AVM Switch TB
..................... Code Coverage
VMM Ethernet sample ..................... Functional Coverage
OVM Tutorial
Verilog
Verification
Verilog Switch TB
Basic Constructs
............VERIFICATION FLOW
..................... Planning
..................... Verification Environment Architecture Plan
............CLOCK GENERATOR
..................... Timescale And Precision Enlightment
............SIMULATION
..................... Simulation Steps
Constructs
..................... Macro Preprocessing
..................... Compilation (Analyzer)
Switch TB
..................... Elaboration
RVM Switch TB
..................... Optimization
RVM Ethernet sample ..................... Initialization
..................... Execution
..................... Simulation Process
OpenVera
Specman E
Interview Questions
............INCREMENTAL COMPILATION
............STORE AND RESTORE
............EVENT CYCLE SIMULATION
..................... Event Based Simulation
..................... Cycle Based Simulation
............TIME SCALE AND PRECISION
..................... Time Scale And Time Precision
..................... $Time Vs $Realtime
..................... System Task Printtimescale
http://testbench.in/TB_00_INDEX.html[9/26/2012 1:58:09 PM]
Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random
A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips
input is what keeps
with time!
..................... System Task Timeformat

............STIMULUS GENERATION
............SYSTEM FUNCTION RANDOM A MYTH
............RACE CONDITION
..................... What Is Race Condition?
..................... Why Race Condition?
..................... When Race Is Visible?
..................... How To Prevent Race Condition?
..................... Types Of Race Condition
..................... Write-Write Race
..................... Read-Write Race
..................... More Race Example
..................... Event Terminology
..................... The Stratified Event Queue
..................... Determinism
..................... Nondeterminism
..................... Guideline To Avoid Race Condition
..................... Avoid Race Between Testbench And Dut
............CHECKER
..................... Protocol Checker
..................... Data_checker
..................... Modularization
............TASK AND FUNCTION
..................... Functions
..................... Task
..................... Task And Function Queries
..................... Constant Function
..................... Reentrant Tasks And Functions
............PROCESS CONTROL
..................... Nonblocking Task
..................... Fork/Join Recap
..................... Fork/Join None
..................... Fork/Join Any
............DISABLEING THE BLOCK
..................... Disable
..................... Goto
..................... Break
..................... Continue
............WATCHDOG
............COMPILATION N SIMULATION SWITCHS
..................... Compilation And Simulation Directives
..................... Example
............DEBUGGING
..................... Pass Or Fail
..................... Waveform Viewer
..................... Log File
..................... Message Control System
..................... Message Severity Levels
..................... Message Controlling Levels
..................... Passing Comments To Waveform Debugger
..................... $Display N $Strobe
..................... Who Should Do The Rtl Debugging?
............ABOUT CODE COVERAGE
..................... Types Of Coverage

..................... Code Coverage
..................... Statement Coverage /Line Coverage
..................... Block/Segment Coverage
..................... Branch / Decision / Conditional Coverage
..................... Path Coverage
..................... Expression Coverage
..................... Toggle Coverage
..................... Variable Coverage
..................... Triggering / Event Coverage
..................... Parameter Coverage
..................... Functional Coverage
..................... Fsm Coverage
..................... State Coverage
..................... Sequence Coverage
..................... Tool Support
..................... Limitation Of Code Coverage
............TESTING STRATIGIES
..................... Bottom-Up
..................... Unit Level
..................... Sub-Asic Level
..................... Asic Level
..................... System Level
..................... Flat
............FILE HANDLING
..................... Fopen And Fclose
..................... Fdisplay
..................... Fmonitor
..................... Fwrite
..................... Mcd
..................... Formating Data To String
............VERILOG SEMAPHORE
..................... Semaphore In Verilog
............FINDING TESTSENARIOUS
..................... Register Tests
..................... System Tests
..................... Interrupt Tests
..................... Interface Tests
..................... Functional Tests
..................... Error Tests
..................... Golden Tests
..................... Performance Tests
............HANDLING TESTCASE FILES
............TERIMINATION
............ERROR INJUCTION
..................... Value Errors
..................... Temporal Errors
..................... Interface Error
..................... Sequence Errors
............REGISTER VERIFICATION
..................... Register Verification
..................... Register Classification
..................... Features
............PARAMETERISED MACROS
............WHITE GRAY BLACK BOX
..................... Black Box Verification
..................... White Box Verification
..................... Gray Box Verification
............REGRESSION
............TIPS
..................... How To Avoid "Module Xxx Already Defined" Error
..................... Colourful Messages

..................... Debugging Macros
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TUTORIALS
SystemVerilog
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Interface
OOPS
Randomization
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Assertion
DPI
UVM Tutorial
INDEX
..................... Configuration
..................... Input Interface
............RTL
............TOP
..................... Top Module
VMM Tutorial
............PACKET
OVM Tutorial
............DRIVER
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
............ENV
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/VS_00_INDEX.html[9/26/2012 1:58:17 PM]
Index
Dut Specification
Rtl
Top
Packet
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
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WWW.TESTBENCH.IN - Verilog Basic Constructs
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TUTORIALS
SystemVerilog
Verification
Constructs
INDEX
..................... Introduction
Interface
............SYNTAX
OOPS
..................... Value Set
..................... Net
..................... Variable Or Reg
..................... Vectors
..................... Memories
..................... Net Types
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
............OPERATORS
..................... Binary Arithmetic Operators
..................... Unary Arithmetic Operators
..................... Relational Operators
..................... Logical Operators
..................... Bitwise Operators
..................... Unary Reduction Operators
..................... Other Operators
..................... Operator Precedence
AVM Switch TB
............ASSIGNMENTS
VMM Ethernet sample ..................... Blocking Procedural Assignments
..................... The Nonblocking Procedural Assignment
..................... Procedural Continuous Assignments
..................... Assign And Deassign Procedural Statements
Verilog
..................... Force And Release Procedural Statements
Verification
..................... Delays
Verilog Switch TB
..................... Inter Assignmnet Delay .
..................... Intra-Assignment Delay Control
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
............CONTROL CONSTRUCTS
..................... If And If Else Statements
..................... Case
..................... Forever
..................... Repeat
..................... While
..................... For
............PROCEDURAL TIMING CONTROLS
..................... Delay Control
..................... Event Control
..................... Named Events
............STRUCTURE
..................... Module
..................... Ports
..................... Signals
............BLOCK STATEMENTS
..................... Sequential Blocks
..................... Parallel Blocks
............STRUCTURED PROCEDURES
http://testbench.in/VT_00_INDEX.html[9/26/2012 1:58:27 PM]
Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
Structured Procedures
input is what keeps
with time!
..................... Initial
..................... Always
..................... Functions
..................... Task
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WWW.TESTBENCH.IN - Vera Constructs
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TUTORIALS
SystemVerilog
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Randomization
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Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
INDEX
..................... Introduction
..................... Comments In Openvera
..................... Numbers In Openvera
..................... Basic Data Types
..................... Integer
..................... Register
..................... String
..................... Event
..................... Enumerated Types
..................... Virtual Ports
..................... Arrays
..................... Fixed-Size Arrays
..................... Dynamic Arrays
..................... Associative Arrays
..................... Smart Queues
..................... Class
............LINKED LIST
..................... Linked List
..................... List Methods
VMM Ethernet sample ............OPERATORS PART 1

..................... Operators
..................... Concatenation
..................... Arithmetic
Verilog
..................... Relational
Verification
..................... Equality
Verilog Switch TB
............OPERATORS PART 2
Basic Constructs
..................... Logical
..................... Bitwise
..................... Reduction
OpenVera
Constructs
............OPERATORS PART 3
..................... Shift
..................... Bit-Reverse
RVM Switch TB
RVM Ethernet sample ..................... Conditional
..................... Set
..................... Replication
Switch TB
Specman E
Interview Questions
............OPERATOR PRECEDENCE
............CONTROL STATEMENTS
..................... Sequential Statements
............PROCEDURES AND METHODS
..................... Procedures And Methods
..................... Pass By Value
..................... Default Arguments
..................... Optional Arguments
http://testbench.in/OV_00_INDEX.html[9/26/2012 1:58:37 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Procedures And Methods
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
............INTERPROCESS
..................... Interprocess Synchronization And Communication
............FORK JOIN
..................... Fork Join
............SHADOW VARIABLES
..................... Shadow Variables
............FORK JOIN CONTROL
..................... Fork And Join Control
..................... Wait_chiled()
..................... Terminate
..................... Suspend_thread
............WAIT VAR
..................... Wait_var
............EVENT SYNC
..................... Event Methods
............EVENT TRIGGER
..................... Event Trigger
..................... Event Variables
............SEMAPHORE
..................... Semaphore
............REGIONS
..................... Regions
............MAILBOX
..................... Mailbox
............TIMEOUTS
..................... Timeouts
............OOP
..................... Object Oriented Programming
..................... Properties
..................... This
..................... Class Extensions
..................... Polymorphism
..................... Super
..................... Abstract Class
............CASTING
............RANDOMIZATION
..................... Constrained Random Verification
..................... Rand Modifier
..................... Randc Modifier
............RANDOMIZATION METHODS
..................... Randomize()
............CONSTRAINT BLOCK
..................... Constraint Block
..................... Inline Constraints
............CONSTRAINT EXPRESSION
..................... Constraint Expressions
..................... Set Membership
..................... Implication
..................... If..Else
..................... Iterative
............VARIABLE ORDARING
..................... Variable Ordaring
............AOP
..................... Aspect Oriented Extensions
............PREDEFINED METHODS
..................... Predefined Methods
..................... New()
..................... Finalize()
..................... Object_print
..................... Deep Object Compare
..................... Deep Object Copy
..................... Pack And Unpack
............STRING METHODS
............QUEUE METHODS
............DUT COMMUNICATION
..................... Connecting To Hdl
..................... Interface Declaration
..................... Direct Hdl Node Connection
..................... Blocking And Non-Blocking Drives
............FUNCTIONAL COVERAGE
..................... Coverage Group
..................... Sample_event
..................... Coverage_point
..................... Cross Coverage
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SystemVerilog
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Interface
OOPS
Randomization
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Assertion
DPI
UVM Tutorial
INDEX
..................... Configuration
..................... Input Interface
............RTL
............TOP
..................... Top Module
VMM Tutorial
OVM Tutorial
............PACKET
Easy Labs : SV
Easy Labs : UVM
............PACKET GENERATOR
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............CFG DRIVER
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..................... Dut Specification
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............PROGRAM BLOCK
..................... Testbench Program
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This testbench is developed in RVM (Vera) for the Ethernet core available from opencores.org. My intension here is
to explore the RVM methodology but not to verify the Ethernet core, as a result there are many bugs in the
environment. I dont remember the versions of RVM but I developed these in the third quarter of 2007. To simulate
this testbench some dependencies on libraries has to be removed from RTL. It takes bit time for these changes in
RTL.
Feauters:
Full support of automatic random, constrained random, and directed testcase creation.
Supports injuction of random errored packets.
Supports 1G Fullduplex modeled both in RX and TX paths.
Protocol Checker/Monitor for self checking.
Built in function coverage support for packets.
Developed in Vera using Synopsys RVM base classes.
NOTE: All trademarks are the property of their respective owners.
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BLOCK DIAGRAM OF ETHERNET VERIFICATION ENVIRONMENT
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This example contains VMM 1.2 based layered testbench architeracture. My intensation here is to demonstrate
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VMM Ethernet sample Whats new in Systemverilog 2009 ? by Ankit Shah.
Verilog
The SystemVerilog working group worked hard in the past four years on improving the language and in 2009
Systemverilog LRM was released. There are 30+ noticeable new constructs and 25+ system task are introduced in
SystemVerilog 2009. Read ...
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Introduction To Ethernet Frames: Part 1 by Bhavani shankar.

The Ethernet protocol basically implements the bottom two layers of the Open Systems Interconnection (OSI) 7layer model, i.e., the data link and physical sub layers. Read ...
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Introduction To Ethernet Frames: Part 2 by Bhavani shankar.

we will see a simple testplan for 10G Ethernet Frames. Read ...
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Introduction To PCI Express by Arjun Shetty.

We will start with a conceptual understanding of PCI Express. This will let us appreciate the importance of PCI
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and improvements of the protocol in the newer 3.0 specs. Read ...
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Graphical TestBench Generation by Donna Mitchell.

Test Benches can be generated from language independent timing diagrams, which are a natural way to design and
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Verilog examples with output: and,or,not,halfadder,fulladder etc Read ...
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............OPERATORS
..................... Unary Bitwise Operators
..................... Binary Bitwise Operations
..................... Shift Operators
..................... Boolean Operators
..................... Arithmetic Operators
..................... Comparison Operators
..................... Extraction And Concatenation Operators
..................... Special-Purpose Operators
............STRUCT
VMM Ethernet sample ............UNITS
..................... Units Vs Structs
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............LIST
..................... Regular List
..................... List Operations
..................... Keyed List
............METHODS
..................... Time-Consuming Methods(Tcms)
..................... Invoking Tcms
..................... Execution Flow
............Concurrency Actions
..................... All Of
..................... First Of
............CONSTRAINTS
............EXTEND
..................... Is Also
..................... Is First
..................... Is Only
............When and Like
..................... Like
..................... When
............EVENTS
............TEMPORAL EXPRESSIONS
..................... Basic Temporal Expressions
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Commands
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Non Extendable Methods
And Gate Evc
input is what keeps
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..................... Temporal Checking

............Temporal operators 1
..................... Not
..................... Fail
..................... And
..................... Or
..................... { Exp ; Exp }
..................... Eventually
..................... [ Exp ]
..................... [ Exp..Exp ]
..................... ~[ Exp..Exp ]
..................... Temporal Yield Operator
............TEMPORAL OPERATORS 2
..................... Detach
..................... Delay
..................... @ Unary Event Operator
..................... @ Sampling Operator
..................... Cycle
..................... True(Exp)
..................... Change(Exp), Fall(Exp), Rise(Exp)
..................... Consume
..................... Exec
............SYNCHRONIZING WITH THE SIMULATOR
............WAIT AND SYNC
..................... Wait Action
..................... Sync Action
..................... Difference Between Wait And Sync
............PHYSICAL VIRUAL FEILDS
..................... Physical Fields
..................... Ungenerated Fields
............PACKING N UNPACKING
..................... Packing.High
..................... Packing.Low
............PRE RUN N ON THE FLY
..................... Pre-Run Generation
..................... On-The-Fly Generation
............COVERAGE
..................... Coverage Groups
..................... Cover Group Options
..................... Cross-Coverage
............COMMANDS
............Extendable Methods
............Non Extendable Methods

............AND GATE EVC
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............TEST YOUR SYSTEMVERILOG SKILLS 1

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RVM Ethernet sample ............TEST YOUR VERILOG SKILLS 14

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He is working with Infinera as Verification Engineer. He has 4 years of experience as ASIC Design Verification
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| HOME | ABOUT | ARTICLES | ACK | FEEDBACK | TOC | LINKS | BLOG |
TABLE OF CONTENTS
............SystemVerilog Verification -- ASIC DESIGN

..................... Mrd
..................... Architecture Specification
..................... Design Specification
..................... Rtl Design
..................... Functional Verification
..................... Synthesis
..................... Physical Design
..................... Timing Analysis
..................... Tapeout
............SystemVerilog Verification -- BOTTLE NECK IN ASIC FLOW
............SystemVerilog Verification -- FUNCTIONAL VERIFICATION NEED
............SystemVerilog Verification -- TESTBENCH
............SystemVerilog Verification -- LINEAR TESTBENCH
............SystemVerilog Verification -- LINEAR RANDOM TESTBENCH
............SystemVerilog Verification -- HOW TO CHECK THE RESULTS
............SystemVerilog Verification -- SELF CHECKING TESTBENCHS
............SystemVerilog Verification -- HOW TO GET SCENARIOS WHICH WE NEVER THOUGHT
............SystemVerilog Verification -- HOW TO CHECK WHETHER THE TESTBENCH HAS SATISFACTORILY EXERCISED THE DESIGN
............SystemVerilog Verification -- TYPES OF CODE COVERAGE
............SystemVerilog Verification -- STATEMENT COVERAGE
............SystemVerilog Verification -- BLOCK COVERAGE
............SystemVerilog Verification -- CONDITIONAL COVERAGE
............SystemVerilog Verification -- BRANCH COVERAGE
............SystemVerilog Verification -- PATH COVERAGE
............SystemVerilog Verification -- TOGGLE COVERAGE
............SystemVerilog Verification -- FSM COVERAGE
..................... State Coverage
............SystemVerilog Verification -- MAKE YOUR GOAL 100 PERCENT CODE COVERAGE NOTHING LESS
..................... Dont Be Fooled By The Code Coverage Report
..................... When To Stop Testing?
............SystemVerilog Verification -- FUNCTIONAL COVERAGE
..................... Introduction To Functional Coverage
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..................... Item
..................... Cross
..................... Transitional
............SystemVerilog Verification -- COVERAGE DRIVEN CONSTRAINT RANDOM VERIFICATION ARCHITECTURE
..................... Verification Components Required For Cdcrv
..................... Stimulus
..................... Transactor
..................... Driver
..................... Monitor
..................... Assertion Based Monitor
..................... Data Checker
..................... Scoreboard
..................... Coverage
..................... Utilities
..................... Environment
..................... Tests
............SystemVerilog Verification -- PHASES OF VERIFICATION
..................... Building Testbench
..................... Writing Tests
..................... Integrating Code Coverage
..................... Analyze Coverage
............SystemVerilog Verification -- ONES COUNTER EXAMPLE
..................... Specification
..................... Test Plan
..................... Block Diagram
..................... Verification Environment Hierarchy
..................... Testbench Components
..................... Stimulus
..................... Driver
..................... Monitor
..................... Scoreboard
..................... Environment
..................... Top
..................... Tests
............SystemVerilog Verification -- VERIFICATION PLAN
..................... Verification Plan Contains The Following
..................... Overview
..................... Resources, Budget And Schedule
..................... System Verilog Verification Flow
..................... Checker Plan
..................... Coverage Plan
..................... Details Of Reusable Components
............SystemVerilog Constructs -- INTRODUCTION

............SystemVerilog Constructs -- DATA TYPES
..................... Signed And Unsigned
..................... Void
............SystemVerilog Constructs -- LITERALS
..................... Integer And Logic Literals
..................... Time Literals
..................... Array Literals
..................... Structure Literals
............SystemVerilog Constructs -- STRINGS
..................... String Methods
..................... String Pattren Match
..................... String Operators
..................... Equality
..................... Inequality.
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..................... Comparison.
..................... Concatenation.
..................... Replication.
..................... Indexing.
............SystemVerilog Constructs -- USERDEFINED DATATYPES
............SystemVerilog Constructs -- ENUMARATIONS
..................... Enumarated Methods
..................... Enum Numerical Expressions
............SystemVerilog Constructs -- STRUCTURES AND UNIOUNS
..................... Structure
..................... Assignments To Struct Members
..................... Union
..................... Packed Structures
............SystemVerilog Constructs -- TYPEDEF
..................... Advantages Of Using Typedef
............SystemVerilog Constructs -- ARRAYS
..................... Fixed Arrays
..................... Operations On Arrays
..................... Accessing Individual Elements Of Multidimensional Arrays
............SystemVerilog Constructs -- ARRAY METHODS
..................... Array Methods
..................... Array Locator Methods
..................... Array Ordering Methods
..................... Array Reduction Methods
..................... Iterator Index Querying
............SystemVerilog Constructs -- DYNAMIC ARRAYS
..................... Declaration Of Dynmic Array
..................... Allocating Elements
..................... Initializing Dynamic Arrays
..................... Resizing Dynamic Arrays
..................... Copying Elements
............SystemVerilog Constructs -- ASSOCIATIVE ARRAYS
..................... Associative Array Methods
............SystemVerilog Constructs -- QUEUES
..................... Queue Operators
..................... Queue Methods
..................... Dynamic Array Of Queues Queues Of Queues
............SystemVerilog Constructs -- COMPARISON OF ARRAYS
..................... Static Array
..................... Associative Array
..................... Dynamic Array
..................... Queues
............SystemVerilog Constructs -- LINKED LIST
..................... List Definitions
..................... Procedure To Create And Use List
..................... List_iterator Methods
..................... List Methods
............SystemVerilog Constructs -- CASTING
..................... Static Casting
..................... Dynamic Casting
..................... Cast Errors
............SystemVerilog Constructs -- DATA DECLARATION
..................... Scope And Lifetime
..................... Global
..................... Local
..................... Alias
..................... Data Types On Ports
..................... Parameterized Data Types
..................... Declaration And Initialization
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............SystemVerilog Constructs -- REG AND LOGIC

............SystemVerilog Constructs -- OPERATORS 1
..................... Operators In Systemverilog
..................... Assignment Operators
..................... Assignments In Expression
..................... Concatenation
..................... Arithmetic
..................... Relational
..................... Equality
............SystemVerilog Constructs -- OPERATORS 2
..................... Logical
..................... Bitwise
..................... Reduction
..................... Shift
..................... Set
..................... Streaming Operator
..................... Re-Ordering Of The Generic Stream
..................... Packing Using Streaming Operator
..................... Unpacking Using Streaming Operator
..................... Streaming Dynamically Sized Data
............SystemVerilog Constructs -- OPERATOR PRECEDENCY
............SystemVerilog Constructs -- EVENTS
..................... Triggered
..................... Wait()
..................... Race Condition
..................... Nonblocking Event Trigger
..................... Merging Events
..................... Null Events
..................... Wait Sequence
..................... Events Comparison
............SystemVerilog Constructs -- CONTROL STATEMENTS
..................... Sequential Control
..................... Enhanced For Loop
..................... Unique
..................... Priority
............SystemVerilog Constructs -- PROGRAM BLOCK
............SystemVerilog Constructs -- PROCEDURAL BLOCKS
..................... Final
..................... Jump Statements
..................... Event Control
..................... Always
............SystemVerilog Constructs -- FORK JOIN
..................... Fork Join None
..................... Fork Join Any
..................... For Join All
............SystemVerilog Constructs -- FORK CONTROL
..................... Wait Fork Statement
..................... Disable Fork Statement
............SystemVerilog Constructs -- SUBROUTINES
..................... Begin End
..................... Tasks
..................... Return In Tasks
..................... Functions
..................... Return Values And Void Functions:
..................... Default Values To Arguments
..................... Argument Binding By Name
..................... Optional Argument List
............SystemVerilog Constructs -- SEMAPHORE
............SystemVerilog Constructs -- MAILBOX
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............SystemVerilog Constructs -- FINE GRAIN PROCESS CONTROL
............SystemVerilog Interface -- INTERFACE

..................... Advantages Of Using Inteface
............SystemVerilog Interface -- PORTS
..................... Interface Ports
..................... Modports
..................... Modport Selection Duing Module Definition.
..................... Modport Selection Duing Module Instance.
............SystemVerilog Interface -- INTERFACE METHODS
..................... Methods In Interfaces
............SystemVerilog Interface -- CLOCKING BLOCK
..................... Clocking Blocks
..................... Skew
..................... Cycle Delay
............SystemVerilog Interface -- VIRTUAL INTERFACE
..................... Virtual Interfaces
..................... Advantages Of Virtual Interface
..................... Multi Bus Interface
............SystemVerilog Interface -- SVTB N VERILOG DUT
..................... Working With Verilog Dut
..................... Connecting In Top
..................... Connecting Using A Wrapper
............SystemVerilog OOPS -- INTRODUCTION

..................... Brief Introduction To Oop
..................... Class
..................... Object
..................... Methods
..................... Inheritance
..................... Abstraction
..................... Encapsulation
..................... Polymorphism
............SystemVerilog OOPS -- CLASS
..................... Class Properties
............SystemVerilog OOPS -- OBJECT
..................... Creating Objects
..................... Declaration
..................... Instantiating A Class
..................... Initializing An Object
..................... Constructor
............SystemVerilog OOPS -- THIS
..................... Using The This Keyword
............SystemVerilog OOPS -- INHERITANCE
..................... What You Can Do In A Subclass
..................... Overriding
..................... Super
..................... Is Only Method
..................... Is First Method
..................... Is Also Method
..................... Overriding Constraints.
..................... Overriding Datamembers
............SystemVerilog OOPS -- ENCAPSULATION
..................... Access Specifiers
............SystemVerilog OOPS -- POLYMORPHISM
............SystemVerilog OOPS -- ABSTRACT CLASSES
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............SystemVerilog OOPS -- PARAMETERISED CLASS

..................... Type Parameterised Class
..................... Value Parameterised Class
..................... Generic Parameterised Class
..................... Extending Parameterised Class
............SystemVerilog OOPS -- NESTED CLASSES
..................... Why Use Nested Classes
............SystemVerilog OOPS -- CONSTANT
..................... Constant Class
..................... Global Constant
..................... Instance Constants
............SystemVerilog OOPS -- STATIC
..................... Static Class Properties
..................... Static Methods
..................... Static Lifetime Method.
............SystemVerilog OOPS -- CASTING
............SystemVerilog OOPS -- COPY
..................... Shallow Copy
..................... Deep Copy
..................... Clone
............SystemVerilog OOPS -- SCOPE RESOLUTION OPERATOR
............SystemVerilog OOPS -- NULL
............SystemVerilog OOPS -- EXTERNAL DECLARATION
............SystemVerilog OOPS -- CLASSES AND STRUCTURES
............SystemVerilog OOPS -- TYPEDEF CLASS
..................... Forward Reference
..................... Circular Dependency
............SystemVerilog OOPS -- PURE
............SystemVerilog OOPS -- OTHER OOPS FEATURES
..................... Multiple Inheritence
..................... Method Overloading
............SystemVerilog OOPS -- MISC
..................... Always Block In Classes
............SystemVerilog Randomization -- CONSTRAINED RANDOM VERIFICATION

..................... Introduction
............SystemVerilog Randomization -- VERILOG CRV
..................... Constrained Random Stimulus Generation In Verilog
............SystemVerilog Randomization -- SYSTEMVERILOG CRV
..................... Systemverilog Constraint Random Stmulus Generaion
..................... Random Number Generator System Functions
..................... $Urandom_range
..................... Scope Randomize Function
..................... Randomizing Objects
..................... Random Unpacked Structs
..................... Rand Case
..................... Rand Sequence
............SystemVerilog Randomization -- RANDOMIZING OBJECTS
..................... Generating Random Stimulus Within Class
............SystemVerilog Randomization -- RANDOM VARIABLES
..................... Rand Modifier
..................... Randc Modifier
............SystemVerilog Randomization -- RANDOMIZATION METHODS
WWW.TESTBENCH.IN

..................... Randomize()
..................... Disabling Random Variable
..................... Random Static Variable
..................... Randomizing Nonrand Varible
............SystemVerilog Randomization -- CHECKER
............SystemVerilog Randomization -- CONSTRAINT BLOCK
..................... Inheritance
..................... Overrighting Constraints
............SystemVerilog Randomization -- INLINE CONSTRAINT
............SystemVerilog Randomization -- GLOBAL CONSTRAINT
............SystemVerilog Randomization -- CONSTRAINT MODE
............SystemVerilog Randomization -- EXTERNAL CONSTRAINTS
..................... Constraint Hiding
............SystemVerilog Randomization -- RANDOMIZATION CONTROLABILITY
..................... Controlability
............SystemVerilog Randomization -- STATIC CONSTRAINT
............SystemVerilog Randomization -- CONSTRAINT EXPRESSION
..................... Set Membership
..................... Implication
..................... If..Else
............SystemVerilog Randomization -- VARIABLE ORDERING
..................... Functions
..................... Iterative Constraints
............SystemVerilog Randomization -- CONSTRAINT SOLVER SPEED
............SystemVerilog Randomization -- RANDCASE
............SystemVerilog Randomization -- RANDSEQUENCE
..................... Random Productions
..................... Random Production Weights
..................... If..Else
..................... Case
..................... Repeat Production Statements
..................... Rand Join
..................... Break
..................... Return
..................... Value Passing Between Productions
............SystemVerilog Randomization -- RANDOM STABILITY
..................... Srandom
............SystemVerilog Randomization -- ARRAY RANDOMIZATION
............SystemVerilog Randomization -- CONSTRAINT GUARDS
............SystemVerilog Randomization -- TITBITS
..................... Constraining Non Integral Data Types
..................... Saving Memory
............SystemVerilog Functional Coverage -- INTRODUCTION

..................... Systemverilog Functional Coverage Features
............SystemVerilog Functional Coverage -- COVER GROUP
............SystemVerilog Functional Coverage -- SAMPLE
............SystemVerilog Functional Coverage -- COVER POINTS
WWW.TESTBENCH.IN
..................... Commands To Simulate And Get The Coverage Report

............SystemVerilog Functional Coverage -- COVERPOINT EXPRESSION
..................... Coverpoint Expression
..................... Coverage Filter
............SystemVerilog Functional Coverage -- GENERIC COVERAGE GROUPS
............SystemVerilog Functional Coverage -- COVERAGE BINS
..................... Implicit Bins
............SystemVerilog Functional Coverage -- EXPLICIT BIN CREATION
..................... Array Of Bins
..................... Default Bin
............SystemVerilog Functional Coverage -- TRANSITION BINS
..................... Single Value Transition
..................... Sequence Of Transitions
..................... Set Of Transitions
..................... Consecutive Repetitions
..................... Range Of Repetition
..................... Goto Repetition
..................... Non Consecutive Repetition
............SystemVerilog Functional Coverage -- WILDCARD BINS
............SystemVerilog Functional Coverage -- IGNORE BINS
............SystemVerilog Functional Coverage -- ILLEGAL BINS
............SystemVerilog Functional Coverage -- CROSS COVERAGE
..................... User-Defined Cross Bins
............SystemVerilog Functional Coverage -- COVERAGE OPTIONS
..................... Weight
..................... Goal
..................... Name
..................... Comment
..................... At_least
..................... Detect_overlap
..................... Auto_bin_max
..................... Cross_num_print_missing
..................... Per_instance
..................... Get_inst_coverage
............SystemVerilog Functional Coverage -- COVERAGE METHODS
............SystemVerilog Functional Coverage -- SYSTEM TASKS
............SystemVerilog Functional Coverage -- COVER PROPERTY
..................... Cover Property Results
..................... Cover Sequence Results
..................... Comparison Of Cover Property And Cover Group.
............SystemVerilog Assertion -- INTRODUCTION

..................... Advantages Of Assertion
..................... What Assertions Can Verify
............SystemVerilog Assertion -- EVENT SIMULATION
............SystemVerilog Assertion -- ASSERTION TYPES
............SystemVerilog Assertion -- ASSERTION SYSTEM TASKS
..................... Assertion Control System Tasks
..................... Boolean System Function
............SystemVerilog Assertion -- CONCURRENT ASSERTION LAYERS
..................... Boolean Expressions
............SystemVerilog Assertion -- SEQUENCES
..................... Fixed Delay
..................... Zero Delay
WWW.TESTBENCH.IN
..................... Constant Range Delay

..................... Unbounded Delay Range
..................... Repetation Operators
..................... Consecutive Repetition
..................... Goto Repetition
..................... Nonconsecutive Repetition
..................... Sequence And
..................... Sequence Or
..................... Sequence Intersect
..................... Sequence Within
..................... Sequence First_match
..................... Sequence Throughout
..................... Sequence Ended
..................... Operator Precedence Associativy
............SystemVerilog Assertion -- PROPERTIES
..................... Overlap Implication
..................... Non Overlapping Implication
............SystemVerilog Assertion -- VERIFICATION DIRECTIVE
..................... Assert
..................... Assume
..................... Cover Statement
..................... Expect Statement
..................... Binding
............SystemVerilog DPI -- INTRODUCTIONS

..................... What Is Dpi-C ?
............SystemVerilog DPI -- LAYERS
..................... Two Layers Of Dpi-C
..................... Dpi-C Systemverilog Layer
..................... Dpi-C Foreign Language Layer
............SystemVerilog DPI -- IMPORT
..................... Import Methods
..................... Steps To Write Import Metyhods
..................... Standard C Functions
............SystemVerilog DPI -- NAMING
..................... Global Name
..................... Local Name
..................... Sv Keyword As Linkage Name
............SystemVerilog DPI -- EXPORT
..................... Export Methods
..................... Steps To Write Export Methods
..................... Blocking Export Dpi Task
............SystemVerilog DPI -- PURE AND CONTEXT
..................... Pure Function
..................... Context Function
............SystemVerilog DPI -- DATA TYPES
..................... Passing Logic Datatype
............SystemVerilog DPI -- ARRAYS
..................... Open Arrays
..................... Packed Arrays
..................... Linearized And Normalized
............SystemVerilog DPI -- PASSING STRUCTS AND UNIONS
..................... Passing Structure Example
..................... Passing Openarray Structs
..................... Passing Union Example
............SystemVerilog DPI -- ARGUMENTS TYPE
..................... What You Specify Is What You Get
..................... Pass By Ref
..................... Pass By Value
..................... Passing String
WWW.TESTBENCH.IN
..................... Example Passing String From Sv To C

..................... Example Passing String From C To Sv
............SystemVerilog DPI -- DISABLIE
..................... Disable Dpi-C Tasks And Functions
..................... Include Files
............SystemVerilog VMM Tutorial -- INTRODUCTION

............SystemVerilog VMM Tutorial -- VMM LOG
..................... Vmm Message Type
..................... Message Severity
..................... Vmm Log Macros
..................... Message Handling
..................... Counting Number Of Messages Based Of Message Severity
............SystemVerilog VMM Tutorial -- VMM ENV
............SystemVerilog VMM Tutorial -- VMM DATA
..................... Complete Packet Class
..................... Vmm_data Methods
............SystemVerilog VMM Tutorial -- VMM CHANNEL
..................... Complete Example
..................... Vmm Channel Methods.
............SystemVerilog VMM Tutorial -- VMM ATOMIC GENERATOR
..................... Completed Example
............SystemVerilog VMM Tutorial -- VMM XACTOR
..................... Complete Vmm_xactor Example
..................... Vmm_xactor Members
............SystemVerilog VMM Tutorial -- VMM CALLBACK
..................... Complete Source Code
............SystemVerilog VMM Tutorial -- VMM TEST
..................... Writing A Testcase
..................... Example Of Using Vmm_test
............SystemVerilog VMM Tutorial -- VMM CHANNEL RECORD AND PLAYBACK
..................... Recording
..................... Playing Back
............SystemVerilog VMM Tutorial -- VMM SCENARIO GENERATOR
..................... Example
..................... Scenario Code
..................... Testcase
............SystemVerilog VMM Tutorial -- VMM OPTS
............SystemVerilog UMM Tutorial -- INTRODUCTION

............SystemVerilog UMM Tutorial -- UVM TESTBENCH
..................... Uvm_env
..................... About Uvm_component Class
..................... Uvm_test
..................... Top Module
............SystemVerilog UMM Tutorial -- UVM REPORTING
..................... Actions
..................... Configuration
WWW.TESTBENCH.IN
............SystemVerilog UMM Tutorial -- UVM TRANSACTION

..................... Core Utilities
............SystemVerilog UMM Tutorial -- UVM CONFIGURATION
............SystemVerilog UMM Tutorial -- UVM FACTORY
..................... Registration
..................... Construction
..................... Overriding
............SystemVerilog UMM Tutorial -- UVM SEQUENCE 1
..................... Introduction
..................... Simple Example
..................... Sequence Item
..................... Sequence
..................... Sequencer
..................... Driver
..................... Testcase
..................... Body Callbacks
..................... Lock-Unlock
..................... Grab-Ungrab
............SystemVerilog UMM Tutorial -- UVM TLM 1
..................... Port Based Data Transfer
..................... Task Based Data Transfer
..................... Operation Supported By Tlm Interface
..................... Methods
..................... Tlm Terminology
..................... Tlm Interface Compilation Models
..................... Interfaces
..................... Direction
..................... All Interfaces In Uvm
............SystemVerilog UMM Tutorial -- UVM TLM 2
..................... Analysis
..................... Tlm Fifo
..................... Example
............SystemVerilog UMM Tutorial -- UVM CALLBACK
..................... Driver And Driver Callback Class Source Code
..................... Testcase Source Code
WWW.TESTBENCH.IN

..................... Methods
..................... Macros
............SystemVerilog OVM Tutorial -- INTRODUCTION

............SystemVerilog OVM Tutorial -- OVM TESTBENCH
..................... Ovm_env
..................... About Ovm_component Class
..................... Ovm_test
..................... Top Module
............SystemVerilog OVM Tutorial -- OVM REPORTING
..................... Actions
..................... Configuration
............SystemVerilog OVM Tutorial -- OVM TRANSACTION
..................... Core Utilities
............SystemVerilog OVM Tutorial -- OVM FACTORY
..................... Registration
..................... Construction
..................... Overriding
............SystemVerilog OVM Tutorial -- OVM SEQUENCE 1
..................... Introduction
..................... Simple Example
..................... Sequence Item
..................... Sequence
..................... Sequencer
..................... Driver
..................... Testcase
..................... Body Callbacks
..................... Lock-Unlock
..................... Grab-Ungrab
............SystemVerilog OVM Tutorial -- OVM CONFIGURATION
WWW.TESTBENCH.IN
............SystemVerilog Easy Labs - SV -- INTRODUCTION

............SystemVerilog Easy Labs - SV -- SPECIFICATION
..................... Packet Format
..................... Packet Header
..................... Configuration
..................... Input Port
..................... Output Port
............SystemVerilog Easy Labs - SV -- VERIFICATION PLAN
..................... Overview
..................... Coverage Plan
............SystemVerilog Easy Labs - SV -- PHASE 1 TOP
..................... Interfaces
..................... Testcase
..................... Top Module
............SystemVerilog Easy Labs - SV -- PHASE 2 ENVIRONMENT
..................... Run
............SystemVerilog Easy Labs - SV -- PHASE 3 RESET
............SystemVerilog Easy Labs - SV -- PHASE 4 PACKET
............SystemVerilog Easy Labs - SV -- PHASE 5 DRIVER
............SystemVerilog Easy Labs - SV -- PHASE 6 RECEIVER
............SystemVerilog Easy Labs - SV -- PHASE 7 SCOREBOARD
............SystemVerilog Easy Labs - SV -- PHASE 8 COVERAGE
..................... Source Code Of The Scoreboard Class
............SystemVerilog Easy Labs - SV -- PHASE 9 TESTCASE
..................... Source Code Of Constraint Testcase
............SystemVerilog Easy Labs - OVM -- INTRODUCTION

............SystemVerilog Easy Labs - OVM -- SPECIFICATION
..................... Packet Format
..................... Configuration
............SystemVerilog Easy Labs - OVM -- VERIFICATION PLAN
..................... Overview
WWW.TESTBENCH.IN
............SystemVerilog Easy Labs - OVM -- PHASE 1 TOP

..................... Interface
..................... Top Module
............SystemVerilog Easy Labs - OVM -- PHASE 2 CONFIGURATION
..................... Configuration
............SystemVerilog Easy Labs - OVM -- PHASE 3 ENVIRONMENT N TESTCASE
..................... Environment
..................... Testcase
............SystemVerilog Easy Labs - OVM -- PHASE 4 PACKET
..................... Packet
............SystemVerilog Easy Labs - OVM -- PHASE 5 SEQUENCER N SEQUENCE
..................... Sequencer
..................... Sequence
............SystemVerilog Easy Labs - OVM -- PHASE 6 DRIVER
..................... Driver
............SystemVerilog Easy Labs - OVM -- PHASE 7 RECEIVER
..................... Receiver
............SystemVerilog Easy Labs - OVM -- PHASE 8 SCOREBOARD
..................... Scoreboard
............SystemVerilog Easy Labs - UVM -- INTRODUCTION

............SystemVerilog Easy Labs - UVM -- SPECIFICATION
..................... Packet Format
..................... Configuration
............SystemVerilog Easy Labs - UVM -- VERIFICATION PLAN
..................... Overview
............SystemVerilog Easy Labs - UVM -- PHASE 1 TOP
..................... Interface
..................... Top Module
............SystemVerilog Easy Labs - UVM -- PHASE 2 CONFIGURATION
..................... Configuration
............SystemVerilog Easy Labs - UVM -- PHASE 3 ENVIRONMENT N TESTCASE
..................... Environment
..................... Testcase
............SystemVerilog Easy Labs - UVM -- PHASE 4 PACKET
..................... Packet
............SystemVerilog Easy Labs - UVM -- PHASE 5 SEQUENCER N SEQUENCE
..................... Sequencer
..................... Sequence
............SystemVerilog Easy Labs - UVM -- PHASE 6 DRIVER
..................... Driver
WWW.TESTBENCH.IN
............SystemVerilog Easy Labs - UVM -- PHASE 7 RECEIVER

..................... Receiver
............SystemVerilog Easy Labs - UVM -- PHASE 8 SCOREBOARD
..................... Scoreboard
............SystemVerilog Easy Labs - VMM -- INTRODUCTION

............SystemVerilog Easy Labs - VMM -- SPECIFICATION
..................... Packet Format
..................... Configuration
............SystemVerilog Easy Labs - VMM -- VERIFICATION PLAN
..................... Overview
..................... Coverage Plan
............SystemVerilog Easy Labs - VMM -- PHASE 1 TOP
..................... Interfaces
..................... Testcase
..................... Top Module
............SystemVerilog Easy Labs - VMM -- PHASE 2 ENVIRONMENT
..................... Run
............SystemVerilog Easy Labs - VMM -- PHASE 3 RESET
............SystemVerilog Easy Labs - VMM -- PHASE 4 PACKET
............SystemVerilog Easy Labs - VMM -- PHASE 5 GENERATOR
............SystemVerilog Easy Labs - VMM -- PHASE 6 DRIVER
............SystemVerilog Easy Labs - VMM -- PHASE 7 RECEIVER
............SystemVerilog Easy Labs - VMM -- PHASE 8 SCOREBOARD
............SystemVerilog Easy Labs - VMM -- PHASE 9 COVERAGE
............SystemVerilog AVM Switch TB -- AVM INTRODUCTION

..................... Tlm
..................... Building Blocks
..................... Avm_transactors
..................... Avm_env
..................... Avm_messaging
............SystemVerilog AVM Switch TB -- DUT SPECIFICATION
..................... Configuration
WWW.TESTBENCH.IN

..................... Input Interface
............SystemVerilog AVM Switch TB -- RTL
............SystemVerilog AVM Switch TB -- TOP
..................... Verilog Top
............SystemVerilog AVM Switch TB -- INTERFACE
............SystemVerilog AVM Switch TB -- ENVIRONMENT
............SystemVerilog AVM Switch TB -- PACKET
............SystemVerilog AVM Switch TB -- PACKET GENERATOR
............SystemVerilog AVM Switch TB -- CONFIGURATION
............SystemVerilog AVM Switch TB -- DRIVER
............SystemVerilog AVM Switch TB -- RECIEVER
............SystemVerilog AVM Switch TB -- SCOREBOARD
............Verilog Verification -- INTRODUCTION

..................... Test Bench Overview
............Verilog Verification -- LINEAR TB
..................... Linear Testbench
............Verilog Verification -- FILE IO TB
..................... File I/O Based Testbench
............Verilog Verification -- STATE MACHINE BASED TB
............Verilog Verification -- TASK BASED TB
..................... Task And Function Based Tb
............Verilog Verification -- SELF CHECKING TESTBENCH
..................... Bus Functional Models
..................... Driver
..................... Reciver
..................... Protocol Monitor
..................... Scoreboard
..................... Checker
..................... Coverage
..................... Code Coverage
............Verilog Verification -- VERIFICATION FLOW
..................... Planning
..................... Verification Environment Architecture Plan
............Verilog Verification -- CLOCK GENERATOR
..................... Timescale And Precision Enlightment
............Verilog Verification -- SIMULATION
..................... Simulation Steps
..................... Macro Preprocessing
..................... Compilation (Analyzer)
..................... Elaboration
..................... Optimization
..................... Initialization
..................... Execution
..................... Simulation Process
............Verilog Verification -- INCREMENTAL COMPILATION
............Verilog Verification -- STORE AND RESTORE
WWW.TESTBENCH.IN
............Verilog Verification -- EVENT CYCLE SIMULATION

..................... Event Based Simulation
..................... Cycle Based Simulation
............Verilog Verification -- TIME SCALE AND PRECISION
..................... Time Scale And Time Precision
..................... $Time Vs $Realtime
..................... System Task Printtimescale
..................... System Task Timeformat
............Verilog Verification -- STIMULUS GENERATION
............Verilog Verification -- SYSTEM FUNCTION RANDOM A MYTH
............Verilog Verification -- RACE CONDITION
..................... What Is Race Condition?
..................... Why Race Condition?
..................... When Race Is Visible?
..................... How To Prevent Race Condition?
..................... Types Of Race Condition
..................... Write-Write Race
..................... Read-Write Race
..................... More Race Example
..................... Event Terminology
..................... The Stratified Event Queue
..................... Determinism
..................... Nondeterminism
..................... Guideline To Avoid Race Condition
..................... Avoid Race Between Testbench And Dut
............Verilog Verification -- CHECKER
..................... Protocol Checker
..................... Data_checker
..................... Modularization
............Verilog Verification -- TASK AND FUNCTION
..................... Functions
..................... Task
..................... Task And Function Queries
..................... Constant Function
..................... Reentrant Tasks And Functions
............Verilog Verification -- PROCESS CONTROL
..................... Nonblocking Task
..................... Fork/Join Recap
..................... Fork/Join None
..................... Fork/Join Any
............Verilog Verification -- DISABLEING THE BLOCK
..................... Disable
..................... Goto
..................... Break
..................... Continue
............Verilog Verification -- WATCHDOG
............Verilog Verification -- COMPILATION N SIMULATION SWITCHS
..................... Compilation And Simulation Directives
..................... Example
............Verilog Verification -- DEBUGGING
..................... Pass Or Fail
..................... Waveform Viewer
..................... Log File
..................... Message Control System
..................... Message Severity Levels
..................... Message Controlling Levels
..................... Passing Comments To Waveform Debugger
..................... $Display N $Strobe
..................... Who Should Do The Rtl Debugging?
............Verilog Verification -- ABOUT CODE COVERAGE
..................... Types Of Coverage
WWW.TESTBENCH.IN
..................... Code Coverage

..................... Statement Coverage /Line Coverage
..................... Block/Segment Coverage
..................... Branch / Decision / Conditional Coverage
..................... Path Coverage
..................... Expression Coverage
..................... Toggle Coverage
..................... Variable Coverage
..................... Triggering / Event Coverage
..................... Parameter Coverage
..................... Fsm Coverage
..................... State Coverage
..................... Sequence Coverage
..................... Tool Support
..................... Limitation Of Code Coverage
............Verilog Verification -- TESTING STRATIGIES
..................... Bottom-Up
..................... Unit Level
..................... Sub-Asic Level
..................... Asic Level
..................... System Level
..................... Flat
............Verilog Verification -- FILE HANDLING
..................... Fopen And Fclose
..................... Fdisplay
..................... Fmonitor
..................... Fwrite
..................... Mcd
..................... Formating Data To String
............Verilog Verification -- VERILOG SEMAPHORE
..................... Semaphore In Verilog
............Verilog Verification -- FINDING TESTSENARIOUS
..................... Register Tests
..................... System Tests
..................... Interrupt Tests
..................... Interface Tests
..................... Functional Tests
..................... Error Tests
..................... Golden Tests
..................... Performance Tests
............Verilog Verification -- HANDLING TESTCASE FILES
............Verilog Verification -- TERIMINATION
............Verilog Verification -- ERROR INJUCTION
..................... Value Errors
..................... Temporal Errors
..................... Interface Error
..................... Sequence Errors
............Verilog Verification -- REGISTER VERIFICATION
..................... Register Verification
..................... Register Classification
..................... Features
............Verilog Verification -- PARAMETERISED MACROS
............Verilog Verification -- WHITE GRAY BLACK BOX
..................... Black Box Verification
..................... White Box Verification
..................... Gray Box Verification
............Verilog Verification -- REGRESSION
............Verilog Verification -- TIPS
..................... How To Avoid "Module Xxx Already Defined" Error
..................... Colourful Messages
WWW.TESTBENCH.IN
..................... Debugging Macros
............Verilog Switch TB -- DUT SPECIFICATION

..................... Configuration
..................... Input Interface
............Verilog Switch TB -- RTL
............Verilog Switch TB -- TOP
..................... Top Module
............Verilog Switch TB -- PACKET
............Verilog Switch TB -- DRIVER
............Verilog Switch TB -- RECIEVER
............Verilog Switch TB -- SCOREBOARD
............Verilog Switch TB -- ENV
............Verilog Basic Constructs -- INTRODUCTION

..................... Introduction
............Verilog Basic Constructs -- SYNTAX
............Verilog Basic Constructs -- DATA TYPES
..................... Value Set
..................... Net
..................... Variable Or Reg
..................... Vectors
..................... Memories
..................... Net Types
............Verilog Basic Constructs -- OPERATORS
..................... Binary Arithmetic Operators
..................... Unary Arithmetic Operators
..................... Relational Operators
..................... Logical Operators
..................... Bitwise Operators
..................... Unary Reduction Operators
..................... Other Operators
............Verilog Basic Constructs -- ASSIGNMENTS
..................... Blocking Procedural Assignments
..................... The Nonblocking Procedural Assignment
..................... Procedural Continuous Assignments
..................... Assign And Deassign Procedural Statements
..................... Force And Release Procedural Statements
..................... Delays
..................... Inter Assignmnet Delay .
..................... Intra-Assignment Delay Control
............Verilog Basic Constructs -- CONTROL CONSTRUCTS
..................... If And If Else Statements
..................... Case
..................... Forever
..................... Repeat
..................... While
..................... For
............Verilog Basic Constructs -- PROCEDURAL TIMING CONTROLS
..................... Delay Control
..................... Event Control
WWW.TESTBENCH.IN
..................... Named Events

............Verilog Basic Constructs -- STRUCTURE
..................... Module
..................... Ports
..................... Signals
............Verilog Basic Constructs -- BLOCK STATEMENTS
..................... Sequential Blocks
..................... Parallel Blocks
............Verilog Basic Constructs -- STRUCTURED PROCEDURES
..................... Initial
..................... Always
..................... Functions
..................... Task
............Vera Constructs -- INTRODUCTION

..................... Introduction
..................... Comments In Openvera
..................... Numbers In Openvera
............Vera Constructs -- DATA TYPES
..................... Basic Data Types
..................... Integer
..................... Register
..................... String
..................... Event
..................... Virtual Ports
..................... Arrays
..................... Fixed-Size Arrays
..................... Dynamic Arrays
..................... Associative Arrays
..................... Smart Queues
..................... Class
............Vera Constructs -- LINKED LIST
..................... Linked List
..................... List Methods
............Vera Constructs -- OPERATORS PART 1
..................... Operators
..................... Concatenation
..................... Arithmetic
..................... Relational
..................... Equality
..................... Logical
..................... Bitwise
..................... Reduction
..................... Shift
..................... Bit-Reverse
..................... Conditional
..................... Set
..................... Replication
............Vera Constructs -- OPERATOR PRECEDENCE
............Vera Constructs -- CONTROL STATEMENTS
..................... Sequential Statements
............Vera Constructs -- PROCEDURES AND METHODS
..................... Procedures And Methods
..................... Pass By Value
..................... Default Arguments
WWW.TESTBENCH.IN
..................... Optional Arguments

............Vera Constructs -- INTERPROCESS
..................... Interprocess Synchronization And Communication
............Vera Constructs -- FORK JOIN
..................... Fork Join
............Vera Constructs -- SHADOW VARIABLES
..................... Shadow Variables
............Vera Constructs -- FORK JOIN CONTROL
..................... Fork And Join Control
..................... Wait_chiled()
..................... Terminate
..................... Suspend_thread
............Vera Constructs -- WAIT VAR
..................... Wait_var
............Vera Constructs -- EVENT SYNC
..................... Event Methods
............Vera Constructs -- EVENT TRIGGER
..................... Event Trigger
..................... Event Variables
............Vera Constructs -- SEMAPHORE
..................... Semaphore
............Vera Constructs -- REGIONS
..................... Regions
............Vera Constructs -- MAILBOX
..................... Mailbox
............Vera Constructs -- TIMEOUTS
..................... Timeouts
............Vera Constructs -- OOP
..................... Object Oriented Programming
..................... Properties
..................... This
..................... Class Extensions
..................... Polymorphism
..................... Super
..................... Abstract Class
............Vera Constructs -- CASTING
............Vera Constructs -- RANDOMIZATION
..................... Constrained Random Verification
..................... Rand Modifier
..................... Randc Modifier
............Vera Constructs -- RANDOMIZATION METHODS
..................... Randomize()
............Vera Constructs -- CONSTRAINT BLOCK
..................... Constraint Block
..................... Inline Constraints
............Vera Constructs -- CONSTRAINT EXPRESSION
..................... Constraint Expressions
..................... Set Membership
..................... Implication
..................... If..Else
..................... Iterative
WWW.TESTBENCH.IN
............Vera Constructs -- VARIABLE ORDARING

..................... Variable Ordaring
............Vera Constructs -- AOP
..................... Aspect Oriented Extensions
............Vera Constructs -- PREDEFINED METHODS
..................... Predefined Methods
..................... New()
..................... Finalize()
..................... Object_print
..................... Deep Object Compare
..................... Deep Object Copy
..................... Pack And Unpack
............Vera Constructs -- STRING METHODS
............Vera Constructs -- QUEUE METHODS
............Vera Constructs -- DUT COMMUNICATION
..................... Connecting To Hdl
..................... Interface Declaration
..................... Direct Hdl Node Connection
..................... Blocking And Non-Blocking Drives
............Vera Constructs -- FUNCTIONAL COVERAGE
..................... Coverage Group
..................... Sample_event
..................... Coverage_point
..................... Cross Coverage
............Vera Switch TB -- DUT SPECIFICATION

..................... Configuration
..................... Input Interface
............Vera Switch TB -- RTL
............Vera Switch TB -- TOP
..................... Top Module
............Vera Switch TB -- INTERFACE
............Vera Switch TB -- PACKET
............Vera Switch TB -- PACKET GENERATOR
............Vera Switch TB -- CFG DRIVER
............Vera Switch TB -- DRIVER
............Vera Switch TB -- RECIEVER
............Vera Switch TB -- SCOREBOARD
............Vera Switch TB -- ENV
............Vera RVM Switch TB -- INTRODUCTION

..................... Dut Specification
..................... Configuration
..................... Input Interface
WWW.TESTBENCH.IN
............Vera RVM Switch TB -- RTL

............Vera RVM Switch TB -- TOP
............Vera RVM Switch TB -- INTERFACE
............Vera RVM Switch TB -- PROGRAM BLOCK
..................... Testbench Program
............Vera RVM Switch TB -- ENVIRONMENT
............Vera RVM Switch TB -- PACKET
............Vera RVM Switch TB -- CONFIGURATION
............Vera RVM Switch TB -- DRIVER
............Vera RVM Switch TB -- RECIEVER
............Vera RVM Switch TB -- SCOREBOARD
............Specman E -- INTRODUCTION
............Specman E -- E BASICS
..................... Code Segments
..................... Comments
..................... Literals And Constants
..................... Sized Numbers
..................... PredeNed Constants
............Specman E -- DATA TYPES
............Specman E -- OPERATORS
..................... Unary Bitwise Operators
..................... Binary Bitwise Operations
..................... Shift Operators
..................... Boolean Operators
..................... Arithmetic Operators
..................... Comparison Operators
..................... Extraction And Concatenation Operators
..................... Special-Purpose Operators
............Specman E -- STRUCT
............Specman E -- UNITS
..................... Units Vs Structs
............Specman E -- LIST
..................... Regular List
..................... List Operations
..................... Keyed List
............Specman E -- METHODS
..................... Time-Consuming Methods(Tcms)
..................... Invoking Tcms
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............Specman E -- TEMPORAL OPERATORS 2
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............Specman E -- SYNCHRONIZING WITH THE SIMULATOR
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............Specman E -- AND GATE EVC
............Interview Questions -- FUNCTIONAL VERIFICATION QUESTIONS

............Interview Questions -- FUNCTIONAL VERIFICATION QUESTIONS 2
............Interview Questions -- TEST YOUR SYSTEMVERILOG SKILLS 1
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INTRODUCTION
SystemVerilog
SystemVerilog is a combined Hardware Description Language and Hardware

Verification Language based on extensions to Verilog. SystemVerilog was created by
the donation of the Superlog language to Accellera in 2002. The bulk of the
verification functionality is based on the OpenVera language donated by Synopsys. In
2005, SystemVerilog was adopted as IEEE Standard 1800-2005 .
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Few of SystemVerilog's capabilities are unique, but it is significant that these

capabilities are combined and offered within a single HDL. There is great value in a
common HDL which handles all aspects of the design and verification flow: design
description, functional simulation, property specification, and formal verification.
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Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
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Index
Introduction
Data Types
SystemVerilog
Literals
Verification
SystemVerilog adds extended and new data types to Verilog for better encapsulation Strings
Constructs
and compactness.SystemVerilog extends Verilog by introducing C like data Userdefined Datatypes
types.SystemVerilog adds a new 2-state data types that can only have bits with 0 or Enumarations
Interface
1 values unlike verilog 4-state data types which can have 0, 1, X and Z. Structures And Uniouns
OOPS
Typedef
SystemVerilog also allows user to define new data types.
Arrays
Randomization
Array Methods
Functional Coverage
SystemVerilog offers several data types, representing a hybrid of both Verilog and C Dynamic Arrays
Assertion
data types. SystemVerilog 2-state data types can simulate faster, take less memory, Associative Arrays
and are preferred in some design styles. Then a 4-state value is automatically Queues
DPI
converted to a 2-state value, X and Z will be converted to zeros.
Linked List
UVM Tutorial
Casting
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Data Declaration
Reg And Logic
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Operators 1
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Operator Precedency
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DATA TYPES
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TIP : If you don't need the x and z values then use the SystemVerilog int and bit types
which make execution faster.
Signed And Unsigned :
Integer types use integer arithmetic and can be signed or unsigned.The data types
byte, shortint, int, integer, and longint default to signed. The data types bit, reg, and
logic default to unsigned, as do arrays of these types.
To use these types as unsigned, user has to explicitly declare it as unsigned.
http://testbench.in/SV_02_DATA_TYPES.html[9/26/2012 2:01:21 PM]
intunsignedui;
intsignedsi
byteunsignedubyte;
User can cast using signed and unsigned casting.
if(signed'(ubyte)<150)// ubyte is unsigned
Void :
The void data type represents nonexistent data. This type can be specified as the
return type of functions to indicate no return value.
void=function_call();
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Integer And Logic Literals
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In verilog , to assign a value to all the bits of vector, user has to specify them
explicitly.
reg[31:0]a =32'hffffffff;
Systemverilog Adds the ability to specify unsized literal single bit values with a
preceding (').'0, '1, 'X, 'x, 'Z, 'z // sets all bits to this value.
reg[31:0]a ='1;
'x is equivalent to Verilog-2001'bx
'z is equivalent to Verilog-2001'bz
'1is equivalent to making an assignment of all 1's
'0is equivalent to making an assignment of 0
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Time Literals
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Time is written in integer or fixed-point format, followed without a space by a time

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EXAMPLE
0.1ns
40ps
The time literal is interpreted as a realtime value scaled to the current time unit and
rounded to the current time precision.
Array Literals
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
Array literals are syntactically similar to C initializers, but with the replicate operator Report a Bug or Comment
( {{}} ) allowed.
EXAMPLE
intn[1:2][1:3]='{'{0,1,2},'{3{4}}};
The nesting of braces must follow the number of dimensions, unlike in C. However,
replicate operators can be nested. The inner pair of braces in a replication is
removed. A replication expression only operates within one dimension.
EXAMPLE:
intn[1:2][1:6]='{2{'{3{4,5}}}};// same as '{'{4,5,4,5,4,5},'{4,5,4,5,4,5}}
Structure Literals
Structure literals are structure assignment patterns or pattern expressions with
constant member expressions A structure literal must have a type, which may be
either explicitly indicated with a prefix or implicitly indicated by an assignment-like
context.
EXAMPLE
typedefstruct{inta;shortrealb;}ab;
ab c;
c ='{0,0.0};// structure literal type determined from
// the left-hand context (c)
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Nested braces should reflect the structure.

EXAMPLE
ab abarr[1:0]='{'{1,1.0},'{2,2.0}};
The C-like alternative '{1, 1.0, 2, 2.0} for the preceding example is not allowed.
EXAMPLE: default values
c ='{a:0,b:0.0};
c ='{default:0};
d =ab'{int:1,shortreal:1.0};
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STRINGS
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In Verilog, string literals are packed arrays of a width that is a multiple of 8 bits
which hold ASCII values. In Verilog, if a string is larger than the destination string
variable, the string is truncated to the left, and the leftmost characters will be
lost.SystemVerilog adds new keyword "string" which is used to declare string data
types unlike verilog. String data types can be of arbitrary length and no truncation
occurs.
stringmyName ="TEST BENCH";
String Methods :
DPI
SystemVerilog also includes a number of special methods to work with strings. These
methods use the built-in method notation. These methods are:
1.str.len() returns the length of the string, i.e., the number of characters in the
VMM Tutorial
string.
OVM Tutorial
2.str.putc(i, c) replaces the ith character in str with the given integral value.
3.str.getc(i) returns the ASCII code of the ith character in str.
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4.str.toupper() returns a string with characters in str converted to uppercase.
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5.str.tolower() returns a string with characters in str converted to lowercase.
6.str.compare(s) compares str and s, and return value. This comparison is case
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sensitive.
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7.str.icompare(s) compares str and s, and return value.This comparison is case
insensitive.
AVM Switch TB
8.str.substr(i, j) returns a new string that is a substring formed by index i through
VMM Ethernet sample j of str.
9.str.atoi() returns the integer corresponding to the ASCII decimal representation
in str.
10. str.atoreal() returns the real number corresponding to the ASCII decimal
Verilog
representation in str.
Verification
11. str.itoa(i) stores the ASCII decimal representation of i into str (inverse of atoi).
Verilog Switch TB
12. str.hextoa(i) stores the ASCII hexadecimal representation of i into str (inverse of
atohex).
Basic Constructs
13. str.bintoa(i) stores the ASCII binary representation of i into str (inverse of
atobin).
14. str.realtoa(r) stores the ASCII real representation of r into str (inverse of
OpenVera
atoreal)
UVM Tutorial
Constructs
Switch TB
RVM Switch TB
EXAMPLE : String methods
RVM Ethernet sample modulestr;
Specman E
Interview Questions
stringA;
stringB;
initial
begin
A ="TEST ";
B ="Bench";
$display(" %d ",A.len());
$display(" %s ",A.getc(5));
$display(" %s ",A.tolower);
$display(" %s ",B.toupper);
$display(" %d ",B.compare(A));
$display(" %d ",A.compare("test"));
$display(" %s ",A.substr(2,3));A ="111";
$display(" %d ",A.atoi());
end
http://testbench.in/SV_04_STRINGS.html[9/26/2012 2:01:38 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
endmodule
RESULTS :
5
test
BENCH
-18
-32
ST
111
String Pattren Match
Use the following method for pattern matching in SystemVerilog. Match method which
is in OpenVera or C , is not available in SystemVerilog . For using match method which
is in C , use the DPI calls . For native SystemVerilog string match method, hear is the
example.
CODE:
functionmatch(strings1,s2);
intl1,l2;
l1 =s1.len();
l2 =s2.len();
match =0;
if(l2 >l1 )
return0;
for(inti =0;i <l1 -l2 +1;i ++)
if(s1.substr(i,i+l2 -1)==s2)
return1;
endfunction
EXAMPLE:
programmain;
stringstr1,str2;
inti;
initial
begin
str1 ="this is first string";
str2 ="this";
if(match(str1,str2))
$display(" str2 : %s : found in :%s:",str2,str1);
str2 ="first";
str2 ="string";

str2 ="this is ";
str2 ="first string";
str2 ="first string ";// one space at end
end
endprogram
RESULTS:
str2
str2
str2
str2
str2
:
:
:
:
:
this : found in :this is first string:

first : found in :this is first string:
string : found in :this is first string:
this is : found in :this is first string:
first string : found in :this is first string:
String Operators
SystemVerilog provides a set of operators that can be used to manipulate
combinations of string variables and string literals. The basic operators defined on the
string data type are
Equality
Syntax : Str1 == Str2
Checks whether the two strings are equal. Result is 1 if they are equal and 0 if they
are not. Both strings can be of type string. Or one of them can be a string literal. If
both operands are string literals, the operator is the same Verilog equality operator as
for integer types.
EXAMPLE
programmain;
initial
begin
stringstr1,str2,str3;
str1 ="TEST BENCH";
str2 ="TEST BENCH";
str3 ="test bench";
if(str1 ==str2)
$display(" Str1 and str2
else
if(str1 ==str3)
else
end
endprogram
RESULT
Str1 and str2 are equal
Str1 and str3 are not equal
are equal");
are not equal");
are equal");
are not equal");
Inequality.
Syntax: Str1 != Str2
Logical negation of Equality operator.Result is 0 if they are equal and 1 if they are
not. Both strings can be of type string. Or one of them can be a string literal. If both
operands are string literals, the operator is the same Verilog equality operator as for
integer types.
EXAMPLE
programmain;
initial
begin
stringstr1,str2,str3;
str1 ="TEST BENCH";
str2 ="TEST BENCH";
str3 ="test bench";
if(str1 !=str2)
else
if(str1 !=str3)
else
end
endprogram
RESULT
are not equal");

are equal");
are not equal");
are equal");
Str1 and str2 are equal

Str1 and str3 are not equal
Comparison.
Syntax:
Str1 <Str2
Str1 <=Str2
Str1 >Str2
Str1 >=Str2
Relational operators return 1 if the corresponding condition is true using the
lexicographical ordering of the two strings Str1 and Str2. The comparison uses the
compare string method. Both operands can be of type string, or one of them can be a
string literal.
EXAMPLE
programmain;
initial
begin
stringStr1,Str2,Str3;
Str1 ="c";
Str2 ="d";
Str3 ="e";
if(Str1 <Str2)
$display(" Str1 < Str2 ");
if(Str1 <=Str2)
$display(" Str1 <= Str2 ");
if(Str3 >Str2)
$display(" Str3 > Str2");
if(Str3 >=Str2)
$display(" Str3 >= Str2");
end
endprogram
RESULT
Str1 < Str2
Str1 <= Str2
Str3 > Str2
Str3 >= Str2

Concatenation.
Syntax:{Str1,Str2,...,Strn}
Each operand can be of type string or a string literal (it shall be implicitly converted
to type string). If at least one operand is of type string, then the expression evaluates
to the concatenated string and is of type string. If all the operands are string literals,
then the expression behaves like a Verilog concatenation of integral types; if the
result is then used in an expression involving string types, it is implicitly converted to
the string type.
EXAMPLE
programmain;
initial
begin
stringStr1,Str2,Str3,Str4,Str5;
Str1 ="WWW.";
Str2 ="TEST";
Str3 ="";
Str4 ="BENCH";
Str5 =".IN";
$display(" %s ",{Str1,Str2,Str3,Str4,Str5});
end
endprogram
RESULT
WWW.TESTBENCH.IN
Replication.
Syntax :{multiplier{Str}}
Str can be of type string or a string literal. Multiplier must be of integral type and can
be nonconstant. If multiplier is nonconstant or Str is of type string, the result is a
string containing N concatenated copies of Str, where N is specified by the multiplier.
If Str is a literal and the multiplier is constant, the expression behaves like numeric
replication in Verilog (if the result is used in another expression involving string types,
it is implicitly converted to the string type).
EXAMPLE
programmain;
initial
begin
stringStr1,Str2;
Str1 ="W";
Str2 =".TESTBENCH.IN";
$display(" %s ",{{3{Str1}},Str2});
end
endprogram
RESULT
WWW.TESTBENCH.IN
Indexing.
Syntax:Str[index]
Returns a byte, the ASCII code at the given index. Indexes range from 0 to N-1, where
N is the number of characters in the string. If given an index out of range, returns 0.
Semantically equivalent to Str.getc(index)
EXAMPLE
programmain;
initial
begin
stringStr1;
Str1 ="WWW.TESTBENCH.IN";
for(inti =0;i <16;i++)
$write("%s ",Str1[i]);
end
endprogram
RESULT
WWW.TESTBENCH.IN
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Index
Introduction
Data Types
SystemVerilog
Systemverilog allos the user to define datatypes. There are different ways to define Literals
Verification
Strings
user defined datatypes. They are
Constructs
1.Class.
Enumarations
2.Enumarations.
Interface
3.Struct.
OOPS
Typedef
4.Union.
Arrays
5.Typedef.
Randomization
Array Methods
Functional Coverage
Dynamic Arrays
Associative Arrays
Assertion
Queues
DPI
Linked List
UVM Tutorial
Casting
VMM Tutorial
Data Declaration
Reg And Logic
OVM Tutorial
Operators 1
Easy Labs : SV
Operators 2
Operator Precedency
Easy Labs : UVM
Events
Easy Labs : OVM
Control Statements
Easy Labs : VMM
Program Block
Procedural Blocks
AVM Switch TB
Fork Join
VMM Ethernet sample
Fork Control
Subroutines
Semaphore
Mailbox
Verilog
Fine Grain Process
Verification
Control
TUTORIALS
USERDEFINED DATATYPES
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
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with time!
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TUTORIALS
ENUMARATIONS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
You'll sometimes be faced with the need for variables that have a limited set of
possible values that can be usally referred to by name.For example, the state
variable like IDLE,READY,BUZY etx of state machine can only have the all the states
defined and Refraining ordisplayingthese states using the state name will be more
comfortable. There's a specific facility, called an enumeration in SystemVerilog .
Enumerated data types assign a symbolic name to each legal value taken by the data
type.Let's create an example using one of the ideas I just mentioned-a state
machine .
You can define this as follows:
enum{IDLE,READY,BUZY}states;
This declares an enumerated data type called states, and variables of this type can
only have values from the set that appears between the braces, IDLE,READY and
BUZY. If you try to set a variable of type states to a value that isn't one of the values
specified, it will cause an error. Enumerated data type are strongly typed.
Easy Labs : UVM
One more advantage of enumerated datatypesis that if you don't initialize then ,
each one would have a unique value. By defaule they are int types.In the previous
examples, IDLE is 0, READY is 1 and BUZY is 2. These values can be printed as values
Easy Labs : VMM
or strings.
The values can be set for some of the names and not set for other names. A name
AVM Switch TB
without a value is automatically assigned an increment of the value of the previous
VMM Ethernet sample name. The value of first nameby default is 0.
Easy Labs : OVM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
// c is automatically assigned the increment-value of 8

enum{a=3,b=7,c}alphabet;
// Syntax error: c and d are both assigned 8

enum{a=0,b=7,c,d=8}alphabet;
// a=0, b=7, c=8

enum{a,b=7,c}alphabet;
Enumarated Methods:
Switch TB
RVM Switch TB
SystemVerilog includes a set of specialized methods to enable iterating over the
RVM Ethernet sample values of enumerated.
The first() method returns the value of the first member of the enumeration.
Specman E
Interview Questions
The last() method returns the value of the last member of the enumeration.
The next() method returns the Nth next enumeration value (default is the next one)
starting from the current value of the given variable.
The prev() method returns the Nth previous enumeration value (default is the
previous one) starting from the current value of the given variable.
The name() method returns the string representation of the given enumeration value.
If the given value is not a member of the enumeration, the name() method returns the
empty string.
http://testbench.in/SV_06_ENUMARATIONS.html[9/26/2012 2:01:54 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
EXAMPLE : ENUM methods

moduleenum_method;
typedefenum{red,blue,green}colour;
colour c;
initial
begin
c =c.first();
$display(" %s ",c.name);
c =c.next();
c =c.last();
c =c.prev();
end
endmodule
RESULTS :
red
blue
green
blue
Enum Numerical Expressions
Elements of enumerated type variables can be used in numerical expressions. The
value used in the expression is the numerical value associated with the enumerated
value.
An enum variable or identifier used as part of an expression is automatically cast to
the base type of the enum declaration (either explicitly or using int as the default). A
cast shall be required for an expression that is assigned to an enum variable where
the type of the expression is not equivalent to the enumeration type of the variable.
EXAMPLE:
moduleenum_method;
colour c,d;
inti;
initial
begin
$display("%s",c.name());
d =c;
$display("%s",d.name());
d =colour'(c +1);// use casting
$display("%s",d.name());
i =d;// automatic casting
$display("%0d",i);
c =colour'(i);
$display("%s",c.name());
end
endmodule
RESULT
red
red
blue
1
blue
TIP: If you want to use X or Z as enum values, then define it using 4-state data type
explicitly.
enuminteger{IDLE,XX='x,S1='b01,S2='b10}state,next;
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TUTORIALS
STRUCTURES AND UNIOUNS
SystemVerilog
Structure:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
The disadvantage of arrays is that all the elements stored in then are to be of the
same data type. If we need to use a collection of different data types, it is not
possible using an array. When we require using a collection of different data items of
different data types we can use a structure.Structure is a method of packing data of
different types. A structure is a convenient method of handling a group of related
data items of different data types.
struct{
inta;
byteb;
bit[7:0]c;
}my_data_struct;
The keyword "struct" declares a structure to holds the details of four fields namely a,b
and c. These are members of the structures. Each member may belong to different or
same data type. The structured variables can be accessed using the variable name
"my_data_struct".
my_data_struct.a =123;
$display(" a value is %d ",my_data_struct.a);
Assignments To Struct Members:
A structureliteral must have a type, which may be either explicitly indicated with a
prefix or implicitly indicated by anassignment-like context.
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
Verification
my_data_struct =`{1234,8'b10,8'h20};
Verilog Switch TB
Structure literals can also use member name and value, or data type and default
value.
Basic Constructs
my_data_struct =`{a:1234,default:8'h20};
OpenVera
Constructs
Union
Unions like structure contain members whose individual data types may differ from
one another. However the members that compose a union all share the same storage
RVM Switch TB
area.A union allows us to treat the same space in memory as a number of different
RVM Ethernet sample variables. That is a Union offers a way for a section of memory to be treated as a
variable of one type on one occasion and as a different variable of a different type on
another occasion.
Switch TB
Specman E
Interview Questions
union{
inta;
byteb;
bit[7:0]c;
}my_data;
memory allocation for the above defined struct "my_data_struct".
http://testbench.in/SV_07_STRUCTURES_AND_UNIOUNS.html[9/26/2012 2:02:03 PM]

input is what keeps
with time!
Memory allocation for the above defined union "my_data_union".
Packed Structures:
In verilog , it is not convenient for subdividing a vector into subfield. Accessing
subfield requires the index ranges.
For example
reg[0:47]my_data;
`definea_indx 16:47
`defineb_indx 8:15
`definec_indx 0:7
my_data[`b_indx]=8'b10;// writing to subfield b

$display(" %d ",my_data[à_indx]);// reading subfield a
A packed structure is a mechanism for subdividing a vector into subfields that can be
conveniently accessed as members. Consequently, a packed structure consists of bit
fields, which are packed together in memory without gaps.A packed struct or union
type must be declared explicitly using keyword "packed".
structpacked{
integera;
byteb;
bit[0:7]c;
}my_data;
my_data.b =8'b10;
$display("%d",my_data.a);
Memory allocation for the above defined packed struct "my_data".
One or more bits of a packed structure can be selected as if it were a packed array,
assuming an [n-1:0] numbering:
My_data [15:8]// b
If all members of packed structure are 2-state, the structure as a whole is treated as
a 2-state vector.
If all members of packed structure is 4-state, the structure as a whole is treated as a
4-state vector.
If there are also 2-state members, there is an implicit conversion from 4-state to 2state when reading those members, and from 2-state to 4-state when writing them.
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Index
Introduction
Data Types
SystemVerilog
A typedef declaration lets you define your own identifiers that can be used in place of Literals
Verification
type specifiers such as int, byte, real.Let us see an example of creating data type Strings
Constructs
"nibble".
Enumarations
Interface
typedefbit[3:0]nibble;// Defining nibble data type.
OOPS
Typedef
Arrays
nibble a,b;// a and b are variables with nibble data types.
Randomization
Array Methods
Functional Coverage
Dynamic Arrays
Advantages Of Using Typedef :
Associative Arrays
Assertion
Queues
Shorter
names
are
easier
to
type
and
reduce
typing
errors.
DPI
Improves readability by shortening complex declarations.
Linked List
UVM Tutorial
Improves understanding by clarifying the meaning of data.
Changing a data type in one place is easier than changing all of its uses throughout Casting
VMM Tutorial
Data Declaration
the code.
Reg And Logic
OVM Tutorial
Allows defining new data types using structs, unions and Enumerations also.
Operators 1
Increases
reusability.
Easy Labs : SV
Operators 2
Useful is type casting.
Operator Precedency
Easy Labs : UVM
Events
Example
oftypedef
using
struct,
union
and
enum
data
types.
Easy Labs : OVM
Control Statements
Easy Labs : VMM
Program Block
typedefenum{NO,YES}boolean;
Procedural Blocks
typedefunion{inti;shortrealf;}num;// named union type
AVM Switch TB
Fork Join
typedefstruct{
VMM Ethernet sample bitisfloat;
Fork Control
Subroutines
union{inti;shortrealf;}n;// anonymous type
Semaphore
}tagged_st;// named structure
Mailbox
Verilog
Fine Grain Process
boolean
myvar;//
Enum
type
variable
Verification
Control
numn; // Union type variable
Verilog Switch TB
tagged_st a[9:0];// array of structures
TUTORIALS
TYPEDEF
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_08_TYPEDEF.html[9/26/2012 2:02:14 PM]

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TUTORIALS
ARRAYS
SystemVerilog
Arrays hold a fixed number of equally-sized data elements. Individual elements are
accessed by index using a consecutive range of integers.Some type of arrays allows
to access individual elements using non consecutive values of any data types.Arrays
can be classified as fixed-sized arrays (sometimes known as static arrays) whose size
cannot change once their declaration is done, or dynamic arrays, which can be
resized.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Fixed Arrays:
"Packed array" to refer to the dimensions declared before the object name and
"unpacked array" refers to the dimensions declared after the object name.
SystemVerilog accepts a single number, as an alternative to a range, to specify the
size of an unpacked array. That is, [size] becomes the same as [0:size-1].
intArray[8][32];is the same as:intArray[0:7][0:31];
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
// Packed Arrays
reg[0:10]vari;// packed array of 4-bits
wire[31:0][1:0]vari;// 2-dimensional packed array
// Unpacked Arrays
wirestatus[31:0];// 1 dimensional unpacked array
wirestatus[32];// 1 dimensional unpacked array
integermatrix[7:0][0:31][15:0];// 3-dimensional unpacked array of integers

integermatrix[8][32][16];// 3-dimensional unpacked array of integers
reg[31:0]registers1 [0:255];// unpacked array of 256 registers; each

reg[31:0]registers2 [256]; // register is packed 32 bit wide
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_09_ARRAYS.html[9/26/2012 2:02:26 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
Operations On Arrays
The following operations can be performed on all arrays, packed or unpacked:
register1 [6][7:0]=`1; // Packed indexes can be sliced
register1 =~register1 ; // Can operate on entire memory
register1 =register2 ;// Reading and writing the entire array
register1[7:4]=register2[3:0]// Reading and writing a slice of the array
register1[4+:i]=register2[4+;i]// Reading and writing a variable slice
if(register1 ==register2) //Equality operations on the entire array
intn[1:2][1:3]=`{`{0,1,2},`{4,4,3}};// multidimensional assignment
inttriple [1:3]=`{1:1,default:0};// indexes 2 and 3 assigned 0
Accessing Individual Elements Of Multidimensional Arrays:
In a list of multi dimensions, the rightmost one varies most rapidly than the left most
one.Packed dimension varies more rapidly than an unpacked.
In the following example, each dimension is having unique range and reading and
writing to a element shows exactly which index corresponds to which dimension.
moduleindex();
bit[1:5][10:16]foo [21:27][31:38];
initial
begin
foo[24][34][4][14]=1;
$display(" foo[24][34][4][14] is %d ",foo[24][34][4][14]);
end
endmodule
The result of reading from an array with an out of the address bounds or if any bit in
the address is X or Z shall return the default uninitialized value for the array element
type.
As in Verilog, a comma-separated list of array declarations can be made. All arrays in
the list shall have the same data type and the same packed array dimensions.
modulearray();
bit[1:5][10:16]foo1 [21:27][31:38],foo2 [31:27][33:38];
initial
begin
$display("
dimensions
of
foo1
is
%d
foo2
is
%d",$dimensions(foo1),$dimensions(foo2));
$display(" reading with out of bound resulted %d",foo1[100][100][100][100]);
$display(" reading with index x resulted %d",foo1[33][1'bx]);
end
endmodule
RESULT:
dimensions of foo1 is 4 foo2 is 4
reading with out of bound resulted x
reading with index x resulted x
bit[3:4][5:6]Array [0:2];
Accessing "Array[2]" will access 4 elements Array[2][3][5],Array[2][3][6],Array[2][4][5]
and Array[2][4][6].
Accessing "Array[1][3]" will access 2 elements Array[1][3][5] and Array[1][3][6].
Accessing "Array[0][3][6]" will access one element.
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Index
Introduction
Data Types
SystemVerilog
Literals
Array Methods:
Verification
Strings
Constructs
Systemverilog provides various kinds of methods that can be used on arrays. They are Userdefined Datatypes
Enumarations
Interface
Array
querying
functions
OOPS
Typedef
Array Locator Methods
Arrays
Randomization
Array ordering methods
Array Methods
Functional Coverage
Array reduction methods
Dynamic Arrays
Iterator index querying
Associative Arrays
Assertion
Queues
DPI
Array Querying Functions:
Linked List
UVM Tutorial
Casting
VMM Tutorial
SystemVerilog provides new system functions to return information about an array. Data Declaration
They are
Reg And Logic
OVM Tutorial
Operators 1
Easy Labs : SV
$left
Operators 2
Operator Precedency
Easy Labs : UVM
$left shall return the left bound (MSB) of the dimension.
Events
Easy Labs : OVM
Control Statements
Easy Labs : VMM
$right
Program Block
Procedural Blocks
AVM Switch TB
$right shall return the right bound (LSB) of the dimension.
Fork Join
VMM Ethernet sample
Fork Control
$low
Subroutines
Semaphore
$low shall return the minimum of $left and $right of the dimension.
Mailbox
Verilog
Fine Grain Process
Verification
$high
Control
TUTORIALS
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
ARRAY METHODS
$high shall return the maximum of $left and $right of the dimension.

$increment
input is what keeps
$increment shall return 1 if $left is greater than or equal to $right and -1 if $left is with time!
less than $right.

$size
$size shall return the number of elements in the dimension, which is equivalent to
RVM Ethernet sample $high - $low +1.
$dimensions
Specman E
Interview Questions
$dimensions shall return the total number of dimensions in the array.
EXAMPLE : arrays
modulearr;
bit[2:0][3:0]arr [4:0][5:0];
initial
begin
$display(" $left %0d $right %0d $low %0d $high %0d $increment %0d $size %0d
$dimensions
http://testbench.in/SV_10_ARRAY_METHODS.html[9/26/2012 2:02:34 PM]
%0d",$left(arr),$right(arr),$low(arr),$high(arr),$increment(arr),$size(arr),$dimensions(arr)
);
end
endmodule
RESULTS :
$left 4 $right 0 $low 0 $high 4 $increment 1 $size 5 $dimensions 4
Array Locator Methods:
Array locator methods operate on any unpacked array, including queues, but their
return type is a queue. These locator methods allow searching an array for elements
(or their indexes) that satisfies a given expression. Array locator methods traverse the
array in an unspecified order. The optional "with" expression should not include any
side effects; if it does, the results are unpredictable.
The following locator methods are supported (the "with" clause is mandatory) :
find()
find() returns all the elements satisfying the given expression
find_index()
find_index() returns the indexes of all the elements satisfying the given expression
find_first()
find_first() returns the first element satisfying the given expression
find_first_index()
find_first_index() returns the index of the first element satisfying the given expression
find_last()
find_last() returns the last element satisfying the given expression
find_last_index()
find_last_index() returns the index of the last element satisfying the given expression
For the following locator methods the "with" clause (and its expression) can be
omitted if the relational operators (<, >, ==) are defined for the element type of the
given array. If a "with" clause is specified, the relational operators (<, >, ==) must be
defined for the type of the expression.
min()
min() returns the element with the minimum value or whose expression evaluates to a
minimum
max()
max() returns the element with the maximum value or whose expression evaluates to
a maximum
unique()
unique() returns all elements with unique values or whose expression is unique
unique_index()
unique_index() returns the indexes of all elements with unique values or whose
expression is unique
EXAMPLE :
modulearr_me;
stringSA[10],qs[$];
intIA[*],qi[$];
initial
begin
SA[1:5]={"Bob","Abc","Bob","Henry","John"};
IA[2]=3;
IA[3]=13;
IA[5]=43;
IA[8]=36;
IA[55]=237;
IA[28]=39;
// Find all items greater than 5
qi =IA.find(x )with(x >5);
for(intj =0;j <qi.size;j++)$write("%0d_",qi[j]);
$display("");
// Find indexes of all items equal to 3
qi =IA.find_indexwith(item ==3);
$display("");
// Find first item equal to Bob
qs =SA.find_firstwith(item =="Bob");
for(intj =0;j <qs.size;j++)$write("%s_",qs[j]);
$display("");
// Find last item equal to Henry
qs =SA.find_last(y )with(y =="Henry");
$display("");
// Find index of last item greater than Z
qi =SA.find_last_index(s )with(s >"Z");
$display("");
// Find smallest item
qi =IA.min;
$display("");
// Find string with largest numerical value
qs =SA.maxwith(item.atoi);
$display("");
// Find all unique strings elements
qs =SA.unique;
$display("");
// Find all unique strings in lowercase
qs =SA.unique(s )with(s.tolower);
end
endmodule
RESULTS :
13_43_36_39_237_
2_
Bob_
Henry_
3_
_
_Bob_Abc_Henry_John_
_Bob_Abc_Henry_John_
Array Ordering Methods:
Array ordering methods can reorder the elements of one-dimensional arrays or
queues. The following ordering methods are supported:
reverse()
reverse() reverses all the elements of the packed or unpacked arrays.
sort()
sort() sorts the unpacked array in ascending order, optionally using the expression in
the with clause.
rsort()
rsort() sorts the unpacked array in descending order, optionally using the with clause
expression.
shuffle()
shuffle() randomizes the order of the elements in the array.
EXAMPLE:
modulearr_order;strings[]='{"one","two","three"};
initial
begin
s.reverse;
for(intj =0;j <3;j++)$write("%s",s[j]);
s.sort;
s.rsort;
s.shuffle;
end
endmodule
RESULT:
three two one
one three two
two three one
three one two
Array Reduction Methods :
Array reduction methods can be applied to any unpacked array to reduce the array to
a single value. The expression within the optional "with" clause can be used to specify
the item to use in the reduction.The following reduction methods are supported:
sum()
sum() returns the sum of all the array elements.
product()
product() returns the product of all the array elements
and()
and() returns the bit-wise AND ( & ) of all the array elements.
or()
or() returns the bit-wise OR ( | ) of all the array elements
xor()
xor() returns the logical XOR ( ^ ) of all the array elements.

EXAMPLE:
modulearray_redu();
byteb[]={1,2,3,4};
intsum,product,b_xor;
initial
begin
sum=b.sum;// y becomes 10 => 1 + 2 + 3 + 4
product=b.product;// y becomes 24 => 1 * 2 * 3 * 4
b_xor =b.xorwith(item +4);// y becomes 12 => 5 ^ 6 ^ 7 ^ 8
$display(" Sum is %0d, product is %0d, xor is %0b ",sum,product,b_xor);
end
endmodule
RESULT
Sum is 10, product is 24, xor is 1100
Iterator Index Querying:
The expressions used by array manipulation methods sometimes need the actual array
indexes at each iteration, not just the array element. The index method of an iterator
returns the index value of the specified dimension.
// find all items equal to their position (index)
q =arr.findwith(item ==item.index);
// find all items in mem that are greater than corresponding item in mem2
q =mem.find(x )with(x >mem2[x.index(1)][x.index(2)]);
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TUTORIALS
DYNAMIC ARRAYS
SystemVerilog
Verilog does not allow changing the dimensions of the array once it is declared.Most
of the time in verification, we need arrays whose size varies based on the some
behavior. For example Ethernet packet varies length from one packet to other packet.
In verilog, for creating Ethernet packet, array with Maximum packet size is declared
and only the number of elements which are require for small packets are used and
unused elements are waste of memory.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
To overcome this deficiency, System Verilog provides Dynamic Array. A dynamic array
is unpacked array whose size can be set or changed at runtime unlike verilog which
needs size at compile time.Dynamic arrays allocate storage for elements at run time
along with the option of changing the size.
Declaration Of Dynmic Array:
VMM Tutorial
integerdyna_arr_1[],dyn_arr_2[],multi_dime_dyn_arr[][];
OVM Tutorial
Allocating Elements:
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Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
New[]:The built-in function new allocates the storage and initializes the newly
allocated array elements either to their default initial value.
dyna_arr_1 =new[10];// Allocating 10 elements
multi_dime_dyn_arr =new[4];// subarrays remain unsized and uninitialized
Initializing Dynamic Arrays:
Verification
The size argument need not match the size of the initialization array. When the
initialization array<92>s size is greater, it is truncated to match the size argument;
when it is smaller, the initialized array is padded with default values to attain the
specified size.
Verilog Switch TB
dyna_arr_2 =new[4]('{4,5,6});// elements are {4,5,6,0}
Verilog
Basic Constructs
OpenVera
Constructs

input is what keeps
Using new[] constructor and its argument, we can increase the array size without Testbench.in improving
with time!
losing the data content.
Resizing Dynamic Arrays:
Switch TB
Dyna_arr_1 =new[100](dyna_arr_1);// Previous 10 data preserved
RVM Switch TB
Copying Elements:
RVM Ethernet sample
Specman E
Interview Questions
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
Copy constructor of dynamic arrays is an easy and faster way of creating duplicate
copies of data.
Dyna_arr_2 =new[100](dyna_arr_1);// allocating and copying 100 elements.
Dyna_arr_1 =[1000];// Previous data lost. 1000 elements are allocated.
http://testbench.in/SV_11_DYNAMIC_ARRAYS.html[9/26/2012 2:02:43 PM]
RESULT
4
8
0
The information about the size of the dynamic array is with the array itself. It can be
obtained using .size() method. This will be very helpful when you are playing with
array. You don't need to pass the size information explicitly. We can also use system
task $size() method instead of .size() method. SystemVerilog also provides delete()
method clears all the elements yielding an empty array (zero size).
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TUTORIALS
ASSOCIATIVE ARRAYS
SystemVerilog
Dynamic arrays are useful for dealing with contiguous collections of variables whose
number changes dynamically. Associative arrays give you another way to store
information. When the size of the collection is unknown or the data space is sparse,
an associative array is a better option. In Associative arrays Elements Not Allocated
until Used.Index Can Be of Any Packed Type, String or Class. Associative elements
are stored in an order that ensures fastest access.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
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VMM Tutorial
OVM Tutorial
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In an associative array a key is associated with a value. If you wanted to store the
information of various transactions in an array, a numerically indexed array would not
be the best choice. Instead, we could use the transaction names as the keys in
associative array, and the value would be their respective information. Using
associative arrays, you can call the array element you need using a string rather than
a number, which is often easier to remember.
The syntax to declare an associative array is:
data_type array_id [key _type];
data_type is the data type of the array elements.
array_id is the name of the array being declared.
key_type is the data-type to be used as an key.
Examples of associative array declarations are:
intarray_name[*];//Wildcard index. can be indexed by any integral datatype.

intarray_name [string];// String index
VMM Ethernet sample intarray_name [some_Class ];// Class index
intarray_name [integer];// Integer index
typedefbitsigned[4:1]Nibble;
intarray_name [Nibble ];// Signed packed array
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Elements in associative array elements can be accessed like those of one dimensional
arrays. Associative array literals use the '{index:value} syntax with an optional default Report a Bug or Comment
index.
//associative array of 4-state integers indexed by strings, default is '1.
integertab [string]='{"Peter":20,"Paul":22,"Mary":23,default:-1};
Switch TB
Associative Array Methods
RVM Switch TB
SystemVerilog provides several methods which allow analyzing and manipulating
RVM Ethernet sample associative arrays. They are:
Specman E
Interview Questions
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
The num() or size() method returns the number of entries in the associative array.
The delete() method removes the entry at the specified index.
The exists() function checks whether an element exists at the specified index within
the given array.
The first() method assigns to the given index variable the value of the first (smallest)
index in the associative array. It returns 0 if the array is empty; otherwise, it returns
1.
The last() method assigns to the given index variable the value of the last (largest)
index in the associative array. It returns 0 if the array is empty; otherwise, it returns
1.
The next() method finds the entry whose index is greater than the given index. If
there is a next entry, the index variable is assigned the index of the next entry, and
the function returns 1. Otherwise, the index is unchanged, and the function returns 0.
The prev() function finds the entry whose index is smaller than the given index. If
http://testbench.in/SV_12_ASSOCIATIVE_ARRAYS.html[9/26/2012 2:02:55 PM]
input is what keeps

with time!
there is a previous entry, the index variable is assigned the index of the previous
entry, and the function returns 1. Otherwise, the index is unchanged, and the
function returns 0.
EXAMPLE
moduleassoc_arr;
inttemp,imem[*];
initial
begin
imem[2'd3]=1;
imem[16'hffff]=2;
imem[4'b1000]=3;
$display("%0d entries",imem.num);
if(imem.exists(4'b1000))
$display("imem.exists( 4b'1000) ");
imem.delete(4'b1000);
if(imem.exists(4'b1000))
$display(" imem.exists( 4b'1000) ");
else
$display(" ( 4b'1000) not existing");
if(imem.first(temp))
$display(" First entry is at index %0db ",temp);
if(imem.next(temp))
$display(" Next entry is at index %0h after the index 3",temp);
// To print all the elements alone with its indexs
if(imem.first(temp))
do
$display("%d : %d",temp,imem[temp]);
while(imem.next(temp));
end
endmodule
RESULT
3 entries
imem.exists( 4b'1000)
( 4b'1000) not existing
First entry is at index 3b
Next entry is at index ffff after the index 3
3 : 1
65535 : 2
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TUTORIALS
QUEUES
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
A queue is a variable-size, ordered collection of homogeneous elements. A Queue is

analogous to one dimensional unpacked array that grows and shrinks automatically.
Queues can be used to model a last in, first out buffer or first in, first out buffer.
Queues support insertion and deletion of elements from random locations using an
index. Queues Can be passed to tasks / functions as ref or non-ref arguments. Type
checking is also done.
Queue Operators:
Queues and dynamic arrays have the same assignment and argument passing
semantics. Also, queues support the same operations that can be performed on
unpacked arrays and use the same operators and rules except as defined below:
VMM Tutorial
intq[$]={2,4,8};
intp[$];
inte,pos;
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e =q[0];//read the first (leftmost) item
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e =q[$];//read the last (rightmost) item
q[0]=e;//write the first item
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p =q; //read and write entire queue (copy)
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q ={q,6};// insert '6' at the end (append 6)
q ={e,q };// insert 'e' at the beginning (prepend e)
AVM Switch TB
q =q[1:$];// delete the first (leftmost) item
VMM Ethernet sample q =q[0:$-1];// delete the last (rightmost) item
q =q[1:$-1];// delete the first and last items
q ={};// clear the queue (delete all items)
q ={q[0:pos-1],e,q[pos,$]}; // insert 'e' at position pos
Verilog
q ={q[0:pos],e,q[pos+1,$]}; // insert 'e' after position pos
Verification
OVM Tutorial
Verilog Switch TB
Basic Constructs
Queue Methods:
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
In addition to the array operators, queues provide several built-in methods. They are: on This section - Your
input is what keeps
The size() method returns the number of items in the queue. If the queue is empty, it Testbench.in improving
OpenVera
with time!
returns 0.
Constructs
The insert() method inserts the given item at the specified index position.
The delete() method deletes the item at the specified index.
Switch TB
The pop_front() method removes and returns the first element of the queue.
RVM Switch TB
The pop_back() method removes and returns the last element of the queue.
RVM Ethernet sample The push_front() method inserts the given element at the front of the queue.
The push_back() method inserts the given element at the end of the queue.
Specman E
Interview Questions
EXAMPLE
modulequeues;
bytequ [$];
initial
begin
qu.push_front(2);
qu.push_front(12);
qu.push_front(22);
qu.push_back(11);
qu.push_back(99);
http://testbench.in/SV_13_QUEUES.html[9/26/2012 2:03:03 PM]
$display(" %d ",qu.size());
$display(" %d ",qu.pop_front());
$display(" %d ",qu.pop_back());
qu.delete(3);
$display(" %d ",qu.size());
end
endmodule
RESULTS :
5
22
99
Dynamic Array Of Queues Queues Of Queues
EXAMPLE:
moduletop;
typedefintqint_t[$];
// dynamic array of queues
qint_t DAq[];// same as int DAq[][$];
// queue of queues
qint_t Qq[$];// same as int Qq[$][$];
// associative array of queues
qint_t AAq[string];// same as int AAq[string][$];
initialbegin
// Dynamic array of 4 queues
DAq =new[4];
// Push something onto one of the queues
DAq[2].push_back(1);
// initialize another queue with three entries
DAq[0]={1,2,3};
$display("%p",DAq);
// Queue of queues -two
Qq={{1,2},{3,4,5}};
Qq.push_back(qint_t'{6,7});
Qq[2].push_back(1);
$display("%p",Qq);
// Associative array of queues
AAq["one"]={};
AAq["two"]={1,2,3,4};
AAq["one"].push_back(5);
$display("%p",AAq);
end
endmodule:top
RESULTS:
'{'{1, 2, 3}, '{}, '{1}, '{}}
'{'{1, 2}, '{3, 4, 5}, '{6, 7, 1}}
'{one:'{5}, two:'{1, 2, 3, 4} }
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TUTORIALS
SystemVerilog
COMPARISON OF ARRAYS
Verification
Static Array
Constructs
Size should be known at compilation time.

Time require to access any element is less.
if not all elements used by the application, then memory is wasted.
Not good for sparse memory or when the size changes.
Good for contagious data.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Associativearray
No need of size information at compile time.
Time require to access an element increases with size of the array.
Compact memory usage for sparse arrays.
User don't need to keep track of size. It is automatically resized.
Good inbuilt methods for Manipulating and analyzing the content.
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Dynamicarray
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To set the size or resize, the size should be provided at runtime.
Performance to access elements is same as Static arrays.
AVM Switch TB
Good for contagious data.
VMM Ethernet sample Memory usage is very good, as the size can be changed dynamically.
Easy Labs : VMM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Queues
Performance to access elements is same as Static arrays.
User doesn't need to provide size information to change the size. It is automatically
resized.
Rich set of inbuilt methods for Manipulating and analyzing the content.
Useful in self-checking modules. Very easy to work with out of order transactions.
Inbuilt methods for sum of elements, sorting all the elements.
Searching for elements is very easy even with complex expressions.
Useful to model FIFO or LIFO.
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_14_COMPARISON_OF_ARRAYS.html[9/26/2012 2:03:12 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
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TUTORIALS
LINKED LIST
SystemVerilog
The List package implements a classic list data-structure, and is analogous to the STL
(Standard Template Library) List container that is popular with C++ programmers. The
container is defined as a parameterized class, meaning that it can be customized to
hold data of any type. The List package supports lists of any arbitrary predefined
type, such as integer, string, or class object. First declare the Linked list type and
then take instances of it. SystemVerilog has many methods to operate on these
instances.
A double linked list is a chain of data structures called nodes.Each node has 3
members, one points to the next item or points to a null value if it is last node, one
points to the previous item or points to a null value if it is first node and other has the
data.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
The disadvantage of the linked list is that data can only be accessed sequentially and
not in random order. To read the 1000th element of a linked list, you must read the
999 elements that precede it.
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
List Definitions:
list :- A list is a doubly linked list, where every element has a predecessor and
successor. It is a sequence that supports both forward and backward traversal, as well
as amortized constant time insertion and removal of elements at the beginning, end,
or middle.
container :- A container is a collection of objects of the same type .Containers are
objects that contain and manage other objects and provide iterators that allow the
contained objects (elements) to be addressed. A container has methods for accessing
its elements. Every container has an associated iterator type that can be used to
iterate through the containers elements.
iterator :- Iterators provide the interface to containers. They also provide a means to
traverse the container elements. Iterators are pointers to nodes within a list. If an
iterator points to an object in a range of objects and the iterator is incremented, the
iterator then points to the next object in the range.
Procedure To Create And Use List:
Specman E
1.include the generic List class declaration
Interview Questions
ìnclude<List.vh>
2.Declare list variable
List#(integer)il;// Object il is a list of integer
3.Declaring list iterator
List_Iterator#(integer)itor;//Object s is a list-of-integer iterator
List_iterator Methods
http://testbench.in/SV_15_LINKED_LIST.html[9/26/2012 2:03:22 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
The List_Iterator class provides methods to iterate over the elements of lists.
The next() method changes the iterator so that it refers to the next element in the
list.
The prev() method changes the iterator so that it refers to the previous element in
the list.
The eq() method compares two iterators and returns 1 if both iterators refer to the
same list element.
The neq() method is the negation of eq().
The data() method returns the data stored in the element at the given iterator
location.
List Methods
The List class provides methods to query the size of the list; obtain iterators to the
head or tail of the list;
retrieve the data stored in the list; and methods to add, remove, and reorder the
elements of the list.
The size() method returns the number of elements stored in the list.
The empty() method returns 1 if the number elements stored in the list is zero and 0
otherwise.
The push_front() method inserts the specified value at the front of the list.
The push_back() method inserts the specified value at the end of the list.
The front() method returns the data stored in the first element of the list.
The back() method returns the data stored in the last element of the list.
The pop_front() method removes the first element of the list.
The pop_back() method removes the last element of the list.
The start() method returns an iterator to the position of the first element in the list.
The finish() method returns an iterator to a position just past the last element in the
list.
The insert() method inserts the given data into the list at the position specified by the
iterator.
The insert_range() method inserts the elements contained in the list range specified
by the iterators first and last at the specified list position.
The erase() method removes from the list the element at the specified position.
The erase_range() method removes from a list the range of elements specified by the
first and last iterators.
The set() method assigns to the list object the elements that lie in the range specified
by the first and last iterators.
The swap() method exchanges the contents of two equal-size lists.
The clear() method removes all the elements from a list, but not the list itself.
The purge() method removes all the list elements (as in clear) and the list itself.
EXAMPLE
modulelists();
List#(integer)List1;
List_Iterator#(integer)itor;
initialbegin
List1 =new();
$display(" size of list is %d
List1.push_back(10);
List1.push_front(22);
$display(" size of list is %d
$display(" poping from list
$display(" poping from list
\n",List1.size());
\n",List1.size());
: %d \n",List1.front());
: %d \n",List1.front());
List1.pop_front();
List1.pop_front();
$display(" size of list is %d \n",List1.size());
List1.push_back(5);
$display(" size of list is %d \n",List1.size());
itor =List1.start();
$display(" startn of list %d \n",itor.data());
itor.next();
$display(" second element of list is %d \n",itor.data());
itor.next();
$display(" third element of list is %d \n",itor.data());
itor.next();
$display(" fourth element of list is %d \n",itor.data());
itor =List1.erase(itor);
$display(" after erasing element,the itor element of list is %d \n",itor.data());
itor.prev();
$display(" prevoious element is %d \n",itor.data());
end
endmodule
RESULT:
size of list is 0
size of list is 2
poping from list : 22
size of list is 0
size of list is 4
startn of list 5
second element of list is 55
third element of list is 555
fourth element of list is 5555
after erasing element,the itor element of list is x
prevoious element is 555
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TUTORIALS
CASTING
SystemVerilog
Verilog is loosely typed . Assignments can be done from one data type to other data
types based on predefined rules.The compiler only checks that the destination
variable and source expression are scalars. Otherwise, no type checking is done at
compile time. Systemverilog has complex data types than Verilog.It's necessary for
SystemVerilog to be much stricter about type conversions than Verilog, so
Systemverilog provided the cast(`) operator, which specifies the type to use for a
specific expression. Using Casting one can assign values to variables that might not
ordinarily be valid because of differing data type. SystemVerilog adds 2 types of
casting. Static casting and dynamic casting.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
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Easy Labs : OVM
Easy Labs : VMM
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Static Casting
A data type can be changed by using a cast ( ' ) operation. In a static cast, the
expression to be cast shall be enclosed in parentheses that are prefixed with the
casting type and an apostrophe. If the expression is assignment compatible with the
casting type, then the cast shall return the value that a variable of the casting type
would hold after being assigned the expression.
EXAMPLE:
int'(2.0*3.0)
shortint'{{8'hFA,8'hCE}}
signed'(x)
17'(x -2)
VMM Ethernet sample Dynamic Casting
Verilog
Verification
Verilog Switch TB
Basic Constructs
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
SystemVerilog provides the $cast system task to assign values to variables that might
not ordinarily be valid because of differing data type. $cast can be called as either a
task or a function.
The syntax for $cast is as follows:
function int $cast( singular dest_var, singular source_exp );
or
task $cast( singular dest_var, singular source_exp );
input is what keeps
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
The dest_var is the variable to which the assignment is made. The source_exp is the Testbench.in improving
expression that is to be assigned to the destination variable. Use of $cast as either a with time!
task or a function determines how invalid assignments are handled. When called as a
task, $cast attempts to assign the source expression to the destination variable. If the
assignment is invalid, a run-time error occurs, and the destination variable is left
unchanged.
EXAMPLE:
typedefenum{red,green,blue,yellow,white,black }Colors;
Colors col;
$cast(col,2+3);
Cast Errors
Following example shows the compilation error.
EXAMPLE:
moduleenum_method;
colour c,d;
inti;
initial
http://testbench.in/SV_16_CASTING.html[9/26/2012 2:03:29 PM]
begin
d =(c +1);
end
endmodule
RESULT
Illegal assignment
Following example shows the simulation error. This is compilation error free. In this
example , d is assigned c + 10 , which is out of bound in enum colour.
EXAMPLE:
moduleenum_method;
colour c,d;
inti;
initial
begin
$cast(d,c +10);
end
endmodule
RESULT
Dynamic cast failed
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TUTORIALS
DATA DECLARATION
SystemVerilog
Scope And Lifetime:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Global :
SystemVerilog adds the concept of global scope. Any declarations and definitions
which is declared outside a module, interface, task, or function, is global in scope.
Global variables have a static lifetime (exists for the whole elaboration and simulation
time). Datatypes, tasks,functions, class definitions can be in global scope. Global
members can be referenced explicitly via the $root . All these can be accessed from
any scope as this is the highest scope and any other scope will be below the global.
Local :
Local declarations and definitions are accessible at the scope where they are defined
and below. By default they are static in life time. They can be made to automatic. To
access these local variables which are static, hierarchical pathname should be used.
intst0; //Static. Global Variable. Declared outside module
taskdisp(); //Static. Global Task.
modulemsl;
intst0; //static. Local to module
initialbegin
intst1; //static. Local to module
VMM Ethernet sample staticintst2;//static. Local to Module
automaticintauto1;//automatic.
end
Verilog
taskautomatict1();//Local task definition.
Verification
intauto2; //automatic. Local to task
Verilog Switch TB
staticintst3;//static.Local to task. Hierarchical path access allowed
automaticintauto3;//automatic. Local to task
Basic Constructs
$root.st0 =st0; //$root.sto is global variable, st0 is local to module.
OpenVera
endtask
Constructs
endmodule
AVM Switch TB
Switch TB
RVM Switch TB
Alias:
RVM Ethernet sample The Verilog assign statement is a unidirectional assignment. To model a bidirectional
short-circuit connection it is necessary to use the alias statement.
Specman E
Interview Questions
This example strips out the least and most significant bytes from a four byte bus:
modulebyte_rip (inoutwire[31:0]W,inoutwire[7:0]LSB,MSB);
aliasW[7:0]=LSB;
aliasW[31:24]=MSB;
endmodule
Data Types On Ports:
Verilog restricts the data types that can be connected to module ports. Only net types
are allowed on the receiving side and Nets, regs or integers on the driving side.
SystemVerilog removes all restrictions on port connections.Any data type can be
used on either side of the port. Real numbers, Arrays, Structures can also be passed
http://testbench.in/SV_17_DATA_DECLARATION.html[9/26/2012 2:03:39 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
through ports.
Parameterized Data Types:
Verilog allowed only values to be parameterized.SystemVerilog allows data types to
be "parameterized".A data-type parameter can only be set to a data-type.
modulefoo #(parametertypeVAR_TYPE=integer);
foo #(.VAR_TYPE(byte))bar ();
Declaration And Initialization:
integeri =1;
In Verilog, an initialization value specified as part of the declaration is executed as if
the assignment were made from an initial block, after simulation has started.This
creates an event at time 0 and it is same as if the assiginment is done in initial block.
In Systemverilog , setting the initial value of a static variable as part of the variable
declaration is done before initial block and so does not generate an event.
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TUTORIALS
REG AND LOGIC
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Historically, Verilog used the terms wire and reg as a descriptive way to declare wires
and registers. The original intent was soon lost in synthesis and verification coding
styles, which soon gave way to using terns Nets and Variables in Verilog-2001. The
keyword reg remained in SystemVerilog, but was now misleading its intent.
SystemVerilog adds the keyword logic as a more descriptive term to remind users that
it is not a hardware register. logic and reg are equivalent types.
SystemVerilog extended the variable type so that, it can be used to connect gates and
modules. All variables can be written either by one continuous assignment, or by one
or more procedural statements. It shall be an error to have multiple continuous
assignments or a mixture of procedural and continuous assignments.
Now we saw logic and wire are closer. Wire (net) is used when driven by multiple
drivers, where as logic is used when it is driven by only one driver. logic just holds the
last value assigned to it, while a wire resolves its value based on all the drivers.
Easy Labs : SV
For example:
Easy Labs : UVM
logicabc;
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
The following statements are legal assignments to logic abc:

1)assignabc =sel ?1:0;
VMM Ethernet sample 2)not(abc,pqr),
3)always#10abc =~abc;
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_18_REG_AND_LOGIC.html[9/26/2012 2:03:52 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
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TUTORIALS
OPERATORS 1
SystemVerilog
The SystemVerilog operators are a combination of Verilog and C operators. In both

languages, the type and size of the operands is fixed, and hence the operator is of a
fixed type and size. The fixed type and size of operators is preserved in
SystemVerilog. This allows efficient code generation.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Verilog does not have assignment operators or increment and decrement operators.
SystemVerilog includes the C assignment operators, such as +=, and the C increment
and decrement operators, ++ and --.
Verilog-2001 added signed nets and reg variables, and signed based literals. There is a
difference in the rules for combining signed and unsigned integers between Verilog
and C. SystemVerilog uses the Verilog rules.
Operators In Systemverilog
OVM Tutorial
Easy Labs : SV
Following are the operators in systemverilog
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_19_OPERATORS_1.html[9/26/2012 2:04:02 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
Assignment Operators
In addition to the simple assignment operator, =, SystemVerilog includes the C
assignment operators and special bitwise assignment operators:
+=,-=,*=,/=,%=,&=,|=,^=,<<=,>>=,<<<=,>>>=.
An assignment operator is semantically equivalent to a blocking assignment, with the
exception that any left-hand side index expression is only evaluated once.
For example:
a[i]+=2;// same as a[i] = a[i] +2;
Following are the new SystemVerilog assignment operators and its equivalent in
verilog
Assignments In Expression
In SystemVerilog, an expression can include a blocking assignment. such an
assignment must be enclosed in parentheses to avoid common mistakes such as using
a=b for a==b, or a|=b for a!=b.
if((a=b))b =(a+=1);// assign b to a
a =(b =(c =5));// assign 5 to c
if(a=b)// error in systemverilog

(a=b) statement assigns b value to a and then returns a value.
if((a=b)) is equivalent to
a=b;
if(a)
EXAMPLE
moduleassignment();
inta,b,c;
initialbegin
a =1;b =2;c =3;
if((a=b))
$display(" a value is %d ",a);
a =(b =(c =5));
$display(" a is %d b is %d c is %d ",a,b,c);
end
endmodule
RESULT
a value is 2
a is 5 b is 5 c is 5
Concatenation :
{} concatenation right of assignment.
{} concatenation left of assignment.
EXAMPLE :Concatenation
programmain ;
bit[4:0]a;
regb,c,d;
initialbegin
b =0;
c =1;
d =1;
a ={b,c,0,0,d};
{b,c,d}=3'b111;
$display(" a %b b %b c %b d %b ",a,b,c,d);
end
endprogram
RESULTS
a 00001 b 1 c 1 d 1
Arithmetic:
EXAMPLE :Arithmetic
programmain;
integera,b;
initial
begin
b =10;
a =22;
$display(" -(nagetion) is %0d",-(a));

$display(" a + bis %0d",a+b);
$display(" a - bis %0d",a-b);
$display(" a * bis %0d",a*b);
$display(" a / bis %0d",a/b);
$display(" a modulus bis %0d",a%b);
end
endprogram
RESULTS
-(nagetion) is -22
a + bis 32
a - bis 12
a * bis 220
a / bis 2
a modules b is 2
Following tabel shows the opwer operator rules for calculating the result.
programmain;
integerop1_neg,op1_n1,op1_0,op1_p1,op1_pos;
integerop2_pos_odd,op2_pos_even,op2_zero,op2_neg_odd,op2_neg_even;
initial
begin
op1_neg =-10;op1_n1 =-1;op1_0 =0;op1_p1 =1;op1_pos =10;
op2_pos_odd
=9;op2_pos_even
=10;op2_zero=0;op2_neg_odd
=-9;op2_neg_even=-10;
$display(" | -10-101 10");
$display("---|--------------------------------------------------------");
$display("9|
%d
%d
%d
%d
%d",op1_neg**op2_pos_odd,op1_n1**op2_pos_odd,op1_0**op2_pos_odd,op1_p1**op2_pos_odd,op1_pos**op2_pos_odd
);
$display("
10|
%d
%d
%d
%d
%d",op1_neg**op2_pos_even,op1_n1**op2_pos_even,op1_0**op2_pos_even,op1_p1**op2_pos_even,op1_pos**op2_pos_even
);
$display("0|
%d
%d
%d
%d
%d",op1_neg**op2_zero,op1_n1**op2_zero,op1_0**op2_zero,op1_p1**op2_zero,op1_pos**op2_zero
);
$display("
-9|
%d
%d
%d
%d
%d",op1_neg**op2_neg_odd,op1_n1**op2_neg_odd,op1_0**op2_neg_odd,op1_p1**op2_neg_odd,op1_pos**op2_neg_odd
);
$display("-10|
%d
%d
%d
%d
%d",op1_neg**op2_neg_even,op1_n1**op2_neg_even,op1_0**op2_neg_even,op1_p1**op2_neg_even,op1_pos**op2_neg_even
);
end
endprogram
RESULT
| -10-101 10
---|-------------------------------------------------------9| 3294967296 429496729501 1000000000
10| 1410065408101 1410065408
0|11111
-9|0 4294967295x10
-10|01x10
Relational:
# > >= < <=relational
EXAMPLE :Relational
programmain ;
integera,b;
initial
begin
b =10;
a =22;
$display(" a < bis %0d\n",a <b);

$display(" a > bis %0d\n",a >b);
$display(" a <= bis %0d\n",a <=b);
$display(" a >= bis %0d\n",a >=b);
end
endprogram
RESULTS
a < bis 0
a > bis 1
a <= bis 0
a >= bis 1
Equality:
The different types of equality (and inequality) operators in SystemVerilog behave

differently when their operands contain unknown values (X or Z). The == and !=
operators may result in X if any of their operands contains an X or Z. The === and !==
check the 4-state explicitly, therefore, X and Z values shall either match or mismatch,
never resulting in X. The ==? and !=? operators may result in X if the left operand
contains an X or Z that is not being compared with a wildcard in the right operand.
EXAMPLE : logical Equality
programmain;
reg[3:0]a;
reg[7:0]x,y,z;
initialbegin
a =4'b0101;
x =8'b1000_0101;
y =8'b0000_0101;
z =8'b0xx0_0101;
if(x ==a)
$display("x equals a is TRUE.\n");
if(y ==a)
$display("y equals a is TRUE.\n");
if(z ==a)
$display("z equals a is TRUE.\n");
end
endprogram
RESULTS:
y equals a is TRUE.
EXAMPLE:case equality:
programmain ;
rega_1,a_0,a_x,a_z;
regb_1,b_0,b_x,b_z;
initial
begin
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
$display("--------------------------");
$display(" ==01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 ==b_0,a_0 ==b_1,a_0 ==b_x,a_0 ==b_z);
$display(" 1 %b %b %b %b ",a_1 ==b_0,a_1 ==b_1,a_1 ==b_x,a_1 ==b_z);
$display(" x %b %b %b %b ",a_x ==b_0,a_x ==b_1,a_x ==b_x,a_x ==b_z);
$display(" z %b %b %b %b ",a_z ==b_0,a_z ==b_1,a_z ==b_x,a_z ==b_z);
$display("--------------------------");
$display("--------------------------");
$display(" === 01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 ===b_0,a_0 ===b_1,a_0 ===b_x,a_0
===b_z);
$display(" 1 %b %b %b %b ",a_1 ===b_0,a_1 ===b_1,a_1 ===b_x,a_1
===b_z);
$display(" x %b %b %b %b ",a_x ===b_0,a_x ===b_1,a_x ===b_x,a_x
===b_z);
$display(" z %b %b %b %b ",a_z ===b_0,a_z ===b_1,a_z ===b_x,a_z
===b_z);
$display("--------------------------");
$display("--------------------------");
$display(" =?= 01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 =?=b_0,a_0 =?=b_1,a_0 =?=b_x,a_0 =?
=b_z);
$display(" 1 %b %b %b %b ",a_1 =?=b_0,a_1 =?=b_1,a_1 =?=b_x,a_1 =?
=b_z);
$display(" x %b %b %b %b ",a_x =?=b_0,a_x =?=b_1,a_x =?=b_x,a_x =?
=b_z);
$display(" z %b %b %b %b ",a_z =?=b_0,a_z =?=b_1,a_z =?=b_x,a_z =?
=b_z);
$display("--------------------------");
$display("--------------------------");
$display(" !=01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0
!=b_0,a_0!=b_1,a_0!=b_x,a_0!=b_z);
$display(" 1 %b %b %b %b ",a_1
!=b_0,a_1!=b_1,a_1!=b_x,a_1!=b_z);
$display(" x %b %b %b %b ",a_x !=b_0,a_x!=b_1,a_x!=b_x,a_x!=b_z);
$display(" z %b %b %b %b ",a_z !=b_0,a_z!=b_1,a_z!=b_x,a_z!=b_z);
$display("--------------------------");
$display("--------------------------");
$display(" !== 01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 !==b_0,a_0 !==b_1,a_0 !==b_x,a_0
!==b_z);
$display(" 1 %b %b %b %b ",a_1 !==b_0,a_1 !==b_1,a_1 !==b_x,a_1
!==b_z);
$display(" x %b %b %b %b ",a_x !==b_0,a_x !==b_1,a_x !==b_x,a_x
!==b_z);
$display(" z %b %b %b %b ",a_z !==b_0,a_z !==b_1,a_z !==b_x,a_z
!==b_z);
$display("--------------------------");
$display("--------------------------");
$display(" !?= 01xz");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 !?=b_0,a_0 !?=b_1,a_0 !?=b_x,a_0 !?
=b_z);
$display(" 1 %b %b %b %b ",a_1 !?=b_0,a_1 !?=b_1,a_1 !?=b_x,a_1 !?
=b_z);
$display(" x %b %b %b %b ",a_x !?=b_0,a_x !?=b_1,a_x !?=b_x,a_x !?
=b_z);
$display(" z %b %b %b %b ",a_z !?=b_0,a_z !?=b_1,a_z !?=b_x,a_z !?
=b_z);
$display("--------------------------");
end
endprogram
RESULTS
------------------------- ==01xz
-------------------------0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
------------------------- ------------------------- === 01xz
-------------------------0 1 0 0 0
1 0 1 0 0
x 0 0 1 0
z 0 0 0 1
------------------------- ------------------------- =?= 01xz
-------------------------0 1 0 1 1
1 0 1 1 1
x 1 1 1 1
z 1 1 1 1
--------------------------
------------------------- !=01xz
-------------------------0 0 1 x x
1 1 0 x x
x x x x x
z x x x x
------------------------- ------------------------- !== 01xz
-------------------------0 0 1 1 1
1 1 0 1 1
x 1 1 0 1
z 1 1 1 0
------------------------- ------------------------- !?= 01xz
-------------------------0 0 1 0 0
1 1 0 0 0
x 0 0 0 0
z 0 0 0 0
--------------------------
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TUTORIALS
OPERATORS 2
SystemVerilog
Logical :
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
SystemVerilog added two new logical operators logical implication (->), and logical
equivalence (<->). The logical implication expression1 -> expression2 is logically
equivalent to (!expression1 || expression2), and the logical equivalence expression1
<-> expression2 is logically equivalent to ((expression1 -> expression2) &&
(expression2 -> expression1)).
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
EXAMPLE : Logical
programmain ;
rega_1,a_0,a_x,a_z;
regb_1,b_0,b_x,b_z;
OpenVera
initialbegin
Constructs
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
Switch TB
$display("--------------------------");
RVM Switch TB
$display(" && 0 1 x z");
RVM Ethernet sample $display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 &&b_0,a_0 &&b_1,a_0
&&b_z);
$display(" 1 %b %b %b %b ",a_1 &&b_0,a_1 &&b_1,a_1
Specman E
&&b_z);
$display(" x %b %b %b %b ",a_x &&b_0,a_x &&b_1,a_x
Interview Questions
&&b_z);
$display(" z %b %b %b %b ",a_z &&b_0,a_z &&b_1,a_z
&&b_z);
$display("--------------------------");
$display("--------------------------");
$display(" || 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 ||b_0,a_0 ||b_1,a_0
||b_z);
$display(" 1 %b %b %b %b ",a_1 ||b_0,a_1 ||b_1,a_1

input is what keeps
with time!
Basic Constructs
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
&&b_x,a_0
&&b_x,a_1
&&b_x,a_x
&&b_x,a_z
||b_x,a_0
||b_x,a_1
||b_z);
$display(" x %b %b %b %b ",a_x ||b_0,a_x ||b_1,a_x ||b_x,a_x
||b_z);
$display(" z %b %b %b %b ",a_z ||b_0,a_z ||b_1,a_z ||b_x,a_z
||b_z);
$display("--------------------------");
$display("--------------------------");
$display(" ! 0 1 x z");
$display("--------------------------");
$display(" %b %b %b %b ",!b_0,!b_1,!b_x,!b_z);
$display("--------------------------");
end
endprogram
RESULTS
-------------------------&& 0 1 x z
-------------------------0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
--------------------------------------------------|| 0 1 x z
-------------------------0 0 1 x x
1 1 1 1 1
x x 1 x x
z x 1 x x
--------------------------------------------------! 0 1 x z
------------------------- 1 0 x x
-------------------------Bitwise :
In Systemverilog, bitwise exclusive nor has two notations (~^ and ^~).
EXAMPLE : Bitwise
programmain ;
rega_1,a_0,a_x,a_z;
regb_1,b_0,b_x,b_z;
initialbegin
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
$display("--------------------------");
$display(" ~ 0 1 x z");
$display("--------------------------");
$display(" %b %b %b %b ",~b_0,~b_1,~b_x,~b_z);
$display("--------------------------");
$display("--------------------------");
$display(" & 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 &b_0,a_0 &b_1,a_0 &b_x,a_0 &b_z);
$display(" 1 %b %b %b %b ",a_1 &b_0,a_1 &b_1,a_1 &b_x,a_1 &b_z);
$display(" x %b %b %b %b ",a_x &b_0,a_x &b_1,a_x &b_x,a_x &b_z);
$display(" z %b %b %b %b ",a_z &b_0,a_z &b_1,a_z &b_x,a_z &b_z);
$display("--------------------------");
$display("--------------------------");
$display(" &~ 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 &~b_0,a_0 &~b_1,a_0 &~b_x,a_0
&~b_z);
$display(" 1 %b %b %b %b ",a_1 &~b_0,a_1 &~b_1,a_1 &~b_x,a_1
&~b_z);
$display(" x %b %b %b %b ",a_x &~b_0,a_x &~b_1,a_x &~b_x,a_x
&~b_z);
$display(" z %b %b %b %b ",a_z &~b_0,a_z &~b_1,a_z &~b_x,a_z
&~b_z);
$display("--------------------------");
$display("--------------------------");
$display(" | 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 |b_0,a_0 |b_1,a_0 |b_x,a_0 |b_z);
$display(" 1 %b %b %b %b ",a_1 |b_0,a_1 |b_1,a_1 |b_x,a_1 |b_z);
$display(" x %b %b %b %b ",a_x |b_0,a_x |b_1,a_x |b_x,a_x |b_z);
$display(" z %b %b %b %b ",a_z |b_0,a_z |b_1,a_z |b_x,a_z |b_z);
$display("--------------------------");
$display(" |~ 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 |~b_0,a_0 |~b_1,a_0 |~b_x,a_0 |~b_z);
$display(" 1 %b %b %b %b ",a_1 |~b_0,a_1 |~b_1,a_1 |~b_x,a_1 |~b_z);
$display(" x %b %b %b %b ",a_x |~b_0,a_x |~b_1,a_x |~b_x,a_x |~b_z);
$display(" z %b %b %b %b ",a_z |~b_0,a_z |~b_1,a_z |~b_x,a_z |~b_z);
$display("--------------------------");
$display("--------------------------");
$display(" ^ 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 ^b_0,a_0 ^b_1,a_0 ^b_x,a_0 ^b_z);
$display(" 1 %b %b %b %b ",a_1 ^b_0,a_1 ^b_1,a_1 ^b_x,a_1 ^b_z);
$display(" x %b %b %b %b ",a_x ^b_0,a_x ^b_1,a_x ^b_x,a_x ^b_z);

$display(" z %b %b %b %b ",a_z ^b_0,a_z ^b_1,a_z ^b_x,a_z ^b_z);
$display("--------------------------");
$display(" ^~ 0 1 x z");
$display("--------------------------");
$display(" 0 %b %b %b %b ",a_0 ^~b_0,a_0 ^~b_1,a_0 ^~b_x,a_0 ^~b_z);
$display(" 1 %b %b %b %b ",a_1 ^~b_0,a_1 ^~b_1,a_1 ^~b_x,a_1 ^~b_z);
$display(" x %b %b %b %b ",a_x ^~b_0,a_x ^~b_1,a_x ^~b_x,a_x ^~b_z);
$display(" z %b %b %b %b ",a_z ^~b_0,a_z ^~b_1,a_z ^~b_x,a_z ^~b_z);
$display("--------------------------");
end
endprogram
RESULTS
------------------------- ~ 0 1 x z
------------------------- 1 0 x x
-------------------------------------------------- & 0 1 x z
------------------------- 0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
-------------------------------------------------- &~ 0 1 x z
------------------------- 0 0 0 0 0
1 1 0 x x
x x 0 x x
z x 0 x x
-------------------------------------------------- | 0 1 x z
------------------------- 0 0 1 x x
1 1 1 1 1
x x 1 x x
z x 1 x x
------------------------- |~ 0 1 x z
------------------------- 0 1 0 x x
1 1 1 1 1
x 1 x x x
z 1 x x x
-------------------------------------------------- ^ 0 1 x z
------------------------- 0 0 1 x x
1 1 0 x x
x x x x x
z x x x x
------------------------- ^~ 0 1 x z
------------------------- 0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
-------------------------Reduction :
EXAMPLE : Reduction
programmain ;
reg[3:0]a_1,a_0,a_01xz,a_1xz,a_0xz,a_0dd1,a_even1;
initial
begin
a_1 =4'b1111;
a_0 =4'b0000;
a_01xz=4'b01xz;
a_1xz =4'b11xz;
a_0xz =4'b00xz;
a_0dd1=4'b1110;
a_even1 =4'b1100;
$display("-------------------------------------------");
$display(" a_1 a_0 a_01xz a_1xz a_0xz");
$display("-------------------------------------------");
$display("& %b %b %b %b
%b",&a_1,&a_0,&a_01xz,&a_1xz,&a_0xz);
$display("| %b %b %b %b
%b",|a_1,|a_0,|a_01xz,|a_1xz,|a_0xz);
$display("~&%b %b %b %b
%b",~&a_1,~&a_0,~&a_01xz,~&a_1xz,~&a_0xz);
$display("~|%b %b %b %b
%b",~|a_1,~|a_0,~|a_01xz,~|a_1xz,~|a_0xz);
$display("-------------------------------------------");
$display("a_ood1 a_even1a_1xz");
$display("-------------------------------------------");
$display(" ^ %b %b%b",â_0dd1,â_even1,â_1xz);
$display(" ~^%b %b%b",~â_0dd1,~â_even1,~â_1xz);
$display("-------------------------------------------");
end
endprogram
RESULTS
------------------------------------------ a_1 a_0 a_01xz a_1xz a_0xz
------------------------------------------&100x0
|1011x
~& 011x1
~| 0100x
------------------------------------------a_ood1 a_even1a_1xz
------------------------------------------ ^ 1 0x
~^0 1x
------------------------------------------
Shift :
The left shift operators, << and <<<, shall shift their left operand to the left by the
number by the number of bit positions given by the right operand. In both cases, the
vacated bit positions shall be filled with zeros. The right shift operators, >> and >>>,
shall shift their left operand to the right by the number of bit positions given by the
right operand. The logical right shift shall fill the vacated bit positions with zeros.
The arithmetic right shift shall fill the vacated bit positions with zeros if the result
type is unsigned. It shall fill the vacated bit positions with the value of the most
significant (i.e., sign) bit of the left operand if the result type is signed. If the right
operand has an x or z value, then the result shall be unknown. The right operand is
always treated.
EXAMPLE :Shift
programmain ;
integera_1,a_0;
initialbegin
a_1 =4'b1100;
a_0 =4'b0011;
$display(" << by 1a_1is %b a_0 is %b",a_1 <<1,a_0 <<1);

$display(" >> by 2a_1is %b a_0 is %b",a_1 >>2,a_0 >>2);
$display(" <<< by 1a_1is %b a_0 is %b",a_1 <<<1,a_0 <<<1);
$display(" >>> by 2a_1is %b a_0 is %b",a_1 >>>2,a_0 >>>2);
end
endprogram
RESULTS
<< by 1a_1is 1000 a_0 is 0110
>> by 2a_1is 0011 a_0 is 0000
<<< by 1a_1is 1000 a_0 is 0110
>>> by 2a_1is 1111 a_0 is 0000
Increment And Decrement :
# ++ increment
# -- decrement
SystemVerilog includes the C increment and decrement assignment operators ++i, --i,
i++, and i--. These do not need parentheses when used in expressions. These
increment and decrement assignment operators behave as blocking assignments.
The ordering of assignment operations relative to any other operation within an
expression is undefined. An implementation can warn whenever a variable is both
written and read-or-written within an integral expression or in other contexts where
an implementation cannot guarantee order of evaluation.
For example:
i = 10;
j = i++ + (i = i - 1);
After execution, the value of j can be 18, 19, or 20 depending upon the relative
ordering of the increment and the assignment statements. The increment and
decrement operators, when applied to real operands, increment or decrement the
operand by 1.0.
EXAMPLE : Increment and Decrement
programmain ;
integera_1,a_0;
initialbegin
a_1=20;
a_0=20;
a_1 ++;
a_0 --;
$display(" a_1 is %d a_0 is %d ",a_1,a_0);
end
endprogram
RESULTS
a_1 is21 a_0 is19
Set :
# inside !inside dist
SystemVerilog supports singular value sets and set membership operators.
The syntax for the set membership operator is:
inside_expression ::= expression inside { open_range_list }
The expression on the left-hand side of the inside operator is any singular expression.
The set-membership open_range_list on the right-hand side of the inside operator is a
comma-separated list of expressions or ranges. If an expression in the list is an
aggregate array, its elements are traversed by descending into the array until
reaching a singular value. The members of the set are scanned until a match is found
and the operation returns 1'b1. Values can be repeated, so values and value ranges
can overlap. The order of evaluation of the expressions and ranges is nondeterministic.
EXAMPLE : Set
programmain ;
integeri;
initialbegin
i =20;
if(i inside{10,20,30})
$display(" I is in 10 20 30 ");
end
endprogram
RESULTS
I is in 10 20 30
Streaming Operator
The streaming operators perform packing of bit-stream types into a sequenceof bits
in a user-specified order.
When used in the left-hand side ,the streaming operators perform the
reverseoperation,i.e.,unpack a stream of bits intoone ormore variables.
Re-Ordering Of The Generic Stream
The stream_operator << or >> determines the order in which blocks of data are
streamed.
>> causes blocks of data to be streamed in left-to-right order
<< causes blocks of data to be streamed in right-to-left order
For Example
intj ={"A","B","C","D"};
{>>{j}}// generates stream "A" "B" "C" "D"
{<<byte{j}}// generates stream "D" "C" "B" "A" (little endian)
{<<16{j}}// generates stream "C" "D" "A" "B"
{<<{8'b0011_0101}}// generates stream 'b1010_1100 (bit reverse)
{<<4{6'b11_0101}}// generates stream 'b0101_11
{>>4{6'b11_0101}}// generates stream 'b1101_01 (same)
{<<2{{<<{4'b1101}}}}// generates stream 'b1110
Packing Using Streaming Operator
Packing is performed by using the streaming operator on thr RHS of the expression.
For example:
intj ={"A","B","C","D"};
bit[7:0]arr;
arr ={>>{j}}
arr ={<<byte{j}}
arr ={<<16{j}}
arr ={<<{8'b0011_0101}}
arr ={<<4{6'b11_0101}}
arr ={>>4{6'b11_0101}}
arr ={<<2{{<<{4'b1101}}}}
Unpacking Using Streaming Operator
UnPacking is performed by using the streaming operator on thr LHS of the expression.
For example
inta,b,c;
logic[10:0]up [3:0];
logic[11:1]p1,p2,p3,p4;
bit[96:1]y ={>>{a,b,c }};// OK: pack a, b, c
intj ={>>{a,b,c }};// error: j is 32 bits < 96 bits
bit[99:0]d ={>>{a,b,c }};// OK: d is padded with 4 bits
{>>{a,b,c }}=23'b1;// error: too few bits in stream
{>>{a,b,c }}=96'b1;// OK: unpack a = 0, b = 0, c = 1
{>>{a,b,c }}=100'b1;// OK: unpack as above (4 bits unread)
{>>{p1,p2,p3,p4}}=up;// OK: unpack p1 = up[3], p2 = up[2],
// p3 = up[1], p4 = up[0]
Streaming Dynamically Sized Data

Stream ={<<byte{p.header,p.len,p.payload,p.crc}};// packing
Stream ={<<byte{p.header,p.len,p.payload with[0+:p.len],p.crc}};
{<<byte{p.header,p.len,p.payload
with[0+:p.len],p.crc
}}=stream;//unpacking
q ={<<byte{p}};// packing all the contents of an object.( p is a object )
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TUTORIALS
OPERATOR PRECEDENCY
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
()Highest precedence
++ -& ~& | ~| ^ ~^ ~ >< (unary)
* / %
+ << >>
< <= > >= in !in dist
=?= !?= == != === !==
& &~
^ ^~
| |~
&&
||
?:
= += -= *= /= %=
<<= >>= &= |= ^= ~&= ~|= ~^=Lowest precedence
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SV_21_OPERATOR_PRECEDENCY.html[9/26/2012 2:04:23 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
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TUTORIALS
EVENTS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
An identifier declared as an event data type is called a named event. Named event is
a data type which has no storage. In verilog, a named event can be triggered
explicitly using "->" . Verilog Named Event triggering occurrence can be recognized by
using the event control "@" . Named events and event control give a powerful and
efficient means of describing the communication between, and synchronization of,
two or more concurrently active processes.
SystemVerilog named events support the same basic operations as verilog named
event, but enhance it in several ways.
Triggered
The "triggered" event property evaluates to true if the given event has been triggered
in the current time-step and false otherwise. If event_identifier is null, then the
triggered event property evaluates to false. Using this mechanism, an event trigger
shall unblock the waiting process whether the wait executes before or at the same
simulation time as the trigger operation.
In the following example, event "e" is triggered at time 20,40,60,80 . So the Value of
"e.triggered" should be TRUE at time 20,40,60,80 and FALSE at rest of the time.
AVM Switch TB
VMM Ethernet sample EXAMPLE:
modulemain;
evente;
Verilog
initial
Verification
repeat(4)
Verilog Switch TB
begin
#20;
Basic Constructs
->e ;
$display(" e is triggered at %t ",$time);
end
OpenVera
Constructs
initial
#100$finish;
Switch TB
RVM Switch TB
always
RVM Ethernet sample begin
#10;
if(e.triggered)
$display(" e is TRUE at %t",$time);
Specman E
else
$display(" e is FALSE at %t",$time);
Interview Questions
end
endmodule
RESULT
e
e
e
e
is
is
is
is
FALSE at 10
triggered at 20
TRUE at 20
FALSE at 30
http://testbench.in/SV_22_EVENTS.html[9/26/2012 2:04:32 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
e
e
e
e
e
e
e
e
e
is
is
is
is
is
is
is
is
is
triggered at 40
TRUE at 40
FALSE at 50
triggered at 60
TRUE at 60
FALSE at 70
triggered at 80
TRUE at 80
FALSE at 90
Wait()
In SystemVerilog , Named Event triggering occurrence can also be recognized by using
the event control wait(). Wait() statement gets blocked until it evaluates to TRUE.As
we have seen in the previous example, that "event_name.triggered" returns the
trigging status of the event in the current time step.
EXAMPLE:
moduleevent_m;
eventa;
initial
repeat(4)
#20->a;
always
begin
@a;
$display(" ONE:: EVENT A is triggered ");
end
always
begin
wait(a.triggered);
$display(" TWO:: EVENT A is triggered ");
#1;
end
endmodule
RESULT:
ONE:: EVENT A is triggered
TWO:: EVENT A is triggered
Race Condition
For a trigger to unblock a process waiting on an event, the waiting process must
execute the @ statement before the triggering process executes the trigger operator,
->. If the trigger executes first, then the waiting process remains blocked.
Using event_name.triggered statement, an event trigger shall unblock the waiting
process whether the wait executes before or at the same simulation time as the
trigger operation. The triggered event property, thus, helps eliminate a common race
condition that occurs when both the trigger and the wait (using @) happen at the
same time. A process that blocks waiting for an event might or might not unblock,
depending on the execution order of the waiting and triggering
processes (race condition) . However, a process that waits on the triggered state
always unblocks, regardless of the order of execution of the wait and trigger
operations.
In the following example, event "e1" is triggered and a process is waiting on "e1" in
the same time step. The process can never catch the triggering of "e1" as it occurs
after the event "e1" triggering. Event "e2" triggering occurrence can be recognized by
wait (e2.triggered) in spite of the above condition.
EXAMPLE:
modulemain;
evente1,e2;
initial
repeat(4)
begin
#20;
->e1 ;
@(e1)
$display(" e1 is triggered at %t ",$time);
end
initial
repeat(4)
begin
#20;
->e2 ;
wait(e2.triggered);
$display(" e2 is triggered at %t ",$time);
end
endmodule
RESULT
e2 is
e2 is
e2 is
e2 is
triggered
triggered
triggered
triggered
at 20
at 40
at 60
at 80
Nonblocking Event Trigger

Nonblocking events are triggered using the ->> operator. The effect of the ->>
operator is that the statement executes without blocking and it creates a nonblocking
assign update event in the time in which the delay control expires, or the eventcontrol occurs. The effect of this update event shall be to trigger the referenced
event in the nonblocking assignment region of the simulation cycle.
Merging Events
An event variable can be assigned to another event variable. When a event variable is
assigned to other , both the events point to same synchronization object. In the
following example, Event "a" is assigned to event "b" and when event "a" is triggered,
event occurrence can be seen on event "b" also.
EXAMPLE:
moduleevents_ab;
eventa,b;
initialbegin
#1->b;// trigger both always blocks
->a;
#10b =a;// merge events
#20->a;// both will trigger , 3 trigger events but have 4 trigger responses.
end
always@(a)begin
$display(" EVENT A is triggered ");
#20;
end
always@(b)begin
$display(" EVENT B is triggered ");
#20;
end
endmodule
RESULTS:
EVENT
EVENT
EVENT
EVENT
B is triggered
A is triggered
B is triggered
A is triggered
When events are merged, the assignment only affects the execution of subsequent
event control or wait operations. If a process is blocked waiting for event1 when
another event is assigned to event1, the currently waiting process shall never unblock.
In the following example, "always@(b)" is waiting for the event on "b" before the
assignment "b = a" and this waiting always block was never unblocked.
EXAMPLE:
moduleevents_ab;
eventa,b;
initial
begin
#20->a;
b =a;
#20->a;
end
always@(a)
$display(" EVENT A is triggered ");
always@(b)
$display(" EVENT B is also triggered ");
endmodule
RESULTS:
EVENT A is triggered
EVENT A is triggered
Null Events
SystemVerilog event variables can also be assigned a null object, when assigned null
to event variable, the association between the synchronization object and the event
variable is broken.
EXAMPLE:
programmain;
evente;
initial
begin
repeat(4)
#($random()%10)->e;
e =null;
repeat(4)
#($random()%10)->e;
end
initial
forever
begin
@e ;
$display(" e is triggered at %t",$time);
end
endprogram
RESULT:
e
e
e
e
is
is
is
is
triggered
triggered
triggered
triggered
at348
at 4967
at 9934
at14901
** ERROR **Accessed Null object

Wait Sequence
The wait_order construct suspends the calling process until all of the specified events
are triggered in the given order (left to right) or any of the un-triggered events are
triggered out of order and thus causes the operation to fail. Wait_order() does not
consider time, only ordering in considered.
EXAMPLE:
modulemain;
evente1,e2,e3;
initial
begin
#10;
->e1;
->e2;
->e3;
#10;
->e3;
->e1;
->e2;
#10;
->e3;
->e2;
->e3;
end
always
begin
wait_order(e1,e2,e3)
$display(" Events are in order ");
else
$display(" Events are out of order ");
end
endmodule
RESULT:
Events are in order
Events are out of order
Events are out of order
Events Comparison
Event variables can be compared against other event variables or the special value
null. Only the following operators are allowed for comparing event variables:
------
Equality (==) with another event or with null.

Inequality (!=) with another event or with null.
Case equality (===) with another event or with null (same semantics as ==).
Case inequality (!==) with another event or with null (same semantics as !=).
Test for a Boolean value that shall be 0 if the event is null and 1 otherwise.
EXAMPLE:
modulemain;
evente1,e2,e3,e4;
initial
begin
e1 =null;
e2 =e3;
if(e1)
$display(" e1 is not null ");
else
$display(" e1 is null ");
if(e2)
$display(" e2 is not null");
else
$display(" e2 is null");
if(e3 ==e4)
$display(" e3 and e4 are same events ");
else
$display(" e3 and e4 are not same events ");
if(e3 ==e2)
$display(" e3 and e2 are same events ");
else
$display(" e3 and e2 are not same events ");
end
endmodule
RESULT:
e1 is null
e2 is not null
e3 and e4 are not same events
e3 and e2 are same events
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Index
Introduction
Data Types
SystemVerilog
Sequential Control:
Literals
Verification
Strings
Statements inside sequential control constructs are executed
Constructs
sequentially.
Enumarations
Interface
- if-else Statement
OOPS
Typedef
- case Statement
Arrays
Randomization
- repeat loop
Array Methods
for
loop
Functional Coverage
Dynamic Arrays
- while loop
Associative Arrays
Assertion
- do-while
Queues
foreach
DPI
- Loop Control
Linked List
UVM Tutorial
- randcase Statements
Casting
VMM Tutorial
if-else Statement:The if-else statement is the general form of selection Data Declaration
Reg And Logic
OVM Tutorial
statement.
Operators 1
Easy Labs : SV
Operators 2
case Statement :The case statement provides for multi-way branching.
Operator Precedency
Easy Labs : UVM
Events
repeat
loop:Repeat
statements
can
be
used
to
repeat
the
execution
of
a
Easy Labs : OVM
Control Statements
statement or statement block a fixed number of times.
Easy Labs : VMM
Program Block
Procedural Blocks
for loop :The for construct can be used to create loops.
AVM Switch TB
Fork Join
VMM Ethernet sample while loop :The loop iterates while the condition is true.
Fork Control
Subroutines
Semaphore
do-while :condition is checked after loop iteration.
Mailbox
Verilog
Fine Grain Process
foreach:foreach
construct
specifies
iteration
over
the
elements
of
an
single
Verification
Control
dimensional fixed-size arrays, dynamic arrays and SmartQs.
TUTORIALS
Verilog Switch TB
Basic Constructs
CONTROL STATEMENTS
Loop Control :The break and continue statements are used for flow control Report a Bug or Comment
within loops.
input is what keeps
with time!
OpenVera
Constructs
EXAMPLE : if
programmain ;
RVM Switch TB
integeri;
RVM Ethernet sample initialbegin
i =20;
if(i ==20)
$display(" I is equal to %d ",i);
Specman E
else
$display(" I is not equal to %d ",i);
Interview Questions
end
endprogram
RESULTS
Switch TB
I is equal to 20
EXAMPLE : case and repeat

programmain ;
http://testbench.in/SV_23_CONTROL_STATEMENTS.html[9/26/2012 2:04:42 PM]
integeri;
initialbegin
repeat(10)begin
i =$random();
case(1)begin
(i<0) :$display(" i is less than zero i==%d\n",i);
(i>0) :$display(" i is grater than zero i=%d\n",i);
(i ==0):$display(" i is equal to zero i=%d\n",i);
end
end
end
endprogram
RESULTS
i is
i is
i is
i is
i is
i is
i is
i is
i is
i is
grater
grater
grater
grater
grater
grater
grater
grater
grater
grater
than
than
than
than
than
than
than
than
than
than
zero
zero
zero
zero
zero
zero
zero
zero
zero
zero
i=69120
i=475628600
i=1129920902
i=773000284
i=1730349006
i=1674352583
i=1662201030
i=2044158707
i=1641506755
i=797919327
EXAMPLE : forloop
programfor_loop;
integercount,i;
initialbegin
for(count =0,i=0;i*count<50;i++,count++)
$display("Value i = %0d\n",i);
end
endprogram
RESULTS
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
0
1
2
3
4
5
6
7
EXAMPLE : whileloop
programwhile_loop;
integeroperator=0;
initialbegin
while(operator<5)begin
operator +=1;
$display("Operator is %0d\n",operator);
end
end
endprogram
RESULTS
Operator
Operator
Operator
Operator
Operator
is
is
is
is
is
1
2
3
4
5
EXAMPLE : dowhile
programtest;
integeri =0;
initialbegin
do
begin
$display("i = %0d \n",i);
i++;
end
while(i <10);
end
endprogram
RESULTS
i=
i=
i=
i=
i=
i=
i=
i=
i=
i=
0
1
2
3
4
5
6
7
8
9
The foreach construct specifies iteration over the elements of an array. Its argument
is an identifier that designates any type of array (fixed-size, dynamic, or associative)
followed by a list of loop variables enclosed in square brackets. Each loop variable
corresponds to one of the dimensions of the array. The foreach construct is similar to
a repeat loop that uses the array bounds to specify the repeat count instead of an
expression.
The mapping of loop variables to array indexes is determined by the dimension
cardinality, as described in multidimentional topic.
The foreach arranges for higher cardinality indexes to change more rapidly.
//1 2 3 34 1 2 -> Dimension numbers
intA [2][3][4];bit[3:0][2:1]B [5:1][4];
foreach(A [i,j,k ])...
foreach(B [q,r,,s ])...
The first foreach causes i to iterate from 0 to 1, j from 0 to 2, and k from 0 to 3. The
second foreach causes q to iterate from 5 to 1, r from 0 to 3, and s from 2 to 1
(iteration over the third index is skipped).
EXAMPLE : foeach
programexample;
stringnames[$]={"Hello","SV"};
intfxd_arr[2][3]='{'{1,2,3},'{4,5,6}};
initialbegin
foreach(names[i])
$display("Value at index %0d is %0s\n",i,names[i]);
foreach(fxd_arr[,j])
$display(fxd_arr[1][j]);
end
endprogram
RESULTS
Value at index 0 is Hello

Value at index 1 is SV
4
5
6
EXAMPLE : randcase
programrand_case;
integeri;
initialbegin
repeat(10)begin
randcase
begin
10:i=1;
20:i=2;
50:i=3;
end
$display(" i is %d \n",i);end
end
endprogram
RESULTS
i is
i is
i is
i is
i is
i is
i is
i is
i is
i is
3
2
3
3
3
3
1
1
1
2
Enhanced For Loop

In Verilog, the variable used to control a for loop must be declared prior to the loop.
If loops in two or more parallel procedures use the same loop control variable, there is
a potential of one loop modifying the variable while other loops are still using it.
SystemVerilog adds the ability to declare the for loop control variable within the for
loop. This creates a local variable within the loop. Other parallel loops cannot
inadvertently affect the loop control variable.
For example:
modulefoo;
initialbegin
for(inti =0;i <=255;i++)
...
end
initialbegin
loop2:for(inti =15;i >=0;i--)
...
end
endmodule
Unique:
A unique if asserts that there is no overlap in a series of if...else...if conditions, i.e.,
they are mutually exclusive and hence it is safe for the expressions to be evaluated in
parallel. In a unique if, it shall be legal for a condition to be evaluated at any time
after entrance into the series and before the value of the condition is needed. A
unique if shall be illegal if, for any such interleaving of evaluation and use of the
conditions, more than one condition is true. For an illegal unique if, an
implementation shall be required to issue a warning, unless it can demonstrate a legal
interleaving so that no more than one condition is true.
EXAMPLE :
moduleuniq;
initial
begin
for(inta =0;a<6;a++)
uniqueif((a==0)||(a==1))$display("0 or 1");
elseif(a ==2)$display("2");
elseif(a ==4)$display("4");// values 3,5,6 cause a warning
end
endmodule
RESULTS:
0 or 1
0 or 1
2
RT Warning: No condition matches in 'unique if' statement.
4
RT Warning: No condition matches in 'unique if' statement.
Priority:
A priority if indicates that a series of if...else...if conditions shall be evaluated in the
order listed. In the preceding example, if the variable a had a value of 0, it would
satisfy both the first and second conditions, requiring priority logic. An
implementation shall also issue a warning if it determines that no condition is true, or
it is possible that no condition is true, and the final if does not have a corresponding
else.
EXAMPLE:
moduleprioriti;
initial
priorityif(a[2:1]==0)$display("0 or 1");
elseif(a[2]==0)$display("2 or 3");
else$display("4 to 7");//covers all other possible values, so no warning
endmodule
RESULTS:
0
0
2
2
4
4
4
or 1
or 1
or 3
or 3
to 7
to 7
to 7
If the case is qualified as priority or unique, the simulator shall issue a warning
message if no case item matches. These warnings can be issued at either compile time
or run time, as soon as it is possible to determine the illegal condition.
EXAMPLE:
modulecasee;
initial
begin
uniquecase(a)// values 3,5,6,7 cause a warning
0,1:$display("0 or 1");
2:$display("2");
4:$display("4");
endcase
prioritycasez(a)// values 4,5,6,7 cause a warning
3'b00?:$display("0 or 1");
3'b0??:$display("2 or 3");
endcase
end
endmodule
RESULTS:
0 or 1
0 or 1
2
Warning: No condition matches in 'unique case' statement.
0 or 1
0 or 1
2 or 3
2 or 3
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TUTORIALS
PROGRAM BLOCK
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
The module is the basic building block in Verilog which works well for Design.
However, for the testbench, a lot of effort is spent getting the environment properly
initialized and synchronized, avoiding races between the design and the testbench,
automating the generation of input stimuli, and reusing existing models and other
infrastructure.
Systemverilog adds a new type of block called program block. It is declared using
program and endprogram keywords.
The program block serves these basic purposes:
-> Separates the testbench from the DUT.
-> The program block helps ensure that test bench transitions do not have race
conditions with the design
-> It provides an entry point to the execution of testbenches.
-> It creates a scope that encapsulates program-wide data.
-> It provides a syntactic context that specifies scheduling in the Reactive region
which avoids races.
-> It doesnot allow always block. Only initial and methods are allowed, which are
more controllable.
-> Each program can be explicitly exited by calling the $exit system task. Unlike
$finish, which exits simulation immediately, even if there are pending events.
-> Just like a module, program block has ports. One or more program blocks can be
instantiated in a top-level netlist, and connected to the DUT.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
The program construct serves as a clear separator between design and testbench,
and, more importantly, it specifies specialized execution semantics in the Reactive
region for all elements declared within the program. Together with clocking blocks,
the program construct provides for race-free interaction between the design and the
testbench, and enables cycle and transaction level abstractions.
For example:
programtest (inputclk,input[16:1]addr,inout[7:0]data);
initial...
endprogram
RVM Ethernet sample programtest (interfacedevice_ifc );
initial...
endprogram
Specman E
Interview Questions
http://testbench.in/SV_24_PROGRAM_BLOCK.html[9/26/2012 2:04:53 PM]

input is what keeps
with time!
program schedules events in the Reactive region, the clocking block construct is very
useful to automatically sample the steady-state values of previous time steps or clock
cycles. Programs that read design values exclusively through clocking blocks with #0
input skews are insensitive to read-write races. It is important to note that simply
sampling input signals (or setting non-zero skews on clocking block inputs) does not
eliminate the potential for races. Proper input sampling only addresses a single
clocking block.With multiple clocks, the arbitrary order in which overlapping or
simultaneous clocks are processed is still a potential source for races.
Following example demonstrates the difference between the module based testbench
and program based testbenchs.
moduleDUT();
regq =0;
regclk =0;
initial
#10clk =1;
always@(posedgeclk)
q <=1;
endmodule
moduleModule_based_TB();
always@(posedgeDUT.clk)$display("Module_based_TB : q = %b\n",DUT.q);
endmodule
programProgram_based_TB();
initial
forever@(posedgeDUT.clk)$display("Program_based_TB : q = %b\n",DUT.q);
endprogram
RESULT:
Module_based_TB : q = 0
program_based_TB : q = 1
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Index
Introduction
Data Types
SystemVerilog
Final:
Literals
Verification
Verilog procedural statements are in initial or always blocks, tasks, or functions. Strings
Constructs
SystemVerilog adds a final block that executes at the end of simulation.SystemVerilog Userdefined Datatypes
final blocks execute in an arbitrary but deterministic sequential order. This is possible Enumarations
Interface
because final blocks are limited to the legal set of statements allowed for functions.
OOPS
Typedef
Arrays
Randomization
Array Methods
EXAMPLE
:
Functional Coverage
Dynamic Arrays
modulefini;
Associative Arrays
Assertion
Queues
initial
DPI
#100$finish;
Linked List
UVM Tutorial
Casting
final
VMM Tutorial
Data Declaration
$display(" END OF SIMULATION at %d ",$time);
Reg And Logic
OVM Tutorial
endmodule
Operators 1
RESULTS:
Easy Labs : SV
Operators 2
Operator Precedency
Easy Labs : UVM
END OF SIMULATION at100
Events
Easy Labs : OVM
Control Statements
Easy Labs : VMM
Program Block
Jump Statements:
Procedural Blocks
AVM Switch TB
Fork Join
SystemVerilog has statements to control the loop statements.
VMM Ethernet sample break: to go out of loop as C
Fork Control
Subroutines
continue : skip to end of loop as C
Semaphore
return expression : exit from a function
Mailbox
return: exit from a task or void function
Verilog
Fine Grain Process
Verification
Control
Verilog Switch TB
Event Control:
TUTORIALS
Basic Constructs
OpenVera
Constructs
PROCEDURAL BLOCKS
Any change in a variable or net can be detected using the @ event control, as in on This section - Your
Verilog. If the expression evaluates to a result of more than 1 bit, a change on any of input is what keeps
the bits of the result (including an x to z change) shall trigger the event control.
with time!
SystemVerilog adds an iff qualifier to the @ event control.
Switch TB
EXAMPLE:
modulelatch (outputlogic[31:0]y,input[31:0]a,inputenable);
RVM Ethernet sample always@(a iffenable ==1)
y <=a;//latch is in transparent mode
endmodule
RVM Switch TB
Specman E
Interview Questions
Always:
In an always block that is used to model combinational logic, forgetting an else leads
to an unintended latch. To avoid this mistake, SystemVerilog adds specialized
always_comb and always_latch blocks, which indicate design intent to simulation,
synthesis, and formal verification tools. SystemVerilog also adds an always_ff block to
indicate sequential logic.
EXAMPLE:
always_comb
a =b &c;
always_latch
http://testbench.in/SV_25_PROCEDURAL_BLOCKS.html[9/26/2012 2:05:03 PM]
if(ck)q <=d;
always_ff@(posedgeclock iffreset ==0orposedgereset)
r1 <=reset ?0:r2 +1;
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http://testbench.in/SV_25_PROCEDURAL_BLOCKS.html[9/26/2012 2:05:03 PM]
Search
Index
Introduction
Data Types
SystemVerilog
A Verilog fork...join block always causes the process executing the fork statement to Literals
Verification
block until the termination of all forked processes. With the addition of the join_any Strings
Constructs
and join_none keywords, SystemVerilog provides three choices for specifying when the Userdefined Datatypes
Enumarations
parent (forking) process resumes execution.
Interface
OOPS
Typedef
Arrays
Randomization
Array Methods
Functional Coverage
Dynamic Arrays
Associative Arrays
Assertion
Queues
DPI
Linked List
UVM Tutorial
Casting
VMM Tutorial
Data Declaration
Reg And Logic
OVM Tutorial
Operators 1
Easy Labs : SV
Operators 2
Operator Precedency
Easy Labs : UVM
Events
Easy Labs : OVM
Control Statements
Easy Labs : VMM
Program Block
Procedural Blocks
AVM Switch TB
Fork Join
VMM Ethernet sample
Fork Control
Subroutines
Semaphore
Mailbox
Verilog
Fine Grain Process
Verification
Control
TUTORIALS
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
FORK JOIN
Fork Join None

The parent process continues to execute concurrently with all the processes spawned input is what keeps
by the fork. The spawned processes do not start executing until the parent thread Testbench.in improving
executes a blocking statement.
with time!
Switch TB
EXAMPLE : fork/join none

programmain ;
RVM Ethernet sample initial
begin
#10;
$display(" BEFORE forktime = %d ",$time);

Specman E
fork
Interview Questions
begin
#(20);
$display("time = %d # 20",$time);
end
begin
#(10);
end
begin
#(5);
RVM Switch TB
http://testbench.in/SV_26_FORK_JOIN.html[9/26/2012 2:05:13 PM]
end
join_none
$display(" time = %d Outside the main fork ",$time);
#(40);
end
endprogram
RESULTS
BEFORE forktime = 10
time = 10 Outside the main fork
time = 15 # 5
time = 20 # 10
time = 30 # 20
Fork Join Any
The parent process blocks until any one of the processes spawned by this fork
completes.
EXAMPLE : fork/join any
programmain;
initialbegin
#(10);
fork
begin
#(20);
end
begin
#(10);
end
begin
#(5);
end
join_any
#(40);
end
endprogram
RESULTS
time = 15 # 5
time = 20 # 10
time = 30 # 20
For Join All
The parent process blocks until all the processes spawned by this fork complete.
EXAMPLE : fork/join all
programmain ;
initial
begin
#(10);
fork
begin
#(20);
end
begin
#(10);
end
begin
#(5);
end
join
#(40);
end
endprogram
RESULTS
time = 15 # 5
time = 20 # 10
time = 30 # 20
When defining a fork/join block, encapsulating the entire fork inside begin..end,
results in the entire block being treated as a single thread, and the code executes
consecutively.
EXAMPLE : sequential statement in fork/join
programmain ;
initialbegin
#(10);
$display(" First forktime = %d ",$time);
fork
begin
#(20);
end
begin
#(10);
end
begin
#(5);
#(2);
end
join_any
#(40);
end
endprogram
RESULTS:
First forktime = 10
time = 15 # 5
time = 17 # 2
time = 20 # 10
time = 30 # 20
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Index
Introduction
Data Types
SystemVerilog
Wait Fork Statement
Literals
Verification
The wait fork statement is used to ensure that all immediate child subprocesses Strings
Constructs
(processes created by the current process, excluding their descendants) have Userdefined Datatypes
Enumarations
completed their execution.
Interface
OOPS
Typedef
EXAMPLE
Arrays
Randomization
programmain();
Array Methods
Functional Coverage
Dynamic Arrays
initialbegin
Associative Arrays
Assertion
#(10);
Queues
$display("
BEFORE
forktime
=
%0d
",$time);
DPI
fork
Linked List
UVM Tutorial
begin
Casting
#(20);
VMM Tutorial
Data Declaration
$display(" time = %0d # 20",$time);
Reg And Logic
OVM Tutorial
end
Operators 1
begin
Easy Labs : SV
Operators 2
#(10);
Operator Precedency
Easy Labs : UVM
Events
end
Easy Labs : OVM
Control Statements
begin
Easy Labs : VMM
Program Block
#(5);
Procedural Blocks
AVM Switch TB
Fork Join
end
VMM Ethernet sample join_any
Fork Control
Subroutines
$display(" time = %0d Outside the main fork ",$time);
Semaphore
end
Mailbox
endprogram
Verilog
Fine Grain Process
Verification
Control
RESULTS
TUTORIALS
FORK CONTROL
Verilog Switch TB
Basic Constructs
time = 15 # 5
OpenVera
Constructs
Switch TB
RVM Switch TB
In the above example, Simulation ends before the #10 and #20 gets executed. In
some situations, we need to wait until all the threads got finished to start the next
task. Using wait fork, will block thetill all the child processes complete.
RVM Ethernet sample
EXAMPLE:
programmain();
Specman E
Interview Questions
initialbegin
#(10);
$display(" BEFORE forktime = %0d ",$time);
fork
begin
#(20);
end
begin
#(10);
end
http://testbench.in/SV_27_FORK_CONTROL.html[9/26/2012 2:05:22 PM]

input is what keeps
with time!
begin
#(5);
end
join_any
waitfork;
$display(" time = %0dAfter wait fork ",$time);
end
endprogram
RESULTS
time = 15 # 5
time = 20 # 10
time = 30 # 20
time = 30After wait fork
Disable Fork Statement
The disable fork statement terminates all active descendants (subprocesses) of the
calling process.
In other words, if any of the child processes have descendants of their own, the
disable fork statement shall terminate them as well. Sometimes, it is required to kill
the child processes after certain condition.
EXAMPLE
programmain();
initialbegin
#(10);
fork
begin
#(20);
end
begin
#(10);
end
begin
#(5);
end
join_any
end
initial
#100$finish;
endprogram
RESULTS
time = 15 # 5
time = 20 # 10
time = 30 # 20
In the following example, disable for kills the threads #10 and #20.
EXAMPLE
programmain();
initialbegin
#(10);
fork
begin
#(20);
end
begin
#(10);
end
begin
#(5);
end
join_any
disablefork;
$display(" Killed the child processes");
end
initial
#100$finish;
endprogram
RESULTS
time = 15 # 5
Killed the child processes
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TUTORIALS
SystemVerilog
SUBROUTINES
Verification
Begin End
Constructs
With SystemVerilog, multiple statements can be written between the task declaration
and endtask, which means that the begin .... end can be omitted. If begin .... end is
omitted, statements are executed sequentially, the same as if they were enclosed in
a begin .... end group. It shall also be legal to have no statements at all.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Tasks:
A Verilog task declaration has the formal arguments either in parentheses or in
declaration.
VMM Tutorial
taskmytask1 (outputintx,inputlogicy);
OVM Tutorial
With SystemVerilog, there is a default direction of input if no direction has been

specified. Once a direction is given, subsequent formals default to the same direction.
In the following example, the formal arguments a and b default to inputs, and u and v
are both outputs.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
taskmytask3(a,b,outputlogic[15:0]u,v);
Return In Tasks
In Verilog, a task exits when the endtask is reached. With SystemVerilog, the return
statement can be used to exit the task before the endtask keyword.
In the following example, Message "Inside Task : After return statement" is not
executed because the task exited before return statement.
EXAMPLE
programmain();
tasktask_return();
$display("Inside Task : Before return statement");
return;
$display("Inside Task : After return statement");
endtask
initial
task_return();
endprogram
RESULT:
Inside Task : Before return statement
Functions:
functionlogic[15:0]myfunc1(intx,inty);
http://testbench.in/SV_28_SUBROUTINES.html[9/26/2012 2:05:29 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
Function declarations default to the formal direction input if no direction has been
specified. Once a direction is given, subsequent formals default to the same direction.
In the following example, the formal arguments a and b default to inputs, and u and v
are both outputs:
functionlogic[15:0]myfunc3(inta,intb,outputlogic[15:0]u,v);
Return Values And Void Functions::
SystemVerilog allows functions to be declared as type void, which do not have a
return value. For nonvoid functions, a value can be returned by assigning the function
name to a value, as in Verilog, or by using return with a value. The return statement
shall override any value assigned to the function name. When the return statement is
used, nonvoid functions must specify an expression with the return.
EXAMPLE:
function[15:0]myfunc2 (input[7:0]x,y);
returnx *y -1;//return value is specified using return statement
endfunction
// void functions
functionvoidmyprint (inta);
Pass By Reference:
In verilog,method arguments takes as pass by value.The inputs are copyed when the
method is called and the outputs are assigned to outputs when exiting the method.In
SystemVerilog ,methods can have pass by reference.Arguments passed by reference
are not copied into the subroutine area, rather, a reference to the original argument
is passed to the subroutine. The subroutine can then access the argument data via the
reference.
In the following example, variable a is changed at time 10,20 and 30. The method
pass_by_val , copies only the value of the variable a, so the changes in variable a
which are occurred after the task pass_by_val call, are not visible to pass_by_val.
Method pass_by_ref is directly referring to the variable a. So the changes in variable a
are visible inside pass_by_ref.
EXAMPLE:
programmain();
inta;
initial
begin
#10a =10;
#10a =20;
#10a =30;
#10$finish;
end
taskpass_by_val(inti);
forever
@i $display("pass_by_val: I is %0d",i);
endtask
taskpass_by_ref(refinti);
forever
@i $display("pass_by_ref: I is %0d",i);
endtask
initial
pass_by_val(a);
initial
pass_by_ref(a);
endprogram
RESULT
pass_by_ref: I is 10
Default Values To Arguments:

SystemVerilog allows to declare default values to arguments.When the subrotunies
are called,arguments those are omited,will take default value.
EXAMPLE:
programmain();
taskdisplay(inta =0,intb,intc =1);

$display(" %0d %0d %0d ",a,b,c);
endtask
initial
begin
display(,5); // is equivalent to display( 0, 5, 1 );
display(2,5);// is equivalent to display( 2, 5, 1 );
display(,5,);// is equivalent to display( 0, 5, 1 );
display(,5,7);// is equivalent to display( 0, 5, 7 );
display(1,5,2);// is equivalent to display( 1, 5, 2 );
end
endprogram
RESULT:
0
2
0
0
1
5
5
5
5
5
1
1
1
7
2
Argument Binding By Name

SystemVerilog allows arguments to tasks and functions to be bound by name as well
as by position. This allows specifying non-consecutive default arguments and easily
specifying the argument to be passed at the call.
EXAMPLE:
programmain();
functionvoidfun(intj =1,strings ="no");
$display("j is %0d : s is %s ",j,s);
endfunction
initial
begin
fun(.j(2),.s("yes"));// fun( 2, "yes" );
fun(.s("yes"));// fun( 1, "yes" );
fun(,"yes");// fun( 1, "yes" );

fun(.j(2));// fun( 2, "no" );
fun(.s("yes"),.j(2));// fun( 2, "yes" );
fun(.s(),.j());// fun( 1, "no" );
fun(2);// fun( 2, "no" );
fun();// fun( 1, "no" );
end
endprogram
RESULT
j
j
j
j
j
j
j
j
is
is
is
is
is
is
is
is
2
1
1
2
2
1
2
1
:
:
:
:
:
:
:
:
s
s
s
s
s
s
s
s
is
is
is
is
is
is
is
is
yes
yes
yes
no
yes
no
no
no
Optional Argument List

When a task or function specifies no arguments, the empty parenthesis, (), following
the task/function name shall be optional. This is also true for tasks or functions that
require arguments, when all arguments have defaults
specified.
EXAMPLE
programmain();
functionvoidfun();
$display("Inside function");
endfunction
initial
begin
fun();
fun;
end
endprogram
RESULT
Inside function
Inside function
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TUTORIALS
SEMAPHORE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Conceptually, a semaphore is a bucket. When a semaphore is allocated, a bucket that

contains a fixed number of keys is created. Processes using semaphores must first
procure a key from the bucket before they can continue to execute. If a specific
process requires a key, only a fixed number of occurrences of that process can be in
progress simultaneously. All others must wait until a sufficient number of keys is
returned to the bucket. Semaphores are typically used for mutual exclusion, access
control to shared resources, and basic synchronization.
Semaphore is a built-in class that provides the following methods:
--Create a semaphore with a specified number of keys: new()
--Obtain one or more keys from the bucket: get()
--Return one or more keys into the bucket: put()
--Try to obtain one or more keys without blocking: try_get()
VMM Tutorial
OVM Tutorial
EXAMPLE:semaphore
programmain ;
semaphoresema =new(1);
Easy Labs : UVM
initialbegin
repeat(3)begin
Easy Labs : OVM
fork
Easy Labs : VMM
////////// PROCESS 1 ////////////////
begin
AVM Switch TB
$display("1: Waiting for key");
VMM Ethernet sample sema.get(1);
$display("1: Got the Key");
#(10);// Do some work
sema.put(1);
Verilog
$display("1: Returning back key ");
Verification
#(10);
Verilog Switch TB
end
////////// PROCESS 2 ////////////////
Basic Constructs
begin
$display("2: Waiting for Key");
sema.get(1);
OpenVera
$display("2: Got the Key");
Constructs
#(10);//Do some work
sema.put(1);
Switch TB
$display("2: Returning back key ");
RVM Switch TB
#(10);
RVM Ethernet sample end
join
end
#1000;
Specman E
end
endprogram
Interview Questions
Easy Labs : SV
RESULTS:
1:
1:
2:
1:
2:
2:
1:
Waiting for key

Got the Key
Waiting for Key
Returning back key
Got the Key
Returning back key
Waiting for key
http://testbench.in/SV_29_SEMAPHORE.html[9/26/2012 2:05:38 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
1:
2:
1:
2:
2:
1:
1:
2:
1:
2:
2:
Got the Key

Waiting for Key
Returning back key
Got the Key
Returning back key
Waiting for key
Got the Key
Waiting for Key
Returning back key
Got the Key
Returning back key
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Search
Index
Introduction
Data Types
SystemVerilog
A mailbox is a communication mechanism that allows messages to be exchanged Literals
Verification
between processes. Data can be sent to a mailbox by one process and retrieved by Strings
Constructs
another.
Enumarations
Interface
Mailbox is a built-in class that provides the following methods:
OOPS
Typedef
--Create a mailbox: new()
Arrays
--Place a message in a mailbox: put()
Randomization
Array Methods
--Try to place a message in a mailbox without blocking: try_put()
Functional Coverage
Dynamic Arrays
--Retrieve a message from a mailbox: get() or peek()
Associative Arrays
Assertion
--Try to retrieve a message from a mailbox without blocking: try_get() or try_peek()
Queues
--Retrieve
the
number
of
messages
in
the
mailbox:
num()
DPI
Linked List
UVM Tutorial
EXAMPLE:
Casting
programmeain ;
VMM Tutorial
Data Declaration
mailboxmy_mailbox;
Reg And Logic
OVM Tutorial
initialbegin
Operators 1
my_mailbox
=new();
Easy Labs : SV
Operators 2
if(my_mailbox)
Operator Precedency
Easy Labs : UVM
begin
Events
fork
Easy Labs : OVM
Control Statements
put_packets();
Easy Labs : VMM
Program Block
get_packets();
Procedural Blocks
#10000;
AVM Switch TB
Fork Join
join_any
VMM Ethernet sample end
Fork Control
Subroutines
Semaphore
#(1000);
Mailbox
$display("END of Program");
Verilog
Fine Grain Process
end
Verification
Control
Verilog Switch TB
taskput_packets();
integeri;
Basic Constructs
begin
input is what keeps
for(i=0;i<10;i++)
begin
OpenVera
with time!
#(10);
Constructs
my_mailbox.put(i);
$display("Done putting packet %d @time %d",i,$time);
Switch TB
RVM Switch TB
end
endtask
taskget_packets();
Specman E
integeri,packet;
begin
Interview Questions
for(inti=0;i<10;i++)
begin
my_mailbox.get(packet);
$display("Got packet %d @time %d",packet,$time);
end
end
endtask
endprogram
TUTORIALS
MAILBOX
RESULTS:
http://testbench.in/SV_30_MAILBOX.html[9/26/2012 2:05:47 PM]
Done putting packet 0 @time 10

Got packet0 @time 10
Done putting packet 9 @time100
Got packet9 @time100
END of Program
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TUTORIALS
FINE GRAIN PROCESS CONTROL
SystemVerilog
A process is a built-in class that allows one process to access and control another
process once it has started.Users can declare variables of type process and safely pass
them through tasks or incorporate them into other objects. The prototype for the
process class is:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
classprocess;
enumstate {FINISHED,RUNNING,WAITING,SUSPENDED,KILLED};
staticfunctionprocess self();
functionstate status();
taskkill();
taskawait();
tasksuspend();
taskresume();
endclass
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Objects of type process are created internally when processes are spawned. Users
cannot create objects of type process; attempts to call new shall not create a new
process, and instead result in an error. The process class cannot be extended.
Attempts to extend it shall result in a compilation error. Objects of type process are
unique; they become available for reuse once the underlying process terminates and
all references to the object are discarded. The self() function returns a handle to the
current process, that is, a handle to the process making the call.
VMM Ethernet sample The status() function returns the process status, as defined by the state enumeration:
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
FINISHED Process terminated normally.

RUNNING Process is currently running (not in a blocking statement).
WAITING Process is waiting in a blocking statement.
SUSPENDED Process is stopped awaiting a resume.
KILLED Process was forcibly killed (via kill or disable).
Kill
The kill() task terminates the given process and all its sub-processes, that is,
processes spawned using fork statements by the process being killed. If the process to
be terminated is not blocked waiting on some other condition, such as an event, wait
expression, or a delay then the process shall be terminated at some unspecified time
in the current time step.
await
Specman E
Interview Questions
The await() task allows one process to wait for the completion of another process. It
shall be an error to call this task on the current process, i.e., a process cannot wait
for its own completion.
suspend
The suspend() task allows a process to suspend either its own execution or that of
another process. If the process to be suspended is not blocked waiting on some other
condition, such as an event, wait expression, or a delay then the process shall be
suspended at some unspecified time in the current time step. Calling this method
more than once, on the same (suspended) process, has no effect.
resume
http://testbench.in/SV_31_FINE_GRAIN_PROCESS_CONTROL.html[9/26/2012 2:05:57 PM]
Index
Introduction
Data Types
Literals
Strings
Enumarations
Typedef
Arrays
Array Methods
Dynamic Arrays
Associative Arrays
Queues
Linked List
Casting
Data Declaration
Reg And Logic
Operators 1
Operators 2
Operator Precedency
Events
Control Statements
Program Block
Procedural Blocks
Fork Join
Fork Control
Subroutines
Semaphore
Mailbox
Fine Grain Process
Control
input is what keeps
with time!
The resume() task restarts a previously suspended process. Calling resume on a

process that was suspended while blocked on another condition shall re-sensitize the
process to the event expression, or wait for the wait condition to become true, or for
the delay to expire. If the wait condition is now true or the original delay has
transpired, the process is scheduled onto the Active or Reactive region, so as to
continue its execution in the current time step. Calling resume on a process that
suspends itself causes the process to continue to execute at the statement following
the call to suspend.
The example below starts an arbitrary number of processes, as specified by the task
argument N. Next, the task waits for the last process to start executing, and then
waits for the first process to terminate. At that point the parent process forcibly
terminates all forked processes that have not completed yet.
taskdo_n_way(intN );
process job[1:N];
for(intj =1;j <=N;j++)
fork
automaticintk =j;
beginjob[j]=process::self();...;end
join_none
for(intj =1;j <=N;j++)// wait for all processes to start
wait(job[j]!=null);
job[1].await();// wait for first process to finish
for(intk =1;k <=N;k++)begin
if(job[k].status!=process::FINISHED)
job[k].kill();
end
endtask
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Index
Interface
Ports
The communication between blocks of a digital system is a critical area. In Verilog, Interface Methods
modules are connected using module ports. For large modules, this is not productive Clocking Block
Virtual Interface
as it involves
Svtb N Verilog Dut
INTERFACE
Manually connecting hundreds of ports may lead to errors.

Detailed knowledge of all the port is required.
Difficult to change if the design changes.
More time consuming.
Most port declaration work is duplicated in many modules.
Let us see a verilog example:
UVM Tutorial
moduleDut (inputclk,read,enable,
Input [7:0]addr,
output[7:0]data);
OVM Tutorial
....
Easy Labs : SV
assigndata=temp1 ?temp2 :temp3 ;
always@(posedgeclk)
Easy Labs : UVM
....
Easy Labs : OVM
endmodule
Easy Labs : VMM
moduleTestbench(inputclk,
AVM Switch TB
Output read,enable,
VMM Ethernet sample output[7:0]addr,
input[7:0]data);
endmodule
Verilog
VMM Tutorial
Verification
Verilog Switch TB
Integrating the above two modules in top module.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
1moduletop();
2regclk;
3wireread,enable;
4wire[7:0]addr;
5wire[7:0]data;
6
http://testbench.in/IF_01_INTERFACE.html[9/26/2012 2:06:13 PM]

input is what keeps
with time!
7Dut D (clk,read,enable,Addr,data);
8
9Testbench TB(clk,read,enable,Addr,data);
10
11endmodule
All the connection clk, read, enable, addr, data are done manually.Line 7 and 9 has
same code structure which is duplicating work. If a new port is added, it needs
changes in DUT ports, TestBench Ports, and in 7, 10 lines of Top module.This is timeconsuming and maintaining it is complex as the port lists increases.
To resolve the above issues, SystemVerilog added a new powerful features called
interface. Interface encapsulates the interconnection and communication between
blocks.
Interface declaration for the above example:
interfaceintf #(parameterBW=8)(inputclk);
logicread,enable;
logic[BW-1:0]addr,data;
endinterface:intf
Here the signals read, enable, addr, data are grouped in to "intf".Interfaces can have
direction as input, output and inout also. In the above example, clk signal is used as
input to interface. Interfaces can also have parameters like modules. Interface
declaration is just like a module declaration. Uses keywords interface, endinterface
for defining. Inside a module, use hierarchical names for signals in an interface.
TIP: Use wire type in case of multiple drivers. Use logic type in case of a single
driver.
Let use see the DUT and Testbench modules using the above declared interface.
moduleDut (intf dut_if);// declaring the interface
always@(posedgedut_if.clk)
if(dut_if.read)// sampling the signal
$display(" Read is asserted");
endmodule
moduleTestbench(intf tb_if);
initial
begin
tb_if.read =0;
repeat(3)#20tb_if.read =~tb_if.read;// driving a signal
$finish;
end
endmodule
Integrating the above two modules in top module.
moduletop();
bitclk;
initial
forever#5clk =~clk;
intf bus_if(clk);// interface instantiation
Dut d(bus_if);// use interface for connecting D and TB
Testbench TB(bus_if);
endmodule
See, how much code we got reduced in this small example itself. In the above
example, I demonstrated the connectivity between DUT and TestBench. Interfaces can
also be used for connectivity between the DUT sub modules also.
Advantages Of Using Inteface:
An interface can be passed as single item.
It allows structured information flow between blocks.
It can contain anything that could be in a module except other module definitions
or instance.
Port definitions are independent from modules.
Increases the reusability.
It Interface can be declared in a separate file and can be compiled separately.
Interfaces can contain tasks and functions; with this methods shared by all modules
connecting to this information can be in one place.
Interface can contain protocol checking using assertions and functional coverage
blocks.
Reduces errors which can cause during module connections.
Easy to add or remove a signal. Easy maintainability.
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Constructs
Interface
OOPS
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DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Index
Interface
Ports
Interface Ports
Interface Methods
Clocking Block
In the previous example, signal clk is declared as port to the interface. Interface Ports Virtual Interface
work similar to the module ports. Members of port list can be connected externally by Svtb N Verilog Dut
name or position when the interface is instantiated as shown in line 3 of module top
code.
PORTS
Modports
In the above example, we did not mention the direction of signals. The direction of
the clk signal in input for both theDut and Testbench modules. But for the rest of
the signals, the direction is not same.To specify the direction of the signal w.r.t
module which uses interface instead of port list, modports are used. Modport restrict
interface access within a module based on the direction declared. Directions of
signals are specified as seen from the module. In the modeport list, only signal names
are used.
Easy Labs : OVM
Let us see the modport usage with the previous example.2 mod port definitions are
needed, one for DUT and other for TestBench.
Easy Labs : VMM
Interface declaration for the above example:
AVM Switch TB
interfaceintf (inputclk);
VMM Ethernet sample logicread,enable,
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
logic[7:0]addr,data;
modportdut (inputread,enable,addr,outputdata);
modporttb (outputread,enable,addr,inputdata);
endinterface:intf
In this example, the modport name selects the appropriate directional information for
the interface signals accessed in the module header.Modport selection can be done
in two ways. One at Module declaration , other at instantication.
Switch TB
Modport Selection Duing Module Definition.
RVM Switch TB
moduleDut (intf.dut dut_if);// declaring the interface with modport
RVM Ethernet sample ....
Specman E
Interview Questions
assigndut_if.data=temp1 ?temp2 :temp3 ;// using the signal in interface

always@(posedgeintf.clk)
....
endmodule
moduleTestbench(intf.tb tb_if);
.....
.....
endmodule
1moduletop();
2 logicclk;
3 intf bus_if(clk);// interface instantiation
4 Dut d(bus_if);// Pass the interface
5 Testbench TB(Bus_if);// Pass the interface
http://testbench.in/IF_02_PORTS.html[9/26/2012 2:06:22 PM]

input is what keeps
with time!
6endmodule
Modport Selection Duing Module Instance.
moduleDut (intf dut_if);// declaring the interface
....
assigndut_if.data=temp1 ?temp2 :temp3 ;// using the signal in interface
always@(posedgeintf.clk)
....
endmodule
moduleTestbench(intf tb_if);
.....
.....
endmodule
1moduletop();
2logicclk;
3intf bus_if(clk);// interface instantiation
4Dut d(bus_if.dut);// Pass the modport into the module
5Testbench TB(Bus_if.tb);// Pass the modport into the module
6endmodule
A mod port can also define expressions. They can also define their own names. Module
can use the modport declared name. For example
modportdut (inputread,enable,.addr(2),output.d(data[1:5]);
moduledut(intf.dutdut_if);
assigndut_if.d =temp;// using the signal name declared by modport.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Index
Interface
Ports
Methods In Interfaces
Interface Methods
Interfaces can include task and function definitions. This allows a more abstract level Clocking Block
Virtual Interface
of modeling.
Svtb N Verilog Dut
INTERFACE METHODS
logicread,enable,
taskmasterRead(inputlogic[7:0]raddr);// masterRead method

...
endtask:masterRead
taskslaveRead;// slaveRead method

...
endtask:slaveRead
endinterface:intf
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/IF_03_INTERFACE_METHODS.html[9/26/2012 2:06:29 PM]

input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Index
Interface
Ports
Clocking Blocks
Interface Methods
SystemVerilog adds the clocking block that identifies clock signals, and captures the Clocking Block
timing and synchronization requirements of the blocks being modeled. A clocking Virtual Interface
block assembles signals that are synchronous to a particular clock, and makes their Svtb N Verilog Dut
timing explicit. The clocking block is a key element in a cycle-based methodology,
which enables users to write testbenches at a higher level of abstraction. Simulation Report a Bug or Comment
is faster with cycle based methodology.
CLOCKING BLOCK
input is what keeps
Depending on the environment, a testbench can contain one or more clocking blocks, Testbench.in improving
each containing its own clock plus an arbitrary number of signals. These operations with time!
are as follows:
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Synchronous events
Input sampling
Synchronous drives
clockingcb @(posedgeclk);
defaultinput#10ns output#2ns;
Easy Labs : VMM
outputread,enable,addr;
inputnegedgedata;
VMM Ethernet sample endclocking
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
In the above example, the first line declares a clocking block called cb that is to be
clocked on the positive edge of the signal clk. The second line specifies that by
default all signals in the clocking block shall use a 10ns input skew and a 2ns output
skew by default. The next line adds three output signals to the clocking block: read,
enable and addr. The fourth line adds the signal data to the clocking block as input.
Fourth line also contains negedge which overrides theskew ,so that data is sampled
on the negedge of the clk.
Skew
Switch TB
If an input skew is specified then the signal is sampled at skew time units before the
clock event. If output skew is specified, then output (or inout) signals are driven skew
RVM Switch TB
time units after the corresponding clock event. A skew must be a constant expression,
RVM Ethernet sample and can be specified as a parameter.
Specman E
Interview Questions
http://testbench.in/IF_04_CLOCKING_BLOCK.html[9/26/2012 2:06:38 PM]
Skew can be specified in 3 ways.

#d : The skew is d time units. The time unit depends on the timescale of the block.
#dns : The skew is d nano seconds.
#1step :Sampling is done in the preponed region of current time stamp.
If skew is not specified, default input skew is 1step and output skew is 0.
Specifying a clocking block using a SystemVerilog interface can significantly reduce
the amount of code needed to connect the TestBench without race condition.
Clocking blocks add an extra level of signal hierarchy while accessing signals.
Interface declaration with clocking block:
logicread,enable,
clockingcb @(posedgeclock);// clocking block for testbench

defaultinput#10ns output#2ns;
outputread,enable,addr;
inputdata;
endclocking
modportdut (inputread,enable,addr,outputdata);
modporttb (clockingcb);// synchronous testbench modport
endinterface:intf
moduletestbench(intf.tb tb_if);
......
initial
tb_if.cb.read <=1;//writing to synchronous signal read
...
endmodule
Cycle Delay
The ## operator can be used to delay execution by a specified number of clocking
events, or clock cycles. What constitutes a cycle is determined by the default clocking
in effect of module, interface, or program.
##<integer_expression>;
##3;// wait 3 cycles
##1tb_if.addr <=8'h00;// waits for 1 cycle and then writes address.
Using clocking blocks,cycle delays syntax gets reduced.
Insted of writing
repeat(3)@(posedgeclock);sync_block.a <=1;
Just use
##3sync_block.a <=1;
To schedule the assignment after 3 clocks,Just use,
sync_block.a <=##31;
To simply wait for 3 clock cycles,
##3;can be used.
But there may be more than one clocking block is defined in a project.
##3 waits for 3 clocks cycles,of the block which is defined as default.
defaultclockingsync_block @(posedgeclock);
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Verification
Constructs
Interface
OOPS
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Easy Labs : SV
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Index
Interface
Ports
Virtual Interfaces
Interface Methods
Virtual interfaces provide a mechanism for separating abstract models and test Clocking Block
programs from the actual signals that make up the design.A virtual interface allows Virtual Interface
the same subprogram to operate on different portions of a design, and to dynamically Svtb N Verilog Dut
control the set of signals associated with the subprogram. Instead of referring to the
actual set of signals directly, users are able to manipulate a set of virtual signals.
VIRTUAL INTERFACE
1moduletestbench(intf.tb tb_if);
2 virtualinterfaceintf.tb local_if;// virtual interface.
3 ....
4 taskread(virtualinterfaceintf.tb l_if)// As argument to task
5 ....
6 initial
7 begin
8 Local_if =tb_if;// initializing virtual interface.
9 Local_if.cb.read <=1;//writing to synchronous signal read
10read(Local_if);// passing interface to task.
11end
12endmodule
Easy Labs : VMM
In the above program, local_if is just like a pointer. It represents an interface

instance. Using keyword "virtual" , virtual interfaces instance is created. It does not
VMM Ethernet sample have any signal. But it can hold physical interface. Tb_if is the physical interface
which is allocated during compilation time. You can drive and sample the signals in
physical interface. In line 8, the physical interface tb_if is assigned to local_if. With
this , we can drive and sample the physical signals. In line 9, read signal of tb_if is
Verilog
accessed using local_if.
Verification
AVM Switch TB
Verilog Switch TB
Basic Constructs
Advantages Of Virtual Interface
1)Virtual interface can be used to make the TestBench independent of the

physical interface. It allows developing the test component independent of the DUT
port while working with multi port protocol.
Constructs
2)With virtual interface, we can change references to physical interface
dynamically. Without virtual interfaces, all the connectivity is determined during
Switch TB
compilation time, and therefore can't be randomized or reconfigured.
RVM Switch TB
3)In multi port environment, it allows to access the physical interfaces using array
RVM Ethernet sample index.
4)Physical interfaces are not allowed in object oriented programming, as physical
interface is allocated at compilation time itself. Virtual interface which are set at run
time allows to do object oriented programming with signals rather than just with
Specman E
variables.
5)Virtual interface variables can be passed as arguments to tasks, functions, or
Interview Questions
methods.
6)Allows to use Equality ( == ) and inequality ( != ) .
A virtual interface must be initialized before it can be used, by default, it points to

null. Attempting to use an uninitialized virtual interface will result in a run-time
error.
OpenVera
Multi Bus Interface
http://testbench.in/IF_05_VIRTUAL_INTERFACE.html[9/26/2012 2:06:47 PM]

input is what keeps
with time!
If you are working on protocol which has multiple sub bus protocol, there are several
ways to create interfaces.
One Big single interface with all the sub protocol signals inside it. With single
interface, it is easy to pass around the whole system. You have to name all the signals
with the sub protocol prefix like pcie_enable, Eth_enable etc. Restrict the access
using clocking blocks else all signals can be accessed by all the modules using this
interface. Reusability will be very less as all the sub protocols are in one interface.
Using multiple interfaces, one for each sub protocol, each interface for each sub
bus will increase the complexity while passing around the system.No need to prefix
the sub protocol name as the sub protocol name is reflected in the interface name
itself. With this you can only pass the sub interfaces required by other modules. All
the interfaces will be reusable as each interface represents an individual protocol.
Using one big interface with sub multiple interfaces will be easy for passing
around the system. With this the sub interfaces can be reused for other components
and other designs.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Interface
Ports
Working With Verilog Dut:
Interface Methods
There are several ways to connect the Verilog DUT to SystemVerilog TestBench. Clocking Block
Verilog DUT has port list where as SystemVerilog testbenchs uses interfaces.We will Virtual Interface
Svtb N Verilog Dut
discuss 2 ways of connecting Verilog DUT to SystemVerilog TestBench.
SVTB N VERILOG DUT

input is what keeps
Verilog port list can be connected during DUT instantiation using interface hibachi Testbench.in improving
with time!
signal names as shown in following code.
Connecting In Top:
DPI
// DUT in Verilog
moduleDut (inputclk,read,enable,
Input [7:0]addr,
VMM Tutorial
output[7:0]data);
OVM Tutorial
....
assigndata=temp1 ?temp2 :temp3 ;
Easy Labs : SV
always@(posedgeclk)
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....
endmodule
Easy Labs : OVM
Easy Labs : VMM

// SystemVerilog Code
//interface declaration with clocking block:
AVM Switch TB
VMM Ethernet sample logicread,enable,
endinterface
Verilog
moduletestbench(intf.tb tb_if);
Verification
.....
Verilog Switch TB
endmodule
Basic Constructs
// integrating in top module.
moduletop();
OpenVera
logicclk;
UVM Tutorial
Constructs

Testbench TB(bus_if);// Pass the modport into the module
RVM Switch TB
Dut d(.clk(clk),// connect the verilog
RVM Ethernet sample .read(bus_if.read),// RTL port using interface hierarchy signal name.
.enable(bus_if.enable),
.addr(bus_if.addr),
.data(bus_if.data);
Switch TB
Specman E
Interview Questions
endmodule
Connecting Using A Wrapper
We can also convert the verilog module with port list in to SystemVerilog module with
interface by creating wrapper around the verilog module.
//wrapper for verilog DUT
modulew_dut(intf wif);
Dut d(.clk(wif.clk),// connect the verilog
http://testbench.in/IF_06_SVTB_N_VERILOG_DUT.html[9/26/2012 2:06:56 PM]
.read(wif.read),// RTL port using interface hierarchy signal name.

.enable(wif.enable),
.addr(wif.addr),
.data(wif.data);
endmodule
//connecting the dut wrapper and testbench in top.
moduletop();
logicclk;
w_dut d(bus_if);// instance of dut wrapper
Testbench TB(Bus_if);
endmodule
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TUTORIALS
INTRODUCTION
SystemVerilog
Brief Introduction To Oop
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Unlike procedural programming, here in the OOP programming model programs are
organized around objects and data rather than actions and logic. Objects represent
some concepts or things and like any other objects in the real Objects in programming
language have certain behavior, properties, type, and identity. In OOP based language
the principal aim is to find out the objects to manipulate and their relation between
each other. OOP offers greater flexibility and compatibility then procedural language
like verilog.
Objects are key to understanding object-oriented technology. Look around right now
and you'll find many examples of real-world objects: your system, your desk, your
chair.
Real-world objects share two characteristics: They all have state and behavior.
System have state (name, color) and behavior (playing music,switch off). Identifying
the state and behavior for real-world objects is a great way to begin thinking in terms
of object-oriented programming.
SystemVerilog is a object oriented programmingand to understand the functionality
of OOP in SystemVerilog, we first need to understand several fundamentals related to
objects. These include class, method, inheritance, encapsulation, abstraction,
polymorphism etc.
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc

VMM Ethernet sample
input is what keeps
It is the central point of OOP and that contains data and codes with behavior. In Testbench.in improving
SystemVerilog OOPS , everything happens within class and it describes a set of objects with time!
AVM Switch TB
Verilog
Verification
Class
with common behavior. The class definition describes all the properties, behavior, and
identity of objects present within that class.
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Object
Objects are the basic unit of object orientation with behavior, identity. As we
mentioned above, these are part of a class but are not the same. An object is
expressed by the variable and methods within the objects. Again these variables and
methods are distinguished from each other as instant variables, instant methods and
class variable and class methods.
RVM Switch TB
RVM Ethernet sample Methods
Specman E
We know that a class can define both attributes and behaviors. Again attributes are
defined by variables and behaviors are represented by methods. In other words,
methods define the abilities of an object.
Interview Questions
Inheritance
This is the mechanism of organizing and structuring program. Though objects are
distinguished from each other by some additional features but there are objects that
share certain things common. In object oriented programming classes can inherit some
common behavior and state from others. Inheritance in OOP allows to define a general
class and later to organize some other classes simply adding some details with the old
class definition. This saves work as the special class inherits all the properties of the
old general class and as a programmer you only require the new features. This helps
http://testbench.in/CL_01_INTRODUCTION.html[9/26/2012 2:07:04 PM]
in a better data analysis, accurate coding and reduces development time. In Verilog ,
to write a new definition using the exesisting definitioan is done inserting ìfdef
conpilation controls into the exesisting code.
Abstraction
The process of abstraction in SystemVerilog is used to hide certain details and only
show the essential features of the object. In other words, it deals with the outside
view of an object.
Encapsulation
This is an important programming concept that assists in separating an object's state
from its behavior. This helps in hiding an object's data describing its state from any
further modification by external component. In SystemVerilog there are three
different terms used for hiding data constructs and these are public, private and
protected . As we know an object can associated with data with predefined classes
and in any application an object can know about the data it needs to know about. So
any unnecessary data are not required by an object can be hidden by this process. It
can also be termed as information hiding that prohibits outsiders in seeing the inside
of an object in which abstraction is implemented.
Polymorphism
It describes the ability of the object in belonging to different types with specific
behavior of each type. So by using this, one object can be treated like another and in
this way it can create and define multiple level of interface. Here the programmers
need not have to know the exact type of object in advance and this is being
implemented at runtime.
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TUTORIALS
CLASS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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A class is an actual representation of an Abstrace data type. It therefore provides

implementation details for the data structure used and operations.
EXAMPLE:
classA ;
// attributes:
inti
// methods:
taskprint
endclass
Definition (Class) : A class is the implementation of an abstract data type . It defines
attributes and methods which implement the data structure and operations of the
abstract data type, respectively. Instances of classes are called objects.
Consequently, classes define properties and behaviour of sets of objects.
In SV classes also contain Constraints for randomization control.
Class Properties:
Instance Variables (Non-Static Fields) :

Technically
speaking, objects store their individual states in "non-static fields", that
VMM Ethernet sample
is, fields declared without the static keyword. Non-static fields are also known as
instance variables because their values are unique to each instance of a class (to each
object, in other words);
Verilog
Verification
Class Variables (Static Fields) :
A class variable is any field declared with the static modifier; this tells the compiler
Verilog Switch TB
that there is exactly one copy of this variable in existence, regardless of how many
Basic Constructs
times the class has been instantiated.
AVM Switch TB
Local Variables :
Local Variables Similar to how an object stores its state in fields, a method will often
store its temporary state in local variables. The syntax for declaring a local variable is
Constructs
similar to declaring a field (for example, int count = 0;). There is no special keyword
Switch TB
designating a variable as local; that determination comes entirely from the location in
which the variable is declared , which is between the opening and closing braces of a
RVM Switch TB
method. As such, local variables are only visible to the methods in which they are
RVM Ethernet sample declared; they are not accessible from the rest of the class.
OpenVera
Specman E
Interview Questions
Parameters :
The important thing to remember is that parameters are always classified as
"variables" not "fields".
Constants :
Class properties can be made read-only by a const declaration like any other
SystemVerilog variable.
http://testbench.in/CL_02_CLASS.html[9/26/2012 2:07:12 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
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TUTORIALS
OBJECT
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Objects are uniquely identifiable by a name. Therefore you could have two
distinguishable objects with the same set of values. This is similar to traditional
programming languages like verilog where you could have, say two integers i and j
both of which equal to 2. Please notice the use of i and j in the last sentence to name
the two integers. We refer to the set of values at a particular time as the state of the
object.
EXAMPLE:
classsimple ;
inti;
intj;
taskprintf();
$display(i ,j );
OVM Tutorial
endtask
endclass
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programmain;
initial
Easy Labs : OVM
begin
Easy Labs : VMM
simple obj_1;
simple obj_2;
AVM Switch TB
obj_1 =new();
VMM Ethernet sample obj_2 =new();
obj_1.i =2;
obj_2.i =4;
obj_1.printf();
Verilog
obj_2.printf();
Verification
end
Verilog Switch TB
endprogram
VMM Tutorial
Basic Constructs
OpenVera
Constructs
RESULT
20
40
Switch TB
RVM Switch TB
Definition (Object) An object is an instance of a class. It can be uniquely identified by
RVM Ethernet sample its name and it defines a state which is represented by the values of its attributes at a
particular time.
Specman E
Interview Questions
The state of the object changes according to the methods which are applied to it. We
refer to these possible sequence of state changes as the behaviour of the object.
Definition (Behaviour) The behaviour of an object is defined by the set of methods
which can be applied on it.
We now have two main concepts of object-orientation introduced, class and object.
Object-oriented programming is therefore the implementation of abstract data types
or, in more simple words, the writing of classes. At runtime instances of these
classes, the objects, achieve the goal of the program by changing their states.
Consequently, you can think of your running program as a collection of objects.
http://testbench.in/CL_03_OBJECT.html[9/26/2012 2:07:19 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
Creating Objects
As you know, a class provides the blueprint for objects; you create an object from a
class. In the following statements ,program creates an object and assigns it to a
variable:
packet pkt =new(23,94);
driver drvr =new(pkt,intf);
The first line creates an object of the packet class, and the second create an
object of the driver class.
Each of these statements has three parts (discussed in detail below):
1. Declaration: The code set in bold are all variable declarations that associate
a variable name with an object type.
2. Instantiation: The new keyword is a SV operator that creates the object.
3. Initialization: The new operator is followed by a call to a constructor, which
initializes the new object.
Declaration:
Declaring a Variable to Refer to an Object
Previously, you learned that to declare a variable, you write:
type name;
This notifies the compiler that you will use name to refer to data whose type is type.
With a primitive variable, this declaration also reserves the proper amount of memory
for the variable.
You can also declare a reference variable on its own line. For example:
packet pkt;
If you declare pkt like this, its value will be undetermined until an object is actually
created and assigned to it using the new method. Simply declaring a reference
variable does not create an object. For that, you need to use the new operator. You
must assign an object to pkt before you use it in your code. Otherwise, you will get a
compiler error.
A variable in this state, which currently references no object, can be illustrated as
follows (the variable name, pkt, plus a reference pointing to nothing): . During
simulation, the tool will not allocate memory for this object and error is reported.
There will not be any compilation error.
EXAMPLE:
classpacket ;
intlength =0;
functionnew(intl);
length =l;
endfunction
endclass
programmain;
initial
begin
packet pkt;
pkt.length =10;
end
endprogram
RESULT
Error: null object access
Instantiating A Class:
The new operator instantiates a class by allocating memory for a new object and
returning a reference to that memory. The new operator also invokes the object
constructor.
The new operator returns a reference to the object it created. This reference is
usually assigned to a variable of the appropriate type, like:
packet pkt =new(10);
Initializing An Object
Here's the code for the packet class:
EXAMPLE
classpacket ;
intlength =0;
//constructor
functionnew(intl);
length =l;
endfunction
endclass
This class contains a single constructor. You can recognize a constructor because its
declaration uses the same name as the class and it has no return type. The
constructor in the packet class takes one integer arguments, as declared by the code
(int l). The following statement provides 10 as value for those arguments:
packet pkt =new(10);
If a class does not explicitly declare any, the SV compiler automatically provides a noargument constructor, called the default constructor. This default constructor calls
the class parent's no-argument constructor, or the Object constructor if the class has
no other parent.
Constructor
SystemVerilog does not require the complex memory allocation and deallocation of
C++. Construction of an object is straightforward; and garbage collection, as in Java,
is implicit and automatic. There can be no memory leaks or other subtle behavior that
is so often the bane of C++ programmers.
The new operation is defined as a function with no return type, and like any other
function, it must be nonblocking. Even though new does not specify a return type, the
left-hand side of the assignment determines the return type.
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TUTORIALS
THIS
SystemVerilog
Using The This Keyword
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Within an instance method or a constructor, this is a reference to the current

object , the object whose method or constructor is being called. You can refer to any
member of the current object from within an instance method or a constructor by
using this.
The most common reason for using the this keyword is because a field is shadowed
by a method or constructor parameter.
For example, in the packet class was written like this
EXAMPLE
classpacket ;
intlength =0;
//constructor
functionnew(intl);
length =l;
endfunction
endclass
Easy Labs : OVM

Easy Labs : VMM
but it could have been written like this:
AVM Switch TB
EXAMPLE:
VMM Ethernet sample classpacket ;
intlength =0;
//constructor
functionnew(intlength);
Verilog
this.length =length;
Verification
endfunction
Verilog Switch TB
endclass
Basic Constructs
programmain;
OpenVera
initial
Constructs
begin
packet pkt;
Switch TB
pkt =new(10);
RVM Switch TB
$display(pkt.length);
endprogram
Specman E
Interview Questions
RESULT
10
Each argument to the second constructor shadows one of the object's fields inside
the constructor "length" is a local copy of the constructor's first argument. To refer to
the legnth field inside the object , the constructor must use "this.length".
http://testbench.in/CL_04_THIS.html[9/26/2012 2:07:28 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
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Search
TUTORIALS
INHERITANCE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Object-oriented programming allows classes to inherit commonly used state and

behavior from other classes.
Definition (Inheritance) Inheritance is the mechanism which allows a class A to inherit
properties of a class B. We say `À inherits from B''. Objects of class A thus have
access to attributes and methods of class B without the need to redefine them. The
following definition defines two terms with which we are able to refer to participating
classes when they use inheritance.
DPI
Definition (Superclass) If class A inherits from class B, then B is called superclass of

A.
UVM Tutorial
Definition (Subclass) If class A inherits from class B, then A is called subclass of B.
VMM Tutorial
OVM Tutorial
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Objects of a subclass can be used where objects of the corresponding superclass are
expected. This is due to the fact that objects of the subclass share the same
behaviour as objects of the superclass. Superclasses are also called parent classes.
Subclasses may also be called child classes or extended classes or just derived classes
.Of course, you can again inherit from a subclass, making this class the superclass of
the new subclass. This leads to a hierarchy of superclass/subclass relationships.
The idea of inheritance is simple but powerful: When you want to create a new class
and there is already a class that includes some of the code that you want, you can
VMM Ethernet sample derive your new class from the existing class. In doing this, you can reuse the fields
and methods of the existing class without having to write (and debug!) them yourself.
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
A subclass inherits all the members (fields, methods, and nested classes) from its
superclass. Constructors are not members, so they are not inherited by subclasses, but
the constructor of the superclass can be invoked from the subclass.
What You Can Do In A Subclass:
A subclass inherits all of the public and protected members of its parent. You can use
the inherited members as is, replace them, hide them, or supplement them with new
members:
Switch TB
The inherited fields can be used directly, just like any other fields.
You can declare a field in the subclass with the same name as the one in the
RVM Ethernet sample superclass, thus hiding it (not recommended).
RVM Switch TB
You can declare new fields in the subclass that are not in the superclass.
Specman E
Interview Questions
The inherited methods can be used directly as they are.

You can write a new instance method in the subclass that has the same signature
as the one in the superclass, thus overriding it.
You can write a new static method in the subclass that has the same signature as
the one in the superclass, thus hiding it.
You can declare new methods in the subclass that are not in the superclass.
You can write a subclass constructor that invokes the constructor of the
http://testbench.in/CL_05_INHERITANCE.html[9/26/2012 2:07:36 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
superclass, either implicitly or by using the keyword super.
Overriding
Following example shows, adding new varibles, new methods, redefining existing
methods.
EXAMPLE:
classparent;
taskprintf();
$display(" THIS IS PARENT CLASS ");
endtask
endclass
classsubclass extendsparent;
taskprintf();
$display(" THIS IS SUBCLASS ");
endtask
endclass
programmain;
initial
begin
parent p;
subclass s;
p =new();
s =new();
p.printf();
s.printf();
end
endprogram
RESULT
THIS IS PARENT CLASS
THIS IS SUBCLASS
Super
The super keyword is used from within a derived class to refer to members of the
parent class. It is necessary to use super to access members of a parent class when
those members are overridden by the derived class.
EXAMPLE:
classparent;
taskprintf();
endtask
endclass
taskprintf();
super.printf();
endtask
endclass
programmain;
initial
begin
subclass s;
s =new();
s.printf();
end
endprogram
RESULT
The member can be a member declared a level up or be inherited by the class one
level up. There is no way to reach higher (for example, super.super.count is not
allowed).
Subclasses (or derived classes) are classes that are extensions of the current class
whereas superclasses (parent classes or base classes) are classes from which the
current class is extended, beginning with the original base class.
NOTE: When using the super within new, super.new shall be the first statement
executed in the constructor. This is because the superclass must be initialized before
the current class and, if the user code does not provide an initialization, the compiler
shall insert a call to super.new automatically.
Is Only Method
Programmers canoverride the existing code/functionality before existing code and
replaces with new code as shown in below example.
EXAMPLE:
classparent;
taskprintf();
endtask
endclass
taskprintf();
endtask
endclass
programmain;
initial
begin
subclass s;
s =new();
s.printf();
end
endprogram
RESULT:
THIS IS SUBCLASS
Is First Method
Programmers canadd new lines of code/functionality before existing code as shown
in below example.
EXAMPLE:
classparent;
taskprintf();
endtask
endclass
taskprintf();
super.printf();
endtask
endclass
programmain;
initial
begin
subclass s;
s =new();
s.printf();
end
endprogram
RESULT:
THIS IS SUBCLASS
Is Also Method
Programmers canadd new lines of code/functionality after the existing code as
shown in below example.
EXAMPLE:
classparent;
taskprintf();
endtask
endclass
taskprintf();
super.printf();
endtask
endclass
programmain;
initial
begin
subclass s;
s =new();
s.printf();
end
endprogram
RESULT:
THIS IS SUBCLASS
Overriding Constraints.
Programmers canoverride the existing constraint and replaces with new constraint as
shown in below example.
EXAMPLE:
classBase;
randintegerVar;
constraintrange {Var <100;Var >0;}
endclass
classExtended extendsBase;
constraintrange {Var <100;Var >50;}// Overrighting the Base class
constraints.
endclass
programinhe_31;
Extended obj;
initial
begin
obj =new();
for(inti=0;i <100;i++)
if(obj.randomize())
$display(" Randomization sucsessfull : Var = %0d ",obj.Var);
else
$display("Randomization failed");
end
endprogram
RESULT:
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
77
86
76
89
86
76
96
Overriding Datamembers
Only virtual methods truly override methods in base classes. All other methods and
properties do not override but provide name hiding.
EXAMPLE
classbase;
intN =3;
functionintget_N();
returnN;
endfunction
endclass
classext extendsbase;
intN =4;
functionintget_N();
returnN;
endfunction
functionintget_N1();
returnsuper.N;
endfunction
endclass
programmain;
initial
begin
ext e =new;
base b =e;// Note same object!
$display(b.get_N());// "3"
$display(e.get_N());// "4"
$display(e.get_N1());// "3"- super.N
end
endprogram
RESULT
3
4
3
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TUTORIALS
ENCAPSULATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Encapsulation is a technique for minimizing interdependencies among modules by

defining a strict external communication. This way, internal coding can be changed
without affecting the communication, so long as the new implementation supports the
same (or upwards compatible) external communication.
Encapsulation prevents a program from becoming so interdependent that a small
change has massive ripple effects.
The implementation of an object can be changed without affecting the application
that uses it for:
Improving performance, fix a bug, consolidate code or for porting.
VMM Tutorial
Access Specifiers:
OVM Tutorial
In SystemVerilog, unqualified class properties and methods are public, available to

anyone who has access to the objects name.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
A member identified as local is available only to methods inside the class. Further,
these local members are not visible within subclasses. Of course, nonlocal methods
that access local class properties or methods can be inherited and work properly as
methods of the subclass.
AVM Switch TB
EXAMPLE: local variblg error

VMM Ethernet sample classbase;
localinti;
endclass
Verilog
programmain;
Verification
initial
Verilog Switch TB
begin
base b =new();
Basic Constructs
b.i =123;
end
endprogram
OpenVera
Constructs
RESULT:
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Local member 'i' of class 'base' is not accessible from scope 'main'
The above examples gives compilation error.
EXAMPLE:local varible access using method
classbase;
localinti;
taskset(intj);
i =j;
$display(i);
endtask
endclass
programmain;
initial
begin
http://testbench.in/CL_06_ENCAPSULATION.html[9/26/2012 2:07:44 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
base b =new();
b.set(123);
end
endprogram
RESULT
123
EXAMPLE:local varible access in subclass
classbase;
localinti;
endclass
functionnew();
i =10;
endfunction
endclass
RESULT
Local member 'i' of class 'base' is not accessible from scope 'ext'
A protected class property or method has all of the characteristics of a local member,
except that it can be inherited; it is visible to subclasses.
EXAMPLE: protected varible
classbase;
protectedinti;
endclass
functionnew();
i =10;
endfunction
endclass
EXAMPLE: protected varible in 2 level of inheritence
classbase;
localinti;
endclass
protectedinti;
endclass
classext2 extendsext;
functionnew();
i =10;
endfunction
endclass
In the above example, the varible i is overloaded in subclass with different qualifier.
EXAMPLE: Error access to protected varible.
classbase;
protectedinti;
endclass
programmain;
initial
begin
base b =new();
b.i =123;
end
endprogram
RESULT
Protected member 'i' of class 'base' is not accessible from scope 'main'
Within a class, a local method or class property of the same class can be referenced,
even if it is in a different instance of the same class.
EXAMPLE
classPacket;
localintegeri;
functionintegercompare(Packet other);
compare=(this.i ==other.i);
endfunction
endclass
A strict interpretation of encapsulation might say that other.i should not be visible
inside of this packet because it is a local class property being referenced from outside
its instance. Within the same class, however, these references are allowed. In this
case, this.i shall be compared to other.i and the result of the logical comparison
returned.
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TUTORIALS
POLYMORPHISM
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Polymorphism allows an entity to take a variety of representations. Polymorphism

means the ability to request that the sameOperationsbe performed by a wide range
of different types of things. Effectively, this means that you can ask many different
objects to perform the same action.Override polymorphism is an override of existing
code. Subclasses of existing classes are given a "replacement method" for methods in
the superclass. Superclass objects may also use the replacement methods when
dealing with objects of the subtype. The replacement method that a subclass provides
has exactly the same signature as the original method in the superclass.
Polymorphism allows the redefining of methods for derived classes while enforcing a
common interface.To achieve polymorphism the 'virtual' identifier must be used when
defining the base class and method(s) within that class.
VMM Tutorial
EXAMPLE: without virtual

classA ;
taskdisp ();
Easy Labs : SV
$display(" This is class A ");
Easy Labs : UVM
endtask
endclass
Easy Labs : OVM
Easy Labs : VMM

classEAextendsA ;
taskdisp ();
AVM Switch TB
$display(" This is Extended class A ");
VMM Ethernet sample endtask
endclass
programmain ;
Verilog
EAmy_ea;
Verification
A my_a;
Verilog Switch TB
initial
Basic Constructs
begin
my_a =new();
my_a.disp();
OpenVera
Constructs
my_ea =new();
my_a =my_ea;
Switch TB
my_a.disp();
RVM Switch TB
end
RVM Ethernet sample endprogram
RESULTS
OVM Tutorial
Specman E
This is class A
This is class A
Interview Questions
EXAMPLE: with virtual

classA ;
virtualtaskdisp ();
endtask
endclass
classEAextendsA ;
taskdisp ();
http://testbench.in/CL_07_POLYMORPHISM.html[9/26/2012 2:07:51 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!

endtask
endclass
programmain ;
EAmy_ea;
A my_a;
initial
begin
my_a =new();
my_a.disp();
my_ea =new();
my_a =my_ea;
my_a.disp();
end
endprogram
RESULTS
This is class A
This is Extended class A
Observe the above two outputs. Methods which are declared as virtual are executing
the code in the object which is created.
The methods which are added in the subclasses which are not in the parent class
canot be acessed using the parent class handle. This will result in a compilation error.
The compiler check whether the method is exesting the parent class definition or not.
EXAMPLE:
classA ;
endclass
classEAextendsA ;
taskdisp ();
endtask
endclass
programmain ;
EAmy_ea;
A my_a;
initial
begin
my_ea =new();
my_a =my_ea;
my_ea.disp();
my_a.disp();
end
endprogram
RESULT:
Member disp not found in class A
To access the varible or method which are only in the subclass and not in the parent
class, revert back the object to the subclass handle.
EXAMPLE:
classA ;
endclass
classEAextendsA ;
taskdisp ();
endtask
endclass
programmain ;
EAmy_ea;
A my_a;
initial
begin
my_ea =new();
my_a =my_ea;
just(my_a);
end
endprogram
taskjust(A my_a);
EAloc;
$cast(loc,my_a);
loc.disp();
endtask
RESULT
Let us see one more example, A parent class is extended and virtual method is
redefined in the subclass as non virtual method. Now if furthur extention is done to
the class, then the method is still considered as virtual method and Polymorphism can
be achived still. It is advised to declare a method as virtual in all its subclass, if it is
declared as virtual in baseclass , to avoid confusion to the end user who is extend the
class.
EXAMPLE:
classA ;
virtualtaskdisp ();
endtask
endclass
classEA_1extendsA ;
taskdisp ();
$display(" This is Extended1 class A ");
endtask
endclass
classEA_2extendsEA_1;
taskdisp ();
$display(" This is Extended2 class A ");
endtask
endclass
programmain ;
EA_2my_ea;
EA_1my_a;
initial
begin
my_ea =new();
my_a =my_ea;
my_a.disp();
just(my_a);
end
endprogram
taskjust(A my_a);
EA_1loc;
$cast(loc,my_a);
loc.disp();
endtask
RESULT
This is Extended2 class A
This is Extended2 class A
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TUTORIALS
ABSTRACT CLASSES
SystemVerilog
With inheritance we are able to force a subclass to offer the same properties like
their superclasses. Consequently, objects of a subclass behave like objects of their
superclasses.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Sometimes it make sense to only describe the properties of a set of objects without
knowing the actual behaviour beforehand
Abstract classes are those which can be used for creation of handles. However their
methods and constructors can be used by the child or extended class. The need for
abstract classes is that you can generalize the super class from which child classes can
share its methods. The subclass of an abstract class which can create an object is
called as "concrete class".
UVM Tutorial
EXAMPLE: useing abstract class

virtualclassA ;
virtualtaskdisp ();
OVM Tutorial
endtask
Easy Labs : SV
endclass
Easy Labs : UVM
classEAextendsA ;
Easy Labs : OVM
taskdisp ();
Easy Labs : VMM
endtask
AVM Switch TB
endclass
VMM Ethernet sample
programmain ;
EAmy_ea;
A my_a;
Verilog
Verification
initial
Verilog Switch TB
begin
my_ea =new();
Basic Constructs
my_a =my_ea;
my_ea.disp();
my_a.disp();
OpenVera
end
Constructs
endprogram
VMM Tutorial
Switch TB
RVM Switch TB
RESULT
RVM Ethernet sample This is Extended class A
Specman E
Interview Questions
EXAMPLE: creating object of virtual class

virtualclassA ;
virtualtaskdisp ();
endtask
endclass
programmain ;
A my_a;
initial
begin
http://testbench.in/CL_08_ABSTRACT_CLASSES.html[9/26/2012 2:07:59 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
my_a =new();
my_a.disp();
end
endprogram
RESULT
Abstract class A cannot be instantiated
Virtual keyword is used to express the fact that derived classes must redefine the
properties to fulfill the desired functionality. Thus from the abstract class point of
view, the properties are only specified but not fully defined. The full definition
including the semantics of the properties must be provided by derived classes.
Definition (Abstract Class) A class A is called abstract class if it is only used as a
superclass for other classes. Class A only specifies properties. It is not used to create
objects. Derived classes must define the properties of A.
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TUTORIALS
PARAMETERISED CLASS
SystemVerilog
Type Parameterised Class
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
At the time, when we write down a class definition, we must be able to say that this
class should define a generic type. However, if we don't know with which types the
class will be used. Consequently, we must be able to define the class with help of a
placeholder to which we refer as if it is the type on which the class operates. Thus,
the class definition provides us with a template of an actual class. The actual class
definition is created once we declare a particular object. Let's illustrate this with the
following example. Suppose, you want to define a list class which should be a generic
type. Thus, it should be possible to declare list objects for integers, bits,objects or
any other type.
EXAMPLE
classList #(typeT =int);
//attributes:
T data_node;
......
......
// methods:
taskappend(T element);
functionT getFirst();
functionT getNext();
......
......
endclass
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc

VMM Ethernet sample
input is what keeps
The above template class List looks like any other class definition. However, the first with time!
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
line declares List to be a template for various types. The identifier T is used as a
placeholder for an actual type. For example, append() takes one element as an
argument. The type of this element will be the data type with which an actual list
object is created. For example, we can declare a list object for "packet" if a
definition fot the type "packet" exists:
EXAMPLE
List#(packet)pl;// Object pl is a list of packet
List#(string)sl;// Object sl is a list of strings
The first line declares List#(packet) to be a list for packets. At this time, the compiler
uses the template definition, substitutes every occurrence of T with "packet" and
RVM Switch TB
creates an actual class definition for it. This leads to a class definition similar to the
RVM Ethernet sample one that follows:
Switch TB
Specman E
Interview Questions
EXAMPLE
classList {
//attributes:
packet data_node;
......
......
// methods:
taskappend(packet element);
functionpacket getFirst();
functionpacket getNext();
......
......
}
http://testbench.in/CL_09_PARAMETERISED_CLASS.html[9/26/2012 2:08:07 PM]
This is not exactly, what the compiler generates. The compiler must ensure that we
can create multiple lists for different types at any time. For example, if we need
another list for, say "strings", we can write:
EXAMPLE
List#(packet)pl;// Object pl is a list of packet
List#(string)sl;// Object sl is a list of strings
In both cases the compiler generates an actual class definition. The reason why both
do not conflict by their name is that the compiler generates unique names. However,
since this is not viewable to us, we don't go in more detail here. In any case, if you
declare just another list of "strings", the compiler can figure out if there already is an
actual class definition and use it or if it has to be created. Thus,
EXAMPLE
List#(packet)rcv_pkt;// Object rcv_pkt is a list of packet
List#(packet)sent_pkt;// Object sent_pkt is a list of packet
will create the actual class definition for packet List and will reuse it for another List.
Consequently, both are of the same type. We summarize this in the following
definition:
Definition (Parameterized Class) If a class A is parameterized with a data type B, A is
called template class. Once an object of A is created, B is replaced by an actual data
type. This allows the definition of an actual class based on the template specified for
A and the actual data type.
We are able to define template classes with more than one parameter. For example,
directories are collections of objects where each object can be referenced by a key.
Of course, a directory should be able to store any type of object. But there are also
various possibilities for keys. For instance, they might be strings or numbers.
Consequently, we would define a template class Directory which is based on two type
parameters, one for the key and one for the stored objects.
Value Parameterised Class
The normal Verilog parameter mechanism is also used to parameterize a class.
EXAMPLE
classBase#(intsize=3);
bit[size:0]a;
taskdisp();
$display(" Size of the vector a is %d ",$size(a));
endtask
endclass
programmain();
initial
begin
Base B1;
Base#(4)B2;
Base#(5)B3;
B1=new();
B2=new();
B3=new();
B1.disp();
B2.disp();
B3.disp();
end
endprogram
RESULT
Size of the vector a is 4
Instances of this class can then be instantiated like modules or interfaces:

EXAMPLE
vector #(10)vten;// object with vector of size 10
vector #(.size(2))vtwo;// object with vector of size 2
typedefvector#(4)Vfour;// Class with vector of size 4
Generic Parameterised Class
A specialization is the combination of a specific generic class with a unique set of
parameters. Two sets of parameters shall be unique unless all parameters are the
same as defined by the following rules:
a) A parameter is a type parameter and the two types are matching types.
b) A parameter is a value parameter and both their type and their value are the
same.
All matching specializations of a particular generic class shall represent the same
type. The set of matching specializations of a generic class is defined by the context
of the class declaration. Because generic classes in a package are visible throughout
the system, all matching specializations of a package generic class are the same type.
In other contexts, such as modules or programs, each instance of the scope containing
the generic class declaration creates a unique generic class, thus, defining a new set
of matching specializations.
A generic class is not a type; only a concrete specialization represents a type. In the
example above, the class vector becomes a concrete type only when it has had
parameters applied to it, for example:
typedef vector my_vector; // use default size of 1
EXAMPLE
vector#(6)vx;// use size 6
To avoid having to repeat the specialization either in the declaration or to create
parameters of that type, a typedef should be used:
EXAMPLE
typedefvector#(4)Vfour;
typedefstack#(Vfour)Stack4;
Stack4 s1,s2;// declare objects of type Stack4
Extending Parameterised Class
A parameterized class can extend another parameterized class. For example:
EXAMPLE
classC #(typeT =bit);
...
endclass// base class
classD1#(typeP =real)extendsC;// T is bit (the default)

Class D1 extends the base class C using the base classs default type (bit) parameter.
classD2#(typeP =real)extendsC #(integer);// T is integer
Class D2 extends the base class C using an integer parameter.
classD3#(typeP =real)extendsC #(P);// T is P
Class D3 extends the base class C using the parameterized type (P) with which the
extended class is parameterized.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
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Easy Labs : OVM
Easy Labs : VMM
Index
Introduction
A nested class is a class whose definition appears inside the definition of another Class
class, as if it were a member of the other class. The SystemVerilog programming Object
This
language allows you to define a class within another class.
Inheritance
Encapsulation
EXAMPLE
Polymorphism
classStringList;
Abstract Classes
Parameterised Class
classNode;// Nested class for a node in a linked list.
Nested Classes
stringname;
Constant
Node link;
Static
endclass
Casting
Copy
endclass
Scope Resolution
Operator
classStringTree;
Null
classNode;// Nested class for a node in a binary tree.
stringname;
Typedef Class
Node left,right;
Pure
endclass
Other Oops Features
Misc
endclass
// StringList::Node is different from StringTree::Node
NESTED CLASSES
AVM Switch TB
Nesting allows hiding of local names and local allocation of resources. This is often
VMM Ethernet sample desirable when a new type is needed as part of the implementation of a class.
Declaring types within a class helps prevent name collisions and the cluttering of the
outer scope with symbols that are used only by that class. Type declarations nested
inside a class scope are public and can be accessed outside the class
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Why Use Nested Classes

There are several compelling reasons for using nested classes, among them:
It is a way of logically grouping classes that are only used in one place.
It increases encapsulation.
Nested classes can lead to more readable and maintainable code.
Logical grouping of classes : If a class is useful to only one other class, then it is
logical to embed it in that class and keep the two together. Nesting such "helper
classes" makes their package more streamlined.
Increased encapsulation : Consider two top-level classes, A and B, where B needs
access to members of A that would otherwise be declared private. By hiding class B
within class A, A's members can be declared private and B can access them. In
addition, B itself can be hidden from the outside world.
More readable, maintainable code:Nesting small classes within top-level classes
places the code closer to where it is used.
http://testbench.in/CL_10_NESTED_CLASSES.html[9/26/2012 2:08:16 PM]

input is what keeps
with time!
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TUTORIALS
CONSTANT
SystemVerilog
Verification
Constructs
Interface
SystemVerilog adds another form of a local constant, const. A const form of constant
differs from a localparam constant in that the localparam must be set during
elaboration, whereas a const can be set during simulation, such as in an automatic
task.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Constant Class
An instance of a class (an object handle) can also be declared with the const keyword.
EXAMPLE
constclass_name object =new(3,3,4);
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
In other words, the object acts like a variable that cannot be written. The arguments
to the new method must be constant expressions. The members of the object can be
written (except for those members that are declared const).
Easy Labs : OVM

Easy Labs : VMM
Global Constant
AVM Switch TB
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
Global constant class properties include an initial value as part of their declaration. on This section - Your
VMM Ethernet sample They are similar to other const variables in that they cannot be assigned a value input is what keeps
anywhere other than in the declaration.
with time!
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE
classJumbo_Packet;
constintmax_size =9*1024;// global constant
bytepayload [];
functionnew(intsize);
payload =new[size>max_size ?max_size :size];
endfunction
endclass
Switch TB
EXAMPLE: error : chaning const varible

classA ;
RVM Ethernet sample constinti =10;
endclass
programmain ;
Specman E
A my_a;
Interview Questions
initial
begin
my_a =new();
my_a.i =55;
end
endprogram
RVM Switch TB
RESULT
Error : Variable 'i' declared as 'const' .
http://testbench.in/CL_11_CONSTANT.html[9/26/2012 2:08:24 PM]
Instance Constants
Instance constants do not include an initial value in their declaration, only the const
qualifier. This type of constant can be assigned a value at run time, but the
assignment can only be done once in the corresponding class constructor not from
outside or any other method.
EXAMPLE
classA ;
constinti;
functionnew();
i =20;
endfunction
endclass
programmain ;
A my_a;
initial
begin
my_a =new();
$display(my_a.i);
end
endprogram
RESULT
20
EXAMPLE: error : assignment done twice
classA ;
constinti;
functionnew();
i =20;
i++;
endfunction
endclass
RESULT
Instance constants assignment can only be done once
EXAMPLE: error : assignment in other method
classA ;
constinti;
taskset();
i =20;
endtask
endclass
RESULT
Instance constants assignment allowed only in class constructor.
Typically, global constants are also declared static because they are the same for all
instances of the class. However, an instance constant cannot be declared static
because that would disallow all assignments in the constructor
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TUTORIALS
STATIC
SystemVerilog
Static Class Properties
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
A static property is a class variable that is associated with the class, rather than with
an instance of the class (a.k.a., an object). This means that when it is changed, its
change is reflected in all instances of the class. Static properties are declared with
the static keyword. If you need to access a static property inside a class, you can also
use the magic keywords "this" and"super", which resolve to the current class and the
parent of the current class, respectively. Using "this" and "super" allows you to avoid
having to explicitly reference the class by name.
DPI
EXAMPLE: Using object name

classA ;
staticinti;
VMM Tutorial
endclass
OVM Tutorial
programmain ;
Easy Labs : SV
A obj_1;
Easy Labs : UVM
A obj_2;
Easy Labs : OVM

initial
Easy Labs : VMM
begin
obj_1 =new();
AVM Switch TB
obj_2 =new();
VMM Ethernet sample obj_1.i =123;
$display(obj_2.i);
end
endprogram
Verilog
Verification
RESULT
UVM Tutorial
Verilog Switch TB
Basic Constructs
123
OpenVera
Constructs
The static class properties can be accessed using class name.
Switch TB
EXAMPLE: using class name

classA ;
RVM Ethernet sample staticinti;
endclass
programmain ;
Specman E
A obj_1;
Interview Questions
initial
begin
obj_1 =new();
obj_1.i =123;
$display(A::i);
end
endprogram
RVM Switch TB
RESULT
http://testbench.in/CL_12_STATIC.html[9/26/2012 2:08:32 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
123
The static class properties can be used without creating an object of that type.
EXAMPLE: without creating object
classA ;
staticinti;
endclass
programmain ;
A obj_1;
A obj_2;
initial
begin
obj_1.i =123;
$display(obj_2.i);
end
endprogram
RESULT
123
EXAMPLE: using the object name, without creating object
classA ;
staticinti;
endclass
programmain ;
A obj_1;
initial
begin
obj_1.i =123;
$display(A::i);
end
endprogram
RESULT
123
Static Methods
Methods can be declared as static. A static method is subject to all the class scoping
and access rules, but behaves like a regular subroutine that can be called outside the
class.
EXAMPLE
classA ;
statictaskincr();
intj;//automatic variable
j++;
$display("J is %d",j);
endtask
endclass
programmain ;
A obj_1;
A obj_2;
initial
begin
$display("Static task - static task with automatic variables");
obj_1=new();
obj_2=new();
obj_1.incr();
obj_2.incr();
obj_1.incr();
obj_2.incr();
obj_1.incr();
$display("Static task - Each call to task will create a separate copy of 'j' and
increment it");
end
endprogram
RESULT
Static task - static task with automatic variables
J is 1
J is 1
J is 1
J is 1
J is 1
Static task - Each call to task will create a separate copy of 'j' and increment it
A static method has no access to nonstatic members (class properties or methods),

but it can directly access static class properties or call static methods of the same
class. Access to nonstatic members or to the special this handle within the body of a
static method is illegal and results in a compiler error.
EXAMPLE
classA ;
intj;
statictaskincr();
j++;
endtask
endclass
programmain ;
A obj_1;
A obj_2;
initial
begin
obj_1=new();
obj_2=new();
obj_1.incr();
obj_2.incr();
end
endprogram
RESULT
A static method has no access to nonstatic members (class properties or methods).
Static methods cannot be virtual.

EXAMPLE
classA ;
intj;
virtualstatictaskincr();
endtask
endclass
RESULT
Error : Static methods cannot be virtual.
The static methods can be accessed using class name.

EXAMPLE: using class name
classA ;
statictaskwho();
$display(" Im static method ");
endtask
endclass
programmain;
initial
A.who();
endprogram
RESULT
Im static method.
The static methods can be used without creating an object of that type.
EXAMPLE: without creating object
classA ;
statictaskwho();
$display(" Im static method ");
endtask
endclass
programmain;
A a;
initial
a.who();
endprogram
RESULT
Im static method.
Static Lifetime Method.
By default, class methods have automatic lifetime for their arguments and
variables.
All variables of a static lifetime method shall be static in that there shall be a single
variable corresponding to each declared local variable in a class, regardless of the
number of concurrent activations of the method.
EXAMPLE
classA ;
taskstaticincr();
inti;//static variable
$display(" i is %d ",i);
i++;
endtask
endclass
programmain;
A a;
A b;
initial
begin
$display("Static lifetime - non static task with static variables");
a =new();
b =new();
a.incr();
b.incr();
a.incr();
b.incr();
a.incr();
$display("Static lifetime - Each call to task will use a single value of 'j' and
increment it");
end
endprogram
RESULT
Static lifetime - non static task with static variables
i is 0
i is 1
i is 2
i is 3
i is 4
Static lifetime - Each call to task will use a single value of 'j' and increment it
Verilog-2001 allows tasks to be declared as automatic, so that all formal arguments

and local variables are stored on the stack. SystemVerilog extends this capability by
allowing specific formal arguments and local variables to be declared as automatic
within a static task, or by declaring specific formal arguments and local variables as
static within an automatic task.
By default, class methods haveautomatic lifetime for their argumentsand variables.
EXAMPLE
classpacket;
staticintid;
//----static task using automatic fields ---//
statictaskpacket_id();
intcount; // by default static task fields are automatic
id=count;// writing in to static variable
$display("id=%d count=%d",id,count);
count++;
endtask
functionnew();
intpckt_type;
pckt_type++;
$display("pckt_type=%d",pckt_type);
endfunction
endclass
programstic_1;
packet jumbo,pause,taggd;
initial
begin
jumbo=new();
jumbo.packt_id();
pause=new();
pause.packt_id();
taggd=new();
taggd.packt_id();
end
endprogram
RESULTS
pckt_type=1; id=0;count=0
pckt_type=1; id=0 ; count=0
pckt_type=1; id=0;count=0
SystemVerilog allows specific formal arguments and local variables to be declared as

automatic within a static task, or by declaring specific formal arguments and local
variables as static within an automatic task.
EXAMPLE
classpacket;
staticintid,pckt_type;
//---static task with static field----//
statictaskpackt_id();
staticintcount;//explicit declaration of fields as static
id=count; //writing in to static variable
$display("id=%d count=%d",id,count);
count++;
endtask
functionnew();
pckt_type++;
$display("pckt_type=%d",pckt_type);
endfunction
endclass
programstic_2;
packet jumbo,pause,taggd;
initial
begin
jumbo=new();
jumbo.packt_id();
pause=new();
pause.packt_id();
taggd=new();
taggd.packt_id();
end
endprogram
RESULTS
pckt_type=1;id=0 count=0;
pckt_type=2;id=1 count=1;
pckt_type=3 ; id=2 count=2;
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Index
Introduction
Class
SystemVerilog
It is always legal to assign a subclass variable to a variable of a class higher in the Object
Verification
This
inheritance tree.
Constructs
Inheritance
Encapsulation
EXAMPLE
Interface
Polymorphism
classparent;
OOPS
Abstract Classes
inti =10;
Parameterised Class
endclass
Randomization
Nested Classes
Functional Coverage
Constant
Static
Assertion
intj;
Casting
DPI
Copy
functionnew();
Scope Resolution
UVM Tutorial
j =super.i;
Operator
VMM Tutorial
Null
endfunction
OVM Tutorial
endclass
Easy Labs : SV
Typedef Class
programmain;
Pure
Easy Labs : UVM
initial
Other Oops Features
begin
Easy Labs : OVM
Misc
subclass s;
Easy Labs : VMM
s =new();
end
AVM Switch TB
endprogram
VMM Ethernet sample RESULT
input is what keeps
TUTORIALS
Verilog
CASTING
J is10
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
It is never legal to directly assign a superclass variable to a variable of one of its

subclasses.
However, it is legal to assign a superclass handle to a subclass variable if the
superclass handle refers to an object of the given subclass.
SystemVerilog provides the $cast system task to assign values to variables that might
not ordinarily be valid because of differing data type. To check whether the
assignment is legal, the dynamic cast function $cast() is used . The syntax for $cast()
is as follows:
task $cast( singular dest_handle, singular source_handle );
or
function int $cast( singular dest_handle, singular source_handle );
When called as a task, $cast attempts to assign the source expression to the
destination variable. If the assignment is invalid, a run-time error occurs, and the
destination variable is left unchanged.
EXAMPLE : $cast as task
classB;
virtualtaskprint();
$display(" CLASS B ");
endtask
endclass
http://testbench.in/CL_13_CASTING.html[9/26/2012 2:08:41 PM]
with time!
classE_1extendsB;
virtualtaskprint();
$display(" CLASS E_1 ");
endtask
endclass
classE_2extendsB;
virtualtaskprint();
endtask
endclass
programmain;
initial
begin
B b;
E_1e1;
E_2e2;
e1 =new();
$cast(b,e1);
b.print();
end
endprogram
RESULT
CLASS E_1
EXAMPLE : $cast as task with error
classB;
virtualtaskprint();
endtask
endclass
classE_1extendsB;
virtualtaskprint();
endtask
endclass
classE_2extendsB;
virtualtaskprint();
endtask
endclass
programmain;
initial
begin
B b;
E_1e1;
E_2e2;
e1 =new();
$cast(e2,e1);
end
endprogram
RESULT
Error: Dynamic cast failed
When called as a function, $cast attempts to assign the source expression to the
destination variable and returns 1 if the cast is legal. If the cast fails, the function
does not make the assignment and returns 0. When called as a function, no run-time
error occurs, and the destination variable is left unchanged. It is important to note
that $cast performs a run-time check. No type checking is done by the compiler,
except to check that the destination variable and source expression are singulars.
EXAMPLE : $cast as function

classB;
virtualtaskprint();
endtask
endclass
classE_1extendsB;
virtualtaskprint();
endtask
endclass
classE_2extendsB;
virtualtaskprint();
endtask
endclass
programmain;
initial
begin
B b;
E_1e1;
E_2e2;
e1 =new();
//calling $cast like a task
//Return value is not considered
$cast(b,e1);
which_class(b);
e2 =new();
//calling $cast like a task
//Return value is not considered
$cast(b,e2);
which_class(b);
end
endprogram
taskwhich_class(B b);
E_1e1;
E_2e2;
//calling $cast like a function
//Return value is considered for action
if($cast(e1,b))
if($cast(e2,b))
endtask
RESULT
CLASS E_1
CLASS E_2
When used with object handles, $cast() checks the hierarchy tree (super and
subclasses) of the source_expr to see whether it contains the class of dest_handle. If
it does, $cast() does the assignment. Otherwise, the error is issued.
Assignment of Extended class object to Base class object is allowed. It is Illegal to
assign Base class object to Extended class.
EXAMPLE
classBase;
endclass
classExten extendsBase;
endclass
programmain;
initial
begin
Base B;
Exten E;
B =new();
if(!$cast(E,B))
$display(" Base class object B canot be assigned to Extended class
Handle.");
// Deallocate object B
B =null;
E =new();
if(!$cast(B,E))
$display(" Extended class object E canot be assigned to Base class
Handle.");
end
endprogram
RESULT
Base class object B canot be assigned to Extended class Handle.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Index
Introduction
The terms "deep copy"and"shallow copy"refer to the way objects are Class
copied,forexample,during the invocation of a copy constructor orassignment Object
This
operator.
Inheritance
Encapsulation
EXAMPLE:
Polymorphism
classB;
Abstract Classes
inti;
Parameterised Class
endclass
Nested Classes
Constant
programmain;
Static
initial
Casting
begin
Copy
B b1;
Scope Resolution
B b2;
Operator
b1 =new();
Null
b1.i =123;
b2 =b1;
$display(b2.i );
Typedef Class
end
Pure
endprogram
Other Oops Features
RESULTS:
Misc
123
COPY

VMM Ethernet sample
input is what keeps
In the above example, both objects are pointing to same memory. The properties did Testbench.in improving
with time!
not get copied. Only the handle is copied.
AVM Switch TB
Verilog
Verification
Shallow Copy
Verilog Switch TB
A shallow copy of an object copies all of the member field values.
Basic Constructs
EXAMPLE:
classB;
inti;
OpenVera
endclass
Constructs
programmain;
Switch TB
initial
RVM Switch TB
begin
RVM Ethernet sample B b1;
B b2;
b1 =new();
b1.i =123;
Specman E
b2 =newb1;
b2.i =321;
Interview Questions
$display(b1.i );
$display(b2.i );
end
endprogram
RESULTS:
123
321
http://testbench.in/CL_14_COPY.html[9/26/2012 2:08:49 PM]
This works well if the fields are values, but may not be what you want for fields that
point to dynamically allocated memory. The pointer will be copied. but the memory it
points to will not be copied -- the field in both the original object and the copy will
then point to the same dynamically allocated memory, which is not usually what you
want. The assignment operator make shallow copies.
EXAMPLE:
classA;
inti;
endclass
classB;
A a;
endclass
programmain;
initial
begin
B b1;
B b2;
b1 =new();
b1.a =new();
b1.a.i =123;
b2 =newb1;
$display(b1.a.i );
$display(b2.a.i );
b1.a.i =321;
$display(b1.a.i );
$display(b2.a.i );
end
endprogram
RESULT
123
123
321
321
In the above example, the varible i is changed to which is inside the object of .This
changes in seen in also because both the objects are pointing to same memory
location.
Deep Copy
A deep copy copies all fields, and makes copies of dynamically allocated memory
pointed to by the fields. To make a deep copy, you must write a copy constructor and
overload the assignment operator, otherwise the copy will point to the original, with
disasterous consequences.
EXAMPLE:
classA;
inti;
endclass
classB;
A a;
taskcopy(A a);
this.a =newa;
endtask
endclass
programmain;
initial
begin
B b1;
B b2;
b1 =new();
b1.a =new();
b1.a.i =123;
b2 =newb1;
b2.copy(b1.a);
$display(b1.a.i );
$display(b2.a.i );
b1.a.i =321;
$display(b1.a.i );
$display(b2.a.i );
end
endprogram
RESULTS:
123
123
321
123
Clone
A clone method returns a new object whose initial state is a copy of the current state
of the object on which clone was invoked. Subsequent changes to the clone will not
affect the state of the original. Copying is usually performed by a clone() method
method of a class which is user defined. This method usually, in turn, calls the clone()
method of its parent class to obtain a copy, and then does any custom copying
procedures. Eventually this gets to the clone() method of Object (the uppermost
class), which creates a new instance of the same class as the object and copies all the
fields to the new instance (a "shallow copy"). After obtaining a copy from the parent
class, a class's own clone() method may then provide custom cloning capability, like
deep copying (i.e. duplicate some of the structures referred to by the object) .
One disadvantage is that the return type of clone() is Object, and needs to be
explicitly cast back into the appropriate type (technically a custom clone() method
could return another type of object; but that is generally inadvisable).
One advantage of using clone() is that since it is an overridable method, we can call
clone() on any object, and it will use the clone() method of its actual class, without
the calling code needing to know what that class is (which would be necessary with a
copy constructor).
EXAMPLE:
????
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TUTORIALS
SCOPE RESOLUTION OPERATOR
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
EXAMPLE:
classBase;
typedefenum{bin,oct,dec,hex}radix;
taskprint(radix r,integern );
$display(" Enum is %s ",r.name());
$display(" Val is %d",n);
endtask
endclass
programmain;
initial
begin
Base b =new;
intbin =123;
b.print(Base::bin,bin );// Base::bin and bin are different
end
endprogram
RESULT:
Enum is bin
Val is123
In addition, to disambiguating class scope identifiers, the :: operator also allows

access to static members (class properties and methods) from outside the class,
Verilog Switch TB
Basic Constructs
EXAMPLE:
classBase;
OpenVera
taskprint(radix r,integern );
$display(" Enum is %s ",r.name());
$display(" Val is %d",n);
Switch TB
endtask
RVM Switch TB
endclass
RVM Ethernet sample
programmain;
Constructs
Specman E
Interview Questions
initial
begin
intbin =123;
Base::print(Base::bin,bin );// Base::bin and bin are different
end
endprogram
RESULT:
Enum is bin
Val is123
http://testbench.in/CL_15_SCOPE_RESOLUTION_OPERATOR.html[9/26/2012 2:08:56 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
Scope resolution operator ::can be used to access to public or protected elements of

a superclass from within the derived classes.
EXAMPLE:
classBase;
endclass
classExt extendsBase;
typedefenum{dec,hex,bin,oct}radix;
taskprint();
$display(" Extclasss :: enum values %d %d %d %d ",bin,oct,dec,hex);
$display("
Base
classs
::
enum
values
%d
%d
%d
",Base::bin,Base::oct,Base::dec,Base::hex);
endtask
endclass
programmain;
initial
begin
Ext e;
e =new();
e.print();
end
endprogram
RESULT:
%d
Extclasss :: enum values 2 3 0 1

Base classs :: enum values 0 1 2 3
In SystemVerilog, the class scope resolution operator applies to all static elements of
a class: static class properties, static methods, typedefs, enumerations, structures,
unions, and nested class declarations. Class scope resolved expressions can be read (in
expressions), written (in assignments or subroutines calls), or triggered off (in event
expressions). They can also be used as the name of a type or a method call.
The class scope resolution operator enables the following:

Access to static public members (methods and class properties) from outside the
class hierarchy.
Access to public or protected class members of a superclass from within the
derived classes.
Access to type declarations and enumeration named constants declared inside the
class from outside the class hierarchy or from within derived classes.
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TUTORIALS
NULL
SystemVerilog
The Null is perhaps the most "intelligent" pattern of all. It knows exactly what to do
all the time, every time. Its does nothing. The Null is somewhat difficult to describe,
since it resides in an abstract hierarchy tree, having no particular place at all, but
occupying many roles. It is somewhat like the mathematical concept of zero: it is a
placeholder, but is in itself nothing, and has no value. Null Object is a behavioral
pattern designed to act as a default value of an object in most OOPs tools. These
references need to be checked to ensure they are not null before invoking any
methods, because one can't invoke anything on a null reference; this tends to make
code less readable. If you forgot to creat an object ane passed it to method, where
the method has some operation on the object, the simulation fails.So , If the method
is expecting an object , then check weathe the object is created or not else take
nessesary action.The advantage of this approach over a working default
implementation is that a Null Object is very predictable and has no side effects.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
EXAMPLE
classB;
Easy Labs : SV
taskprintf();
$display(" Hi ");
endtask
Easy Labs : OVM
endclass
Easy Labs : VMM
programmain;
AVM Switch TB
initial
VMM Ethernet sample begin
B b;
print(b);
end
Verilog
endprogram
Verification
Verilog Switch TB
taskprint(B b);
if(b ==null)
Basic Constructs
$display(" b Object is not created ");
else
b.printf();
OpenVera
endtask
Easy Labs : UVM
Constructs
Switch TB
RVM Switch TB
RESULT:
RVM Ethernet sample b Object is not created
Specman E
Interview Questions
http://testbench.in/CL_16_NULL.html[9/26/2012 2:09:04 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
<< PREVIOUS PAGE
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http://testbench.in/CL_16_NULL.html[9/26/2012 2:09:04 PM]
Search
Index
Introduction
Class
SystemVerilog
Class methods and Constraints can be defined in the following places:
Object
Verification
inside a class.
This
outside a class in the same file.
Constructs
Inheritance
outside a class in a separate file.
Encapsulation
Interface
Polymorphism
The process of declaring an out of block method involves:
OOPS
Abstract Classes
declaring the method prototype or constraint within the class declaration with Parameterised Class
Randomization
extern qualifier.
Nested Classes
Functional Coverage
declaring the full method or constraint outside the class body.
Constant
Static
Assertion
The extern qualifier indicates that the body of the method (its implementation) or Casting
DPI
constraint block is to be found outside the declaration.
Copy
Scope Resolution
UVM Tutorial
NOTE :class scope resolution operator :: should be used while defining.
Operator
VMM Tutorial
Null
OVM Tutorial
EXAMPLE:
Easy Labs : SV
classB;
Typedef Class
externtaskprintf();
Pure
Easy Labs : UVM
endclass
Other Oops Features
Easy Labs : OVM
Misc
Easy Labs : VMM
taskB::printf();
$display(" Hi ");
AVM Switch TB
endtask
VMM Ethernet sample
input is what keeps
programmain;
initial
with time!
begin
Verilog
B b;
Verification
b =new();
b.printf();
Verilog Switch TB
end
Basic Constructs
endprogram
TUTORIALS
EXTERNAL DECLARATION
OpenVera
RESULT:
Constructs
Switch TB
Hi
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CL_17_EXTERNAL_DECLARATION.html[9/26/2012 2:09:11 PM]
<< PREVIOUS PAGE
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http://testbench.in/CL_17_EXTERNAL_DECLARATION.html[9/26/2012 2:09:11 PM]
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TUTORIALS
CLASSES AND STRUCTURES
SystemVerilog
class differs from struct in three fundamental ways:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
SystemVerilog structs are strictly static objects; they are created either in a static
memory location (global or module scope) or on the stack of an automatic task.
Conversely, SystemVerilog objects (i.e., class instances) are exclusively dynamic;
their declaration does not create the object. Creating an object is done by calling
new.
SystemVerilog objects are implemented using handles, thereby providing C-like
pointer functionality. But, SystemVerilog disallows casting handles onto other data
types; thus, unlike C, SystemVerilog handles are guaranteed to be safe.
SystemVerilog objects form the basis of an Object-Oriented data abstraction that
provides true polymorphism. Class inheritance, abstract classes, and dynamic casting
are powerful mechanisms that go way beyond the mere encapsulation mechanism
provided by structs.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CL_18_CLASSES_AND_STRUCTURES.html[9/26/2012 2:09:19 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
<< PREVIOUS PAGE
TOP
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http://testbench.in/CL_18_CLASSES_AND_STRUCTURES.html[9/26/2012 2:09:19 PM]
Search
TUTORIALS
TYPEDEF CLASS
SystemVerilog
Forward Reference
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
A forward declaration is a declaration of a object which the programmer has not yet
given a complete definition. The term forward reference is sometimes used as a
synonym of forward declaration. However, more often it is taken to refer to the
actual use of an entity before any declaration. The SystemVerilog language supports
the typedef class construct for forward referencing of a class declaration. This allows
for the compiler to read a file from beginning to end without concern for the
positioning of the class declaration.
Easy Labs : SV
EXAMPLE:
classY ;
X x;// refers to Class X, which is not yet defined
endclass
classX;
inti;
endclass
Easy Labs : UVM
RESULT
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : OVM

Easy Labs : VMM
Error : Class X is not defined
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc

VMM Ethernet sample When the compiler encounters the handle x of class type X referred to in class Y, it input is what keeps
does not yet know the definition for class X since it is later in the file. Thus, Testbench.in improving
with time!
compilation fails.
AVM Switch TB
Verilog
To rectify this situation, typedef is used to forward reference the class declaration.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
EXAMPLE:
typedefclassX;
classY ;
X x;// refers to Class X, which is not yet defined
endclass
classX;
inti;
endclass
The typedef of class X allows the compiler to process Y before X is fully defined. Note
that typedef cannot be used to forward reference a class definition in another file.
This must be done using the inclusion of a header file.
Circular Dependency
A Circular dependency is a situation which can occur in programming languages
wherein the definition of an object includes the object itself.One famous example is
Linked List.
EXAMPLE:
classY ;
inti;
http://testbench.in/CL_19_TYPEDEF_CLASS.html[9/26/2012 2:09:26 PM]
Y y;// refers to Class Y, which is not yet defined

endclass
As you seen, there is a compilation error. To avoid this situation, typedef is used to
forward reference the class declaration and this circular dependency problem can be
avoided.
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TUTORIALS
PURE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
As we have already seen in the previous topics , a virtual method may or may not be
overridden in the derived lasses. It means, it is not necessary for a derived class to
override a virtual method.
But there are times when a base class is not able to define anything meaningful for
the virtual method in that case every derived class must provide its own definition of
the that method.
A pure virtual method is a virtual method that you want to force derived classes to
override. If a class has any unoverridden pure virtuals, it is an "abstract class" and you
can't create objects of that type.
" pure virtual function " or " pure virtual task " declaration is supposed to represent
the fact that the method has no implementation.
There are two major differences between a virtual and a pure virtual function, these
are below:
There CAN'T be a definition of the pure virtual function in the base class.
There MUST be a definition of the pure virtual function in the derived class.
Easy Labs : VMM

AVM Switch TB
EXAMPLE:
VMM Ethernet sample classBase;
purevirtualtaskdisp();
endclass
Verilog
programmain
initial
Verification
begin
Verilog Switch TB
Base B;
Basic Constructs
B =new();
B.disp();
end
endprogram
OpenVera
Constructs
Switch TB
RVM Switch TB
RESULT
Error: pure virtual task disp(); must be overridden in derived class
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CL_20_PURE.html[9/26/2012 2:09:34 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
<< PREVIOUS PAGE
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http://testbench.in/CL_20_PURE.html[9/26/2012 2:09:34 PM]
Search
TUTORIALS
OTHER OOPS FEATURES
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Multiple inheritence and Function overloadingand the OOPs features which are not
supported by System Verilog.
Multiple Inheritence
Multiple inheritance refers to a feature of some object-oriented programming
languages in which a class can inherit behaviors and features from more than one
superclass. This contrasts with single inheritance, where a class may inherit from at
most one superclass. SystemC supports multiple inheritance, SystemVerilog supports
only single inheritance.
Multiple inheritance allows a class to take on functionality from multiple other
classes, such as allowing a class named D to inherit from a class named A, a class
named B, and a class named C.
Easy Labs : SV
EXAMPLE:
classA;
.....
Easy Labs : OVM
endclass
Easy Labs : VMM
classB;
AVM Switch TB
......
VMM Ethernet sample endclass
classC;
......
Verilog
endclass
Verification
Verilog Switch TB
classD extendsA,B,C;
.....
Basic Constructs
endclass
Easy Labs : UVM
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Multiple inheritance is not implemented well in SystemVerilog languages .

Implementation problems include:
Increased complexity
Not being able to explicitly inherit from multiple times from a single class
Order of inheritance changing class semantics.
Method Overloading
Method overloading is the practice of declaring the same method with different
signatures. The same method name will be used with different data type . This is Not
Supported by SystemVerilog as of 2008.
EXAMPLE:
taskmy_task(integeri){...}
taskmy_task(strings){...}
programtest {
integernumber =10;
stringname="vera";
my_task(number);
http://testbench.in/CL_21_OTHER_OOPS_FEATURES.html[9/26/2012 2:09:43 PM]
Index
Introduction
Class
Object
This
Inheritance
Encapsulation
Polymorphism
Abstract Classes
Parameterised Class
Nested Classes
Constant
Static
Casting
Copy
Scope Resolution
Operator
Null
Typedef Class
Pure
Other Oops Features
Misc
input is what keeps
with time!
my_task(name);
}
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Search
Index
Introduction
Class
SystemVerilog
Always Block In Classes
Object
Verification
This
Constructs
SystemVerilog doesnot allow to define always block in program block or class, as Inheritance
Encapsulation
these are meant for testbench purpose.
Interface
Polymorphism
OOPS
Abstract Classes
Example to show the implimentation of always block in program block.
Parameterised Class
Randomization
Nested Classes
EXAMPLE:
Functional Coverage
Constant
programmain;
Static
Assertion
Casting
integera,b;
DPI
Copy
Scope Resolution
UVM Tutorial
initial
Operator
repeat(4)
VMM Tutorial
Null
begin
OVM Tutorial
#({$random()}%20)
a
=$random();
Easy Labs : SV
Typedef Class
#({$random()}%20)
Pure
Easy Labs : UVM
b =$random();
Other Oops Features
end
Easy Labs : OVM
Misc
Easy Labs : VMM

initial
always_task();
AVM Switch TB
VMM Ethernet sample

input is what keeps
taskalways_task();
with time!
fork
forever
Verilog
begin
Verification
@(a,b);
Verilog Switch TB
$display(" a is %d : b is %d at %t ",a,b,$time);
end
Basic Constructs
join_none
endtask
OpenVera
endprogram
TUTORIALS
Constructs
MISC
Switch TB
RESULT
RVM Switch TB
a is -1064739199 : b is x at8
RVM Ethernet sample a is -1064739199 : b is -1309649309 at 25
Specman E
Interview Questions
a
a
a
a
a
a
is1189058957 : b is -1309649309 at 42
is1189058957 : b is -1992863214 at 47
is 114806029 : b is -1992863214 at 48
is 114806029 : b is 512609597 at 66
is1177417612 : b is 512609597 at 75
is1177417612 : b is-482925370 at 84
Example to show the implimentation of always block in class.

EXAMPLE
classBase;
integera,b;
http://testbench.in/CL_22_MISC.html[9/26/2012 2:09:52 PM]
taskalways_task();
fork
forever
begin
@(a,b);
$display(" a is %d : b is %d at %t ",a,b,$time);
end
join_none
endtask
endclass
programmain;
initial
begin
Base obj;
obj =new();
// start the always block.
fork
obj.always_task();
join_none
repeat(4)
begin
#({$random()}%20)
obj.a =$random();
#({$random()}%20)
obj.b =$random();
end
end
endprogram
RESULT
a
a
a
a
a
a
a
a
is -1064739199 : b is x at8
is -1064739199 : b is -1309649309 at 25
is1189058957 : b is -1309649309 at 42
is1189058957 : b is -1992863214 at 47
is 114806029 : b is -1992863214 at 48
is 114806029 : b is 512609597 at 66
is1177417612 : b is 512609597 at 75
is1177417612 : b is-482925370 at 84
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TUTORIALS
CONSTRAINED RANDOM VERIFICATION
SystemVerilog
Introduction :
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Historically,verification engineers used directed test bench to verify the functionality

of their design.Rapid changes have occurred during the past decades in design and
verification.High Level Verification Languages (HVLS) such as e, System
c,Vera,SystemVerilog have become a necessity for verification environments.
Constraint Random stimulus generation is not new. Everybody uses verilog and VHDL
at very low level abstraction for this purpose. HVLS provide constructs to express
specification of stimulus at high level of abstraction and constraint solver generates
legal stimulus.
DPI
UVM Tutorial
VMM Tutorial
Writing constraints at higher level of absctraction,makes the programming closer to

spec.
OVM Tutorial
A constraint language should support:
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Expressions to complex scenarios.

Felxibility to control dynamically.
Combinational and sequential constraints.
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
EXAMPLE:
Combinational constraint :
In ethernet, 13 & 14 th bytes should be equal to payload length.
Sequential constraint:
If request comes, then acknoldegement should be given between 4th to 10th cycles.
NOTE:SystemVerilog doec not support sequential constraints.
This article is about Constrained random verification using SystemVerilog.I tried to
explain every point using examples.
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CR_01_CONSTRAINED_RANDOM_VERIFICATION.html[9/26/2012 2:10:00 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
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Index
Constrained Random
Verification
SystemVerilog
Constrained Random Stimulus Generation In Verilog:
Verilog Crv
Verification
Verilog has system function $random, which can be used to generate random input Systemverilog Crv
Constructs
vectors. With this approach,we can generate values which we wouldnt have got, if Randomizing Objects
listed manually. In this topic I would like to discuss what natural things happening Random Variables
Interface
behind $random and how we use it in different manners.
OOPS
Checker
Constraint Block
Randomization
Inline Constraint
EXAMPLE:
Functional Coverage
Global Constraint
moduleTb_mem();
Constraint Mode
Assertion
regclock;
regread_write;
DPI
Randomization
reg[31:0]data;
Controlability
UVM Tutorial
reg[31:0]address;
Static Constraint
VMM Tutorial
initial
Variable Ordering
OVM Tutorial
begin
clock
=0;
Easy Labs : SV
Randcase
forever#10clock =~clock;
Randsequence
Easy Labs : UVM
end
Random Stability
Easy Labs : OVM

Array Randomization
initial
Easy Labs : VMM
Constraint Guards
begin
Titbits
repeat(5)@(negedgeclock)
AVM Switch TB
begin
VMM Ethernet sample read_write =$random;data=$random;address =$random;
$display($time," read_write = %d ; data = %d ; address = on This section - Your
input is what keeps
%d;",read_write,data,address);
end
Verilog
with time!
#10$finish;
Verification
end
Verilog Switch TB
Basic Constructs
endmodule
TUTORIALS
VERILOG CRV
OpenVera
RESULT:
Constructs
20 read_write = 0 ; data = 3230228097 ; address = 2223298057;

RVM Switch TB
RVM Ethernet sample 80 read_write = 1 ; data = 992211318 ; address = 512609597;
Switch TB
Specman E
Interview Questions
$randomsystem function returns a new 32-bit random number each time it is called.
The random number is a signed integer; it can be positive or negative.The following
example demonstrates random generation of signed numbers.
EXAMPLE:
moduleTb();
integeraddress;
initial
begin
http://testbench.in/CR_02_VERILOG_CRV.html[9/26/2012 2:10:12 PM]
repeat(5)
#1address =$random;
end
initial
$monitor("address = %0d;",address);
endmodule
RESULT:
address
address
address
address
address
=
=
=
=
=
303379748;
-1064739199;
-2071669239;
-1309649309;
112818957;
We have seen how to generate random numbers.But the numbers randge from - (2**32
-1) to 2 **32. Most of the time, the requirement is dont need this range. For example,
take a memory. The address starts from 0 to some 1k or 1m.Generating a random
address which DUT is not supporting is meaning less. In verilog there are no constructs
to constraint randomization. Following example demonstrated how to generate
random number between 0 to 10.Using % operation,the remainder of any number is
always between 0 to 10.
EXAMPLE:
moduleTb();
integeradd_1;
initial
begin
repeat(5)
begin
#1;
add_1 =$random%10;
end
end
initial
$monitor("add_1 = %0d",add_1);
endmodule
RESULT:
add_1
add_1
add_1
add_1
=
=
=
=
8;
4294967287;
4294967295;
9;
add_1 = 9;
OOPS!...... The results are not what is expected.The reason is $random generates
negative numbers also. The following example demonstrates proper way of generating
a random number between 0 to 10. Concatenation operator returns only bitvector. Bit
vectors are unsigned, so the results are correct as we expected. Verilog also has
$unsigned systemtask to convert signed numbers to signed number.This can also be
used to meet the requirements. The following example shows the usage of
concatenation operator and $unsigned.
EXAMPLE:
moduleTb();
integeradd_2;
reg[31:0]add_1;
integeradd_3;
initial
begin
repeat(5)
begin
#1;
add_1 =$random%10;
add_2 ={$random}%10;
add_3 =$unsigned($random)%10;
end
end
initial
$monitor("add_3 = %0d;add_2 = %0d;add_1 = %0d",add_3,add_2,add_1);
endmodule
RESULT:
add_3
add_3
add_3
add_3
add_3
=
=
=
=
=
7;add_2
7;add_2
1;add_2
7;add_2
9;add_2
=
=
=
=
=
7;add_1
7;add_1
2;add_1
8;add_1
2;add_1
=
=
=
=
=
8
4
4
9
9
The above example shows the generation of numbers from 0 to N. Some specification
require the range to start from non Zero number. MIN + {$random} % (MAX - MIN ) will
generate random numbers between MIN and MAX.
EXAMPLE:
moduleTb();
integeradd;
initial
begin
repeat(5)
begin
#1;
add =40+{$random}%(50-40);
$display("add = %0d",add);
end
end
endmodule
RESULT:
add =
add =
add =
add =
add =
48
47
47
47
47
Nowhow to generate a random number between two ranges? The number should be
between MIN1 and MAX1 or MIN2 and MAX2. The following example show how to
generate this specification.

EXAMPLE:
moduleTb();
integeradd;
initial
begin
repeat(5)
begin
#1;
if($random%2)
add =40+{$random}%(50-40);
else
add =90+{$random}%(100-90);
$display("add = %0d",add);
end
end
endmodule
RESULT:
add =
add =
add =
add =
add =
97
47
47
42
49
All the random numbers generated above are 32 bit vectors, which is not always the
same requirement. For example, to generate a 5 bit and 45 bit vector random
number, the following method can be used.
EXAMPLE:
moduleTb();
reg[4:0]add_1;
reg[44:0]add_2;
initial
begin
repeat(5)
begin
add_1 =$random;
add_2 ={$random,$random};
$display("add_1 = %b,add_2 = %b ",add_1,add_2);
end
end
endmodule
RESULTS:
add_1
add_1
add_1
add_1
add_1
=
=
=
=
=
00100,add_2
00011,add_2
00101,add_2
01101,add_2
01101,add_2
=
=
=
=
=
111101000000110000100100001001101011000001001
110110000110101000110110111111001100110001101
100100001001000000000111100111110001100000001
100010111011000011110100011011100110100111101
101111000110001111100111111011110100111111001
Some protocols require a random number which is multiple to some number. For
example, Ethernet packet is always in multiples of 8bits. Look at the following
example. It generates a random number which is multiple of 3 and 5.
$random * 3 will give random numbers which are multiples of 3. But if the number
after multiplication needs more than 32 bit to reprasent, then the results may be
wrong.
EXAMPLE:
moduleTb();
integernum_1,num_2,tmp;
initial
begin
repeat(5)
begin
num_1 =($random/3)*3;
num_2 =($random/5)*5;
$display("num_1 = %d,num_2 = %d",num_1,num_2);
end
end
endmodule
RESULT:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
303379746,num_2 = -1064739195
-2071669239,num_2 = -1309649305
112818957,num_2 = 1189058955
-1295874969,num_2 = -1992863210
15983361,num_2 = 114806025
All the above examples show that the random numbers are integers only. In verilog
there is no special construct to generate a random real number.The following method
shows generation of random real numbers.
EXAMPLE:
moduleTb();
integernum_1,num_2,num_3;
realr_num;
initial
begin
repeat(5)
begin
#1;
num_1 =$random;
num_2 =$random;
num_3 =$random;
r_num =num_1 +((10)**(-(num_2)))*(num_3);
$display("r_num = %e",r_num);
end
end
endmodule
RESULT:
r_num
r_num
r_num
r_num
r_num
=
=
=
=
=
-2.071669e+03
2641.189059e+013
976361.598336e+01
57645.126096e+02
24589.097015e+0
To generate random real number , system function $bitstoreal can also be used.
EXAMPLE:
moduleTb();
realr_num;
initial
begin
repeat(5)
begin
#1;
r_num =$bitstoreal({$random,$random});
end
end
endmodule
RESULTS:
r_num = 1.466745e-221
r_num = -6.841798e-287
r_num = 2.874848e-276
r_num = -3.516622e-64
r_num = 4.531144e-304
If you want more control over randomizing real numbers interms of sign, exponential
and mantissa, use $bitstoreal() as shown in example below. For positive numbers use
sgn = 0 and for negative numbers use sgn = 1 .
EXAMPLE:
moduleTb();
regsgn;
reg[10:0]exp;
reg[51:0]man;
realr_num;
initial
begin
repeat(5)
begin
sgn =$random;
exp =$random;
man =$random;
r_num =$bitstoreal({sgn,exp,man});
end
end
endmodule
RESULTS:
r_num
r_num
r_num
r_num
r_num
=
=
=
=
=
3.649952e+193
-1.414950e-73
-3.910319e-149
-4.280878e-196
-4.327791e+273
Some times it is required to generate random numbers without repetition. The

random numbers should be unique. For example,to generate 10 random numbers
between 0 to 9 without repetition, the following logic can be used.
EXAMPLE:
moduleTb();
integernum,i,j,index;
integerarr[9:0];
regind[9:0];
reggot;
initial
begin
index=0;
for(i=0;i<10;i=i+1)
begin
arr[i]=i;
ind[i]=1;
end
for(j =0;j<10;j=j+1)
begin
got =0;
while(got ==0)
begin
index={$random}%10;
if(ind[index]==1)
begin
ind[index]=0;
got =1;
num=arr[index];
end
end
$write("| num=%2d |",num);
end
end
endmodule
RESULT:
| num= 8 || num= 7 || num= 5 || num= 2 || num= 1 || num= 9 || num= 6 || num= 4
|| num= 0 || num= 3 |
Random number returned by $random system function should be deterministic, i.e

when ever we run with simulator it should return values in same sequence. Otherwise
the bug found today cant be found return. For this purpose it has one argument called
seed. The seed parameter controls the numbers that $random returns, such that
different seeds generate different random streams. The seed parameter shall be
either a reg, an integer, or a time variable. The seed value should be assigned to this
variable prior to calling $random.
EXAMPLE:
moduleTb();
integernum,seed,i,j;
initial
begin
for(j =0;j<4;j=j+1)
begin
seed =j;
$display(" seed is %d",seed);
for(i =0;i <10;i=i+1)
begin
num={$random(seed)}%10;
end
$display(" ");
end
end
endmodule
RESULT:
seed is 0
| num= 8 || num= 7 ||
|| num= 1 || num= 9 |
seed is 1
| num= 8 || num= 8 ||
|| num= 5 || num= 5 |
seed is 2
| num= 8 || num= 1 ||
|| num= 1 || num= 6 |
seed is 3
| num= 8 || num= 2 ||
|| num= 3 || num= 9 |
num= 7 || num= 7 || num= 7 || num= 7 || num= 5 || num= 2

The $random function has its own implicit variable as seed when user is not giving
explicitly seed. The following example shows that seed = 0 and implicit seed are
having same sequence.It means that the imlicity taken seed is also 0.
EXAMPLE:
moduleTb();
initial
begin
seed =0;
for(j =0;j<2;j=j+1)
begin
if(j ==0)
else
$display(" No seed is given ");
for(i =0;i <10;i=i+1)
begin
if(j ==0)
else
num={$random}%10;
end
$display(" ");
end
end
endmodule
RESULT:
seed is 0
|| num= 1 || num= 9 |
No seed is given
|| num= 1 || num= 9 |
The system functions shall always return same series of values with same seed. This
facilitates debugging by making the operation of the system repeatable. The argument
for the seed parameter should be an integer variable that is initialized by the user and
only updated by the system function. This ensures the desired distribution is achieved.
In the following example, when ever the seed is changed to 2, the sequence 8-1-0-50-8-6-7-11-6......... is followed. Check out in any tool you will see the same
sequence.
EXAMPLE:
moduleTb();
initial
begin
for(j =0;j<4;j=j+1)
begin
seed =2;
for(i =0;i <10;i=i+1)
begin
end
$display(" ");
end
end
endmodule
RESULT:
seed is 2
| num= 8 || num= 1 ||
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 ||
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 ||
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 ||
|| num= 1 || num= 6 |

Seed is inout port. Random number system function returns a random number and
also returns a random number to seed inout argument also. The results of the
following example demonstrates how seed value is getting changed.
EXAMPLE:
moduleTb();
initial
begin
seed =0;
for(j =0;j<10;j=j+1)
begin
$display(" seed is %d ",seed);
end
end
endmodule
RESULT:
|
|
|
|
|
|
|
|
|
|
num=
num=
num=
num=
num=
num=
num=
num=
num=
num=
8
7
7
7
7
7
5
2
1
9
|
|
|
|
|
|
|
|
|
|
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
is
is
is
is
-1844104698
1082744015
75814084
837833973
-2034665166
-958425333
851608272
154620049
-2131500770
-2032678137
From the above results we can make a table of seed values and return values of
$random. If a seed is taken from table, then rest of the sequence has to follow
sequence in table.
Table is as follows for initial seed 0;
| num= 8 | seed is -1844104698
| num= 7 | seed is 1082744015
| num= 7 | seed is 75814084
| num= 7 | seed is 837833973
| num= 7 | seed is -2034665166
| num= 7 | seed is -958425333
| num= 5 | seed is 851608272
| num= 2 | seed is 154620049
| num= 1 | seed is -2131500770
| num= 9 | seed is -2032678137
.
.
.
.
.
table goes on........
In the following example, the seed is 837833973, which is the 4 th seed from the
above table.
EXAMPLE:
moduleTb();
initial
begin
seed =837833973;
for(j =0;j<10;j=j+1)
begin
end
end
endmodule
RESULTS:
|
|
|
|
num=
num=
num=
num=
7
7
5
2
|
|
|
|
seed
seed
seed
seed
is
is
is
is
-2034665166
-958425333
851608272
154620049
|
|
|
|
|
|
num=
num=
num=
num=
num=
num=
1
9
8
7
9
2
|
|
|
|
|
|
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
-2131500770
-2032678137
-1155272804
-1634874387
-153856566
-970066749
From the above example we can come to conclusion that $random is not giving a
random number. It is randomizing seed and returning corresponding number for that
seed.
Total possible seed values are 4294967295(32'hFFFF_FFFF). Is it possible for $random
to generate all the seeds? . Lets say, if the seed gets repeated after 10 iterations,
then after the 10 iterations, same values are repeated. So $random is circulating
inside a chain of 10 numbers.
The following example demonstrates how $random misses many seeds. I tried to
display the seeds between 0 to 20 in the chaining formed by initial seed of 0. Results
show that total possible seeds are 4294967295 , and number of seeds possible in seed
chain are 4030768279 , so we are missing some seeds. Look at the seeds between 0 to
20. Seed == 1 is missing.
EXAMPLE:
moduleTb();
integernum,seed,j;
reg[0:31]i;
initial
begin
i =0;
seed =1;
while(seed !=0)
begin
if(i ==0)
seed =0;
i =i +1;
num=$random(seed);
if(seed <20&&seed >0)
$display(" seed is %d after values %d ",seed,i);
end
$display(" seed is zero after this number of random numbers %0dtotal numbers
available are %d",i,{32'hffff_ffff});
end
endmodule
RESULTS:
seed is 10 after values 93137101
seed is zero after this number of random numbers 4030768279total numbers
available are 4294967295
Now I tried to simulate with seed = 1 . It's interisting to know that some how the
sequence is able to enter this chaining which is formed with seed=0 and there is no
seed value 1 in this chaining and my simulation hanged. So aborted the simulation and
partial results show that the initial seed = 1 enters the chaing formed by seed 0.
EXAMPLE:
moduleTb();
integernum,seed,j;
reg[0:31]i;
initial
begin
i =0;
seed =0;
while(seed !=1)
begin
if(i ==0)
seed =1;
i =i +1;
num=$random(seed);
end
$display(" seed is one after this number of random numbers %0dtotal numbers
end
endmodule
RESULTS:
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
10 after values 357336117

Verilog also has other system functions to generate random numbers. Each of these
functions returns a pseudo-random number whose characteristics are described by the
function name.
Following are the Verilog random number genrator system functions:
$random
$dist_chi_square
$dist_erlang
$dist_exponential
$dist_normal
$dist_poisson
$dist_t
$dist_uniform
All parameters to the system functions are integer values. For the exponential,
poisson, chi-square ,t and erlangfunctions the parameters mean, degree of freedom,
and k_stage must be greater than 0.
$dist_uniform(seed, min, max) is similar to min + {$random(seed)}%(max-min+1), the
difference is that in $dist_uniform the distribution is uniform. $dist_uniform returns a

number between min and max. In the $dist_uniform function, the start and end
parameters are integer inputs that bound the values returned. The start value should
be smaller than the end value.
The mean parameter used by $dist_normal, $dist_exponential, $dist_poisson and
$dist_erlang is an integer input that causes the average value returned by the function
to approach the value specified. The standard deviation parameter used with the
$dist_normal function is an integer input that helps determine the shape of the
density function. Larger numbers for standard deviation spread the returned values
over a wider range.
The degree of freedom parameter used with the $dist_chi_square and $dist_t
functions is an integer input that helps determine the shape of the density function.
Larger numbers spread the returned values over a wider range.
EXAMPLE:
moduleTb();
integernum_1,num_2,seed;
initial
begin
seed =10;
repeat(5)
begin
#1;
num_1 =$dist_uniform(seed,20,25);
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
23,num_2
22,num_2
25,num_2
23,num_2
=
=
=
=
=
50
55
54
51
55
As i discussed $random randomizes its seed, Lets see whether $dist_uniform is also
doing the same.
EXAMPLE:
moduleTb();
integernum_1,num_2,seedd,seedr;
initial
begin
seedd =10;
seedr =10;
repeat(5)
begin
#1;
num_1 =$dist_uniform(seedd,20,25);
num_2 =20+({$random(seedr)}%6);
$display("num_1
=
%d,num_2
%d",num_1,num_2,seedd,seedr);
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
20,num_2
23,num_2
25,num_2
22,num_2
=
=
=
=
=
22,seedd
20,seedd
22,seedd
21,seedd
23,seedd
=
=
=
=
=
%d,seedd
690691 seedr = 690691

460696424 seedr = 460696424
-1571386807 seedr = -1571386807
-291802762 seedr = -291802762
1756551551 seedr = 1756551551
%d
seedr
Look at the results... Its interesting to note that $random and $dist_uniform have
same seed sequence flow also.
As I mentioned, $dist_uniform(seed, min, max) is similar to min +

{$random(seed)}%(max-min+1). "similar" means they have some common functionality.
$dist_uniform is having uniform distribution, $random for that range is also uniformly
distributed. Following example demonstrates that $dist_uniform and $random are
uniformly distributed.
EXAMPLE:
moduleTb();
integernum,seed;
integernum_20,num_21,num_22,num_23,num_24,num_25;
initial
begin
seed =10;
num_20 =0;num_21 =0;num_22 =0;num_23 =0;num_24 =0;num_25 =0;
repeat(6000)
begin
num=$dist_uniform(seed,20,25);
if(num==20)
num_20 =num_20 +1;
if(num==21)
num_21 =num_21 +1;
if(num==22)
num_22 =num_22 +1;
if(num==23)
num_23 =num_23 +1;
if(num==24)
num_24 =num_24 +1;
if(num==25)
num_25 =num_25 +1;
end
$display("num_20 = %0d;num_21 = %0d;num_22 = %0d;num_23 = %0d;num_24 =
%0d;num_25 = %0d",num_20,num_21,num_22,num_23,num_24,num_25);
end
endmodule
RESULTS:
num_20 = 1014;num_21 = 983;num_22 = 946;num_23 = 1023;num_24 = 1014;num_25 =
1020
EXAMPLE:
moduleTb();
integernum;
initial
begin
seed =10;
repeat(6000)
begin
num=20+({$random(seed)}%6);
if(num==20)
num_20 =num_20 +1;
if(num==21)
num_21 =num_21 +1;
if(num==22)
num_22 =num_22 +1;
if(num==23)
num_23 =num_23 +1;
if(num==24)
num_24 =num_24 +1;
if(num==25)
num_25 =num_25 +1;
end

end
endmodule
RESULTS:
1015
As I mentioned ,$dist_uniform(seed, min, max) is similar to min +
{$random(seed)}%(max-min+1). "similar" means they have some difference. The
difference is that they generate different sequence.
EXAMPLE:
moduleTb();
initial
begin
seedd =10;
seedr =10;
repeat(5)
begin
#1;
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
20,num_2
23,num_2
25,num_2
22,num_2
=
=
=
=
=
22
20
22
21
23
Till now what we have seen is $random has uniform distribution over integer values. It
means that distribution should be uniform across all the bits in 32 bit vector also. The
following example shows that bits positions 2,3,4,11,12,13 have equal probability of
getting 0. For demonstration I showed some index only. Try out rest of them and see
that results is same for all the bits.
EXAMPLE:
moduleTb();
integernum;
initial
begin
repeat(6000)
begin
num=$random;
if(num[2]==0)
num_2 =num_2 +1;
if(num[3]==0)
num_3 =num_3 +1;
if(num[4]==0)
num_4 =num_4 +1;
if(num[11]==0)
num_11 =num_11 +1;
if(num[12]==0)
num_12 =num_12 +1;
if(num[13]==0)
num_13 =num_13 +1;
end
end
endmodule
RESULTS:
2975
The distribution is uniform for system function $random. Suppose if the requirement
is to generate random numbers for more than one variable, and all the variables
should have uniform distribution, then use different seeds for each variable. Other
wise distribution is distributed on all the variables as overall variables which mightnot
be our requirement.. But for lower bits, the distribution is same as shown in example.
EXAMPLE:
moduleTb();
integerseed;
reg[1:0]var_1,var_2,var3,var4;
integernum_2,num_3,num_1,num_0;
integercou_2,cou_3,cou_1,cou_0;
initial
begin
seed =10;
num_2 =0;num_3=0;num_1=0;num_0=0;
cou_2=0;cou_3=0;cou_1=0;cou_0=0;
repeat(40000)
begin
var_1 =$random;
var3 =$random;
var4 =$random;
var_2 =$random;
if(var_1 ==0)
num_0 =num_0 +1;
if(var_1 ==1)
num_1 =num_1 +1;
if(var_1 ==2)
num_2 =num_2 +1;
if(var_1 ==3)
num_3 =num_3 +1;
if(var_2 ==0)
cou_0 =cou_0 +1;
if(var_2 ==1)
cou_1 =cou_1 +1;
if(var_2 ==2)
cou_2 =cou_2 +1;
if(var_2 ==3)
cou_3 =cou_3 +1;
end
$display("num_2
=
%0d;num_3=
%0d;",num_2,num_3,num_1,num_0);
$display("cou_2=
%0d;cou_3=
%0d;",cou_2,cou_3,cou_1,cou_0);
end
endmodule
%0d;num_1=
%0d;cou_1=
%0d;num_0=
%0d;cou_0=
RESULTS:
num_2 = 9984;num_3= 10059;num_1= 10002;num_0= 9955;
cou_2= 10060;cou_3= 9934;cou_1= 10072;cou_0= 9934;
Use system time as seed, so the same TB simulated at different times have different
random sequences and there is more probability of finding bugs. The following is C
code useful in PLI to get system time in to verilog.
#include <stdio.h>
#include <time.h>
char *get_time_string(int mode24);
int get_systime() {
time_t seconds;
seconds = time (NULL);
return seconds;
}
In Verilog 1995standard every simulator has its own random number generation
algorithm.But in Verilog 2001a standard is made that every simulator has to follow
same algorithm.So the same random number sequencecan seen on different
simulators forsame seed.
Don't expectthat the same sequenceis generated on all the simulators.They are
only following same algorithm.The reason is race condition.Look at following
example,both the statements_1 andstatement_2 are scheduled to execute at same
simulation time.The order of execution is notnotknown.Some simulators take
statement_1 as the firststatement to execute andsome other statement_2.If the
TBis built without any race condition to $randomfunctioncalls,then the same
random sequencecan be generated on different simulators anda testbench without
a racecondition on $randomcalls is noteasy to build.
Look at the following 2examples.I just changed the order of statements,the results
are reversed.
@edes
EXAMPLE:new
moduleTb();
initial
$display("staement 2 :::%d",$random);
initial
endmodule
staement 2 :::303379748
staement 1 :::-1064739199
EXAMPLE:
moduleTb();
initial
initial
endmodule
staement 1 :::303379748
staement 2 :::-1064739199
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TUTORIALS
SYSTEMVERILOG CRV
SystemVerilog
Systemverilog Constraint Random Stmulus Generaion :
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
We have seen how to get random values and constrain them. These constraints are at
very low level of abstraction. Todays verification needs a better way to describ the
constraints. SystemVerilog has randomization constructs to support todays verification
needs.
Following are the features of SystemVerilog which support Constraint Random
Verification (CRV) :
1) Constraints : Purely random stimulus takes too long to generate interesting
senarious. Specify the interesting subset of all possible stimulus with constraint
blocks. These are features provided by SystemVerilog for constraining randomness.
Random variable generated in verilog Boolean expressions, foreach (for constraining
elements of array), set membership, inline constraints, rand case, rand sequence,
Conditional constraints and implication constraints.
2) Randomization : random function, constrained and unconstrained randomization,
uniform distribution, weighted distribution,weighted range, weighted case, pre
randomization, post randomization, declaration of random variable and non repeating
sequence.
3) Dynamic constraints : inline constraints, guarded constraints, disabling/enabling
VMM Ethernet sample constraints, disabling/enabling random variables and overriding of constraint blocks.
4) Random Stability : Thread stability, object stability and manual seeding.

Verilog
Verification
In verilog only system functions like $random are used for stimulus generation.
In SystemVerilog, constraint random stimulus can be generated in following ways.
Verilog Switch TB
Basic Constructs
Random Number Generator System Functions

Constructs
In addition to the system function which are in verilog, SystemVerilog has $urandom()
and $urandom_range(). $urandom() and $urandom_range() returns a unsigned values.
Switch TB
The following example demonstrates random generation of unsigned numbers.
OpenVera
RVM Switch TB
RVM Ethernet sample EXAMPLE:
Specman E
Interview Questions
moduleTb();
integerunsignedaddress;
initial
begin
repeat(5)
begin
address =$urandom();
$display("address = %d;",address);
end
end
endmodule
RESULTS:
http://testbench.in/CR_03_SYSTEMVERILOG_CRV.html[9/26/2012 2:10:22 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
#
#
#
#
#
address
address
address
address
address
= 3468265955;
=541037099;
= 3836988758;
= 3611785217;
=978699393;
The seed is an optional argument that determines the sequence of random numbers
generated. The seed can be any integral expression. The random number generator
(RNG) shall generate the same sequence of random numbers every time the same seed
is used.
EXAMPLE:
moduleTb();
initial
begin
for(j =0;j<4;j=j+1)
begin
seed =2;
$display(" seed is set %d",seed);
void'($urandom(seed));
for(i =0;i <10;i=i+1)
begin
num=$urandom()%10;
end
$display(" ");
end
end
endmodule
RESULTS:
seed is set2
| num= 1 || num= 2 ||
|| num= 3 || num= 1 |
seed is set2
| num= 1 || num= 2 ||
|| num= 3 || num= 1 |
seed is set2
| num= 1 || num= 2 ||
|| num= 3 || num= 1 |
seed is set2
| num= 1 || num= 2 ||
|| num= 3 || num= 1 |

$Urandom_range
The $urandom_range() function returns an unsigned integer within a specified range.
The syntax for $urandom_range() is as follows:
function int unsigned $urandom_range( int unsigned maxval,int unsigned minval = 0 );
The function shall return an unsigned integer in the range of maxval ... minval.
EXAMPLE:
moduleTb();
integernum_1,num_2;
initial
begin
repeat(5)
begin
#1;
num_1 =$urandom_range(25,20);
$display("num_1 = %0d,num_2 = %0d",num_1,num_2);
end
end
endmodule
RESULTS:
#
#
#
#
#
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
25,num_2
22,num_2
23,num_2
21,num_2
25,num_2
=
=
=
=
=
55
55
52
54
54
If minval is omitted, the function shall return a value in the range of maxval ... 0.
EXAMPLE:
moduleTb();
integernum_1,num_2;
initial
begin
repeat(5)
begin
#1;
num_1 =$urandom_range(3);
num_2 =$urandom_range(5);
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
3,num_2
2,num_2
1,num_2
3,num_2
1,num_2
=
=
=
=
=
5
5
2
4
4
If maxval is less than minval, the arguments are automatically reversed so that the
first argument is larger than the second argument.
EXAMPLE:
moduleTb();
integernum_1,num_2;
initial
begin
repeat(5)
begin
#1;

end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
25,num_2
22,num_2
23,num_2
21,num_2
25,num_2
=
=
=
=
=
55
55
52
54
54
Scope Randomize Function

The scope randomize function, randomize(), enables users to randomize data in the
current scope.Variables which are passed as arguments are randomized and there is
no limit on the number of arguments.For simpler applications,randomize() function
leads to stright farward implimentation.This gives better control over the $random,as
it allows to add constraints using inline constraints and constraint solver gives valid
solution.Variables which are in the constraint block and not passed as arguments to
randomize() function are not randomized.In the following example Variable Var is
randomized and MIN is not randomized.
EXAMPLE:
modulescope_3;
integerVar;
initial
begin
for(inti =0;i<6;i++)
if(randomize(Var))
$display(" Randomization sucsessfull : Var = %0d ",Var);
else
$finish;
end
endmodule
RESULTS:
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
sucsessfull :
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
-826701341
541037099
-457978538
-683182079
978699393
717199556
1114265683
Scope randomize function gives better control over the $random, as it allows to add
constraints using inline constraints and constraint solver gives valid solution. Variables
which are in the constraint block and not passed as arguments to randomize() function
are not randomized. In the following example Variable Var is randomized and MIN is
not randomized.
EXAMPLE:
modulescope_4;
integerVar;
integerMIN;
initial
begin
MIN=50;
if(randomize(Var)with{Var <100;Var >MIN;})
$display(" Randomization sucsessfull : Var = %0d Min = %0d",Var,MIN);
else
$finish;
end
endmodule
RESULTS:
#Randomization sucsessfull :
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
94
69
53
71
51
78
95
Min
Min
Min
Min
Min
Min
Min
=
=
=
=
=
=
=
50
50
50
50
50
50
50
In randomize function, the solver can't solve if X or Z is used. randomize(Var) with {

Var == 'bx ;} or {MIN = 'bx} will result in an error.
Randomizing Objects
Generating random stimulus within objects :
SystemVerilog allows object-oriented programiming for random stimulus generation,
subjected to specified constraints. During randomization, variables declared as rand
or randc inside class are only considered for randomization. Built-in randomize()
method is called to generate new random values for the declared random variables.
EXAMPLE:
programSimple_pro_5;
classSimple;
randintegerVar;
endclass
Simple
obj;
initial
begin
obj =new();
repeat(5)
if(obj.randomize())
$display(" Randomization successful : Var = %0d ",obj.Var);
else
end
endprogram
RESULTS:
Var
Var
Var
Var
Var
=
=
=
=
=
-82993358
-112342886
-867551972
-34537722
1977312553
Random Unpacked Structs:

SystemVerilog allows unpackedstructs to be declared as rand for randomization. Only
members of struct which are declared as rand or randc are only randomized. randc is
not allowed on unpacked structs. If Struct is not declared as rand, solver considers it
as state variable.
EXAMPLE:
classRand_struct;
typedefstruct{
randcintVar1;
intVar2;
}Struct_t;
randStruct_t Str;// To randomize Var1 and Struct_t type has to declared as
rand
endclass
programstru_rand_6;
Rand_struct RS;
initial
begin
RS=new();
repeat(10)
if(RS.randomize())
$display(" Var1 : %d",RS.Str.Var1);
end
endprogram
RESULTS:
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
:-430761355
: 424439941
: -1129955555
:1781908941
:-752252755
: 922477361
: -2115981855
:1551031961
: -91393015
: 262093271
Simillar to struct, the same can be achived using class by calling the randomize()
function on the object, which is created by using class.
EXAMPLE:
programclass_rand_7;
classClass_t;
randintVar1;
intVar2;
endclass
classRand_class;
randClass_t Cla; // To randomize Var1,Class_t type has to declared as rand
functionnew();
Cla =new();
endfunction
endclass
Rand_class RC=new();
initial
repeat(10)
if(RC.randomize())
$display(" Var1 : %0d Var2 : %0d",RC.Cla.Var1,RC.Cla.Var2);
endprogram
RESULTS:
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
:
:
:
:
:
:
:
:
:
:
733126180 Var2 : 0
-119008195 Var2 : 0
342785185 Var2 : 0
679818185 Var2 : 0
-717162992 Var2 : 0
664520634 Var2 : 0
-1944980214 Var2 : 0
-1350759145 Var2 : 0
-1374963034 Var2 : 0
-462078992 Var2 : 0
SystemVerilog structs are static objects, where as class instances are dynamic
objects, declaring a class instance does not allocate memory space for object. Calling
built in new() function creates memory for object. Class have built in functions and
tasks, where as struct dont, this speeds up simulation time if structs are used. Check
your data structure, if they need simple encapsulation use struct otherwise if they
need object oriented mechanisms then choose class.
Rand Case :
You can use randcase to make a weighted choice between different items, without
having to create a class and instance. An items weight divided by the sum of all
weights gives the probability of taking that branch. More details are discussed in the
following units.
Rand Sequence :
SystemVerilog provides randsequnce to generate random sequencess of operation. It
will be useful for randomly generating structured sequences of stimulus such as
instructions or network traffic patterns.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Constrained Random
Verification
Generating Random Stimulus Within Class :
Verilog Crv
SystemVerilog features which support Constraint random generation inside objects are Systemverilog Crv
Randomizing Objects
:
Random Variables
1) Random Variable declaration.
Checker
2) Built in Functions for generation.
Constraint Block
3) Constraints to control random generation.
Inline Constraint
Global Constraint
Constraint Mode
Variables declared as rand or randc are assigned random values when randomize() External Constraints
function is called, where the constraint specifies the valid solution space from which Randomization
the random values are picked.
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
RANDOMIZING OBJECTS
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CR_04_RANDOMIZING_OBJECTS.html[9/26/2012 2:10:30 PM]

input is what keeps
with time!
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TUTORIALS
RANDOM VARIABLES
SystemVerilog
Random Varible Declaration:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Variables declared as rand or randc are only randomized due to call of randomize()
function. All other varibles are considered as state variables.
EXAMPLE:
classex_8;
rand[3:0]var1;
randc[3:0]var2;
randintegervar3;
endclass
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Fixed arrays, dynamic arrays, associative arrays and queues can be declared as rand
or randc. All their elements are treated as random. Individual array elements can also
be constrained,in this case, index expression must be constant. For dynamic arrays,
the size of the array length can be constrained. Non integer data types like shortreal,
real and realtime are not allowed for random variable declaration.
Rand Modifier :
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
Variables declared with rand keyword are standard random variables. When there are
no other control on distrubution, these variables are uniformly distributed across valid
VMM Ethernet sample values.
AVM Switch TB
EXAMPLE:
classrand_cl;
randbit[0:2]Var;
Verilog Switch TB
constraintlimit_c {Var <4;}
endclass
Basic Constructs
programrand_p_9;
rand_cl obj;
OpenVera
integercount_0,count_1,count_2,count_3;
Constructs
initial
begin
Switch TB
obj =new();
RVM Switch TB
count_0 =0;count_1 =0;count_2 =0;count_3 =0;
RVM Ethernet sample repeat(100000)
begin
void'(obj.randomize());
if(obj.Var ==0)count_0 ++;
Specman E
elseif(obj.Var ==1)count_1 ++;
Interview Questions
end
$display(" count_0 = %0d , count_1 = %0d, count_2 = %0d, count_3 = %0d
",count_0,count_1,count_2,count_3);
end
endprogram
Verilog
Verification
RESULTS:
count_0 = 25046 , count_1 = 24940, count_2 = 24969, count_3 = 25045
http://testbench.in/CR_05_RANDOM_VARIABLES.html[9/26/2012 2:10:38 PM]

input is what keeps
with time!
Simulation results show that the rand variable is distrubuted uniformly.

Randc Modifier :
Variables declared as randc are random cyclic that randomly iterates over all the
values in the range and no value is repeated with in an iteration until every possible
value has been assigned. But Iteration sequences are won't be same. Bit and
enumerated types can be randc variables. To reduce memory requirements,
implementations can impose a limit on maximum size of a randc variable, it should be
not be more than 8 bits.
EXAMPLE:
classrand_c;
randcbit[1:0]Var;
endclass
programrand_cp_10;
rand_c obj=new();
initial
begin
$write("%0d_",obj.Var);
if(i%4==3)
$display("");
end
endprogram
RESULTS:
#
#
#
#
#
0_3_1_2_
3_0_2_1_
0_3_1_2_
0_1_2_3_
3_0_2_1_
The permutation sequence for any given randc variable is recomputed whenever the
constraints changes on that variable or when none of the remaining values in the
permutation can satisfy the constraints.
EXAMPLE:
classrand_c;
randcbit[2:0]Var;
integerMIN=4;
constraintC {Var <MIN;}
endclass
programrand_cp_11;
rand_c obj=new();
initial
begin
obj.MIN=4;
if(i>12)
obj.MIN=7;
if(i==12)
$display(" CONSTRAINT CHANGED ");
if((i%4==3))
$display("");
end
endprogram
RESULTS:
0_2_3_1_
0_1_3_2_
3_2_0_1_
CONSTRAINT CHANGED
0_1_4_2_
6_5_3_0_
Permutation sequence is computed on every call of new() function. So if randc

variables won't behave like random cyclic, if new() is called for every randomization.
In the following example variable Var is not behaving like random cyclic.
EXAMPLE:
classrand_c;
randcbit[1:0]Var;
endclass
programrand_cp_12;
rand_c obj=new();
initial
begin
obj=new();
if(i%4==3)
$display("");
end
endprogram
RESULTS:
#
#
#
#
#
1_3_1_2_
3_2_2_1_
2_0_0_0_
3_3_1_0_
3_0_1_0_
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TUTORIALS
RANDOMIZATION METHODS
SystemVerilog
Randomization Built-In Methods
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
SystemVerilog has randomize(),pre_randomize() and post_randomize() built-in

functions for randomization. Calling randomize() causes new values to be selected for
all of the random variables in an object. To perform operations immediately before or
after randomization,pre_randomize() and post_randomize() are used.
Randomize()
Easy Labs : SV
Every class has a virtualpredefined function randomize(), which is provided for

generating a new value.Randomization function returns 1 if the solver finds a valid
solution. We cannot override this predefined function. It is strongly recommended to
check the return value of randomize function. Constraint solver never fails after one
successful randomization, if solution space is not changed. For every randomization
call, check the return value, solver may fail due to dynamically changing the
constraints.In the following example, there is no solution for Var < 100 and Var >
200,so the randomization fails.
Easy Labs : UVM
The best way to check status of randomization return value is by using assertion.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
assert(obj.randomize());
EXAMPLE:
VMM Ethernet sample programSimple_pro_13;
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
classSimple;
randintegerVar;
constraintc1 {Var <100;}
constraintc2 {Var >200;}
endclass
initial
begin
Simple obj =new();
if(obj.randomize())
else
end
endprogram
RVM Ethernet sample RESULTS:
# Randomization failed
Specman E
Interview Questions
If randomize() fails, the constraints are infeasible and the random variables retain
their previous values. In the following example, For the first randomization call there
is a solution. When the constraints are changed, the randomization failed. Simulation
results show that after randomization failed, random variables hold their previous
values.
EXAMPLE:
programSimple_pro_14;
classSimple;
randintegerVar;
http://testbench.in/CR_06_RANDOMIZATION_METHODS.html[9/26/2012 2:10:48 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
integerMIN=20;
constraintc {Var <100;Var >MIN;}
endclass
Simple
obj;
initial
begin
obj =new();
if(obj.randomize())
else
$display("Randomization failed: Var = %0d ",obj.Var);
obj.MIN=200;
$display(" MIN is changed to fail the constraint");
if(obj.randomize())
else
$display(" Randomization failed : Var = %0d",obj.Var);
end
endprogram
RESULTS:
#Randomization sucsessfull : Var = 87
#MIN is changed to fail the constraint.
#Randomization failed : Var = 87
Pre_randomize And Post_randomize
Every class contains pre_randomize() and post_randomize() methods, which are
automatically called by randomize() before and after computing new random values.
When randomize() is called,it first invokes the pre_randomize() then randomize()
finally if the randomization is sucesusful only post_randomize is invoked.
These methods can be used as hooks for the user to perform operations such as
setting initial values and performing functions after assigning random variables.
EXAMPLE:
programpre_post_15;
classsimple;
functionvoidpre_randomize;
$display(" PRE_RANDOMIZATION ");
endfunction
functionvoidpost_randomize;
$display(" POST_RANDOMIZATION ");
endfunction
endclass
simple obj =new();
initial
endprogram
RESULTS:
#PRE_RANDOMIZATION
#POST_RANDOMIZATION
Overriding of pre_randomize and post_randomize functions is allowed by child class. If
parent class functions are not called when overriding pre_randomize() and
post_randomize functions, parent class function definations will be omitted.
EXAMPLE:
classBase;
$display(" BASE PRE_RANDOMIZATION ");
endfunction
$display(" BASE POST_RANDOMIZATION ");
endfunction
endclass
classExtend_1 extendsBase;
$display(" EXTEND_1 PRE_RANDOMIZATION ");
endfunction
$display(" EXTEND_1 POST_RANDOMIZATION ");
endfunction
endclass
classExtend_2 extendsBase;
super.pre_randomize();
$display(" EXTEND_2 PRE_RANDOMIZATION ");
endfunction
super.post_randomize();
$display(" EXTEND_2 POST_RANDOMIZATION ");
endfunction
endclass
programpre_post_16;
Base B =new();
Extend_1 E1=new();
Extend_2 E2=new();
initial
begin
void'(B.randomize());
void'(E1.randomize());
void'(E2.randomize());
end
endprogram
In the extended class EXTEND_1, when overiding the builtin functions, parent class
functions are not called. In the extended class EXTEND_2, super.methods are called
which invokes the parent class methods also.
RESULTS:
#BASE PRE_RANDOMIZATION
#BASE POST_RANDOMIZATION
#EXTEND_1 PRE_RANDOMIZATION
#EXTEND_1 POST_RANDOMIZATION
#EXTEND_2 PRE_RANDOMIZATION
#EXTEND_2 POST_RANDOMIZATION
The pre_randomize() and post_randomize() methods are not virtual. However,
because they are automatically called by the randomize() method, which is virtual,
they appear to behave as virtual methods. This example demonstrates that these
functions are not virtual but simulation results show that, it executed extended class
definition functions. Extended class object is created and assigned to base class
object. Calls to pre_randomize and post_randomize calls in object B ,executed the
extended class definitions.
EXAMPLE:
classBase;
endfunction
virtualfunctionvoidpost_randomize;
endfunction
endclass
classExtend extendsBase;
$display(" EXTEND PRE_RANDOMIZATION ");
endfunction
$display(" EXTEND POST_RANDOMIZATION ");
endfunction
endclass
programpre_post_17;
Base B ;
Extend E =new();
initial
begin
B =E ;
void'(E.randomize());
end
endprogram
RESULTS:
There should be compilation error.
In the above example compilation error is due to the declaration of post_randmoize()
function as virtual. By removing the virtual keyword for the post_randomize()
function, calling the randomize() function by parent and child class, both will execute
functions of child class only. Which is a virtual function behaviour.
EXAMPLE:
classBase;
endfunction
endfunction
endclass
$display(" EXTEND PRE_RANDOMIZATION ");
endfunction
$display(" EXTEND POST_RANDOMIZATION ");
endfunction
endclass
programpre_post_17;
Base B ;
Extend E =new();
initial
begin
B =E ;
end
endprogram
RESULTS:
#EXTEND
#EXTEND
#EXTEND
#EXTEND
PRE_RANDOMIZATION
POST_RANDOMIZATION
PRE_RANDOMIZATION
POST_RANDOMIZATION
If the class is a derived class and no user-defined implementation of pre_randomize()

and post_randomize() exists, then pre_randomize() and post_randomize() will
automatically invoke super.pre_randomize() and super.post_randomize() respectively.
EXAMPLE:
classBase;
endfunction
endfunction
endclass
endclass
programpre_post_19;
Extend E =new();
initial
endprogram
RESULTS:
EXAMPLE:
classBase;
$display(" BASE PRE_RANDOMIZATION \n");
endfunction
$display(" BASE POST_RANDOMIZATION \n");
endfunction
endclass
super.pre_randomize();
$display(" EXTENDED PRE_RANDOMIZATION \n");
endfunction
$display(" EXTENDED POST_RANDOMIZATION \n");
endfunction
endclass
programpre_post;
Base B;
Extend E =new();
initial
begin
B =E;
if(B.randomize())
$display(" randomization done \n");
end
endprogram
RESULTS:
BASE PRE_RANDOMIZATION
EXTENDED PRE_RANDOMIZATION
EXTENDED POST_RANDOMIZATION
randomization done
Results show that, if extended class is having new definition, explicitly super.pre_ or
post_ has to be called.
super.pre_randomize() is called in extended class, but super.post_randomize() is not
called in above example. See thedifference in results.
If a class A instance is in Class B,To randomize class A by calling the randomize
function of class B,Class A instance has to be declared as rand variable.
EXAMPLE:
classA;
randintegerVar;
endclass
classB;
randA obj_1 =new();
A obj_2 =new();
endclass
programa_b_20;
B obj=new();
initial
begin
obj.obj_1.Var =1;
obj.obj_2.Var =1;
repeat(10)
begin
$display(" Var1 = %d ,Var2 = %d ",obj.obj_1.Var,obj.obj_2.Var );
end
end
endprogram
RESULTS:
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
#Var1
=
=
=
=
=
=
=
=
=
=
733126180 ,Var2 = 1
-119008195 ,Var2 = 1
342785185 ,Var2 = 1
679818185 ,Var2 = 1
-717162992 ,Var2 = 1
664520634 ,Var2 = 1
-1944980214 ,Var2 = 1
-1350759145 ,Var2 = 1
-1374963034 ,Var2 = 1
-462078992 ,Var2 = 1
Look at the results. Variable of obj_2 is not randomized. Only variable of obj_1 which
is declared as rand is ranomized.
Upon calling the randomize method of B object which contains rand A object, First B
prerandomize is called, then A prerandomize method is called, then B is randomized,
if a solution was found, new values are assigned to the random A objects.If solution
was found, for each random object that is a class instance it's post_randomize method
is called. That means if randomization is successful next B postrandomize, next A
postrandomize functions are called. Upon calling B randomize function this is
sequence it follow.
B-Prerandomize --> A-prerandomize --> A.randomize --> B-postrandomize --> Apostrandomize
EXAMPLE:
classA;
randintegerVar;
$display(" A PRE_RANDOMIZATION ");

endfunction
$display(" A POST_RANDOMIZATION ");
endfunction
endclass
classB;
randA obj_a;
functionnew();
obj_a =new();
endfunction
$display(" B PRE_RANDOMIZATION ");
endfunction
$display(" B POST_RANDOMIZATION ");
endfunction
endclass
programpre_post_21;
B obj_b =new();
initial
void'(obj_b.randomize());
endprogram
RESULTS:
#B PRE_RANDOMIZATION
#A PRE_RANDOMIZATION
#B POST_RANDOMIZATION
#A POST_RANDOMIZATION
If randomization failed for obj_a, then post_randomize of obj_a and post_randomize

of obj_b won't be called, and randomization will fail for obj_b also.
EXAMPLE:
classA;
randbit[2:0]Var;
constraintrandge_c {Var >2;Var <2;}
$display(" A PRE_RANDOMIZATION ");
endfunction
$display(" A POST_RANDOMIZATION ");
endfunction
endclass
classB;
randA obj_a;
$display(" B PRE_RANDOMIZATION ");
endfunction
$display(" B POST_RANDOMIZATION ");
endfunction
functionnew();
obj_a =new();
endfunction
endclass
programpre_post_22;
B obj_b =new();
initial
void'(obj_b.randomize());
endprogram
RESULTS:
#B PRE_RANDOMIZATION
#A PRE_RANDOMIZATION
Disabling Random Variable
The random nature of variables declared as rand or randc can be turned on or off
dynamically. To change the status of variable which is declared as rand or randc to
state variable, built in rand_mode() method is used. State variables are not
randomized by randomize() mehod. By default all rand and randc variables are active.
When called as a task, the arguments to the rand_mode method determines the
operation to be performed. If the arguments is 0, then all the variables declared as
rand and randc will become non random i.e all random variables treated as state
variables. IF argument is 1, then all variables declares as rand and randc will be
randomized.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
programrand_mo_p_23;
rand_mo obj =new();
initial
begin
$display(" Var1 : %d Var2 : %d
obj.rand_mode(0); //
obj.rand_mode(1);//
variables.
end
endprogram
RESULTS:
",obj.Var1,obj.Var2);
Var1 and Var2 will be treated as State variables.
// Var1 and Var2 will be treated as random
#Var1 : 733126180 Var2 :-119008195

#Var1 : 733126180 Var2 :-119008195
#Var1 : 342785185 Var2 : 679818185
If arguments are Variable name, then only that variable will be non random.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
$display(" Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
obj.Var1.rand_mode(0);// Var1 will become State variable
obj.Var2.rand_mode(0);//Var2 will also become State variable
obj.Var1.rand_mode(1); // // Var1 will become random variable
end
endprogram
RESULTS:
#Var1 : 733126180 Var2 :-119008195
#Var1 : 733126180 Var2 : 342785185
#Var1 : 733126180 Var2 : 342785185

#Var1 : 679818185 Var2 : 342785185
When rand_mode method is called as function, it returns the active status of the
specified random variable.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
obj.Var1.rand_mode(0);
if(obj.Var1.rand_mode())
$display(" Var1 is random");
else
$display(" Var1 is nonrandom");
end
endprogram
RESULTS:
#Var1
#Var1
#Var1
#Var1
: 733126180 Var2 :-119008195

: 733126180 Var2 : 342785185
is nonrandom
: 733126180 Var2 : 679818185
If you are changing the status of a variable, which is not existing it is compilation
error.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
end
endprogram
A compiler error shall be issued if the specified variable does not exist within the
class hierarchy or eventhough it exists but not declared as rand or randc. The
following example illustrates the second case.
EXAMPLE:
classrand_mo;
randintegerVar1;
integerVar2;
endclass
rand_mo obj =new();
initial
begin
end
endprogram
In the above example, Var2 is state variable. If the random variable is an object
handle, only the mode of the object is changed, not the mode of random variables
within that object.
EXAMPLE:
classrand_var;
randintegerVar2;
endclass
classrand_mo;
randintegerVar1;
randrand_var rv;
functionnew();
rv =new();
endfunction
endclass
rand_mo obj =new();
initial
begin
$display(" Var1 : %d Var2 : %d ",obj.Var1,obj.rv.Var2);
obj.rand_mode(0);
void'(obj.rv.randomize());
end
endprogram
RESULTS:
Var1 : 345345423 Var2 : 234563556
Var1 : 345345423 Var2 : 234563556
Var1 : 345345423 Var2 : -2456456
Random Static Variable
Randomization does not depend on life time of variable. Even if a variable is
static,randomization is specfic to object.So rand_mode() on static variable,only
switches off the randomization on the variable of that object.This is true for dist and
randc.
In the following example, Var1 is static and Var2 is automatic.Var1 and Var2 in obj_2
are made nonrandom using rand_mode(0).Var1 and Var2 in obj_1 are getting
randomized.The only difference between Var1 and Var2 is that new random value for
Var1 is appreas on both objects.
EXAMPLE:
classA;
randstaticintegerVar1;
randintegerVar2;
endclass
programA_p_27;
A obj_1 =new;
A obj_2 =new;
initial
begin
obj_2.Var1.rand_mode(0);
obj_2.Var2.rand_mode(0);
repeat(2)
begin
void'(obj_1.randomize());
$display("obj_1.Var1 : %d ,obj_1.Var2 : %d : obj_2.Var1 : %d ,obj_2.Var2 : %d
:",obj_1.Var1,obj_1.Var2,obj_2.Var1,obj_2.Var2);
end
end
endprogram
RESULTS:
obj_1.Var1 : 934734534,obj_1.Var2 : 234232342: obj_2.Var1 : 934734534 ,obj_2.Var2
:0:
obj_1.Var1 : 908123314,obj_1.Var2 : 121891223: obj_2.Var1 : 908123314 ,obj_2.Var2
:0:
Random variables declared as static are shared by all instances of the class in which
they are declared. Each time the randomize() method is called, the variable is
changed in every class instance.
Randomizing Nonrand Varible
All the variables(randc, rand and nonrandom variables) randomization nature can be
changed dynamically. Using rand_mode() rand and randc varibles changes its nature.
The random nature of variables which are not declared as rand or randc can also be
randomized dynamically. When the randomize method is called with no arguments, it
randomizes the variables which are declared as rand or randc,so that all of the
constraints are satisfied. When randomize is called with arguments, those arguments
designate the complete set of random variables within that object, all other variables
in the object are considered state variables.
EXAMPLE:
classCA;
randbytex,y;
bytev,w;
constraintc1 {x <v &&y >w ;}
endclass
programCA_p_28;
CAa =new;
initial
begin
a.x =10;a.y =10;a.v =10;a.w =10;
$display(" x : %3d y : %3d : v : %3d : w : %3d ",a.x,a.y,a.v,a.w);
void'(a.randomize());// random variables: x, y state variables: v, w
void'(a.randomize(x));// random variables: x state variables: y, v, w
void'(a.randomize(v,w));// random variables: v, w state variables: x, y
void'(a.randomize(w,x));// random variables: w, x state variables: y, v
end
endprogram
RESULTS:
#x :10 y :10 : v :10 : w :10
#x : -71 y :96 : v :10 : w :10
#x : -37 y :96 : v :10 : w :10

#x : -37 y :96 : v : -22 : w :80
#x : -90 y :96 : v : -22 : w : -41
In above example x and y are rand variables, v and w are state variables. When
a.randomize() is called, all rand varibles are randomized and state variables are hold
the same value. When a.randomize(w) is called, only w is considered as rand variable
and all others as state varibles. Here w is in constraint block so it has to satisfy the
constraints. v,y and x also are state variables now, they also need to satisfy the
constraint else it fails.
Replacing the class variables, with its hierarchical result also should result same.
EXAMPLE:
programCA_p_29;
CAa =new;
initial
begin
a.x =10;a.y =10;a.v =10;a.w =10;
void'(a.randomize());// random variables: x, y state variables: v, w
void'(a.randomize(a.x ));// random variables: x state variables: y, v, w
void'(a.randomize(a.v,a.w ));// random variables: v, w state variables: x, y
void'(a.randomize(a.w,a.x ));// random variables: w, x state variables: y, v
end
endprogram
RESULTS:
#x
#x
#x
#x
#x
:10 y :10 : v :10 : w :10

: -71 y :96 : v :10 : w :10
: -37 y :96 : v :10 : w :10
: -37 y :96 : v : -22 : w :80
: -90 y :96 : v : -22 : w : -41
If you are not interested to satisfy the constraints in constraint block, instead of
switching off the constraint block, just randomize the variables using scope
randomize() function. Scope randomize provide the ability to randomize class
variables also along with non class variables.
EXAMPLE:
programCA_p_30;
integerx,y,v,w;
initial
begin
x =10;y =10;v =10;w =10;
$display(" x : %3d y : %3d : v : %3d : w : %3d ",x,y,v,w);
randomize(x );// random variables: x state variables: y, v, w
randomize(v,w );// random variables: v, w state variables: x, y
randomize(w,x );// random variables: w, x state variables: y, v
end
endprogram
RESULTS:
#x
#x
#x
#x
:10 y :10 : v :10 : w :10

: -826701341 y :10 : v :10 : w :10
: -826701341 y :10 : v : 541037099 : w : -457978538
: 978699393 y :10 : v : 541037099 : w : -683182079
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TUTORIALS
CHECKER
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Built-in method randomize() not only used for randomization, it can be used as
checker. When randomize() method is called by passing null, randomize() method
behaves as checker instead of random generator. It evaluates all the constraints and
returns the status. This is true for both scope randomization function and class
randomization function. When a randomize() method is called, first RNG assigns
values to random varibles and then solver checks the constraints. When
randomize(null) is called, it wont call the RNG to assign values to random variables, it
just solves constraints.
EXAMPLE:
classEth_rx;
randintegerPkt_len;
randintegerVar;
constraintvar_c {Var <1518;Var >64;}
endclass
Easy Labs : SV
programEth_25;
Eth_rx rx =new();
initial
Easy Labs : OVM
begin
Easy Labs : VMM
rx.Pkt_len =32;
rx.Var =871;
AVM Switch TB
if(rx.randomize(null))
VMM Ethernet sample $display(" VALID PKT IS RECIVED ");
else
$display(" INVALID PKT IS RECIVED ");
end
Verilog
endprogram
Verification
Easy Labs : UVM
Verilog Switch TB
Basic Constructs
RESULTS:
#VALID PKT IS RECIVED
OpenVera
Constructs
Constraints can be written without having random varibles in expressions. If there is

any constraint on state variables and they are dynamically changed, and if you want
to make sure that these dynamic changes should satisfy the constraint, use randomize
RVM Switch TB
check to make sure that relation is satisfied.
RVM Ethernet sample In the following example, MIN and MAX are dynamically controllable state variables.
Constraint checker_c fails when MIn = 50 and MAX = 10.
Switch TB
Specman E
Interview Questions
EXAMPLE:
classBase;
randintegerVar;
integerMIN,MAX;
constraintrandge_r {Var <MAX;Var >MIN;}
constraintchecker_c{MIN<MAX;}// This checks that these dynamic variables are
valid
taskset(integerMIN,integerMAX);
this.MIN=MIN;
this.MAX=MAX;
$display(" SET : MIN = %0d , MAX = %0d ",MIN,MAX);
endtask
http://testbench.in/CR_07_CHECKER.html[9/26/2012 2:10:57 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
endclass
programinhe_26;
Base obj;
initial
begin
obj =new();
obj.set(0,100);
if(obj.randomize())
else
obj.set(50,10);
if(obj.randomize())
else
end
endprogram
RESULTS:
#SET : MIN = 0 , MAX = 100
#SET : MIN = 50 , MAX = 10
Var
Var
Var
Var
Var
=
=
=
=
=
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11
8
36
64
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TUTORIALS
CONSTRAINT BLOCK
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Constraint block contains declarative statements which restrict the range of variable
or defines the relation between variables. Constraint programming is a powerful
method that lets users build generic, resuble objects that can be extended or more
constrained later. constraint solver can only support 2 stete values. If a 4 state
variable is used, solver treates them as 2 state variable.. Constraint solver fails only if
there is no solution which satisfies all the constraints. Constraint block can also have
nonrandom variables, but at least one random variable is needed for randomization.
Constraints are tied to objects. This allows inheritance, hierarchical constraints,
controlling the constraints of specific object.
Inheritance
One of the main advantage of class randomization is Inheritance. Constraints in
derived class with the same name in base class overrides the base class constraints
just like task and functions.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
EXAMPLE:
classBase;
randintegerVar;
endclass
VMM Ethernet sample classExtended extendsBase;
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
constraintrange {Var <100;Var >50;}// Overrighting the Base class constraints.

endclass
programinhe_31;
Extended obj;
initial
begin
obj =new();
if(obj.randomize())
else
end
endprogram
RESULTS:
Var
Var
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
=
=
91
93
77
68
67
52
71
98
69
Adding new constraints in the derived class, can change the solution space. Solver has
to solve both constraints defined in base class and derived class. In the example given
http://testbench.in/CR_08_CONSTRAINT_BLOCK.html[9/26/2012 2:11:07 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
below, Constraint range_1 defines the range that Var is between 0 to 100.Constraint
range_2 limits the Var to be greater than 50 and solver has to solve both the
constraints and the solution space is between 50 to 100.
EXAMPLE:
classBase;
randintegerVar;
constraintrange_1 {Var <100;Var >0;}
endclass
constraintrange_2 {Var >50;}// Adding new constraints in the Extended class
endclass
programinhe_32;
Extended obj;
initial
begin
obj =new();
if(obj.randomize())
$write(": Var = %0d :",obj.Var);
else
end
endprogram
RESULTS:
Var = 91 :: Var = 93 :: Var = 77 :: Var = 68 :: Var = 67 :: Var = 52 :: Var = 71 :: Var =
98 :: Var = 69 :: Var = 70 :: Var = 96 :: Var = 88 :: Var = 84 :: Var = 99 :: Var = 68 ::
Var = 83 :: Var = 52 :: Var = 72 :: Var = 93 :: Var = 80 :
Overrighting Constraints
The randomize() task is virtual. Accordingly it treats the class constraints in a virtual
manner. When a named constraint is redefined in an extended class, the previous
definition is overridden and when casting extended class to base class does not change
the constraint set.
EXAMPLE:
classBase;
randintegerVar;
endclass
constraintrange {Var ==100;}// Overrighting the Base class constraints.
endclass
programinhe_33;
Extended obj_e;
Base
obj_b;
initial
begin
obj_e =new();
obj_b =obj_e;
if(obj_b.randomize())
$display(" Randomization sucsessfull : Var = %0d ",obj_b.Var);
else
end
endprogram
RESULTS:
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
100
100
100
100
100
100
100
When an extended object is casted to base object, all the constraints in extended
object are solved along with the constraints in base object.
EXAMPLE:
classBase;
randintegerVar;
constraintrange_1 {Var <100;Var >0;}
endclass
constraintrange_2 {Var >50;}
endclass
programinhe_34;
Extended obj_e;
Base
obj_b;
initial
begin
obj_e =new();
obj_b =obj_e;
if(obj_b.randomize())
$display(" Randomization sucsessfull : Var = %0d ",obj_b.Var);
else
end
endprogram
RESULTS:
Var
Var
Var
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
=
=
=
91
93
77
68
67
52
71
98
69
70
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SystemVerilog
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Constructs
Interface
OOPS
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DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Constrained Random
Verification
Inline constraints allows to add extra constraints to already existing constraints which Verilog Crv
are declared inside class. If you have constraints already defined for variavle var, Systemverilog Crv
Randomizing Objects
solver solves those constraints along with the in-line constraints.
Random Variables
Checker
EXAMPLE:
Constraint Block
classinline;
Inline Constraint
randintegerVar;
Global Constraint
constraintdefault_c {Var >0;Var <100;}
Constraint Mode
endclass
Randomization
programinline_p_35;
Controlability
inline obj;
Static Constraint
initial
begin
Variable Ordering
obj =new();
repeat(5)
Randcase
if(obj.randomize()with{Var ==50;})
Randsequence
$display(" Randodmize sucessful Var %d ",obj.Var);
Random Stability
else
Array Randomization
$display(" Randomization failes");
Constraint Guards
end
Titbits
endprogram
INLINE CONSTRAINT
VMM Ethernet sample RESULTS:
Verilog
Verification
Verilog Switch TB
#Randodmize
#Randodmize
#Randodmize
#Randodmize
#Randodmize
sucessful
sucessful
sucessful
sucessful
sucessful
Var50
Var50
Var50
Var50
Var50
Basic Constructs
OpenVera
Constructs
In the above example, by default only default_c constraints are considered. Using
inline constraint Var == 50 resulted value on variable Var based on both the default_c
and inline constraints.
Switch TB
The scope for variable names in a constraint block, from inner to outer, is
randomize()...with object class, automatic and local variables, task and function
RVM Ethernet sample arguments, class variables, and variables in the enclosing scope. The
randomize()...with class is brought into scope at the innermost nesting level. In the
f.randomize() with constraint block, x is a member of class Foo and hides the x in
program Bar. It also hides the x argument in the doit() task. y is a member of Bar. z is
Specman E
a local argument.
RVM Switch TB
Interview Questions
In the example below, the randomize()...with class is Foo.

EXAMPLE:
classFoo;
randintegerx;
endclass
programBar_36;
Foo obj =new();
http://testbench.in/CR_09_INLINE_CONSTRAINT.html[9/26/2012 2:11:17 PM]

input is what keeps
with time!
integerx;
integery;
taskdoit(Foo f,integerx,integerz);
intresult;
result =f.randomize()with{x <y +z;};
$display(":: obj.x : %d :: x : %d :: y : %d :: z : %d ::",obj.x,x,y,z);
endtask
initial
begin
x ='d10;
repeat(5)
begin
y =$urandom%10;
doit(obj,x ,'d12);
end
end
endprogram
RESULTS:
::
::
::
::
::
obj.x
obj.x
obj.x
obj.x
obj.x
: -1538701546 :: x :10 :: y : 5 :: z :12 ::

: -1048494686 :: x :10 :: y : 9 :: z :12 ::
: -1122673684 :: x :10 :: y : 8 :: z :12 ::
: -2050360121 :: x :10 :: y : 7 :: z :12 ::
:-886228933 :: x :10 :: y : 3 :: z :12 ::
By seeing this output we can tell the variable which used in inline constraint is class
member x.
constraint { x < y + z } means { obj.x < Bar_36.y + do_it.z }
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Index
Constrained Random
Verification
SystemVerilog
SystemVerilog allows to have constraints between variables of different objects. Verilog Crv
Verification
These are called global constraints. Using the hierarchy notation, constraints can be Systemverilog Crv
Constructs
applied on variables of different objects. When object is randomized, so are the Randomizing Objects
Random Variables
contained objects and all other constraints are considered simultaneously.
Interface
OOPS
Checker
Constraint Block
EXAMPLE:
Randomization
Inline Constraint
classchild;
Functional Coverage
Global Constraint
randintVar1;
Constraint Mode
Assertion
endclass
DPI
Randomization
classparent;
Controlability
UVM Tutorial
rand child child_obj;
Static Constraint
rand intVar2;
VMM Tutorial
constraintglobal_c {Var2 <child_obj.Var1 ;}
Variable Ordering
OVM Tutorial
functionnew();
child_obj
=new();
Easy Labs : SV
Randcase
endfunction
Randsequence
Easy Labs : UVM
endclass
Random Stability
Easy Labs : OVM

Array Randomization
programrandom_37;
Easy Labs : VMM
Constraint Guards
initial
Titbits
for(inti=0;i<5;i++)
AVM Switch TB
begin
VMM Ethernet sample parent parent_obj;
parent_obj =new();
input is what keeps
void'(parent_obj.randomize ());
$display(" Var1 = %0d ,Var2 = %0d ",parent_obj.child_obj.Var1,parent_obj.Var2 ); Testbench.in improving
Verilog
with time!
end
Verification
endprogram
TUTORIALS
GLOBAL CONSTRAINT
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RESULTS:
#Var1
#Var1
#Var1
#Var1
#Var1
=
=
=
=
=
903271284 ,Var2 = -1102515531

2112727279 ,Var2 = -838916208
1614679637 ,Var2 = 1572451945
1284140376 ,Var2 = -373511538
463675676 ,Var2 = -516850003
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CR_10_GLOBAL_CONSTRAINT.html[9/26/2012 2:11:24 PM]
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TUTORIALS
CONSTRAINT MODE
SystemVerilog
Disabling Constraint Block
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
SystemVerilog supports to change the status of constraint block dynamically. To

change the status of a Constraint block, built in constraint_mode() method is used. By
default all the constraint blocks are active. When it is called as task, the arguments
to the task determines the operation to be performed. If the arguments are 0 or 1,
then all the constraints blocks are effected.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
constraintVar_1 {Var1 ==20;}
endclass
rand_mo obj =new();
Easy Labs : UVM
initial
begin
Easy Labs : OVM
void'(obj.randomize());//By default all constraints are active.
Easy Labs : VMM
obj.constraint_mode(0);//Both constraints Var_1 and Var_2 are turned off.
AVM Switch TB
VMM Ethernet sample $display(" Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
obj.constraint_mode(1);//Both constraints Var_1 and Var_2 are turned on.
Verilog
end
Verification
endprogram
Easy Labs : SV
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
RESULTS:
#Var1 :20 Var2 :10
#Var1 : 733126180 Var2 :-119008195
#Var1 :20 Var2 :10
Switch TB
RVM Switch TB
If the arguments are Variable name, then only the status of that constraint block is
RVM Ethernet sample changed.
Specman E
Interview Questions
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
http://testbench.in/CR_11_CONSTRAINT_MODE.html[9/26/2012 2:11:32 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!

obj.Var_1.constraint_mode(0);
end
endprogram
RESULTS:
Var1 : 20 Var2 : 10
Var1 : 3w456456 Var2 : 10
Var1 : 20 Var2 : 10
When it is called as function, it returns the active status of the specified constraint
block.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
void'(obj.randomize());//By default all constraints are active.
obj.Var_1.constraint_mode(0);//Both constraint Var_1 is are turned
off.
if(obj.Var_1.constraint_mode())
$display("Var_1 constraint si active");
else
$display("Var_1 constraint si inactive");
$display("Var_2 constraint si active");
else
$display("Var_2 constraint si inactive");
end
endprogram
RESULTS:
Var1 :20 Var2 :10
Var1 : -2048772810 Var2 :10
Var_1 constraint si inactive
Var_2 constraint si active
Var1 :-673275588 Var2 :10
If you are changing the status of a constraint block, which is not existing, then there
should be a compilation error else contact your Application engineer to file the bug.
EXAMPLE:
classrand_mo;
randintegerVar1;
randintegerVar2;
endclass
rand_mo obj =new();
initial
begin
$display(" Vat_1 constraint block is off");
end
endprogram
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Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Index
Constrained Random
Verification
Constraint blocks can be defined externally in the same file or other files. Defining the Verilog Crv
Systemverilog Crv
constraints in external file, gives some what aspect oriented style of programming.
For example, test_1 requires Var between 0 to 100 and tets_2 requires Var between Randomizing Objects
Random Variables
50 to 100.Declare the constraint block as empty and define them in other files.
Checker
Constraint Block
EXAMPLE:
Inline Constraint
classBase;
Global Constraint
randintegerVar;
Constraint Mode
constraintrange;
endclass
Randomization
Controlability
programinhe_39;
Static Constraint
Base obj;
initial
Variable Ordering
begin
obj =new();
Randcase
Randsequence
if(obj.randomize())
Random Stability
Array Randomization
else
Constraint Guards
Titbits
end
endprogram
EXTERNAL CONSTRAINTS
In test_1 file,include
constraintBase::range {Var <100;Var >0;}
In test_2 file,include
constraintBase::range {Var <100;Var >50;}
Very popular verilog style of including testcases is by using ìnclude which can also be
used hear.
Write the constraints in a file and include it.
//
EXAMPLE:
Constructs
classBase;
randintegerVar;
Switch TB
ìnclude"constraint.sv"
RVM Switch TB
endclass
RVM Ethernet sample
programinhe_40;
Base obj;
initial
Specman E
begin
obj =new();
Interview Questions
if(obj.randomize())
else
end
endprogram
OpenVera
http://testbench.in/CR_12_EXTERNAL_CONSTRAINTS.html[9/26/2012 2:11:39 PM]

input is what keeps
with time!
Constraint Hiding
In SV Std 1800-2005 LRM , its not mentioned any where that constraints can be
declared as local or protected. If they support to declare constraints as local, it would
be helpful not to switchoff the constraint block accedentally is it is not supposed to
be done. The constraint BNF explicitly excludes the local and protected modifiers.
The main reason for their exclusion is because constraints behave like virtual methods
that are called by the built-in randomize method. If a constraint were declared
local/protected it would still be visible to randomize and participate in the constraint
equations. The only limitation would be to call the constraint_mode on
local/protected constraints from certain methods, and this does not seem very useful
and probably create more confusion with regards to overridden methods.
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TUTORIALS
RANDOMIZATION CONTROLABILITY
SystemVerilog
Controlability
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Additional to the controllability feauters supported by SystemVerilog, following are

more points with which controlabiity can be achieved.
In the following example, MACROS MIN_D and MAX_D are defined. Set the MIN and MAX
values in the pre_randomize as shown. As MIN_D and MAX_D are macros, they can be
assigned from command line. Biggest disadvantage for the method shown below is
dynamic controllability.
Assertion
EXAMPLE:
`defineMAX_D100
UVM Tutorial
`defineMIN_D50
classBase;
VMM Tutorial
randintegerVar;
OVM Tutorial
integerMIN,MAX;
constraintrandge {Var <MAX;Var >MIN;}
Easy Labs : SV
functionvoidpre_randomize ();
Easy Labs : UVM
this.MIN=`MIN_D;
this.MAX=`MAX_D;
Easy Labs : OVM
$display(" PRE_RANDOMIZE : MIN = %0d , MAX = %0d ",MIN,MAX);
Easy Labs : VMM
endfunction
endclass
AVM Switch TB
VMM Ethernet sample programinhe_42;

Base obj;
initial
begin
Verilog
obj =new();
Verification
Verilog Switch TB
if(obj.randomize())
Basic Constructs
else
end
OpenVera
endprogram
Constructs
DPI
Switch TB
RVM Switch TB
RESULTS:
RVM Ethernet sample #PRE_RANDOMIZE : MIN = 50 , MAX = 100
Specman E
Interview Questions

#PRE_RANDOMIZE : MIN = 50 , MAX = 100
http://testbench.in/CR_13_RANDOMIZATION_CONTROLABILITY.html[9/26/2012 2:11:48 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
...etc.
As in this example,a single object is created and randomized 100 times. Due to
this,pre_reandomize is called 100 times, which may not be preferred.
By assigning the values while declaration itself this can be avoided. Simpler way to
achieve the above logic.
EXAMPLE:
`defineMAX_D100
`defineMIN_D50
classBase;
randintegerVar;
integerMIN=`MIN_D;
integerMAX=`MAX_D;
constraintrange {Var <MAX;Var >MIN;}
endclass
programinhe_43;
Base obj;
initial
begin
obj =new();
if(obj.randomize())
else
end
endprogram
RESULTS:
...etc.
Var
Var
Var
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
=
=
=
91
93
77
68
67
52
71
98
69
70
With the above approach also, dynamic controlability is lost. For dynamic
controllability, define a task, pass this values as arguments when ever the changed is
needed.
EXAMPLE:
classBase;
randintegerVar;
integerMIN=10,MAX=20;// Define default values,If
called,with this it will work
taskset(integerMIN,integerMAX);
this.MIN=MIN;
this.MAX=MAX;
$display(" SET : MIN = %0d , MAX = %0d ",MIN,MAX);
endtask
endclass
function
set
is not
programinhe_44;
Base obj;
initial
begin
obj =new();
obj.set(0,100);
if(obj.randomize())
else
obj.set(50,100);
if(obj.randomize())
else
end
endprogram
RESULTS:
#SET : MIN = 0 , MAX = 100
#SET : MIN = 50 , MAX = 100
Var
Var
Var
Var
Var
=
=
=
=
=
24
68
43
11
4
Var
Var
Var
Var
Var
=
=
=
=
=
52
71
98
69
70
More simpler way to dynamically modifying the constraints is by modifying the data
members of class via object reference.
EXAMPLE:
classBase;
randintegerVar;
integerMIN=20,MAX=30;
endclass
programinhe_45;
Base obj;
initial
begin
obj =new();
obj.MIN=0;
obj.MAX=100;
if(obj.randomize())

else
$display("MIN and MAX changed");
obj.MIN=50;
obj.MAX=100;
if(obj.randomize())
else
end
endprogram
RESULTS:
# MIN and MAX changed
Var
Var
Var
Var
Var
=
=
=
=
=
24
68
43
11
4
Var
Var
Var
Var
Var
=
=
=
=
=
52
71
98
69
70
<< PREVIOUS PAGE
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TUTORIALS
STATIC CONSTRAINT
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
If a constraint block is declared as static, then constraint mode on that block will
effect on all the instancess of that class. In the following example, two objects obj_1
and obj_2 are declared. Constraints Var1_c is static and Var2_c is not static. When
constraint_mode is used to switch off the constraints in in obj_2, constraint var1_c in
obj_1 is also switched off.
EXAMPLE:
classA;
randintegerVar1,Var2;
staticconstraintVar1_c {Var1 ==10;}
constraintVar2_c {Var2 ==10;}
endclass
VMM Tutorial
programA_p_46;
A obj_1 =new;
A obj_2 =new;
Easy Labs : SV
initial
Easy Labs : UVM
begin
obj_2.Var1_c.constraint_mode(0);
Easy Labs : OVM
obj_2.Var2_c.constraint_mode(0);
Easy Labs : VMM
repeat(10)
begin
AVM Switch TB
VMM Ethernet sample $display("obj_1.Var1 : %d ,obj_1.Var2 : %d ",obj_1.Var1,obj_1.Var2);
end
end
endprogram
Verilog
OVM Tutorial
Verification
Verilog Switch TB
RESULTS:
#
#
#
#
OpenVera
#
Constructs
#
#
Switch TB
#
RVM Switch TB
#
RVM Ethernet sample #
Basic Constructs
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
obj_1.Var1
: 733126180 ,obj_1.Var2 :10

:-119008195 ,obj_1.Var2 :10
: 342785185 ,obj_1.Var2 :10
: 679818185 ,obj_1.Var2 :10
:-717162992 ,obj_1.Var2 :10
: 664520634 ,obj_1.Var2 :10
: -1944980214 ,obj_1.Var2 :10
: -1350759145 ,obj_1.Var2 :10
: -1374963034 ,obj_1.Var2 :10
:-462078992 ,obj_1.Var2 :10
Specman E
Interview Questions
http://testbench.in/CR_14_STATIC_CONSTRAINT.html[9/26/2012 2:11:56 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
<< PREVIOUS PAGE
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http://testbench.in/CR_14_STATIC_CONSTRAINT.html[9/26/2012 2:11:56 PM]
Search
TUTORIALS
CONSTRAINT EXPRESSION
SystemVerilog
Verification
Constructs
Interface
A constraint_expression is any SystemVerilog expression or one of the constraint

specific operators( -> (Implication) and dist). Functions are allowed to certain
limitation. Operators which has side effects are not allowed like ++,--.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Set Membership
A set membership is a list of expressions or a range. This operator searches for the
existences of the value in the specified expression or range and returns 1 if it is
existing.
EXAMPLE:
classset_mem;
randintegerVar;
constraintrange {Var inside{0,1,[50:60],[90:100]};}
functionvoidpost_randomize();
$write("%0d__",Var);
endfunction
endclass
programset_mem_p_47;
set_mem obj=new();
VMM Ethernet sample initial
repeat(10)
endprogram
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
RESULTS:
50__57__60__93__100__94__90__1__54__100__
If you want to define a range which is outside the set, use negation.
Constructs
EXAMPLE:
classset_mem;
RVM Switch TB
randbit[0:2]Var;
RVM Ethernet sample constraintrange {!(Var inside{0,1,5,6});}
$write("%0d__",Var);
endfunction
Specman E
endclass
Interview Questions
set_mem obj=new();
initial
repeat(10)
endprogram
Switch TB
RESULTS:
http://testbench.in/CR_15_CONSTRAINT_EXPRESSION.html[9/26/2012 2:12:07 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
7__4__4__4__7__2__2__3__2__7__
Engineers often mistaken that set membership operator is used only in constraint
block. It can also be used in other scopes also.
classset_mem;
randbit[0:2]Var;
endclass
set_mem obj=new();
integerrepet =0;
initial
begin
obj.Var =1;
repeat(10)
begin
while(obj.Var inside{[1:5]})
begin
$display("Var = %0d",obj.Var);
break;
end
end
end
endprogram
RESULTS:
#
#
#
#
#
#
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
4
5
1
1
2
2
NOTE: X and Z are allowed in set membership operator, but not in constraint block,
inside {....} is a statement which returns 0,1 or X .
Expressions are allowed in value set of inside operator.
randintegery,x;
constraintc1 {x inside{3,5,[y:2*y],z};}
If an expression in the list is an array then just use the array name in the constraint
block. Elements are traversed by descending into the array until reaching a singular
value.
intarray [$]='{3,4,5};
if(ex inside{1,2,array})
Weighted Distribution
There are two types of distribution operators.
The := operator assigns the specified weight to the item or, if the item is a range, to
every value in the range.
The :/ operator assigns the specified weight to the item or, if the item is a range, to
the range as a whole. If there are n values in the range, the weight of each value is
range_weight / n.
Var dist{10:=1;20:=2;30:=2}
The probability of Var is equal to 10,20 and 30 is in the ratio of 1,2,2 respectively.
Var dist{10:=1;20:=2;[30:32]:=2}
The probability of Var is equal to 10,20,30,31 and 32 is in the ratio of 1,2,2,2,2
respectively.
If you use the := operator each element weitht of the range has the assigned weight.
If you want to weight for the whole group,use :/ and the weight is equally distributed
for each element in that group.
Var dist{10:=1;20:=2;[30:32]:/2}
The probability of Var is equal to10,20,30,31,32 is in the ration of 1,2,2/3,2/3,2/3
respectively.
To demonstrate the distribution property,hear is an example.
EXAMPLE:
classDist;
randintegerVar;
constraintrange {Var dist{[0:1]:=50,[2:7]:=50};}
endclass
programDist_p_49;
Dist obj;
integercount_0,count_1,count_2,count_3,count_4,count_5,count_6,count_7;
integercount_0_1 ,count_2_7 ;
initial
begin
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
if(obj.randomize())
begin
if(obj.Var inside{0,1})count_0_1 ++;
elseif(obj.Var inside{[2:7]})count_2_7 ++;
end
$display(" count_0 = %0d , count_1 = %0d, count_2 = %0d, count_3 = %0d, count_4 =
%0d,
count_5
=
%0d,
count_6
=
%0d,
count_7=
%0d
",count_0,count_1,count_2,count_3,count_4,count_5,count_6,count_7);
$display(" count_0_1 = %0d ;count_2_7 = %0d ",count_0_1,count_2_7);
$finish;
end
endprogram
RESULTS:
#count_0 = 1290 , count_1 = 1244, count_2 = 1286, count_3 = 1265, count_4 = 1230,
count_5 = 1243, count_6 = 1189, count_7= 1253
#count_0_1 = 2534 ;count_2_7 = 7466
Now change the constraint to
constraintrange {Var dist{[0:1]:/50,[2:7]:/50};}
EXAMPLE:
classDist;
randintegerVar;
constraintrange {Var dist{[0:1]:/50,[2:7]:/50};}
endclass
programDist_p_50;
Dist obj;
initial
begin
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
if(obj.randomize())
begin
end
%0d,
count_5
=
%0d,
count_6
=
%0d,
count_7=
%0d
$finish;
end
endprogram
RESULTS:
#count_0 = 2496, count_1 = 2508, count_2 = 846, count_3 = 824, count_4 = 833,
#count_0_1 = 5004 ;count_2_7 = 4996
Both the results show, how may times each value occured.
NOTE: If no weight is specified for items,the default weight is 1. Weight 0 is also
allowed.
NOTE: Variable declared as randc are not allowed int dist.
If there are constraints on some expressions that cause the distribution weights on
these expressions to be not satisfiable, implementations are only required to satisfy
the non dist constraints. Use dist only on a one variable in a set of constraint
expression variable.
In the following example, Even though probability of Var2 is equal to 0 to 1 is in ratio
of 50, 50 to satisfy other constraints, the dist is ignored.
EXAMPLE:
classDist;
randintegerVar1,Var2;
constraintdist_c {Var2 dist{[0:1]:=50,[2:7]:=50};}
constraintrelation_c {Var1 <Var2;}
constraintrange_c {Var2 inside{2,3,4};}
endclass
programDist_p_51;
Dist obj;
initial
begin
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
if(obj.randomize())
begin
if(obj.Var2 ==0)count_0 ++;
elseif(obj.Var2 ==1)count_1 ++;
if(obj.Var2 inside{0,1})count_0_1 ++;
elseif(obj.Var2 inside{[2:7]})count_2_7 ++;
end
%0d,
count_5
=
%0d,
count_6
=
%0d,
count_7=
%0d
$finish;
end
endprogram
RESULTS:
#count_0 = 0 , count_1 = 0, count_2 = 3362, count_3 = 3321, count_4 = 3317,
#count_0_1 = 0 ;count_2_7 = 10000
Calling a new(), resets the distrubution algorithem. If new() is called to creat an
object when ever randomized is called,the dist algorithm restarts and the distribution
may not be what is expected.
EXAMPLE:
classDist;
randintegerVar;
endclass
programDist_p_52;
Dist obj;
initial
begin
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
begin
obj =new();
if(obj.randomize())
end
$display("count_0_1 : %0d : count_2_7 : %0d",count_0_1,count_2_7);
end
endprogram
RESULTS:
# count_0_1 : 3478 : count_2_7 : 6522
The distribution is not followed if the variable is declared as randc as distribution may
require repetition and randc doesnot allow. In the below example try changing the
weights in distribution function,you will get always same results otherwise
compilation error.
EXAMPLE:
classDist;
randcbyteVar;
endclass
programDist_p_52;
Dist obj;
initial
begin
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
begin
if(obj.randomize())
end
$display("count_0_1 : %0d : count_2_7 : %0d",count_0_1,count_2_7);
end
endprogram
To constraint enumerated values using dist, if they are less number, give weights
individually. If you want to give weights to enumerated values in groups, then give a
continues group. As enumeration is represented in integer, the discontinuation in the
declaration may not result properly.
EXAMPLE:
programenums_53;
typedefenum{V_SMALL,SMALL,MEDIUM,LARGE,V_LARGE}size_e;
classdist_c;
randsize_e size_d;
constraintsize_dist{size_d
dist{[V_SMALL:MEDIUM]:/40,[LARGE:V_LARGE]:/60};}
endclass
initialbegin
dist_c obj;
obj=new;
for(inti=0;i<=10;i++)
begin
obj.randomize();
$display(" size_d = %0s ",obj.size_d);
end
end
endprogram
Implication
Implication operator can be used to declare conditional relation. The syntax is
expression -> constraint set. If the expression is true,then the constraint solver should
satisfy the constraint set. If the expression is false then the random numbers
generated are unconstrainted by constraint set. The boolean equivalent of a -> b is
(!a || b).
randbita;
randbit[3:0]b;
constraintc {(a ==0)->(b ==1);}
a is one and b is 4 bit, So there are total of 32 solutions. But due to constraint c
(whenever a is 0 b should be 1) 15 solutions are removed. So probability of a = 0 is
1/(32-15) = 1/17. If u observe the following program resultscount_0/count_1
approximately equal to 1/17.
EXAMPLE:
classimpli;
randbita;
randbit[3:0]b;
endclass
programimpli_p_54;
impli obj;
integercount_0 ,count_1 ;
initial
begin
obj=new();
count_0 =0;count_1 =0;
for(inti=0;i<10000;i++)
begin
if(obj.randomize())
if(obj.a ==0)count_0 ++;
elsecount_1 ++;
end
$display(" count_0 = %0d;count_1 = %0d; ",count_0 ,count_1);
end
endprogram
RESULTS:
#count_0 = 571;count_1 = 9429;
If..Else
Just like implication, if...else style constraints are bidirectional.Above example
applies hear too.
EXAMPLE:
classif_else;
randbita;
randbit[3:0]b;
constraintc {if(a ==0)(b ==1);}
endclass
programif_else_p_55;
if_else obj;
initial
begin
obj=new();
for(inti=0;i<10000;i++)
begin
obj =new();
if(obj.randomize())
begin

elseif(obj.a ==1)count_1 ++;
end
end
$display(" count_0 = %0d;count_1 = %0d;",count_0 ,count_1);
end
endprogram
RESULTS:
#count_0 = 571;count_1 = 9429;
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TUTORIALS
VARIABLE ORDERING
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
SystemVerilog constraints provide a mechanism for ordering variables so that some

variables can be chosen independently of some variables. The solution space remains
the same, but the probability of picking up the solution space changes. The syntax for
variable ordering is "solve x before y". The exact meaning of this statement is "choos x
before y"as the this statement is to guide the distribution, but not the solution
space.
Only rand variables are allowed.
EXAMPLE:
classVar_order_56;
randbita;
randbit[3:0]b;
constraintbidirectional {a ->b ==0;}
endclass
OVM Tutorial
Easy Labs : OVM
The probability of a=1 is 1/((2**5)-15)=1/17, as constraints are bidirectional i.e both

the values of a and b are determined together. Constraints will be solved only once,
the solver picks the one solution from the possible set of {a,b} which has 17 solutions.
To guide the probability of selecting a= 0 to 50% and a = 1 to 50%, use
Easy Labs : VMM
constraintorder {solvea beforeb ;}
Easy Labs : SV
Easy Labs : UVM
AVM Switch TB
This guides the solver to give highest priority to a than b while picking the solution
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
VMM Ethernet sample from solution space. This is explicit variable ordering. The solver follows the implicit Report a Bug or Comment
variable ordering also, like randc are solved before rand variables. In dynamic arrays on This section - Your
size and elements are solved with two constraints( size constraint and element value input is what keeps
constraint) ,array size is solved before element.
Verilog
with time!
Verification
Verilog Switch TB
EXAMPLE:
classif_57;
randbita;
randbit[3:0]b;
OpenVera
constraintorder {solvea beforeb;}
Constructs
endclass
Switch TB
programif_p;
RVM Switch TB
if_57 obj;
RVM Ethernet sample integercount_0 ,count_1 ;
initial
begin
Specman E
for(inti=0;i<10000;i++)
Interview Questions
begin
obj =new();
if(obj.randomize())
elseif(obj.a ==1)count_1 ++;
end
$display(" count_0 = %0d;count_1 = %0d;",count_0 ,count_1);
end
endprogram
Basic Constructs
http://testbench.in/CR_16_VARIABLE_ORDERING.html[9/26/2012 2:12:17 PM]
RESULTS:
#count_0 = 4974;count_1 = 5026;
Too many explicit variable ordering may lead to circular dependency. The LRM says
that "Circular dependencies created by the implicit variable ordering shall result in an
error." and "circular dependency is not allowed". But it does not put restriction on
what to do if a explicit circular dependency exists. Check with your tool, if explicit
Circular dependency is existing, it may report warning,it may fail solver or proceed by
just ignoring the order.
EXAMPLE:
programCir_Dip_p_58;
classCir_Dep;
randintegera,b,c;
constrainta_c {solvea beforeb ;}
constraintb_c {solveb beforec ;}
constraintc_c {solvec beforea ;}
endclass
Cir_Dip obj=new();
initial
endprogram
RESULTS:
Error: Cird.sv(14): Cyclical dependency between random variables specified by
solve/before constraints.
LRM says, if the outcome is same, solver can solve without following the rule. In the
following case, x has only one possible assignment (0), so x can be solved for before
y. The constraint solver can use this flexibility to speed up the solving process.
EXAMPLE:
classslove_before;
randintegerx,y;
constraintC {x ==0;
x <y;
solvey beforex;}
endclass
programs_b_59;
slove_before obj ;
initial
begin
obj =new();
repeat(5)
if(obj.randomize())
$display(" x : %d :: y :%d ",obj.x,obj.y);
else
$display("Randomization failed ");
end
endprogram
RESULTS:
#x
#x
#x
#x
#x
: 0
: 0
: 0
: 0
: 0
::
::
::
::
::
y:
y:
y:
y:
y:
2064490291
2035140763
1279931677
2112945927
1977312554
Functions
Functions are allowed in constraints. It will be useful in applications like constrain the
max packet size based on the bandwidth other parameters.Constraint statements are
more error pron. Functions in constraints are called before constraints are solved. The
return value of the function is used to solve the constraint and it is treated as state
variable. There is an implicit variable ordering when solving these constraints.
Function should not be declared as static and should not modify the constraints, for
example calling the rand_mode and constraint_mode methods.
EXAMPLE:
classB_61;
randintx,y;
constraintC {x <=F(y);}
constraintD {y inside{2,4,8};}
endclass
Random variables used as function arguments shall establish an implicit variable
ordering or priority. Constraints that include only variables with higher priority are
solved before other lower priority constraints. Random variables solved as part of a
higher priority set of constraints, become state variables to the remaining set of
constraints. In above example y is solved before x. If y is not rand variable, then F(y)
is equalent to calling it in the pre_randomize method.
Iterative Constraints
Iterative constraints allow Constraining individual elements of fixed-size, dynamic,
associative arrays or queue. foreach construct specifies iteration over the each
elements of array.
EXAMPLE:
classEth_pkt_60;
randbytePayload[];
constraintsize_c {Payload.size()inside{[10:1500]};}
constraintelement_c {foreach(Payload[i ])Payload[i ]inside{[50:100]};}
foreach(Payload[i])
$display(" Payload[ %0d ] :%d ",i,Payload[i ]);
endfunction
endclass
programiterative_60;
Eth_pkt_60 obj;
initial
begin
obj =new();
if(obj.randomize())
$display(" RANDOMIZATION DONE ");
end
endprogram
RESULTS:
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
#Payload[
0 ] :87
1 ] :52
2 ] :70
3 ] :76
4 ] :71
5 ] :63
6 ] :62
7 ] :63
8 ] :66
9 ] :85
10 ] :95
11 ] :57
12 ] :78
NOTE:Remember whilerandomizing each element of array also array should be

declared as random variable otherwise randomization wont happen.
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TUTORIALS
CONSTRAINT SOLVER SPEED
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
IEEE SystemVerilog 2005 LRM does not specify the constraint solver algorithm. So
different vendors use different consraint solver algorithms. Some vendors may get the
solution quickly, some may not.
All the points discussed in this are not specific to a vendor. Just check your tool with
these examples to know how ur vendor constraint solver works.
As it is handy to type int and integer, we always declare some data types like size of
dynamic arrays as integer and constraint it to required range.
This will create 2^32 values and solver has to choose random number and solve the
constraint which will hit only few times.
Probability of a random value to be in solution space is less than appearing it outside
the solution space. To speed up ur solver, use the proper data types.
In the following example i showed the results of Questasim tool.
integeris 32 bit datatype.
shortint is 16 bit datatype.
byte is 8 bit datatype.
Easy Labs : SV
EXAMPLE:
programinte_p_62;
classinte;
Easy Labs : OVM
randintegerVar;
Easy Labs : VMM
constraintrandge_c {Var inside{[0:10]};}
endclass
AVM Switch TB
inte obj=new();
begin
repeat(10000)
Verilog
$finish(2);
Verification
end
Verilog Switch TB
endprogram
RESULT:
Basic Constructs
Easy Labs : UVM
OpenVera
# ** Note: Data structure takes 3407960 bytes of memory

#Process time 2.78 seconds
Constructs
EXAMPLE:
programinte_p_62;
RVM Switch TB
classinte;
RVM Ethernet sample randbit[4:0]Var;
constraintrandge_c {Var inside{[0:10]};}
endclass
inte obj=new();
Specman E
initial
begin
Interview Questions
repeat(10000)
$finish(2);
end
endprogram
Switch TB
RESULT:
http://testbench.in/CR_17_CONSTRAINT_SOLVER_SPEED.html[9/26/2012 2:12:27 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
To generate a random value which is one of the 2**0,2**1,2**2,......2**31.

If data type is integer and randomizing it will consume lot of simulation time.
constraintC {Var inside{2**0,2**1,2**2,......2**31};}
Write a function to check only one bit is high.
constraintC {$countones(array)==1;)
constraintC {Var ==(1<<index);}
Instead declare an 5 bit variable index, randomize it and set the index bit to 1 in post
randomize.
EXAMPLE:
classexpo_cons_64;
randbit[0:4]index;
integerarray; // No need to randomize array
array ='b0;
array[index]=1'b1;
endfunction
endclass
Adding smaller constraints in to a single block, speeds up simulation for some
simulators. Check these examples with your simulator. Some Solver may need more
iterations to get the valid solution. Split the constraints as small as possible. With this
controllability on constraint blocks is also improved.
EXAMPLE:1
classconstr;
randinta,b,c,d;
constraintC {(a ==10)&&(b <20)&&(c >30)&&(d <40);}
endclass
programconstr_p_65;
constr obj;
initial
begin
obj=new();
repeat(10000)
$finish(2);
end
endprogram
RESULT:

EXAMPLE:2
classconstr;
randinta,b,c,d;
constraintAc {(a ==10);}
constraintBc {(b <20);}
constraintCc {(c >30);}
constraintDc {(d <40);}
endclass
programconstr_p_66;
constr obj;
initial
begin
obj=new();
repeat(10000)
$finish(2);
end
endprogram
RESULT:
EXAMPLE:3
classconstr_67;
randinta,b,c,d;
constraintAc {(a ==10);(b <20);(c >30);(d <40);}
endclass
programconstr_p_67;
constr_p_67 obj;
initial
begin
obj=new();
repeat(10000)
$finish(2);
end
endprogram
RESULT:
Run all the above three examples with your simulator and check how your simulation
speed varies.
When iterative constraints are used on arrays, each element has a constraint on it. If
the constraints are simple enough to implement with out using constraint block,
simulation time may be saved. In the following example, there are two constraints
blocks, one for size other for each element. In reality there may be more constraint
blocks.
EXAMPLE:
classEth_pkt;
randbytePayload[];
constraintelement_c {foreach(Payload[i ])Payload[i ]inside{[50:100]};}
endclass
Eth_pkt obj;
initial
begin
obj =new();
for(inti=0;i<10000;i++)
begin
if(obj.randomize())
end
$finish(2);
end
endprogram
RESULT:
The above logic can implemented using post_randomize. Check how these two
example with ur vendor tool and look at the simulation speed. You may find
difference.
EXAMPLE:
classEth_pkt;
randintegerlength;
bytePayload[];
constraintsize_c {length inside{[46:1500]};}
Payload =new[length];
for(inti=0;i<length;i++)
Payload[i ]=50+$urandom%51;
endfunction
endclass
Eth_pkt obj;
initial
begin
obj =new();
for(inti=0;i<10000;i++)
begin
if(obj.randomize())
end
$finish(2);
end
endprogram
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TUTORIALS
RANDCASE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
randcase is a case statement that randomly selects one of its branches. The randcase
item expressions are non-negative integral values that constitute the branch weights.
An item weight divided by the sum of all weights gives the probability of taking that
branch. Randcase can be used in class are modules. The randcase weights can be
arbitrary expressions, not just constants.
EXAMPLE:
randcase
3:x =1;
1:x =2;
4:x =3;
endcase
The sum of all weights is 8; therefore, the probability of taking the first branch is
0.375, the probability of taking the second is 0.125, and the probability of taking the
third is 0.5. If a branch specifies a zero weight, then that branch is not taken. The
sum of all weights (SUM) is computed (negative values contribute a zero weight). If
SUM is zero or exceeds (2*32-1), no branch is taken. Each call to randcae statement
will return a random number in the range from 0 to SUM. $urandom_range(0,SUM) is
used to generate a random number. As the random numbers are generated using
$urandom are thread stable, randcase also exhibit random stability.
AVM Switch TB
modulerand_case_70;
integerx;
integercnt_1,cnt_2,cnt_3;
Verilog
initial
Verification
begin
Verilog Switch TB
cnt_1 =0;cnt_2=0;cnt_3 =0;
repeat(100000)
Basic Constructs
begin
randcase
3:x =1;
OpenVera
1:x =2;
Constructs
4:x =3;
endcase
Switch TB
if(x ==1)
RVM Switch TB
cnt_1++;
RVM Ethernet sample elseif(x ==2)
cnt_2++;
elseif(x ==3)
cnt_3++;
Specman E
end
$display("count_1 =%0d count_2 =%0d count_3 =%0d ",cnt_1,cnt_2,cnt_3);
Interview Questions
$display("Probability
of
count_1
=%0f
count_2
=%0f
count_3
",(cnt_1/100000.0),(cnt_2/100000.0),(cnt_3/100000.0));
end
endmodule
RESULTS:
# count_1 =37578 count_2 =12643 count_3 =49779
# Probability of count_1 =0.375780 count_2 =0.126430 count_3 =0.497790
http://testbench.in/CR_18_RANDCASE.html[9/26/2012 2:12:37 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
=%0f
<< PREVIOUS PAGE
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http://testbench.in/CR_18_RANDCASE.html[9/26/2012 2:12:37 PM]
Search
TUTORIALS
RANDSEQUENCE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
The random sequence generator is useful for randomly generating sequences of

stimulus. For example, to verify a temporal scenario, a sequence of packets are
needed. By randomizing a packet, it will generate most unlikely scenarios which are
not interested. These type of sequence of scenarios can be generated using
randsequence. A randsequence grammar is composed of one or more productions.
Production items are further classified into terminals and nonterminals. A terminal is
an indivisible item that needs no further definition than its associated code block.
Assertion
EXAMPLE:
modulers();
UVM Tutorial
initial
begin
VMM Tutorial
repeat(5)
OVM Tutorial
begin
randsequence(main )
Easy Labs : SV
main :one two three ;
Easy Labs : UVM
one:{$write("one");};
two:{$write(" two");};
Easy Labs : OVM
three:{$display(" three");};
Easy Labs : VMM
endsequence
end
AVM Switch TB
end
VMM Ethernet sample endmodule
DPI
Verilog
Verification
Verilog Switch TB
Basic Constructs
RESULTS:
one
one
one
one
one
two
two
two
two
two
three
three
three
three
three
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
The production main is defined in terms of three nonterminals: one, two and three.
Productions one,two and three are terminals. When the main is chosen, it will select
the sequence one, two and three in order.
Random Productions:
A single production can contain multiple production lists separated by the | symbol.
Production lists separated by a | imply a set of choices, which the generator will
make at random.
EXAMPLE:
modulers();
initial
repeat(8)
randsequence(main )
main :one |two |three ;
one:{$display("one");};
two:{$display("two");};
http://testbench.in/CR_19_RANDSEQUENCE.html[9/26/2012 2:12:47 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
three:{$display("three");};
endsequence
endmodule
RESULTS:
#three
#three
#three
#three
#one
#three
#two
#two
Results show that one, two and three are selected randomly.
Random Production Weights :
The probability that a production list is generated can be changed by assigning
weights to production lists. The probability that a particular production list is
generated is proportional to its specified weight. The := operator assigns the weight
specified by the weight_specification to its production list. A weight_specification
must evaluate to an integral non-negative value. A weight is only meaningful when
assigned to alternative productions, that is, production list separated by a |. Weight
expressions are evaluated when their enclosing production is selected, thus allowing
weights to change dynamically.
EXAMPLE:
modulers();
integerone_1,two_2,three_3;
initial
begin
one_1 =0;
two_2 =0;
three_3 =0;
repeat(6000)
randsequence(main )
main :one :=1|two :=2|three :=3;
one:{one_1++;};
two:{two_2++;};
three:{three_3++;};
endsequence
$display(" one %0d two %0d three %0d",one_1,two_2,three_3);
end
endmodule
RESULTS:
#one 1011 two 2005 three 2984
If..Else
A production can be made conditional by means of an if..else production statement.
The expression can be any expression that evaluates to a boolean value. If the
expression evaluates to true, the production following the expression is generated,
otherwise the production following the optional else statement is generated.
EXAMPLE:
modulers();
regon;
initial
begin
on =0;
one_1 =0;
two_2 =0;
three_3 =0;
repeat(2500)
randsequence(main )
main :onethree;
one:{if(on)one_1++;elsetwo_2 ++;};
three:{three_3++;};
endsequence
$display(" one %0d two %0d three %0d",one_1,two_2,three_3);
end
endmodule
RESULTS:
#one 0 two 2500 three 2500
Case
A production can be selected from a set of alternatives using a case production
statement. The case expression is evaluated, and its value is compared against the
value of each case-item expression, which are evaluated and compared in the order in
which they are given. The production associated with the first case-item expression
that matches the case expression is generated. If no matching case-item expression is
found then the production associated with the optional default item is generated, or
nothing if there no default item. Case-item expressions separated by commas allow
multiple expressions to share the production.
EXAMPLE:
modulers();
initial
begin
one_1 =0;
two_2 =0;
three_3 =0;
begin
randsequence(main )
main :case(i%3)
0:one;
1:two;
default:def;
endcase;
one :{$display("one");};
two :{$display("two");};
def :{$display("default");};
endsequence
end
end
endmodule
RESULTS:
one
two
default
one
two
default
Repeat Production Statements :
The repeat production statement is used to iterate a production over a specified
number of times. The repeat production statement itself cannot be terminated
prematurely. A break statement will terminate the entire randsequence block
PUSH_OPER : repeat( $urandom_range( 2, 6 ) ) PUSH ;
Interleaving productions-rand join :
EXAMPLE:
modulers();
initial
begin
one_1 =0;
two_2 =0;
three_3 =0;
repeat(6000)
randsequence(main )
main :one |repeat(2)two |repeat(3)three ;
one:one_1++;
two:two_2++;
three:three_3++;
endsequence
$display(" one %d two %d three %d",one_1,two_2,three_3);

end
endmodule
RESULTS:
one 989 two 2101 three 2810
Rand Join
The rand join production control is used to randomly interleave two or more
production sequences while maintaining the relative order of each sequence.
EXAMPLE:
modulers();
initial
for(inti =0;i <24;i++)begin
randsequence(main )
main :randjoinS1S2;
S1:A B ;
S2:C D ;
A:$write("A");
B:$write("B");
C:$write("C");
D:$write("D");
endsequence
if(i%4==3)
$display("");
end
endmodule
RESULTS:
ABCD
A
A
C
C
C
C
C
D
A
A
BD
DB
AB
BD
DB
Note that B always comes after A and D comes after C. The optional expression
following the rand join keywords must be a real number in the range 0.0 to 1.0. The
value of this expression represents the degree to which the length of the sequences to
be interleaved affects the probability of selecting a sequence. A sequences length is
the number of productions not yet interleaved at a given time. If the expression is
0.0, the shortest sequences are given higher priority. If the expression is 1.0, the
longest sequences are given priority.
EXAMPLE:
modulers();
initial
randsequence(main )
main :randjoin(0.0)S1S2;
S1:A B ;
S2:C D ;
A:$write("A");
B:$write("B");
C:$write("C");
D:$write("D");
endsequence
if(i%4==3)
$display("");
end
endmodule
RESULTS:
A
C
A
A
C
C
BCD
DAB
CBD
CDB
ABD
ADB
EXAMPLE:
modulers();
initial
randsequence(main )
main :randjoin(1.0)S1S2;
S1:A B ;
S2:C D ;
A:$write("A");
B:$write("B");
C:$write("C");
D:$write("D");
endsequence
if(i%4==3)
$display("");
end
endmodule
RESULTS:
A
A
C
C
A
C
C
CBD
CDB
ADB
ADB
BCD
DAB
ABD
Break
The break statement terminates the sequence generation. When a break statement is
executed from within a production code block, it forces a jump out the randsequence
block.
EXAMPLE:
randsequence()
WRITE:SETUPDATA;
SETUP:{if(fifo_length >=max_length )break;}COMMAND;
DATA:...
endsequence
When the example above executes the break statement within the SETUP production,
the COMMAND production is not generated, and execution continues on the line
labeled next_statement.
Return
The return statement aborts the generation of the current production. When a return
statement is executed from within a production code block, the current production is
aborted. Sequence generation continues with the next production following the
aborted production.
EXAMPLE:
randsequence()
TOP:P1P2;
P1:A B C ;
P2:A {if(flag ==1)return;}B C ;
A :{$display(A );};
B :{if(flag ==2)return;$display(B );};
C :{$display(C );};
endsequence
Depending on the value of variable flag, the example above displays the following:
flag == 0 ==> A B C A B C
flag == 1 ==> A B C A
flag == 2 ==> A C A C
When flag == 1, production P2 is aborted in the middle, after generating A. When flag
== 2, production B is aborted twice (once as part of P1 and once as part of P2), but
each time, generation continues with the next
production, C.
Value Passing Between Productions
Data can be passed down to a production about to be generated, and generated
productions can return data to the non-terminals that triggered their generation.
Passing data to a production is similar to a task call, and uses the same syntax.
Returning data from a production requires that a type be declared for the production,
which uses the same syntax as a variable declaration. Productions that accept data
include a formal argument list. The syntax for declaring the arguments to a
production is similar to a task prototype; the syntax for passing data to the
production is the same as a task call.
EXAMPLE:
randsequence(main )
main :firstsecond gen ;
first:add |dec ;
second :pop |push ;
add :gen("add");
dec :gen("dec");
pop :gen("pop");
push :gen("push");
gen(strings ="done"):{$display(s );};
endsequence
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TUTORIALS
RANDOM STABILITY
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
In verilog,if the source code does not change,with the same seed,the simulator
producess the same random stimulus on any mechine or any operating system.Verilog
has only one Random number generator.Random stimulus is generated using
$random(seed) where the seed is input to the RNG.$random will always return the
same value for same seed.
EXAMPLE:
moduleseed_74();
initial
repeat(5)
$display("random stimuls is%d",$random(Seed);
endmodule
While debugging to produce the same simulation, we should make sure that calls to
RNG is not disturbed. In Verilog if source code changes it is very unlikely that same
stimulus is produced with the same seed and we miss the bug.
Easy Labs : UVM
In SystemVerilog seeding will be done hierachily. Every module instance, interface

instance, program instance and package has initialization RNG. Every thread and
object has independent RNG . When ever dynamic thread is created its RNG is
Easy Labs : VMM
initialized with the next random value from its parent thread. RNG initialization and
RNG generation are different process.During RNG initialization,only seed is set to
AVM Switch TB
RNG.When ever static thread is created its RNG is initialized with the next random
VMM Ethernet sample value from the initialization RNG of module instance, interface instance, program
interface or package containing thread declaration. RNG initialization and RNG
generation are different process. During RNG initialization,only seed is set to RNG.
The random number generator is deterministic. Each time the program executes, it
Verilog
cycles through the same random sequence. This sequence can be made
Verification
nondeterministic by seeding the $urandom function with an extrinsic random variable,
Verilog Switch TB
such as the time of day.
Easy Labs : OVM
Basic Constructs
SystemVerilog system functions $urandom and $urandom_range are thread stable.

Calls to RNG using these system function, uses the RNG of that thread. So next time
while using $random in SystemVerilog,think twice.
OpenVera
Constructs
NOTE: The same stimulus sequence can not be produced on different simulators as
the LRM does not restrict the vendors to impliment specific constraint solver. Verilog
Switch TB
LRM specifies the RNG algorithm for $random ,so the same stimulas can be produced
RVM Switch TB
on different simulators(not always as I discussed in one of the above topic). Even if
RVM Ethernet sample the SystemVerilog LRM specifies RNG algorithm ,the same sequence cannot be
produced on different vendors because of the following are few reasons :
-> LRM doesnot restrict the constraint solver algorithm.
-> Order of threads creation.
Specman E
-> Order of thread execution.
Interview Questions
EXAMPLE:
classRan_Stb_1;
randbit[2:0]Var;
endclass
programRan_Stb_p_75;
Ran_Stb_1 obj_1 =new();
initial
repeat(10)
http://testbench.in/CR_20_RANDOM_STABILITY.html[9/26/2012 2:12:56 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
begin
$display(" Ran_Stb_1.Var : %0d",obj_1.Var);
end
endprogram
RESULTS:
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
:
:
:
:
:
:
:
:
:
:
4
5
1
1
0
2
2
7
6
0
Stimulus generated in a thread or object is independed of other stimulus. So changes

in the source code will not effect threads or objects. This is Valid as long as the order
of the threads is not distrubed. If a new object is created, make sure that that they
are added at the end.
EXAMPLE:
classRan_Stb_1;
randbit[2:0]Var;
endclass
classRan_Stb_2;
randbit[2:0]Var;
endclass
initial
repeat(10)
begin
$display(" Ran_Stb_1.Var : %0d",obj_1.Var);
end
endprogram
New object obj_2 is added after all the objects. Look at the simulation results,they
are same as the above.
RESULTS:
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
:
:
:
:
:
:
:
:
:
:
4
5
1
1
0
2
2
7
6
0
If a new thread is added, make sure that it is added after all the threads.
EXAMPLE:
classRan_Stb_1;
randbit[2:0]Var;
endclass
classRan_Stb_2;
randbit[2:0]Var;
endclass
initial
begin
repeat(5)
begin
$display(" Ran_Stb_1.Var : %0d ",obj_1.Var);
end
repeat(5)
begin
end
end
endprogram
The results show clearly that Random values in obj_1 are same as previous program
simulation.
RESULTS:
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
:
:
:
:
:
:
:
:
:
:
4
5
1
1
0
3
3
6
1
1
Order of the randomize call to different objects doesnot effect the RNG generation.
EXAMPLE:
classRan_Stb_1;
randbit[2:0]Var;
endclass
classRan_Stb_2;
randbit[2:0]Var;
endclass
initial
begin
repeat(5)
begin
end
repeat(5)
begin
end
end
endprogram
RESULTS:
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_2.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
:
:
:
:
:
:
:
:
:
:
3
3
6
1
1
4
5
1
1
0
Adding a constraint in one class, will only effect the stimuls of that object only.
EXAMPLE:
classRan_Stb_1;
randbit[2:0]Var;
constraintC {Var <4;}
endclass
classRan_Stb_2;
randbit[2:0]Var;
endclass
initial
repeat(5)
begin
$display(" Ran_Stb_1.Var : %0d :: Ran_Stb_2.Var : %0d ",obj_1.Var,obj_2.Var);
end
endprogram
RESULTS:
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
#Ran_Stb_1.Var
:
:
:
:
:
0
1
1
1
0
::
::
::
::
::
Ran_Stb_2.Var
Ran_Stb_2.Var
Ran_Stb_2.Var
Ran_Stb_2.Var
Ran_Stb_2.Var
:
:
:
:
:
3
3
6
1
1
Srandom
When an object or thread is created, its RNG is seeded using the next value from the
RNG of the thread that creates the object. This process is called hierarchical object
seeding. Sometimes it is desirable to manually seed an objects RNG using the
srandom() method. This can be done either in a class method or external to the class
definition. Example to demonstrate seeding in objects.
EXAMPLE:
classRand_seed;
randintegerVar;
functionnew(intseed);
srandom(seed);
$display(" SEED is initised to %0d ",seed);
endfunction
$display(": %0d :",Var);
endfunction
endclass
programRand_seed_p_80;
Rand_seed rs;
initial
begin
rs =new(20);
repeat(5)
void'(rs.randomize());
rs =new(1);
repeat(5)
rs =new(20);
repeat(5)
end
endprogram
RESULTS:
#SEED is initised to 20
# : 1238041889 :
# : 1426811443 :
# : 220507023 :
# : -388868248 :
# : -1494908082 :
# : 1910312675 :
# : 632781593 :
# : -453486143 :
# : 671009059 :
# : -967095385 :
# : 1238041889 :
# : 1426811443 :
# : 220507023 :
# : -388868248 :
# : -1494908082 :
Simulation results show that same sequence is repeated when the same seed is used
for initialization.
Example to demonstrate seeding a thread.
EXAMPLE:
integerx,y,z;
fork//set a seed at the start of a thread
beginprocess::self.srandom(100);x =$urandom;end
//set a seed during a thread
beginy =$urandom;process::self.srandom(200);end
// draw 2 values from the thread RNG
beginz =$urandom+$urandom;end
join
The above program fragment illustrates several properties:

Thread locality: The values returned for x, y, and z are independent of the order of
thread execution. This is an important property because it allows development of
subsystems that are independent, controllable, and predictable.
Hierarchical seeding: When a thread is created, its random state is initialized using
the next random value from the parent thread as a seed. The three forked threads are
all seeded from the parent thread.
IEEE 2005 SystemVerilog LRM does not specify whether scope randomization function
is random stable or not.
From LRM
13.13 Random stability
The RNG is localized to threads and objects. Because the sequence of random values
returned by a thread or object is independent of the RNG in other threads or objects,
this property is called random stability.
Random stability applies to the following:
The system randomization calls, $urandom() and $urandom_range()
The object and process random seeding method, srandom()
The object randomization method, randomize()
In above its mentioned that "object randomization method, randomize()". There is
nothing mentioned about std::randomize() method random stability.
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ARRAY RANDOMIZATION
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Functional Coverage
Assertion
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UVM Tutorial
Most application require to randomize elememts of array.Arrays are used to model

payload,port connections etc.
SystemVerilog has Fixed Arrays,Dynamic arrays,queues and Associative arrays.
If an array is constrained by both size constraints and iterative constraints for
constraining every element of array. The size constraints are solved first, and the
iterative constraints next. In the example,size_c is solved first before element_c. As
constraint element_c canot be solved without knowing the size. So there is implicit
ordering while solveing this type of constraints.
This is the only approach for applying constraints to individual elements of arrays,
with this approach,performance is degraded. IfPayload.size() = 1000, then 1000
constraints are created by foreach. it takes much time for the solver to solve all the
constraints. Another simple approach is using a task to randomize each element. This
approach is 5X times faster than foreach.
VMM Tutorial
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE:
classEth_pkt_82;
randbytePayload[];
taskrandomize_foreach;
foreach(Payload[i ])
Payload[i ]=50+$urandom%50;// try with randomize( Payload[i]) with .....
endtask
endclass
programiterative;
Eth_pkt_82 obj;
initial
begin
obj =new();
for(inti=0;i<10000;i++)
begin
obj.randomize_foreach();
end
end
endprogram
Switch TB
RVM Switch TB
In applications where some constraints are dependent on the array elements, the
RVM Ethernet sample following may help. call the randomization function in constraints, define proper
variable ordering.
Specman E
Interview Questions
EXAMPLE:
classEth_pkt;
randbytePayload[];
randbytesize;
bitdummy =1;
constraintdummy_c {dummy ==randomize_size();}

constraintsize_c {sizeinside{[10:100]};}
constraintorder_c1 {solvesizebeforedummy;}
constraintorder_c2 {solvedummy beforePayload;}
functionbitrandomize_size();
Payload =new[size];
http://testbench.in/CR_21_ARRAY_RANDOMIZATION.html[9/26/2012 2:13:07 PM]
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
input is what keeps
with time!
randomize_size =1;
returnrandomize_size;
endfunction
endclass
Eth_pkt obj;
initial
begin
obj =new();
begin
$display("
Eth_pkt.size
:
%d::
",obj.size,obj.Payload.size());
for(intj=0;j<obj.Payload.size();j++)
$write("%4d _",obj.Payload[j]);
$display("");
end
end
endprogram
Payload.size()
%d
In the above example, constraint order_c1 {solve size before dummy;} makes sure
that size is randomized before function ranomize_size() is called.
If constraints are dependent on the sum of the elements of the dynamic array. The
interesting elements are the new random variables which are created by current
randomization call. If you are not using any techinique to get the right size after
randomization sum() returns the sum of all the array elements .
EXAMPLE:
classdynamic_array_89;
randbytesize;
randbytedata[];
constraintsize_c {data.size()==size;size>=0;}
constraintsum_c{data.sum()<1000;}
endclass
Do manually in a function and use it or just use { data.sum() with (item.index < size)
1000;}There is one more bug in the above code.The sum() methodreturns a single
value of the same type as the array element type.So the sum returns only 8 bits in
this case.So a.sum() is allways less than 255 which is less than 1000 and allways the
constraint is satisfied which is not what is expected.
EXAMPLE:
programsumm;
dynamic_array obj =new();
integersum;
initial
begin
sum=0;
for(inti=0;i<obj.size;i++)
sum=sum+obj.data[i];
$display(" Sum is %d ",sum);
end
endprogram
Using y.sum with (item + 32'b0) will result in a 32 bit proper sum.
EXAMPLE:
classdynamic_array;
randintegersize;
randreg[7:0]data[];
constraintsum_c{data.sum()==data[0];}
constraintsize_c {data.size()==size;size>1000;size<2000;}
endclass
programsumm;
dynamic_array obj =new();
integersum;
initial
repeat(10)
begin
sum=0;
for(inti=0;i<obj.size;i++)
begin
sum=sum+obj.data[i];
end
$display(" Sum is %d obj.sum() %d",obj.data[0],obj.data.sum());
end
endprogram
Randomization donot create the objects. So when a array of objects is randomized,
all the objects are pointing to null and randomization can not be done on null
objets.new() has to be called to creat objects then only randomize can be done on
it.So creat array of objects before calling the randomize.
EXAMPLE:
classcls;
randintegerVar;
endclass
classarr_obj;
randcls objcls [0:2];
endclass
programarr_obj_p_91;
arr_obj obj =new();
inti;
initial
begin
if(obj.randomize())
begin
$display(" Randomization is done ");
for(i=0;i<3;i++)
if(obj.objcls[i]==null)
$display(" obj.objcls == null ");
else
$display(" obj.objcls.Var : %d ",obj.objcls[i].Var );
end
else
$display(" Randomization failed ");
end
endprogram
RESULTS:
#Randomization is done
#obj.objcls == null
#obj.objcls == null
#obj.objcls == null
In the following, objects are created during the creation of arr_obj. This can also be
done in pre_randomize. When dynamic arrays of objects are created, similar approach
has to be taken and size of the dynamic array has to be decided before the new() is
called, which makes no sense using the dynamic array of objects.
EXAMPLE:
classcls;
randintegerVar;
endclass
classarr_obj;
randcls objcls [0:2];
functionnew();
foreach(objcls[i])
objcls[i]=new();
endfunction
endclass
programarr_obj_p_91;
arr_obj obj =new();
inti;
initial
begin
if(obj.randomize())
begin
$display(" Randomization is done ");
for(i=0;i<3;i++)
if(obj.objcls[i]==null)
$display(" obj.objcls == null ");
else
$display(" obj.objcls.Var : %d ",obj.objcls[i].Var );
end
else
$display(" Randomization failed ");
end
endprogram
RESULTS:
Randomization is done
obj.objcls.Var : 733126180
obj.objcls.Var :-119008195
obj.objcls.Var : 342785185
To create queue of objects,first length of the queue has to be randomized.Then

number of objects equal to length of queue.Delete the old elements in the
queue.Then push each object new objects in to the queue.Lastly randomize each
object.
EXAMPLE:
classcls;
randintegerVar;
endclass
classq_cls;
randcls obj[$];
randbit[2:0]length;
functionvoidpre_randomize();
length =$urandom%20;// Compute the length of queue.
obj ={}; // Delet all the elements in the queue or .delet can be
used
repeat(length)
begin
cls obj_loc;
obj_loc =new(); // Creat new object.
obj.Push_back(obj_loc); // insert it into queue.
end
endfunction
endclass
programq_obj_p_93;
q_cls obj =new();
initial
begin
if(obj.randomize())
begin
$display("Randomization done");
$write(" Length of q : %0d :::",obj.length);
for(inti ;i<obj.length;i++)
begin
cls obj_temp;
obj_temp =obj.obj.Pop_front();
$write(" : %0d : ",obj_temp.Var);
end
end
else
end
endprogram
RESULT:
Randomization done
Length of q : 6 ::: : 1474208060 :: -1098913923 :: 816460770 :: 41501707 :: 1179418145 :: -212817600 :
Some application like linked list needs to generate an array of random values which
are unique. foreach provides the solution,but the simples and the best solution is
assign all the elements in arrat with its index and use shuffel inside a task.shuffle()
randomizes the order of the elements in the array.Constraint solver is not used
hear,so the preformance is better.
EXAMPLE:
classList;
integerPointer[5];
taskrandomize_unique;
foreach(Pointer[i ])
Pointer[i ]=i;
Pointer.shuffle();
endtask
endclass
programUnique_rand_94;
List obj;
initial
begin
obj =new();
obj.randomize_unique();
for(inti=0;i<5;i++)
begin
$display(" Pointer[%0d] = %d ",i,obj.Pointer[i]);
end
end
endprogram
RESULT:
Pointer[0]
Pointer[1]
Pointer[2]
Pointer[3]
Pointer[4]
= 2
= 1
= 3
= 0
= 4
Using foreach in global constraints in the following way wont work currently. as the .
operator(dot) is not supported in foreach in LRM currently.
EXAMPLE:
classparent;
randbytea[0:9];
endclass
classchild_96;
randparent P;
randbytea[0:9];
constraintNot_supported {foreach(P.a[i])P.a[i]==a[i];}
endclass
The correct way to write the above constraint is
constraint Supported { foreach(a[i]) a[i] == P.a[i];}
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CONSTRAINT GUARDS
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Constraint guards are predicate expressions that function as guards against the
creation of constraints, and not as logical relations to be satisfied by the solver.
These predicate expressions &&,|| and ! are evaluated before the constraints are
solved. This enables users to write constraints that avoid errors due to nonexistent
object handles or array indices out of bounds.
There are 4 states when asub expression is evlauated.
0 FALSE Subexpression evaluates to FALSE.
1 TRUE Subexpression evaluates to TRUE.
E ERROR Subexpression causes an evaluation error like null pointer.
R RANDOM Expression includes random variables and cannot be evaluated.
If any of subexpression results ERROR,then randomization fails.
EXAMPLE:1
classSList_97;
randintn;
randSlist_97 next;
constraintsort{n <next.n;}
endclass
AVM Switch TB
Index
Constrained Random
Verification
Verilog Crv
Systemverilog Crv
Randomizing Objects
Random Variables
Checker
Constraint Block
Inline Constraint
Global Constraint
Constraint Mode
Randomization
Controlability
Static Constraint
Variable Ordering
Randcase
Randsequence
Random Stability
Array Randomization
Constraint Guards
Titbits
VMM Ethernet sample In the Example 1, while sorting the elements of array in ascending order, if next is Report a Bug or Comment
null i.e for last element randomization fails.
input is what keeps
Verilog
EXAMPLE:2
with time!
Verification
classSList_98;
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
randintn;
randSlist_98 next;
constraintsort{if(next!=null)n <next.n;}
endclass
In Example 2, Even if next is null, constraint wont be generated so randomization will

never fail.
EXAMPLE:3
RVM Ethernet sample classD;
Specman E
Interview Questions
intx;
endclass
classC;
randintx,y;
D a,b;
constraintc1 {(x <y ||a.x >b.x ||a.x ==5)->x+y ==10;}
endclass
In Example 3, the predicate subexpressions are (x < y), (a.x > b.x), and (a.x == 5),
which are all
connected by disjunction. Some possible cases are as follows:
Case 1: a is non-null, b is null, a.x is 5.

Because (a.x==5) is true, the fact that b.x generates an error does not result in an
http://testbench.in/CR_22_CONSTRAINT_GUARDS.html[9/26/2012 2:13:28 PM]
error.
The unconditional constraint (x+y == 10) is generated.
Case 2: a is null.
This always results in error, irrespective of the other conditions.
Case 3: a is non-null, b is non-null, a.x is 10, b.x is 20.
All the guard subexpressions evaluate to FALSE.
The conditional constraint (x<y) -> (x+y == 10) is generated.
EXAMPLE:4
classD;
intx;
endclass
classC;
randintx,y;
D a,b;
constraintc1 {(x <y &&a.x >b.x &&a.x ==5)->x+y ==10;}
endclass
In Example 4, the predicate subexpressions are (x < y), (a.x > b.x), and (a.x == 5),
which are all
connected by conjunction. Some possible cases are as follows:
Because (a.x==5) is false, the fact that b.x generates an error does not result in an
error.
The constraint is eliminated.
Case 2: a is null
All the guard subexpressions evaluate to TRUE, producing constraint (x<y) -> (x+y ==
10).
EXAMPLE:5
classD;
intx;
endclass
classC;
randintx,y;
D a,b;
constraintc1 {(x <y &&(a.x >b.x ||a.x ==5))->x+y ==10;}
endclass
In Example 5, the predicate subexpressions are (x < y) and (a.x > b.x || a.x == 5),
which are connected
by disjunction. Some possible cases are as follows:
The guard expression evaluates to (ERROR || a.x==5), which evaluat es to (ERROR ||
TRUE)
The guard subexpression evaluates to TRUE.
The guard expression evaluates to (ERROR || FALSE) and generates an error.
Case 3: a is null
All the guard subexpressions evaluate to TRUE.
EXAMPLE:6
classA_108;
randintegerarr[];
constraintc {foreach(arr[i])arr[i]==arr[i+1];}
endclass
In Example 6, generates an error when i is the last element in the array.
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Index
Constrained Random
Verification
The first constraint program which wrote randomized sucessfully but the results are Verilog Crv
Systemverilog Crv
not what expected.
Randomizing Objects
My constraint is to limit Var between 0 and 100.
Random Variables
EXAMPLE:
Checker
classBase;
Constraint Block
randintegerVar;
Inline Constraint
constraintrandge {0<Var <100;}
Global Constraint
endclass
Constraint Mode
programinhe_109;
Randomization
Base obj;
Controlability
Static Constraint
initial
begin
Variable Ordering
obj =new();
Randcase
if(obj.randomize())
Randsequence
Random Stability
else
Array Randomization
Constraint Guards
end
Titbits
endprogram
TITBITS
Verilog
Verification
Verilog Switch TB
Basic Constructs
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
Randomization
..etc
successful
successful
successful
successful
successful
successful
successful
:
:
:
:
:
:
:
Var
Var
Var
Var
Var
Var
Var
=
=
=
=
=
=
=
2026924861
-1198182564
1119963834
-21424360
-358373705
-345517999
-1435493197
OpenVera
Constructs
The mistake what I have done is simple,this resulted the constraint solver to solve the
statement
(((0 < Var) < 100))
RVM Switch TB
For the above equation, are the results are correct.
RVM Ethernet sample Then I changed the constraint to { 0< Var ;Var < 100 ;}
The solver considered the this constraint as (0 < Var) && (Var < 100); and solution are
correct.
Switch TB
Specman E
Interview Questions
To generate random values less then -10,the following may not work.
EXAMPLE:
classBase_110;
randintegerVar;
constraintrandge {Var +10<=0;}
endclass
RESULTS:
Randomization sucsessfull : Var = -1601810394
Randomization sucsessfull : Var = 2147483646
http://testbench.in/CR_23_TITBITS.html[9/26/2012 2:13:37 PM]

input is what keeps
with time!

Var = 2147483646 is not less -10, but the solver solved it using ((Var + 10) <= 0) i.e
((2147483646 + 10) <= 0) which is true
To solve this use the inside operator.
constraint randge { Var inside {[-10000:-10]};}
Make sure that constraint expression are not mixed up with signed and unsigned
variables.
#Ran_Stb_1.Var :4
#Ran_Stb_1.Var :5
#Ran_Stb_1.Var :1
#Ran_Stb_1.Var :1
#Ran_Stb_1.Var :0
#Ran_Stb_1.Var :2
#Ran_Stb_1.Var :2
#Ran_Stb_1.Var :7
#Ran_Stb_1.Var :6
#Ran_Stb_1.Var :0
Constraining Non Integral Data Types:
Constraints can be any SystemVerilog expression with variables and constants of
integral type (e.g.,
bit, reg, logic, integer, enum, packed struct).
To Constraint a real number, randomize integer and convert it to real as it is
required.
EXAMPLE:
classcls;
randintegerVar;
endclass
classreal_c;
realr;
randintegeri;
randintegerj;
r =$bitstoreal({i,j});
$display("%e ",r);
endfunction
endclass
programreal_p_111;
real_c obj =new();
initial
repeat(5)
endprogram
RESULT:
2.507685e-280
-1.188526e-07
9.658227e-297
-2.912335e+247
2.689449e+219
Saving Memory
In packet protocol application like PCI Express, the packets which are driven to the
DUV has to be manipulated and stored to compare with the actual packet which is
coming from DUV. If the packet size is large and number of packets are huge, it
occupies more momery. In verilog in this case the whole packet need to be stored.
HVL has more advantages w.r.t this case. We can store high level information like
packet size, CRC error, header. But functional verification needs to store the payload
for checking that the payload did not get corrupted. Major part of the storage taken
by the payload itself. If we can avoid storing the payload, we can save lot of storage
space.
The following technique assigns predictable random values to payload fields. Only the
start of the payload need to be stored.
EXAMPLE:
integerpkt_length;
bytepayload[0:MAX];
taskgen_payload(integerseed ,integerlength);
integertemp_seed;
temp_seed =seed;
begin
temp_seed =$random(temp_seed);
payload[i]=temp_seed;
end
endtask
This is the task which checks whether payload is recived didnot get corrupted.
EXAMPLE:
taskcheck_payload(integerseed,integerlength);
integertemp_seed;
temp_seed =seed;
begin
temp_seed =$random(temp_seed);
if(payload[i]!=temp_seed)
$display(" ERROR :: DATA MISMATCH ");
end
endtask
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INTRODUCTION
Systemverilog Functional Coverage Features
Coverage of variables and expressions
Cross coverage
Automatic and user-defined coverage bins
-- Values, transitions, or cross products
Filtering conditions at multiple levels
Flexible coverage sampling
-- Events, Sequences, Procedural
Directives to control and query coverage
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CO_01_INTRODUCTION.html[9/26/2012 2:13:44 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
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Index
Introduction
Cover Group
The covergroup construct encapsulates the specification of a coverage model. Each Sample
Cover Points
covergroup specification can include the following components:
A clocking event that synchronizes the sampling of coverage points
Coverage Bins
A set of coverage points
Cross coverage between coverage points
Transition Bins
Optional formal arguments
Wildcard Bins
Coverage options
Ignore Bins
Illegal Bins
Cross Coverage
A Cover group is defined between key words covergroup&endgroup.
Coverage Options
A Covergroup Instance can be created using the new()operator.
Coverage Methods
System Tasks
covergroupcg;
Cover Property
...
...
...
endgroup
input is what keeps
cg cg_inst =new;
with time!
COVER GROUP
The above example defines a covergroup named "cg". An instance of "cg" is declared
VMM Ethernet sample as "cg_inst" and created using the "new" operator.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CO_02_COVER_GROUP.html[9/26/2012 2:13:52 PM]
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Index
Introduction
Coverage should be triggered to sample the coverage values. Sampling can be done Cover Group
Sample
using
Cover Points
Any event expression -edge, variable
End-point of a sequence
Coverage Bins
Event can be omitted
Calling sample() method.
Transition Bins
Wildcard Bins
Ignore Bins
covergroupcg @(posedgeclk);
Illegal Bins
...
Cross Coverage
...
Coverage Options
...
Coverage Methods
endgroup
System Tasks
Cover Property
SAMPLE
The above example defines a covergroup named "cg". This covergroup will be Report a Bug or Comment
automatically sampled each time there is a posedge on "clk" signal.
Easy Labs : OVM
covergroupcg;
...
...
AVM Switch TB
...
VMM Ethernet sample endgroup
cg cg_inst =new;
Verilog
initial// or task or function or always block
Verification
begin
...
Verilog Switch TB
...
Basic Constructs
cg_inst.sample();
...
...
end
OpenVera
Easy Labs : VMM
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Sampling can also be done by calling explicitly calling .sample() method in procedural
code. This is used when coverage sampling is required based on some calculations
rather than events.
Specman E
Interview Questions
http://testbench.in/CO_03_SAMPLE.html[9/26/2012 2:13:59 PM]
input is what keeps

with time!
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Index
Introduction
A covergroup can contain one or more coverage points. A coverage point can be an Cover Group
integral variable or an integral expression. A coverage point creates a hierarchical Sample
scope, and can be optionally labeled. If the label is specified then it designates the Cover Points
name of the coverage point.
Coverage Bins
programmain;
Transition Bins
bit[0:2]y;
Wildcard Bins
bit[0:2]values[$]='{3,5,6};
Ignore Bins
Illegal Bins
covergroupcg;
Cross Coverage
cover_point_y :coverpointy;
Coverage Options
endgroup
Coverage Methods
System Tasks
cg cg_inst =new();
Cover Property
initial
foreach(values[i])
begin
input is what keeps
y =values[i];
cg_inst.sample();
with time!
end
endprogram
COVER POINTS
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
In the above example, we are sampleing the cover point "y". The cover point is named
"cover_point_y" . In the Coverage report you will see this name. A cover group "cg" is
defined and its instance"cg_inst" is created. The value of "y" is sampled when
cg_inst.sample() method is called. Total possible values for Y are 0,1,2,3,4,5,6,7.The
variable "y" is assigned only values 3,5,6. The coverage engine should report that
only 3 values are covered and there are 8 possible values.
Basic Constructs
Commands To Simulate And Get The Coverage Report:

OpenVera
Constructs
VCS
Switch TB
Compilation command:
vcs -sverilog -ntb_opts dtm filename.sv
RVM Ethernet sample Simulation Command:
./simv
Command to generate Coverage report: Coverage report in html format will be in the
./urgReport directory
Specman E
urg -dir simv.vdb
RVM Switch TB
Interview Questions
NCSIM
ncverilog -sv -access +rwc -coverage functional filename.sv
iccr iccr.cmd
iccr.cmd
load_test *
report_detail -instance -both -d *
http://testbench.in/CO_04_COVER_POINTS.html[9/26/2012 2:14:07 PM]
QUESTASIM
Create the library
vlib library_name
Compilation command
vlog work library_name filename.sv
Simulation Command:
vsimlibrary_name.module_top_name
Coverage will be saved in UCDB Format in Questasim
Case 1) By default in modelsim.ini file to Name of UCDB file will be threre, If it is
there, it will create one filefilename.ucdb
Case 2) Sometimes in modelsim.ini file UCDB File name will be commented in that
case we have to save UCDB File explicitly after vsim command
Coverage save filename.ucdb
Once u are ready with UCDB File u need to generate coverage report from ucdb file
To generate only Functional coverage report
vcover cvg myreport.txt outfilename.ucdb
After running the above program, the coverage report will show,
VARIABLE: cover_point_y
Expected : 8
Covered : 3
Percent: 37.50.
In the above report,the coverage percentage is calculated by Covered/Expected.
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TUTORIALS
COVERPOINT EXPRESSION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A coverage point can be an integral variable or an integral Expression.

SystemVerilog allows specifying the cover points in various ways.
1)Using XMR
Example:
Cover_xmr :coverpointtop.DUT.Submodule.bus_address;
2)Part select
Example:
Cover_part:coverpointbus_address[31:2];
3)Expression
Example:
Cocver_exp:coverpoint(a*b);
4)Function return value
Example:
VMM Ethernet sample Cover_fun:coverpointfuncation_call();
5)Ref variable
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Example:
covergroup(refintr_v)cg;
cover_ref:coverpointr_v;
endgroup
Coverage Filter
The expression within the iff construct specifies an optional condition that disables
coverage for that cover point. If the guard expression evaluates to false at a sampling
point, the coverage point is ignored.
RVM Ethernet sample For example:

Specman E
Interview Questions
covergroupcg;
coverpointcp_varib iff(!reset);// filter condition
endgroup
In the preceding example, cover point varible "cp_varib" is covered only if the value
reset is low.
http://testbench.in/CO_05_COVERPOINT_EXPRESSION.html[9/26/2012 2:14:17 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Index
Introduction
Generic coverage groups can be written by passing their traits as arguments to the Cover Group
coverage constructor. This allows creating a reusable coverage group which can be Sample
Cover Points
used in multiple places.
Generic Coverage
For example, To cover a array of specified index range.
Groups
Coverage Bins
covergroupcg(refintarray,intlow,inthigh )@(clk);
coverpoint// sample variable passed by reference
Transition Bins
{
Wildcard Bins
binss ={[low :high]};
Ignore Bins
}
Illegal Bins
endgroup
Cross Coverage
Coverage Options
intA,B;
Coverage Methods
rgc1 =new(A,0,50);// cover A in range 0 to 50
System Tasks
rgc2 =new(B,120,600);// cover B in range 120 to 600
Cover Property
The example above defines a coverage group, gc, in which the signal to be sampled
as well as the extent of the coverage bins are specified as arguments. Later, two Report a Bug or Comment
instances of the coverage group are created; each instance samples a different signal on This section - Your
input is what keeps
and covers a different range of values.
GENERIC COVERAGE GROUPS
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CO_06_GENERIC_COVERAGE_GROUPS.html[9/26/2012 2:14:25 PM]
with time!
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TUTORIALS
COVERAGE BINS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
A coverage-point bin associates a name and a count with a set of values or a

sequence of value transitions. If the bin designates a set of values, the count is
incremented every time the coverage point matches one of the values in the set. If
the bin designates a sequence of value transitions, the count is incremented every
time the coverage point matches the entire sequence of value transitions.
Bins can be created implicitly or explicitly.
Functional Coverage
Assertion
DPI
UVM Tutorial
Implicit Bins
While define cover point, if you do not specify any bins, then Implicit bins are
created. The number of bins creating can be controlled by auto_bin_maxparameter.
VMM Tutorial
OVM Tutorial
Example for non enum cover point
Easy Labs : SV
Easy Labs : UVM
programmain;
bit[0:2]y;
bit[0:2]values[$]='{3,5,6};
Easy Labs : VMM
covergroupcg;
AVM Switch TB
cover_point_y :coverpointy
VMM Ethernet sample {option.auto_bin_max =4;}
endgroup
cg cg_inst =new();
Verilog
initial
Verification
foreach(values[i])
Verilog Switch TB
begin
y =values[i];
Basic Constructs
cg_inst.sample();
end
OpenVera
endprogram
Easy Labs : OVM
Constructs
Switch TB
In the above example, the auto_bin_max is declared as 4. So, the total possible
values are divided in 4 parts and each part correspoits to one bin.
RVM Ethernet sample The total possible values for variable "y" are 8. They are divided in to 4 groups.
RVM Switch TB
Specman E
Interview Questions
Bin[0]for
Bin[1]for
Bin[2]for
Bin[3]for
0
2
4
6
and 1
and 3
and 5
and 7
Varible Y is assigned values 3,5 and 6. Values 3,5 and 6 belongs to bins bin[1],bin[2]
and bin[3] respectively.Bin[0] is not covered.
Coverage report:
-------------------VARIABLE: cover_point_y
http://testbench.in/CO_07_COVERAGE_BINS.html[9/26/2012 2:14:32 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
Expected : 4
Covered : 3
Percent:75.00
Uncovered bins
-----------------auto[0:1]
Covered bins
-----------------auto[2:3]
auto[4:5]
auto[6:7]
Example of enum data type:

For Enum data type, the numbers of bins are equal to the number of elements of
enum data type. The bin identifiers are the enum member name.
typedefenum{A,B,C,D }alpha;
programmain;
alpha y;
alpha values[$]='{A,B,C};
covergroupcg;
cover_point_y :coverpointy;
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In The above example, the variable "y" is enum data type and it can have 4 enum
members A,B,C and D. Variable Y is assigned only 3 Enum members A,B and C.
Coverage report:
--------------------VARIABLE: cover_point_y
Expected : 4
Covered : 3
Percent:75.00
Uncovered bins
-------------------auto_D
Covered bins
-------------------auto_C
auto_B
auto_A
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Index
Introduction
Cover Group
SystemVerilog
Explicit bin creation is recommended method. Not all values are interesting or Sample
Verification
relevant in a cover point, so when the user knows the exact values he is going to Cover Points
Constructs
cover, he can use explicit bins. You can also name the bins.
Interface
Coverage Bins
OOPS
programmain;
Transition Bins
bit[0:2]y;
Randomization
Wildcard Bins
bit[0:2]values[$]='{3,5,6};
Functional Coverage
Ignore Bins
Illegal Bins
Assertion
covergroupcg;
Cross Coverage
cover_point_y
:coverpointy
{
DPI
Coverage Options
binsa ={0,1};
Coverage Methods
UVM Tutorial
binsb ={2,3};
System Tasks
binsc ={4,5};
VMM Tutorial
Cover Property
binsd ={6,7};
OVM Tutorial
}
Easy Labs : SV
endgroup
Easy Labs : UVM
input is what keeps
cg
cg_inst
=new();
Easy Labs : OVM
with time!
initial
Easy Labs : VMM
foreach(values[i])
begin
AVM Switch TB
y =values[i];
VMM Ethernet sample cg_inst.sample();
end
endprogram
Verilog
TUTORIALS
EXPLICIT BIN CREATION
Verification
Verilog Switch TB
In the above example, bins are created explicitly. The bins are named a,b,c and d.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Coverage report:
------------------VARIABLE: cover_point_y
Expected : 4
Covered : 3
Percent:75.00
RVM Ethernet sample Uncovered bins
-------------------a
Specman E
Interview Questions
Covered bins
-------------------b
c
d
Array Of Bins
To create a separate bin for each value (an array of bins) the square brackets, [],
must follow the bin name.
http://testbench.in/CO_08_EXPLICIT_BIN_CREATION.html[9/26/2012 2:14:40 PM]
programmain;
bit[0:2]y;
bit[0:2]values[$]='{3,5,6};
covergroupcg;
cover_point_y :coverpointy {
binsa[]={[0:7]};
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example, bin a is array of 8 bins and eachbin associates to one number
between 0 to 7.
Coverage report:
Expected : 8
Covered : 3
Percent:37.50
Uncovered bins
------------------a_0
a_1
a_2
a_4
a_7
Covered bins
------------------a_3
a_5
a_6
To create a fixed number of bins for a set of values, a number can be specified inside
the square brackets.
programmain;
bit[0:3]y;
bit[0:2]values[$]='{3,5,6};
covergroupcg;
binsa[4]={[0:7]};
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example, variable y is 4 bit width vector. Total possible values for this
vector are 16.
But in the cover point bins, we have giving the interested range as 0 to 7. So the
coverage report is calculated over the range 0 to 7 only.In this example, we have
shown the number bins to be fixed to size 4.
Coverage report:
Expected : 4
Covered : 3
Percent:75.00
Uncovered bins
------------------a[0:1]
Covered bins
-----------------a[2:3]
a[4:5]
a[6:7]
Default Bin
The default specification defines a bin that is associated with none of the defined
value bins. The default bin catches the values of the coverage point that do not lie
within any of the defined bins. However, the coverage calculation for a coverage
point shall not take into account the coverage captured by the default bin.
programmain;
bit[0:3]y;
bit[0:2]values[$]='{3,5,6};
covergroupcg;
binsa[2]={[0:4]};
binsd=default;
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example, we have specified only 2 bins to cover values from 0 to 4. Rest
of values are covered in default bin <93>d<94> whichis not using in calculating the
coverage percentage.
Coverage report:
Expected : 2
Covered : 1
Percent:50.00
Uncovered bins
-----------------a[0:1]
Covered bins
---------------a[2:4]
Defaultbin
----------------d
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Index
Introduction
Transitional functional point bin is used to examine the legal transitions of a value. Cover Group
SystemVerilog allows to specifies one or more sets of ordered value transitions of the Sample
Cover Points
coverage point.
Type of Transitions:
Coverage Bins
Single Value Transition
Transition Bins
Sequence Of Transitions
Wildcard Bins
Set Of Transitions
Ignore Bins
Consecutive Repetitions
Illegal Bins
Range Of Repetition
Cross Coverage
Coverage Options
Goto Repetition
Coverage Methods
Non Consecutive Repetition
System Tasks
Cover Property
TRANSITION BINS
Single Value Transition

Single value transition is specified as:
value1 =>value2
programmain;
bit[0:3]y;
VMM Ethernet sample bit[0:2]values[$]='{3,5,6};
covergroupcg;
Verilog
binstran_34 =(3=>4);
Verification
binstran_56 =(5=>6);
Verilog Switch TB
}
Basic Constructs
endgroup
cg cg_inst =new();
OpenVera
initial
Constructs
foreach(values[i])
begin
Switch TB
y =values[i];
RVM Switch TB
cg_inst.sample();
endprogram
AVM Switch TB
Specman E
Interview Questions
In the above example, 2 bins are created for covering the transition of point "y" from
3 to 4 and other for 5 to 6.The variable y is given the values and only the transition
5 to 6 is occurring.
Coverage report:
Expected : 2
Covered : 1
Percent:50.00
http://testbench.in/CO_09_TRANSITION_BINS.html[9/26/2012 2:14:49 PM]

input is what keeps
with time!
Uncovered bins
-----------------tran_34
Covered bins
---------------tran_56
Sequence Of Transitions
A sequence of transitions is represented as:
value1 => value3 => value4 => value5
In this case, value1 is followed by value3, followed by value4 and followed by value5.
A sequence can be
of any arbitrary length.
programmain;
bit[0:3]y;
bit[0:2]values[$]='{3,5,6};
covergroupcg;
binstran_345 =(3=>4>=5);
binstran_356 =(3=>5=>6);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example, 2 bins re created for covering the transition of point "y" from 3
to 4 to 5 and other for3 to 5 to 6.The variable y is given the values and only the
transition 3 to 5 to 6 is occurring.
Coverage report:
Expected : 2
Covered : 1
Percent:50.00
Uncovered bins
-----------------tran_345
Covered bins
----------------tran_356
Set Of Transitions
A set of transitions can be specified as:
range_list1 => range_list2

programmain;
bit[0:3]y;
bit[0:2]values[$]='{3,5,6};
covergroupcg;
binstrans[]=(3,4=>5,6);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example, bin trans creates 4 bin for covering 3=>5,4=>5,3=>6 and 4=>6.
Coverage report:
Expected : 4
Covered : 1
Percent:25.00
Uncovered bins
-----------------tran_34_to_56:3->6
tran_34_to_56:4->5
tran_34_to_56:4->6
Covered bins
---------------tran_34_to_56:3->5
Consecutive Repetitions
Consecutive repetitions of transitions are specified using
trans_item [* repeat_range ]
Here, trans_item is repeated for repeat_range times. For example,
3 [* 5]
is the same as
3=>3=>3=>3=>3
programmain;
bit[0:3]y;
bit[0:2]values[$]='{3,3,3,4,4};
covergroupcg;
binstrans_3 =(3[*5]);
binstrans_4 =(4[*2]);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
Coverage report:
Expected : 2
Covered : 1
Percent:50.00
Uncovered bins
-----------------trans_3
Covered bins
---------------trans_4
Range Of Repetition
An example of a range of repetition is:
3 [* 3:5]
is the same as
3=>3=>3, 3=>3=>3=>3, 3=>3=>3=>3=>3
programmain;
bit[0:3]y;
bit[0:2]values[$]='{4,5,3,3,3,3,6,7};
covergroupcg;
binstrans_3[]=(3[*3:5]);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
In the above example,only the sequence 3=>3=>3=>3 isgenerated. Other expected
sequences 3=>3=>3 and 3=>3=>3=>3=>3 are not generated.
Coverage report:
Expected : 3
Covered : 1
Percent:33.33
Uncovered bins
-----------------tran_3:3[*3]
tran_3:3[*5]
Covered bins
---------------tran_3:3[*4]
Goto Repetition
The goto repetition is specified using: trans_item [-> repeat_range]. The required
number of occurrences of a particular value is specified by the repeat_range. Any
number of sample points can occur before the first occurrence of the specified value
and any number of sample points can occur between each occurrence of the specified
value. The transition following the goto repetition must immediately follow the last
occurrence of the repetition.
For example:
3 [-> 3]
is the same as
...=>3...=>3...=>3
where the dots (...) represent any transition that does not contain the value 3.
A goto repetition followed by an additional value is represented as follows:
1 => 3 [ -> 3] => 5
is the same as
1...=>3...=>3...=>3 =>5
programmain;
bit[0:3]y;
bit[0:2]values[$]='{1,6,3,6,3,6,3,5};
covergroupcg;
binstrans_3 =(1=>3[->3]=>5);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
Coverage report:
Expected : 1
Covered : 1
Percent:100.00
Non Consecutive Repetition
The nonconsecutive repetition is specified using: trans_item [= repeat_range]. The
required number of occurrences of a particular value is specified by the repeat_range.
Any number of sample points can occur before the first occurrence of the specified
value and any number of sample points can occur between each occurrence of the
specified value. The transition following the nonconsecutive repetition may occur
after any number of sample points so long as the repetition value does not occur
again.
For example:
3 [= 2]
is same as
...=>3...=>3
A nonconsecutive repetition followed by an additional value is represented as follows:
1 => 3 [=2] => 5
is the same as
1...=>3...=>3...=>5
programmain;
bit[0:3]y;
bit[0:2]values[$]='{1,6,3,6,3,6,5};
covergroupcg;
binstrans_3 =(1=>3[=2]=>5);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
Coverage report:
Expected : 1
Covered : 1
Percent:100.00
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Index
Introduction
Cover Group
SystemVerilog
Sample
By default, a value or transition bin definition can specify 4-state values.
Verification
When a bin definition includes an X or Z, it indicates that the bin count should only be Cover Points
Constructs
incremented when the sampled value has an X or Z in the same bit positions.
The wildcard bins definition causes all X, Z, or ? to be treated as wildcards for 0 or 1 Generic Coverage Groups
Interface
Coverage Bins
(similar to the ==? operator).
OOPS
For example:
Transition Bins
Randomization
Wildcard Bins
wildcardbinsg12_16 ={4'b11??};
Functional Coverage
Ignore Bins
Assertion
The count of bin g12_16 is incremented when the sampled variable is between 12 and Illegal Bins
Cross Coverage
16:
DPI
Coverage Options
Coverage Methods
UVM Tutorial
1100110111101111
System Tasks
VMM Tutorial
Cover Property
programmain;
OVM Tutorial
reg[0:3]y;
reg[0:3]values[$]='{4'b1100,4'b1101,4'b1110,4'b1111};
Easy Labs : SV
Easy Labs : UVM

input is what keeps
covergroupcg;
cover_point_y
:coverpointy
{
Easy Labs : OVM
with time!
wildcardbinsg12_15 ={4'b11??};
Easy Labs : VMM
}
AVM Switch TB
endgroup
VMM Ethernet sample
cg cg_inst =new();
initial
foreach(values[i])
Verilog
begin
Verification
y =values[i];
Verilog Switch TB
cg_inst.sample();
end
Basic Constructs
endprogram
TUTORIALS
WILDCARD BINS
OpenVera
Coverage report:
Switch TB
Expected : 1
RVM Switch TB
Covered : 1
RVM Ethernet sample Percent:100.00
Constructs
Specman E
Interview Questions
Covered bin
--------------g12_15
Number of times g12_15 hit : 4
Similarly, transition bins can define wildcard bins.

For example:
wildcardbinsT0_3=(2'b0x=>2'b1x);
The count of transition bin T0_3 is incremented for the following transitions (as if by
http://testbench.in/CO_10_WILDCARD_BINS.html[9/26/2012 2:14:57 PM]
(0,1=>2,3)):
00=>10,00=>11,01=>10,01=>11
programmain;
reg[0:1]y;
reg[0:1]values[$]='{2'b00,2'b01,2'b10,2'b11};
covergroupcg;
wildcardbinstrans =(2'b0X=>2'b1X);
}
endgroup
cg cg_inst =new();
initial
foreach(values[i])
begin
y =values[i];
cg_inst.sample();
end
endprogram
Coverage report:
Expected : 1
Covered : 1
Percent:100.00
Covered bin
--------------trans
Number of times trans hit : 1(01 => 10)
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Introduction
A set of values or transitions associated with a coverage-point can be explicitly Cover Group
Sample
excluded from coverage by specifying them as ignore_bins.
Cover Points
programmain;
Coverage Bins
bit[0:2]y;
bit[0:2]values[$]='{1,6,3,7,3,4,3,5};
Transition Bins
Wildcard Bins
covergroupcg;
Ignore Bins
Illegal Bins
ignore_binsig ={1,2,3,4,5};
Cross Coverage
}
Coverage Options
Coverage Methods
endgroup
System Tasks
Cover Property
cg cg_inst =new();
initial
foreach(values[i])
begin
input is what keeps
y =values[i];
cg_inst.sample();
with time!
end
endprogram
IGNORE BINS
VMM Ethernet sample In the above program,total possible values for y are 0 to 7.Ignore_bins specified to
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Ignored values between 1 to 5. So the Expected values are 0,6 and 7. Out of these
expected values, only 6 and 7 are generated.
Coverage report:
Expected : 3
Covered : 2
Percent:66.66
Uncovered bins
-----------------auto[0]
Excluded/Illegal bins
------------------------ig
auto[1]
auto[2]
auto[3]
auto[4]
auto[5]
Covered bins
---------------auto[6]
auto[7]
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Index
Introduction
SystemVerilog
A set of values or transitions associated with a coverage-point can be marked as Cover Group
illegal by specifying them as illegal_bins.All values or transitions associated with Sample
Verification
illegal bins are excluded from coverage. If an illegal value or transition occurs, a Cover Points
Constructs
runtime error is issued.
Interface
Coverage Bins
OOPS
programmain;
Transition Bins
bit[0:2]y;
Randomization
Wildcard Bins
bit[0:2]values[$]='{1,6,3,7,3,4,3,5};
Functional Coverage
Ignore Bins
Illegal Bins
Assertion
covergroupcg;
Cross Coverage
cover_point_y
:coverpointy
{
DPI
Coverage Options
illegal_binsib ={7};
Coverage Methods
UVM Tutorial
}
System Tasks
VMM Tutorial
Cover Property
endgroup
OVM Tutorial

cg cg_inst =new();
Easy Labs : SV
initial
Easy Labs : UVM
input is what keeps
foreach(values[i])
begin
Easy Labs : OVM
with time!
y =values[i];
Easy Labs : VMM
cg_inst.sample();
end
AVM Switch TB
VMM Ethernet sample endprogram

TUTORIALS
Verilog
Verification
Verilog Switch TB
ILLEGAL BINS
Result:
-----------** ERROR **
Illegal state bin ib of coverpoint cover_point_y in
covergroup cg got hit with value 0x7
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
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Index
Introduction
SystemVerilog
Cross allows keeping track of information which is received simultaneous on more Cover Group
Sample
than one cover point. Cross coverage is specified using the cross construct.
Verification
Cover Points
Constructs
programmain;
Interface
Coverage Bins
bit[0:1]y;
OOPS
bit[0:1]y_values[$]='{1,3};
Transition Bins
Randomization
Wildcard Bins
bit[0:1]z;
Functional Coverage
Ignore Bins
bit[0:1]z_values[$]='{1,2};
Illegal Bins
Assertion
Cross Coverage
covergroupcg;
DPI
Coverage Options
cover_point_y :coverpointy ;
Coverage Methods
UVM Tutorial
cover_point_z :coverpointz ;
System Tasks
cross_yz :crosscover_point_y,cover_point_z ;
VMM Tutorial
Cover Property
endgroup
OVM Tutorial

cg cg_inst =new();
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initial
Easy Labs : UVM
input is what keeps
foreach(y_values[i])
begin
Easy Labs : OVM
with time!
y =y_values[i];
Easy Labs : VMM
z =z_values[i];
cg_inst.sample();
AVM Switch TB
end
VMM Ethernet sample
endprogram
TUTORIALS
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
CROSS COVERAGE
In the above program, y has can have 4 values 0,1,2 and 3 and similarly z can have 4
values 0,1,2 and 3. The cross product of the y and z will be 16 values
(00),(01),(02),(03),(10),(11)........(y,z)......(3,2)(3,3) .
Only combinations (11) and (32) are generated.
Cross coverage report:cover points are not shown.
Constructs
Covered bins
----------------cover_point_y cover_point_z
RVM Switch TB
auto[3]auto[2]
RVM Ethernet sample auto[1]auto[1]
Switch TB
Specman E
Interview Questions
User-Defined Cross Bins

User-defined bins for cross coverage are defined using bin select expressions.
Consider the following example code:
inti,j;
covergroupct;
coverpointi {binsi[]={[0:1]};}
coverpointj {binsj[]={[0:1]};}
x1:crossi,j;
x2:crossi,j {
http://testbench.in/CO_13_CROSS_COVERAGE.html[9/26/2012 2:15:22 PM]
binsi_zero =binsof(i)intersect{0};
}
endgroup
Cross x1 has the following bins:
<i[0],j[0]>
<i[1],j[0]>
<i[0],j[1]>
<i[1],j[1]>
Cross x2 has the following bins:
i_zero
<i[1],j[0]>
<i[1],j[1]>
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
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Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Index
Introduction
Cover Group
Options control the behavior of the covergroup, coverpoint, and cross.
Sample
There are two types of options:
Cover Points
those that are specific to an instance of a covergroup and
those that specify an option for the covergroup type as a whole.
Coverage Bins
Transition Bins
Weight
Wildcard Bins
Ignore Bins
Syntax : weight= number
Illegal Bins
default value: 1
Cross Coverage
Coverage Options
Description :
Coverage Methods
If set at the covergroup syntactic level, it specifies the weight of this covergroup System Tasks
instance for computing the overall instance coverage of the simulation. If set at the Cover Property
coverpoint (or cross) syntactic level, it specifies the weight of a coverpoint (or cross)
for computing the instance coverage of the enclosing covergroup.The specified
weight shall be a non-negative integral value.
COVERAGE OPTIONS
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Goal
Syntax :goal=number
default value: 100
Description :
Specifies the target goal for a covergroup instance or for a coverpoint or a cross of an
instance.
Name
Syntax :name=string
default value:unique name
Description :
Specifies a name for the covergroup instance. If unspecified, a unique name for each
instance is automatically generated by the tool.
Comment
Syntax :comment=string
default value: ""
Description :
A comment that appears with a covergroup instance or with a coverpoint or cross of
the covergroup instance. The comment is saved in the coverage database and included
in the coverage report.
At_least
Syntax :at_least=number
default value: 1
Description :
http://testbench.in/CO_14_COVERAGE_OPTIONS.html[9/26/2012 2:15:33 PM]

input is what keeps
with time!
Minimum number of hits for each bin. A bin with a hit count that is less than number
is not considered covered.
Detect_overlap
Syntax :detect_overlap=Boolean
default value:0
Description :
When true, a warning is issued if there is an overlap between the range list (or
transition list) of two bins of a coverpoint.
Auto_bin_max
Syntax :auto_bin_max=number
default value:64
Description :
Maximum number of automatically created bins when no bins are explicitly defined
for a coverpoint.
Cross_num_print_missing
Syntax :cross_num_print_missing=number
default value: 0
Description :
Number of missing (not covered) cross product bins that shall be saved to the
coverage database and printed in the coverage report.
Per_instance
Syntax :per_instance=Boolean
default value: 0
Description :
Each instance contributes to the overall coverage information for the covergroup
type. When true, coverage information for this covergroup instance shall be saved in
the coverage database and included in the coverage report. When false,
implementations are not required to save instance-specific information.
Get_inst_coverage
Syntax :get_inst_coverage=Boolean
default value:0
Description :
Only applies when the merge_instances type option is set . Enables the tracking of
per instance coverage with the get_inst_coverage built-in method. When false, the
value returned by get_inst_coverage shall equal the value returned by get_coverage
Following Table summarizes the syntactical level (covergroup, coverpoint, or cross) in
which type options can be specified.
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COVERAGE METHODS
SystemVerilog
The following coverage methods are provided for the covergroup. These methods can
be invoked procedurally at any time.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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void sample():
Description : Triggers sampling of the covergroup
real get_coverage()
real get_coverage(ref int, ref int)
Description : Calculates type coverage number (0...100)
The get_coverage() method returns the cumulative (or type) coverage, which
considers the contribution of all instances of a particular coverage item. and it is a
static method that is available on both types (via the :: operator) and instances (using
the "." operator).
The get_coverage()method both accept an optional set of arguments, a pair of int
values passed by reference. When the optional arguments are specified, the
get_coverage() method assign to the first argument the value of the covered bins, and
to the second argument the number of bins for the given coverage item. These two
values correspond to the numerator and the denominator used for calculating the
particular coverage number (i.e., the return value before scaling by 100).
Easy Labs : VMM
real get_inst_coverage()
real get_inst_coverage(ref int, ref int)
VMM Ethernet sample Description : Calculates the coverage number (0...100)
get_inst_coverage() method returns the coverage of the specific instance on which it
is invoked, thus, it can only be invoked via the "." operator.
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
The get_inst_coverage() method both accept an optional set of arguments, a pair of

int values passed by reference. When the optional arguments are specified, the
get_inst_coverage() method assign to the first argument the value of the covered bins,
and to the second argument the number of bins for the given coverage item. These
two values correspond to the numerator and the denominator used for calculating the
particular coverage number (i.e., the return value before scaling by 100).
void set_inst_name(string)
Description : Sets the instance name to the given string
void start()
Description : Starts collecting coverage information
void stop()
Description : Stops collecting coverage information
Specman E
Interview Questions
http://testbench.in/CO_15_COVERAGE_METHODS.html[9/26/2012 2:15:42 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
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TUTORIALS
SYSTEM TASKS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
SystemVerilog provides the following system tasks and functions to help manage
coverage data collection.
$set_coverage_db_name ( name ) :
Sets the filename of the coverage database into which coverage information is saved
at the end of a simulation run.
$load_coverage_db ( name ) :
Load from the given filename the cumulative coverage information for all coverage
group types.
$get_coverage ( ) :
Returns as a real number in the range 0 to 100 the overall coverage of all coverage
group types. This number is computed as described above.
OVM Tutorial
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Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CO_16_SYSTEM_TASKS.html[9/26/2012 2:15:49 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
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TUTORIALS
COVER PROPERTY
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Cover statement can be used to monitor sequences and other behavioral aspects of
the design. The tools can gather information about the evaluation and report the
results at the end of simulation. When the property for the cover statement is
successful, the pass statements can specify a coverage function, such as monitoring
all paths for a sequence. The pass statement shall not include any concurrent assert,
assume or cover statement. A cover property creates a single cover point.
Coverage results are divided into two: coverage for properties, coverage for
sequences.
For sequence coverage, the statement appears as:
Cover property ( sequence_expr ) statement_or_null
VMM Tutorial
Cover Property Results
OVM Tutorial
The results of coverage statement for a property shall contain:

Number of times attempted
Number of times succeeded
Number of times failed
Number of times succeeded because of vacuity
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AVM Switch TB
In addition, statement_or_null is executed every time a property succeeds.
VMM Ethernet sample Vacuity rules are applied only when implication operator is used. A property succeeds
non-vacuously only if the consequent of the implication contributes to the success.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Cover Sequence Results

Results of coverage for a sequence shall include:
Number of times attempted
Number of times matched (each attempt can generate multiple matches)
In addition, statement_or_null gets executed for every match. If there are multiple
matches at the same time, the statement gets executed multiple times, one for each
match.
It is recommended to cover sequences and not properties and its easy to convert a
property into a sequence if required.
RVM Ethernet sample
Coverage property can be declared in

Specman E
Interview Questions
A design or a separate module

Packages
Interfaces
Program block
Cover properties are not allowed inclass.
Comparison Of Cover Property And Cover Group.
Cover groups can reference data sets where as cover property references a temporal
expression.
http://testbench.in/CO_17_COVER_PROPERTY.html[9/26/2012 2:15:58 PM]
Index
Introduction
Cover Group
Sample
Cover Points
Coverage Bins
Transition Bins
Wildcard Bins
Ignore Bins
Illegal Bins
Cross Coverage
Coverage Options
Coverage Methods
System Tasks
Cover Property
input is what keeps
with time!
Cover group can be triggered using .sample method ()

Cover property dont have this option.
Cover group has multiple bins options.
Cover property has only one bin.
Cover group cannot handle complex temporal relationships.
Cover properties can cover complex temporal expressions.
Cover group automatically handles the crosses.
Cover properties cannot do crosses.
Cover group has lot of filtering options.
Cover property has no specific filtering constructs but it can be filtered.
Cover properties cannot be used in classes.
Cover groups can be used in classes. So, cover groups can reference the variables in
class.
Cover groups are most useful at a higher level of abstractions where as cover property
makes sense to use when we want to work at low level signals.
We can mix cover group and cover property to gain the OO and temporal advantages.
Using properties for temporal expressions and trigger the cover group.
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TUTORIALS
INTRODUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
SystemVerilog adds features to specify assertions of a system. An assertion specifies a

behavior of the system. Assertions are primarily used to validate the behavior of a
design. In addition, assertions can be used to provide functional coverage and
generate input stimulus for validation.
The evaluation of the assertions is guaranteed to be equivalent between simulation,
which is event-based, and formal verification, which is cycle-based.
SystemVerilog allows assertions to communicate information to the test bench and Report a Bug or Comment
allows the test bench to react to the status of assertions without requiring a separate on This section - Your
input is what keeps
application programming interface (API) of any kind
with time!
VMM Tutorial
Advantages Of Assertion:
OVM Tutorial
Improving Observability.
Reduces the debug time.
Bugs can be found earlier and are more isolated.
Controllable severity level.
Can interact with C functions.
Describe the Documentation and Specification of the design.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Index
Introduction
Event Simulation
Assertion Types
Layers
Sequences
Properties
What Assertions Can Verify:

Assertions can be used to capture the information about various level of properties.
conceptual : can be used to verify systemlevel properties which are more
architectural level.
design : These expresses unit level properties.
programming: More specified at RTL level.
1)conditional: It checks the some conditinal to be true using boolean expressions.
2)sequence : Checks whether the properties arr true using temporal expression.
3)signal : Checks on signal types.
a)x detection :Can be used to detect unconnected ports or undriven signal.
b)encoding types: Checks whether the encoding is violated.
1)onehot
2)gray code
RVM Switch TB
RVM Ethernet sample
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Interview Questions
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
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Index
Introduction
Event Simulation
The Problem of race condition exists if the SVA is sampling the signals exactly at Assertion Types
specified event. So in SystemVerilog , the language has very clear semantics to avoid Assertion System Tasks
race condition while evaluating SVA.
Layers
Sequences
Properties
EVENT SIMULATION
Functional Coverage

input is what keeps
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Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
In SV, a new region is added before Active region called preponed.So sampling for
SVA is done in preponed region. No assignments are not done in preponed region.
RVM Ethernet sample Signals are stable from previous timeslot and they are occurring before active and
NBA ,so the race condition is avoided by this new preponed region. Look at the
diagram, regions which are in light cyan color are for SVA.
Specman E
IN preponed region only sampling is done , the evaluation of these sampled values are
Interview Questions
done in another region called observed region. Observed region occurs after NBA
region. Even though the assignments are done in active ,inactive,NBA region, these
updates are not used in observed region. Only signals sample in preponed region are
used in observed region. Observed region occurs before reactive region where the
testbench executes.
RVM Switch TB
But in immediate assertions, the updated values in previous regions of current time
slot are used in observed region.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Index
Introduction
Event Simulation
Assertion Types
There are two types of assertions.
Immediate assertions are useful for checking combinational expression. These are Assertion System Tasks
similar to if and else statement but with assertion control. Immediate assertions Concurrent Assertion
follow simulation event semantics for their execution and are executed like a Layers
Sequences
statement in a procedural block.
Properties
ASSERTION TYPES
Functional Coverage

input is what keeps
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Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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AVM Switch TB
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Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
EXAMPLE:
timet;
always@(posedgeclk)
if(state ==REQ)
assert(req1 ||req2);
elsebegin
t =$time;
#5$error("assert failed at time %0t",t);
end
RVM Ethernet sample
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Interface
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Assertion
DPI
Index
Introduction
Event Simulation
Because the assertion is a statement that something must be true, the failure of an Assertion Types
assertion shall have a
severity associated with it. By default, the severity of an assertion failure is error. Concurrent Assertion
Layers
Other severity levels can
be specified by including one of the following severity system tasks in the fail Sequences
Properties
statement:
$fatal is a run-time fatal.
$error is a run-time error.
$warning is a run-time warning, which can be suppressed in a tool-specific manner.
input is what keeps
$info indicates that the assertion failure carries no specific severity.
ASSERTION SYSTEM TASKS
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Assertion Control System Tasks:
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SystemVerilog provides three system tasks to control assertions.
Easy Labs : UVM
$assertoff shall stop the checking of all specified assertions until a subsequent
$asserton. An assertion that is already executing, including execution of the pass or
fail statement, is not affected.
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
$assertkill shall abort execution of any currently executing specified assertions and
then stop the checking of all specified assertions until a subsequent $asserton.
$asserton shall reenable the execution of all specified assertions. When invoked with
no arguments, the system task shall apply to all assertions. When the task is specified
with arguments, the first argument indicates levels of the hierarchy, consistent with
the corresponding argument to the Verilog $dumpvars system task. Subsequent
arguments specify which scopes of the model to control. These arguments can specify
entire modules or individual assertions.
Basic Constructs
OpenVera
Boolean System Function:
Constructs
$countones : Returns the numbers of 1's in a bit vector.

$past: Returns the values of the past.
$stable: If the Signal is stable, then it returns 1.
RVM Switch TB
$isunknown : If th X is seen in expression , then it returns 1.
RVM Ethernet sample $rose: returns true if the LSB of the expression changed to 1. Otherwise, it
returns false.
$fell: returns true if the LSB of the expression changed to 0. Otherwise, it returns
false.
Specman E
$onehot: returns true if only 1 bit of the expression is high.
$onehot0 : returns true if at most 1 bit of the expression is high.
Interview Questions
Switch TB
What is the difference between $rose and posedge?

posedge returns event where as $rose returns a boolean value. Events cannot be used
in expression, $rose can be used.
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SystemVerilog
Verification
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Assertion
Index
Introduction
Event Simulation
behavior that spans over time. Unlike immediate Assertion Types
is based on a clock so that a concurrent assertion is Assertion System Tasks
of a clock tick.
Layers
Sequences
assertions. They are
Properties
CONCURRENT ASSERTION LAYERS

Concurrent assertions describe
assertions, the evaluation model
evaluated only at the occurrence
There are 4 layers inconcurrent
Boolean expressions.
Sequence expression.
Property declaration.
Verification directives.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
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Interview Questions
These layering concept allows to build hierarchical constructs so its easy to maintain
them.
Boolean Expressions:
Boolean expression doesn't consume time. The result of the expression is 1,0,x & z. If
the result is 1, then the expression is true , else if the expression is 0,x or z , it is
false. Concurrent assertions use boolean expressions along with temporal expressions.
Immediate assertions use only boolean expressions.
Integral data types such as int,integer,reg,bit,byte,logic,array( elements
only),structs,function return values are allowed in boolean expressions. Complex data
types like classes,smart quesus, dynamic arrays, associative arrays are not allowed.
http://testbench.in/AS_05_CONCURRENT_ASSERTION_LAYERS.html[9/26/2012 2:16:39 PM]

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TUTORIALS
SEQUENCES
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Boolean logic doenot have the concept of time. Temporal logic is boolean logic with
time as one more dimention. Sequence allows us to define temporal nature of the
signals using temporal expressions.
Sequences can be composed by concatenation, analogous to a concatenation of lists.
The concatenation specifies a delay, using ##, from the end of the first sequence until
the beginning of the second sequence.
## indicates cycle delay.
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Fixed Delay:
A ## followed by a number specifies the delay from the current clock tick to the
beginning of the sequence that follows.
EXAMPLE:
req ##2gnt
This specifies that req shall be true on the current clock tick, and gnt shall be true on
the second subsequent clock tick
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Zero Delay:
The delay ##0 indicates that the beginning of the second sequence is at the same
clock tick as the end of the first sequence. This can also be archived using boolean
expressions && .
RVM Ethernet sample EXAMPLE:
sig1 ##0sig2
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This specifies that sig1 shall be true on the current clock tick, and sig2 shall be true
on the same clock tick.
http://testbench.in/AS_06_SEQUENCES.html[9/26/2012 2:16:48 PM]
Index
Introduction
Event Simulation
Assertion Types
Layers
Sequences
Properties
input is what keeps
with time!
Constant Range Delay:

A ##[n:m] followed by a range specifies the delay from the current clock tick to the
beginning of the sequence that follows.
EXAMPLE:
req ##[2:5]ack
This specifies that ack shall be true ,2-5 cycles after req. It creates multiple
subsequence threads. This resulst in multiple hits or fails.
Sub sequences created by range delay in above expressions:
req ##2 ack
req ##3 ack
req ##4 ack
req ##5 ack
Unbounded Delay Range:

The $ token is used to indicate the end of simulation.
##[n:$] specifies that delay from between n cycles later and till the end of
simulation.
EXAMPLE:
req##[4:$]ack;
This specifies that ack must be true atleast 4 cycles later .
Repetation Operators:
The number of iterations of a repetition can either be specified by exact count or be
required to fall within a finite range. If specified by exact count, then the number of
iterations is defined by a non-negative integer constant expression. If required to fall
within a finite range, then the minimum number of iterations is defined by a nonnegative integer constant expression; and the maximum number of iterations either is
defined by a non-negative integer constant expression or is $, indicating a finite, but
unbounded, maximum.
Consecutive Repetition:
Consecutive repetition specifies finitely many iterative matches of the operand
sequence, with a delay of one clock tick from the end of one match to the beginning
of the next. The overall repetition sequence matches at the end of the last iterative
match of the operand.
EXAMPLE:
REQ[*4]
This example specifies that ack shell come after req comes 4 times consecutively.
Goto Repetition :
Goto repetition specifies finitely many iterative matches of the operand boolean
expression, with a delay of one or more clock ticks from one match of the operand to
the next successive match and no match of the operand strictly in between. The
overall repetition sequence matches at the last iterative match of the operand.
EXAMPLE:
req[->3]##1ack
This example specifies that ack shell come after req comes 3 times with no gap
between thw last req and ack.
Nonconsecutive Repetition:
Nonconsecutive repetition specifies finitely many iterative matches of the operand
boolean expression, with a delay of one or more clock ticks from one match
of the operand to the next successive match and no match of the operand strictly in
between. The overall repetition sequence matches at or after the last iterative match
of the operand, but before any later match of the operand.
EXAMPLE:
req[=3]##1ack
This example specifies that ack shell come after req comes 4 times with gap between
thw last req and ack.
Sequence And :
Sequence must start and can end at the any time. Match is done after last sequence is
ended.
EXAMPLE:
Seq1 andseq2
Sequence Or:
Sequence must start at the same time and can end at any time. Match is done at both
the sequences ends.
EXAMPLE:
seq1 orseq2
Sequence Intersect:
sequences must start at the same time and end at same tine. Match is done at the end
time.
EXAMPLE:
Seq1 intersectseq2
Sequence Within
One sequence can fully contain another sequence
EXAMPLE:
Seq1 withinseq2
Sequence First_match:
Matches only the first match and ignores other matches.
EXAMPLE:
first_match(seq1)
Sequence Throughout
The throughout operator requires a boolean to be true throughout a sequence.
EXAMPLE:
A throughoutseq1
Sequence Ended:
The end point of a sequence is reached whenever the ending clock tick of a match of
the sequence is reached, regardless of the starting lock tick of the match. The
reaching of the end point can be tested by using the method ended.
EXAMPLE:
sequencee1;
@(posedgesysclk)$rose(ready)##1proc1 ##1proc2 ;
endsequence
sequencerule;
@(posedgesysclk)reset ##1inst ##1e1.ended ##1branch_back;
endsequence
Operator Precedence Associativy:
Operator precedence and associativity are listed in the following Table . The highest
precedence is listed first.
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Index
Introduction
Event Simulation
A property defines a behavior of the design. A property can be used for verification as Assertion Types
an assumption, a checker, or a coverage specification.
Sequences are often used to construct properties. usage of sequences in properties Concurrent Assertion
Layers
brakes down the complexity. Sequence can be reused across various properties.
Sequences
Properties
A property can be declared in any of the following:
A module
An interface
A program
A clocking block
input is what keeps
A package
A compilation-unit scope
PROPERTIES
with time!
Properties constructs:
Disable iff
Implication (if ..else)
overlapping implication (|->)
Non overlapping implication(||->)
not
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AVM Switch TB
EXAMPLE:
VMM Ethernet sample propertyrule6_with_type(bitx,bity);
Verilog
##1x |-> ##[2:10]y;

//antecedent |-> consequent
endproperty
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
The left-hand operand sequence_expr is called the antecedent, while the right-hand
operand property_expr is called the consequent.
if antecedent is false, then consequent is not cared and property is considered as
vacuous success.
if antecedent is True and if consequent is false then property is considered as false.
if antecedent is True and if consequent is true then property is considered as true.
Switch TB
RVM Switch TB
RVM Ethernet sample
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Interview Questions
Overlap Implication:
Consequent expression is evaluated on the same clock of antecedent.
EXAMPLE:
a |->b
http://testbench.in/AS_07_PROPERTIES.html[9/26/2012 2:16:58 PM]
Non Overlapping Implication

Consequent expression is evaluated on the next clock of antecedent
EXAMPLE:
a ||->b
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Index
Introduction
Event Simulation
A property on its own is never evaluated for checking an expression. It must be used Assertion Types
within a verification statement for this to occur. A verification statement states the Assertion System Tasks
verification function to be performed on the property.
Layers
Sequences
The statement can be one of the following:
1)assert to specify the property as a checker to ensure that the property holds for the Properties
design
2)assume to specify the property as an assumption for the environment
3)cover to monitor the property evaluation for coverage
VERIFICATION DIRECTIVE
A concurrent assertion statement can be specified in any of the following:

1) An always block or initial block as a statement, wherever these blocks can appear
2) A module
3) An interface
4) A program
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AVM Switch TB
Assert:
The assert statement is used to enforce a property as a checker. When the property
for the assert statement is evaluated to be true, the pass statements of the action
block are executed. Otherwise, the fail statements of the action_block are executed.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE:
a1_assertion:assertproperty(@(posedgeclk)req inside{0,1});
propertyproto_assertion ;
@(posedgeclk)req |->req[*1:$]##0ack;
endproperty
Assume:
The environment must be constrained so that the properties that are assumed shall
hold. Like an assert property, an assumed property must be checked and reported if
it fails to hold. There is no requirement on the tools to report successes of the
assumed properties.
Switch TB
RVM Switch TB
EXAMPLE:
RVM Ethernet sample a1:assumeproperty(@(posedgeclk)req dist{0:=40,1:=60});
Specman E
Interview Questions
propertyproto ;
@(posedgeclk)req |->req[*1:$]##0ack;
endproperty
Cover Statement:
To monitor sequences and other behavioral aspects of the design for coverage, the
same syntax is used with the cover statement. The tools can gather information about
the evaluation and report the results at the end of simulation. When the property for
the cover statement is successful, the pass statements can specify a coverage
function, such as monitoring all paths for a sequence. The pass statement shall not
include any concurrent assert, assume, or cover statement.
Coverage results are divided into two categories: coverage for properties and
coverage for sequences.
http://testbench.in/AS_08_VERIFICATION_DIRECTIVE.html[9/26/2012 2:17:07 PM]

input is what keeps
with time!
Coverage for sequences:

Number of attempts
Number of matches
Multiple matches per attempt are all counted
Coverage for properties:
Number of attempts
Number of passes
Number of vacuous passes
Number of failures
Expect Statement:
The expect statement is a procedural blocking statement that allows waiting on a
property evaluation. The syntax of the expect statement accepts a named property or
a property declaration. The expect statement accepts the same syntax used to assert
a property. An expect statement causes the executing process to block until the given
property succeeds or fails. The statement following the expect is scheduled to
execute after processing the Observe region in which the property completes its
evaluation. When the property succeeds or fails, the process unblocks, and the
property stops being evaluated
EXAMPLE:
programtst;
initialbegin
#200ms;
expect(@(posedgeclk)a ##1b ##1c )else$error("expect failed");
ABC:...
end
endprogram
Binding:
To facilitate verification separate from design, it is possible to specify properties and
bind them to specific modules or instances. The following are some goals of providing
this feature:
It allows verification engineers to verify with minimum changes to the design code
and files.
It allows a convenient mechanism to attach verification intellectual Protocol (VIP) to
a module or an instance.
No semantic changes to the assertions are introduced due to this feature. It is
equivalent to writing properties external to a module, using hierarchical path names.
The bind directive can be specified in any of the following:
A module
An interface
A compilation-unit scope
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TUTORIALS
INTRODUCTIONS
SystemVerilog
What Is Dpi-C ?
Verification
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DPI
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From long time , Users have needes a simple way of communication to foreign
languages from verilog. VPI and PLI are not easy interfaces to Use . Users need
detailed knowledge of PLI and VPI even for a simple program. Most of the time, users
do not need the sophisticated capabilities of VPI and PLI. DPI also permits C/C++ code
to wait for Verilog events and C/C++ tasks and functions can be disabledfrom
SystemVerilog.
SystemVerilog introduces a new foreign language interface called the Direct
Programming Interface (DPI). The DPI provides a very simple, straightforward, and
efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI.
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie

DPI consists of two separate layers: the SystemVerilog layer and a foreign language input is what keeps
layer. Both sides of DPI-C are fully isolated. Which programming language is actually Testbench.in improving
used as the foreign language is transparent and irrelevant for the System-Verilog side with time!
DPI developed based on the donations from Synopsys "DirectC interface".
of this interface. Neither the SystemVerilog compiler nor the foreign language
compiler is required to analyze the source code in the others language. Different
programming languages can be used and supported with the same intact
SystemVerilog layer.
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DPI-C follows the principle of a black box: the specification and the implementation
of a component are clearly separated, and the actual implementation is transparent
to the rest of the system. Therefore, the actual programming language of the
VMM Ethernet sample implementation is also transparent, although this standard defines only C linkage
semantics. The separation between SystemVerilog code and the foreign language is
based on using functions as the natural encapsulation unit in SystemVerilog.
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/DP_01_INTRODUCTIONS.html[9/26/2012 2:17:14 PM]
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LAYERS
SystemVerilog
Two Layers Of Dpi-C
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DPI
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
DPI-C consists of two separate layers: the SystemVerilog layer and a foreign language
layer. The SystemVerilog layer does not depend on which programming language is
actually used as the foreign language. Although different programming languages can
be supported and used with the intact SystemVerilog layer, SystemVerilog defines a
foreign language layer only for the C programming language. Nevertheless,
SystemVerilog code shall look identical and its semantics shall be unchanged for any
foreign language layer.
Dpi-C Systemverilog Layer

The SystemVerilog side of DPI-C does not depend on the foreign programming input is what keeps
language. In particular, the actual function call protocol and argument passing Testbench.in improving
mechanisms used in the foreign language are transparent and irrelevant to with time!
SystemVerilog. SystemVerilog code shall look identical regardless of what code the
foreign side of the interface is using. The semantics of the SystemVerilog side of the
interface is independent from the foreign side of the interface.
The SystemVerilog DPI-C allows direct inter-language function calls between
SystemVerilog and any foreign programming language with a C function call protocol
and linking model:
Functions implemented in C and given import declarations in SystemVerilog can be
called from SystemVerilog; such functions are referred to as imported functions.
Functions implemented in SystemVerilog and specified in export declarations can

be called from C; such functions are referred to as exported functions.
Tasks implemented in SystemVerilog and specified in export declarations can be
called from C; such functions are referred to as exported tasks.
Functions implemented in C that can be called from SystemVerilog and can in turn
call exported tasks; such functions are referred to as imported tasks.
Constructs
Switch TB
RVM Switch TB
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
Dpi-C Foreign Language Layer

The foreign language layer of the interface (which is transparent to SystemVerilog)
RVM Ethernet sample shall specify how actual arguments are passed, how they can be accessed from the
foreign code, how SystemVerilog-specific data types (such as logic and packed) are
represented, and how they are translated to and from some predefined C-like types.
Specman E
Interview Questions
http://testbench.in/DP_02_LAYERS.html[9/26/2012 2:17:22 PM]
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TUTORIALS
IMPORT
SystemVerilog
Import Methods
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
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OVM Tutorial
Methods implemented in C and given import declarations in SystemVerilog can be

called from SystemVerilog, such methods are referred to as imported
methods.Imported tasks or functions are similar to SystemVerilog tasks or functions.
Imported tasks or functions can have zero or more formal input, output, and inout
arguments.
Imported tasks always return an int result as part of the DPI-C disable protocol and,
thus, are declared in foreign code as int functions. We will discusses about the DPI-C
disable protocol in following sections.
Imported functions can return a result or be defined as void functions.
The syntax import method:
import{"DPI"|"DPI-C"}[context|pure][c_identifier
=][function|task][function_identifier|task_identifier]([tf_port_list]);
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Steps To Write Import Metyhods
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In SV Code
Step1 : Import the C function
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
import"DPI-C"string_sv2c=taskstring_sv2c();
Step2 :Invoke the Importted C function
initial
begin
string_sv2c();
end
In C code:
Step3: Define the Imported function
voidstring_sv2c(){
printf(" C: Hellow from C ");
}
Full Example:
RVM Ethernet sample CODE: SV_file
Specman E
Interview Questions
programmain;
stringstr;
import"DPI-C"string_sv2c=taskstring_sv2c();
initial
begin
string_sv2c();
end
endprogram
CODE: C_file
#include"svdpi.h"
http://testbench.in/DP_03_IMPORT.html[9/26/2012 2:17:29 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
voidstring_sv2c(){
printf(" C: Hellow from C ");
}
RESULTS
C: Hellow from C
EXAMPLE: optional default arguments
Standard C Functions
Users can also call the standared C functions.
EXAMPLE:
import"DPI"functionchandlemalloc(intsize);
import"DPI"functionvoidfree(chandleptr);
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TUTORIALS
NAMING
SystemVerilog
Global Name
Verification
Constructs
Interface
OOPS
Randomization
Every task or function imported to SystemVerilog must eventually resolve to a global

symbol. Similarly, every task or function exported from SystemVerilog defines a global
symbol. Global names of imported and exported tasks and functions must be unique
(no overloading is allowed ) and shall follow C conventions for naming; specifically,
such names must start with a letter or underscore, and they can be followed by
alphanumeric characters or underscores.
Functional Coverage
Assertion
DPI
UVM Tutorial
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OVM Tutorial
EXAMPLE
export"DPI-C"foo_plus =function\foo+;// "foo+" exported as "foo_plus"
import"DPI-C"init_1 =functionvoid\init[1]();// "init_1" is a linkage name

input is what keeps
Local Name
If a global name is not explicitly given, it shall be the same as the SystemVerilog task with time!
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or function name.
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EXAMPLE:
export"DPI-C"functionfoo;
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Sv Keyword As Linkage Name
AVM Switch TB
If a C method is named same as the SystemVerilog Keyword, then use a leading
VMM Ethernet sample backslash ( \ ) character to create the linkage identifier.
Verilog
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
EXAMPLE:
import"DPI-C"\begin=functionvoid\init[2]();// "begin" is a linkage name
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/DP_04_NAMING.html[9/26/2012 2:17:37 PM]
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Assertion
Index
Introductions
Layers
Export Methods
Import
Methods implemented in SystemVerilog and specified in export declarations can be Naming
Export
called from C, such methods are referred to as exported methods.
Pure And Context
Data Types
Arrays
Steps To Write Export Methods
Passing Structs And
Unions
In SV Code :
Arguments Type
Setp1: Export the systemverilog function
Disablie
DPI
export"DPI-C"functionexport_func;
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EXPORT
Step2: Define the systemverilog function

functionvoidexport_func();
$display("SV: Hello from SV ");
endfunction
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In C code :
Step3: Export the Systemverilog function
AVM Switch TB
externvoidexport_func(void);
VMM Ethernet sample
Step4: Invoke the systemverilog function

Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
voidimport_func()
{
export_func();
}
Full Example:
Constructs
CODE: SV_file.sv
programmain;
RVM Switch TB
RVM Ethernet sample import"DPI-C"functionvoidimport_func();
$display("SV: Hello from SV ");
Specman E
endfunction
Interview Questions
initial
begin
import_func();
end
endprogram
Switch TB
CODE: C_file.c
#include"stdio.h"
http://testbench.in/DP_05_EXPORT.html[9/26/2012 2:17:44 PM]

input is what keeps
with time!
#include"vc_hdrs.h"
#include"svdpi.h"
voidimport_func()
{
export_func();
}
RESULTS:
SV: Hello from SV
Blocking Export Dpi Task
SV Dpi allows C to call a SystemVerilog method which consumes time.
CODE:SV_file.sv
programmain;
export"DPI-C"taskexport_task;
import"DPI-C"contexttaskimport_task();
taskexport_task();
$display("SV: Entered the export function . wait for some time : %0d
",$time);
#100;
$display("SV: After waiting %0d",$time);
endtask
initial
begin
$display("SV: Before calling import function %0d",$time);
import_task();
$display("SV: Aftercalling import function %0d",$time);
end
endprogram
CODE: C_file.c
externvoidexport_task();
voidimport_task()
{
printf(" C: Before calling export function\n");
export_task();
printf(" C: Aftercalling export function\n");
}
RESULTS
SV: Before calling import function 0
C: Before calling export function
SV: Entered the export function . wait for some time : 0
SV: After waiting 100
C: Aftercalling export function
SV: Aftercalling import function 100
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PURE AND CONTEXT
SystemVerilog
Pure Function
Verification
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OVM Tutorial
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A function whose result depends solely on the values of its input arguments and with
no side effects can be specified as pure. This can usually allow for more optimizations
and thus can result in improved simulation performance.
A pure function call can be safely eliminated if its result is not needed or if the
previous result for the same values of input arguments is available somehow and can
be reused without needing to recalculate. Only nonvoid functions with no output or
inout arguments can be specified as pure.
Specifically, a pure function is assumed not to directly or indirectly (i.e., by calling
other functions) perform the following:
Perform any file operations.
Read or write anything in the broadest possible meaning, including input/output,
environment variables, objects from the operating system or from the program or
other processes, shared memory, sockets, etc.
Access any persistent data, like global or static variables.
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Context Function
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Some DPI imported tasks or functions or other interface functions called from them
require that the context of their call be known. The SystemVerilog context of DPI
VMM Ethernet sample export tasks and functions must be known when they are called, including when they
are called by imports. When an import invokes the svSetScope utility prior to calling
the export, it sets the context explicitly. Otherwise, the context will be the context
of the instantiated scope where the import declaration is located.
Verilog
AVM Switch TB
Verification
CODE: SV_file_1.sv
modulemodule_1;
Basic Constructs
import"DPI-C"contextfunctionvoidimport_func();
OpenVera
module_2 instance_1();
Constructs
Switch TB
initial
import_func();
RVM Switch TB
RVM Ethernet sample functionvoidexport_func();

$display("SV: My scope is %m \n");
endfunction
Specman E
endmodule
Verilog Switch TB
Interview Questions
CODE: SV_file_2.sv
modulemodule_2;
import"DPI-C"contextfunctionvoidimport_func();
initial
import_func();
http://testbench.in/DP_06_PURE_AND_CONTEXT.html[9/26/2012 2:17:52 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
$display("SV: My Scope is %m \n");

endfunction
endmodule
CODE:C_file.c
#include"svdpi.h"
#include"stdio.h"
voidimport_func()
{
printf("
C:
Im
called
fronm
",svGetNameFromScope(svGetScope()));
export_func();
}
Scope
::
RESULTS
C: Im called fronm Scope :: module_1.instance_1
SV: My Scope is module_1.instance_1.export_func
C: Im called fronm Scope :: module_1
SV: My scope is module_1.export_func
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%s
\n\n
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TUTORIALS
DATA TYPES
SystemVerilog
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AVM Switch TB
The SystemVerilog DPI supports only SystemVerilog data types, which are the data
types that can cross the boundary between SystemVerilog and a foreign language in
both the direction. On the other hand, the data types used in C code shall be C types.
A value that is passed through the DPI is specified in SystemVerilog code as a value of
SystemVerilog data type, while the same value is declared C code as a value of C data
type. Therefore, a pair of matching type definitions is required to pass a value
through DPI, the SystemVerilog definition and the C definition.
The following SystemVerilog types are the only permitted types for formal arguments
of import and export tasks or functions:
void, byte, shortint, int, longint, real, shortreal, chandle, and string
Scalar values of type bit and logic
Packed arrays, structs, and unions composed of types bit and logic. Every packed
type is eventually equivalent to a packed one-dimensional array. On the foreign
language side of the DPI, all packed types are perceived as packed one-dimensional
arrays regardless of their declaration in the SystemVerilog code.
Enumeration types interpreted as the type associated with that enumeration
Types constructed from the supported types with the help of the constructs: struct
, union , Unpacked array , typedef
Mapping data types
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Passing Logic Datatype

The DPI defines the canonical representation of packed 2-state (type svBitVecVal) and
4-state arrays (type svBitVecVal). svLogicVecVal is fully equivalent to type
s_vpi_vecval, which is used to represent 4-state logic in VPI.
http://testbench.in/DP_07_DATA_TYPES.html[9/26/2012 2:18:00 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
CODE:SV_file.sv
programmain;
logica;
import"DPI"functionvoidshow(logica);
initialbegin
a =1'b0;
show(a);
a =1'b1;
show(a);
a =1'bX;
show(a);
a =1'bZ;
show(a);
end
endprogram
CODE: C_file.v
#include<stdio.h>
#include<svdpi.h>
voidshow(svLogic a){
if(a ==0)
printf(" a is 0 \n");
elseif(a ==1)
printf(" a is 1 \n");
elseif(a ==2)
printf(" a is x \n");
elseif(a ==3)
printf(" a is z \n");
}
RESULTS
a
a
a
a
is
is
is
is
0
1
z
x
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TUTORIALS
ARRAYS
SystemVerilog
Open Arrays
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
The size of the packed dimension, the unpacked dimension, or both dimensions can
remain unspecified,such cases are referred to as open arrays (or unsized arrays).
Open arrays allow the use of generic code to handle different sizes. Formal arguments
in SystemVerilog can be specified as open arrays solely in import declarations,
exported. SystemVerilog functions cannot have formal arguments specified as open
arrays.
OpenArrays are good for generic programming, since C language doesn't have concept
of parameterizable arguments. Standared query and library functions are provided to
determine array information to acess array elements.
VMM Tutorial
EXAMPLE: open arrays
OVM Tutorial
CODE:SV_file.sv
Easy Labs : SV
programmain;
intfxd_arr_1[8:3];
Easy Labs : OVM
intfxd_arr_2[12:1];
Easy Labs : VMM
import"DPI-C"contextfunctionvoidpass_array(inputintdyn_arr[]);
AVM Switch TB

begin
for(inti =3;i<=8;i++)
begin
Verilog
fxd_arr_1[i]=$random();
Verification
$display("SV:fxd_arr_1%0d %d ",i,fxd_arr_1[i]);
Verilog Switch TB
end
Basic Constructs
$display("\n Passing fxd_arr_1 to C \n");
pass_array(fxd_arr_1 );
OpenVera
for(inti =1;i<=12;i++)
Constructs
begin
fxd_arr_2[i]=$random();
Switch TB
$display("SV: fxd_arr_2 %0d %d ",i,fxd_arr_2[i]);
RVM Switch TB
end
RVM Ethernet sample
end
Specman E
endprogram
Easy Labs : UVM
Interview Questions
CODE: C_file.c
#include<stdio.h>
#include<svdpi.h>
voidpass_array(constsvOpenArrayHandle dyn_arr ){
inti;
printf("Array
Left
%d,
Array
\n\n",svLeft(dyn_arr,1),svRight(dyn_arr,1));
http://testbench.in/DP_08_ARRAYS.html[9/26/2012 2:18:08 PM]
Right
%d
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
for(i=svRight(dyn_arr,1);i <=svLeft(dyn_arr,1);i++){
printf("C: %d %d \n",i,*(int*)svGetArrElemPtr1(dyn_arr,i));
}
printf("\n\n");
}
RESULTS:
SV:fxd_arr_13 303379748
SV:fxd_arr_14 -1064739199
SV:fxd_arr_15 -2071669239
SV:fxd_arr_16 -1309649309
SV:fxd_arr_17 112818957
SV:fxd_arr_181189058957
Passing fxd_arr_1 to C
Array Left 8, Array Right 3
C:
C:
C:
C:
C:
C:
3
4
5
6
7
8
SV:
SV:
SV:
SV:
SV:
SV:
SV:
SV:
SV:
SV:
SV:
SV:
303379748
-1064739199
-2071669239
-1309649309
112818957
1189058957
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
fxd_arr_2
1 -1295874971
2 -1992863214
315983361
4 114806029
5 992211318
6 512609597
71993627629
81177417612
92097015289
10-482925370
11-487095099
12-720121174
C:
C:
C:
C:
C:
C:
C:
C:
C:
C:
C:
C:
1 -1295874971
2 -1992863214
3 15983361
4 114806029
5 992211318
6 512609597
7 1993627629
8 1177417612
9 2097015289
10 -482925370
11 -487095099
12 -720121174
Packed Arrays
A packed array is represented as an array of one or more elements (of type
svBitVecVal for 2-state values and svLogicVecVal for 4-state values), each element
representing a group of 32 bits.
CODE:SV_file.sv
programmain;
import"DPI-C"functionvoidget_nums(outputlogic[15:0]nums[10]);
logic[15:0]nums[10];
initialbegin
get_nums(nums);
foreach(nums[i])$display(i,nums[i]);
end
endprogram
CODE:C_file.c
#include"svdpi.h"
voidfib(svLogicVecVal nums[10]){
inti;
for(i=0;i<10;i++){
nums[i]=i ;
}
}
RESULTS:
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Linearized And Normalized

Arrays usenormalized ranges forthe packed[n-1:0]andthe unpacked part [0:n-1]
For example,ifSVcode defines an array as follows:
logic[2:3][1:3][2:0]b [1:10][31:0];
Then C code would see it as defined like this:
logic[17:0]b [0:9][0:31];
Array Querying Functions
svLeft() shall return the left bound (MSB) of the dimension.
svRight() shall return the right bound (LSB) of the dimension.
svLow() shall return the minimum of left index and right index of the dimension.
svHigh() shall return the maximum of left index and right index of the dimension.
svIncrement() shall return 1 if left index is greater than or equal to right index and
-1 if left index is less than right index.
svLength() shall return the number of elements in the dimension, which is
equivalent to high index - low index + 1.
svDimensions() shell returntotal number of dimensions in the array
CODE: SV_file.sv
programmain;
intfxd_arr_1[8:3];
intfxd_arr_2[1:13];
import"DPI-C"contextfunctionvoidpass_array(inputintdyn_arr[]);
initial
begin
end
endprogram
CODE: C_file.c
#include<stdio.h>
#include<svdpi.h>
voidpass_array(constsvOpenArrayHandle dyn_arr ){
printf("Array Pointer is %x \n",svGetArrayPtr(dyn_arr));
printf(" Lowerindex %d \n",svLow(dyn_arr,1));
printf(" Higher index %d \n",svHigh(dyn_arr,1));
printf(" Left index %d \n",svLeft(dyn_arr,1),svRight(dyn_arr,1));
printf(" Rightindex %d \n",svRight(dyn_arr,1));
printf(" Length of array %d \n",svLength(dyn_arr,1));
printf(" Incremental %d \n",svIncrement(dyn_arr,1));
printf("Dimentions of Array %d \n",svDimensions(dyn_arr ));
printf("Size of Array in bytes %d \n",svSizeOfArray(dyn_arr));
}
RESULTS:
Array Pointer is 80fdc58
Lowerindex 3
Higher index 8
Left index 8
Rightindex 3
Length of array 6
Incremental 1
Dimentions of Array 1
Size of Array in bytes 24
Array Pointer is 80fdc70
Lowerindex 1
Higher index 13
Left index 1
Rightindex 13
Length of array 13
Incremental -1
Dimentions of Array 1
Size of Array in bytes 52
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TUTORIALS
PASSING STRUCTS AND UNIONS
SystemVerilog
Passing Structure Example
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
DPI allows to pass the structs and Unions . This can be done by passing pointers or by
packing.
In the following example, a "struct" is passed from SystemVerilog to C and also from C
to Systemverilog using import and export functions.While passing the "struct" data
type, the data is packed in to array and passed from SV to C and then the array is
decoded back to Struct in C. The same when the Struct is passed from C to
SystemVerilog.
CODE: C_file.c
#include"stdio.h"
#include"vc_hdrs.h"
OVM Tutorial
#include"svdpi.h"
Easy Labs : SV
extern"C"{
Easy Labs : UVM
Easy Labs : OVM

typedefstruct{
Easy Labs : VMM
inta;
intb;
AVM Switch TB
char c;
VMM Ethernet sample
}C_struct;
externvoidexport_func(svBitVec32 x[3]);
Verilog
Verification
voidimport_func()
Verilog Switch TB
{
C_structs_data;
Basic Constructs
unsignedintarr[3];
s_data.a =51;
OpenVera
s_data.b =242;
Constructs
s_data.c =35;
Switch TB
printf("C : s_data.a = %d\n",s_data.a );
RVM Switch TB
printf("C : s_data.b = %d\n",s_data.b );
RVM Ethernet sample printf("C : s_data.c = %d\n\n",s_data.c );
arr[0]=s_data.a ;
arr[1]=s_data.b ;
Specman E
arr[2]=s_data.c ;
Interview Questions
export_func(arr);
}
}
CODE: SV_file.sv
programmain;
VMM Tutorial
http://testbench.in/DP_09_PASSING_STRUCTS_AND_UNIONS.html[9/26/2012 2:18:17 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
import"DPI-C"functionvoidimport_func();
typedefstructpacked{
inta;
intb;
bytec;
}SV_struct;
functionvoidexport_func(inputintarr[3]);
SV_struct s_data;
s_data.a =arr[0];
s_data.b =arr[1];
s_data.c =arr[2];
$display("SV: s_data.a = %0d",s_data.a );

$display("SV: s_data.b = %0d",s_data.b );
$display("SV: s_data.c = %0d \n",s_data.c );
endfunction
initial
begin
import_func();
end
endprogram
RESULTS:
C : s_data.a = 51
C : s_data.b = 242
C : s_data.c = 35
SV: s_data.a = 51
SV: s_data.b = 242
SV: s_data.c = 35
Passing Openarray Structs
CODE: C_file.c
#include"svdpi.h"
typedefstruct{intp;intq}PkdStru;
voidsend2c(constsvOpenArrayHandle dyn_arr)
{
inti;
PkdStru Sele;
printf("\n
\n
Array
Left
%d,
\n\n",svLeft(dyn_arr,1),svRight(dyn_arr,1));
for(i=svLeft(dyn_arr,1);i <=svRight(dyn_arr,1);i++){
Sele =*(PkdStru*)svGetArrElemPtr1(dyn_arr,i);
printf("C : %d : [%d,%d]\n",i,Sele.q,Sele.p );
}
printf("\n\n");
}
CODE: SV_file.sv
programopen_array_struct ();
typedefstructpacked{intp;intq;}PkdStru;
import"DPI-C"functionvoidsend2c (inputPkdStru arr []);
Array
Right
%d
PkdStru arr_data [0:4];
initialbegin
foreach(arr_data[i])begin
arr_data[i]={$random,$random};
$display("SV: %0d : [%0d,%0d]",i,arr_data[i].p,arr_data[i].q);
end
send2c(arr_data);
end
endprogram
RESULTS:
SV:
SV:
SV:
SV:
SV:
0
1
2
3
4
:
:
:
:
:
[303379748,-1064739199]
[-2071669239,-1309649309]
[112818957,1189058957]
[-1295874971,-1992863214]
[15983361,114806029]

C
C
C
C
C
:
:
:
:
:
0
1
2
3
4
:
:
:
:
:
[303379748,-1064739199]
[-2071669239,-1309649309]
[112818957,1189058957]
[-1295874971,-1992863214]
[15983361,114806029]
Passing Union Example

CODE:SV_file
modulem;
typedefbit[2:0]A;
typedefunionpacked{A a;S s;}U;

U u;
A a;
// Import function takes three arguments

import"DPI-C"functionvoidfoo8(inputA fa,inputU fu);
initialbegin
a =3'b100;
u.a =3'b100;
foo8(a,u);
end
endmodule
CODE:C_file
#include"svdpi.h"
voidfoo8(
constsvBitVecVal*fa,
constsvBitVecVal*fu)
{
printf("fa is %d,fu is %d\n",*fa,*fu);
}
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TUTORIALS
SystemVerilog
ARGUMENTS TYPE
Verification
What You Specify Is What You Get
Constructs
For input and inout arguments, the temporary variable is initialized with the value of
the actual argument with the appropriate coercion. For output or inout arguments,
the value of the temporary variable is assigned to the actual argument with the
appropriate conversion. Arguments specified in SystemVerilog as input must not be
modified by the foreign language code. The initial values of formal arguments
specified in SystemVerilog as output are undetermined and implementation
dependent.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog

For arguments passed by reference, a reference (a pointer) to the actual data object input is what keeps
is passed. In the case of packed data, a reference to a canonical data object is Testbench.in improving
passed. The actual argument is usually allocated by a caller. The caller can also pass a with time!
Pass By Ref
reference to an object already allocated somewhere else, for example, its own
formal argument passed by reference. If an argument of type T is passed by
reference, the formal argument shall be of type T*. Packed arrays are passed using a
pointer to the appropriate canonical type definition, either svLogicVecVal* or
svBitVecVal*.
Pass By Value
Only small values of formal input arguments are passed by value. Function results are
also directly passed by value. The user needs to provide the C type equivalent to the
SystemVerilog type of a formal argument if an argument is passed by value.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Passing String
The layout of SystemVerilog string objects is implementation dependent. However,
when a string value is passed from SystemVerilog to C, implementations shall ensure
that all characters in the string are laid out in memory per C string conventions,
including a trailing null character present at the end of the C string.
Example : Passing String From Sv To C
RVM Ethernet sample CODE: SV_file.sv
Specman E
Interview Questions
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
programmain;
stringstr;
import"DPI-C"string_sv2c=taskstring_sv2c(stringstr);
initial
begin
str =" HELLO: This string is created in SystemVerilog \n";
string_sv2c(str);
end
endprogram
CODE: C_file.c
#include"svdpi.h"
http://testbench.in/DP_10_ARGUMENTS_TYPE.html[9/26/2012 2:18:26 PM]
intstring_sv2c(constchar*str){
printf(" C: %s",str);
return0;
}
RESULTS
C:HELLO: This string is created in SystemVerilog
Example: Passing String From C To Sv
From the Data type mapping table, a SystemVerilog "String" is mapped to "const char*"
in C. In the Following example, string "HELLO: This string is created in C" is assigned
to a string and passed as return value to function import "string_c2sv" and this import
function is called in SystemVerilog.
CODE: SV_file.v
programmain;
stringstr;
import"DPI-C"contextfunctionstringstring_c2sv();
initial
begin
str =string_c2sv();
$display(" SV: %s ",str);
end
endprogram
CODE: C_file.c
#include"svdpi.h"
constchar*string_c2sv(void){
char*str;
str =" HELLO: This string is created in C ";
returnstr;
}
RESULTS:
SV: HELLO: This string is created in C
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TUTORIALS
DISABLIE
SystemVerilog
Disable Dpi-C Tasks And Functions
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
It is possible for a disable statement to disable a block that is currently executing a

mixed language callchain. When a DPI import task or function is disabled, the C code
is required to follow a simple disable protocol. The protocol gives the C code the
opportunity to perform any necessary resource cleanup, such as closing open file
handles, closing open VPI handles, or freeing heap memory.
The protocol is composed of the following items:
a) When an exported task returns due to a disable, it must return a value of 1.
Otherwise, it must return 0.
b) When an imported task returns due to a disable, it must return a value of 1.
Otherwise, it must return 0.
c) Before an imported function returns due to a disable, it must call the API
function svAckDisabledState().
d) Once an imported task or function enters the disabled state, it is illegal for the
current function invocation to make any further calls to exported tasks or functions.
Easy Labs : UVM

Easy Labs : OVM
Include Files
Easy Labs : VMM
Applications that use the DPI with C code usually need this main include file. The
include file svdpi.h defines the types for canonical representation of 2-state (bit) and
VMM Ethernet sample 4-state (logic) values and passing references to SystemVerilog data objects. The file
also provides function headers and defines a number of helper macros and constants.
The content of svdpi.h does not depend on any particular implementation; all
simulators shall use the same file.
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/DP_11_DISABLIE.html[9/26/2012 2:18:33 PM]
Index
Introductions
Layers
Import
Naming
Export
Pure And Context
Data Types
Arrays
Passing Structs And
Unions
Arguments Type
Disablie
input is what keeps
with time!
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TUTORIALS
ASIC DESIGN
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
The term Asic stands for Application Specific Integrated Circuit. Is an integrated
circuit (IC) customized for a particular use, rather than intended for general-purpose
use.Generally an ASIC design will be undertaken for a product that will have a large
production run, and the ASIC may contain a very large part of the electronics needed
on a single integrated circuit. As feature sizes have shrunk and design tools improved
over the years, the complexity in an ASIC has grown from 5,000 over 100 million gates
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Mrd
A Marketing Requirements Document (MRD) outlines the requirements a new product.
Engineers use an MRD to create the product.Marketing requirement document covers
market needs, the customer value proposition, and product functionality. It is
developed by the Marketing team and upper management.
Architecture Specification
The architect based on the MRD specification, develops the overall architecture of the
chip.This is a very high level plan.Architecture Specification includes functional
descriptions of each module, Properties and weights.
Design Specification
The designers and architects sit together to come up with detailed design documents.
Design strategies, design partitions, type of memories to use, etc.
Verification Plan
A Verification specification is called a Verification/test plan. The verification
http://testbench.in/TS_01_ASIC_DESIGN.html[9/26/2012 2:18:42 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
engineer goes through all the above documents and prepares verification plan to
verify the design.
Rtl Design
RTL stands for Register Transfer Level. The designer starts implementing the RTL
design in HDL like verilog or VHDL.
The verification engineers starts developing TestBench and verifies whether the DUT
works according to specification or not.
Synthesis
Synthesis is the process of taking a design written in a hardware description language,
compiling it into a net list of interconnected gates which are selected from a userprovided library of various gates.The design after synthesis is a gate-level design.
Physical Design
Physical design process includes logic partitioning, floor planning, global routing,
detailed routing, compaction, and performance-driven layout. PD team transforms net
list representation of a system into layout representation.
Timing Analysis
Static timing analysis is an important step in analyzing the performance of a design. In
the Timing analysis Setup time, hold time ,recovery time ,removal time , Clock
latency, clock skew, clock uncertainty etc checks are done.
Tapeout
This is the final stage of the design cycle of integrated circuits. Once all the checks
are done, the design is ready to be sent to Foundry.
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TUTORIALS
BOTTLE NECK IN ASIC FLOW
SystemVerilog
Verification
What is Bottle neck in the asic design flow?
Constructs
Verificationconsumes 50% to 70% of the effort of design cycle and is on the critical
path in the design flow of multimillion gate ASICs, so verification became the main
bottleneck in the design process.The functional verification bottleneck is an effect
of rising the design abstraction level. Majority of ASICs require at least one re-spin
with 71% of re-spins are due to functional bugs.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_02_BOTTLE_NECK_IN_ASIC_FLOW.html[9/26/2012 2:18:49 PM]
Index
Asic Design
Bottle Neck In Asic
Flow
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TUTORIALS
FUNCTIONAL VERIFICATION NEED
SystemVerilog
Verification
Why we need functional verification?
Constructs
To build confidence and stay in business.

A primary purpose for functional verification is to detect failures so that bugs can be
identified and corrected before it gets shipped to costumer.If RTL designer makes a
mistake in designing or coding, this results as a bug in the Chip. If this bug is
executed, in certain situations the system will produce wrong results, causing a
failure. Not all mistakes will necessarily result in failures. The bug in the dead code
will never result in failure. A single mistake may result in a wide range of failure
symptoms. Not all bugs are caused by coding errors. There are possibilities that error
may in the specification itself. Sometimes miscommunications between teams may
lead to wrong design.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Example of coding error:
1reg[1:0]state;
Easy Labs : SV
2
Easy Labs : UVM
3parameterzero=0,one=1,two=2,three=3;
4
Easy Labs : OVM
5always@(state)
Easy Labs : VMM
6 begin
7case(State)
AVM Switch TB
8 zero:
VMM Ethernet sample 9out =4'b0000;
10 one:
11 out =4'b0001;
12 two:
Verilog
13 out =4'b0010;
Verification
14 three:
Verilog Switch TB
15 out =4'b0100;
16default:
Basic Constructs
17 out =4'b0000;
18endcase
19 end
OpenVera
Constructs
OVM Tutorial
Switch TB
RVM Switch TB
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan

input is what keeps
There is a coding error in the preceding example. Designer declared "state" in the with time!
line-1. Later in the code it is reference in the line-5. In the line-7 also, the designer
RVM Ethernet sample intention is to refer "state". But mistakenly he typed "State".Verilog is a case-
sensitive language, and variable "State" and "state" are different and this will produce
wrong results.
Specman E
Interview Questions
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Index
Asic Design
SystemVerilog
What is TestBench?
Verification
Need
Constructs
TestBench mimic the environment in which the design will reside. It checks whether Testbench
the RTL Implementation meets the design spec or not.This Environment creates Linear Testbench
Interface
Linear Random
invalid and unexpected as well as valid and expected conditions to test the design.
OOPS
Testbench
How To Check The
Randomization
Results
Functional Coverage
Assertion
DPI
The Testbench Has
UVM Tutorial
VMM Tutorial
The Design
OVM Tutorial
Statement Coverage
Easy Labs : SV
Block Coverage
Easy Labs : UVM
Branch Coverage
Easy Labs : OVM
Path Coverage
Easy Labs : VMM
Toggle Coverage
Fsm Coverage
AVM Switch TB
Make Your Goal 100
VMM Ethernet sample
Nothing Less
Functional Coverage
Coverage Driven
Verilog
Constraint Random
Verification
Verilog Switch TB
Basic Constructs
Verification Plan
TUTORIALS
TESTBENCH
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_04_TESTBENCH.html[9/26/2012 2:19:07 PM]

input is what keeps
with time!
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TUTORIALS
LINEAR TESTBENCH
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Linear TestBench is the simplest, fastest and easiest way of writing testbenchs. This
became novice verification engineer choice.It is also slowest way to execute
stimulus. Typically, linear testbenchs are written in the VHDL or Verilog.In this
TestBench, simple linear sequence of test vectors is mentioned. Stimulus code like
this is easy to generate translating a vector file with a Perl script, for example.
Small models like simple state machine or adder can be verified with this approach.
The following code snippet shows linear TestBench. The code snippet shows some
input combination only. This is also bad for simulator performance as the simulator
must evaluate and schedule a very large number of events. This reduces simulation
performance in proportion to the size of the stimulus process.
Typically, linear testbenchs perform the following tasks:
Instantiate the design under test (DUT)
Stimulate the DUT by applying test vectors.
Output results waveform window or to a terminal for visual inspection manually.
Easy Labs : UVM

Easy Labs : OVM
Example:Linear TestBench
moduleadder(a,b,c);//DUT code start
input[15:0]a;
AVM Switch TB
input[15:0]b;
VMM Ethernet sample output[16:0]c;
assignc =a +b;
Verilog
endmodule//DUT code end
Verification
moduletop();//TestBench code start

Verilog Switch TB
reg[15:0]a;
Basic Constructs
reg[15:0]b;
wire[16:0]c;
adder DUT(a,b,c); //DUT Instantiation

OpenVera
Constructs
initial
Switch TB
begin
a =16'h45; //apply the stimulus
RVM Switch TB
b =16'h12;
RVM Ethernet sample #10$display(" a=%0d,b=%0d,c=%0d",a,b,c);
//send the output to terminal for visual inspection
end
endmodule//TestBench code end
Specman E
Easy Labs : VMM
Interview Questions
To test all possible scenarios which are known to us, it is not an easy task.
Development time increases exponentially as the number of scenarios increases and
maintain them is nightmare. Instead of listing out all the possible scenarios, pickup
some randomly and check the DUT.
NOTETONOVOICEENGINEERS:
Generally tendency of any novice engineer is to see the outputs in the waveform
viewer. Waveform viewers are for debugging designs, not for testbench.Most of the
http://testbench.in/TS_05_LINEAR_TESTBENCH.html[9/26/2012 2:19:14 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
operation in TestBench executes in zero time, where waveform viewer will not be
helpful. All the examples in the book outputs messages to terminal for analyzing its
behavior.
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TUTORIALS
LINEAR RANDOM TESTBENCH
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Random TestBench don't use Hardcoded values like linear testbenchs.Input stimulus
is generated using random values.In Verilog, system function $random provides a
mechanism for generating random numbers. The function returns a new 32-bit
random number each time it is called. These test cases are not easily readable and
are also not reusable. New tests have to be created when the specification or design
changes, to accommodate the changes.The main disadvantage of this testing is that
we never know what random values are generated and it may waste simulation cycles
by generating same values again and again.
Assertion
EXAMPLE: Linear Random TestBench

UVM Tutorial
input[15:0]a,b;
output[16:0]c;
VMM Tutorial
assignc =a +b;
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
reg[15:0]a;
reg[15:0]b;
Easy Labs : OVM
wire[16:0]c;
Easy Labs : VMM

AVM Switch TB

repeat(100)begin
a =$random;//apply random stimulus
b =$random;
Verilog
#10$display(" a=%0d,b=%0d,c=%0d",a,b,c);
Verification
end
Verilog Switch TB
DPI
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_06_LINEAR_RANDOM_TESTBENCH.html[9/26/2012 2:19:22 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TOP
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TUTORIALS
HOW TO CHECK THE RESULTS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
How does a Verification engineer check whether the results obtained from the
simulation match the original specification of the design?For simple testbenchs like
the above, output is displayed in waveform window or messages are sent to terminal
for visual checking.Visually checking is the oldest and most labor intensive
technique. The quality of the verification depends on the determination and
dedication of the individual who is doing the checking. It is not practical to verify a
complex model merely by examining the waveform or text file. Whenever a change is
made to the DUT to add a new feature or to fix a bug, same amount of effort needs
to be deployed to check the simulation results.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_07_HOW_TO_CHECK_THE_RESULTS.html[9/26/2012 2:19:30 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TOP
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TUTORIALS
SELF CHECKING TESTBENCHS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
A self-checking TestBench checks expected results against actual results obtained

from the simulation. Although Self-checking testbenchs require considerably more
effort during the initial test bench creation phase, this technique can dramatically
Reduce the amount of effort needed to re-check a design after a change has been
made to the DUT. Debugging time is significantly shortened by useful error-tracking
information that can be built into the TestBench to show where a design fails.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A self-checking TestBench has two major parts, the input blocks and output blocks.
Input block consist of stimulus and driver to drive the stimulus to DUT. The output
block consists of monitor to collect the DUT outputs and verify them.
VMM Ethernet sample All the above approaches require the test writer to create an explicit test for each
feature of the design. Verification approach in which each feature is written in a

separate test case file is called directed verification.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
EXAMPLE:adder example
input[15:0]a,b;
output[16:0]c;
assignc =a +b;
Switch TB
reg[15:0]a;
RVM Switch TB
reg[15:0]b;
RVM Ethernet sample wire[16:0]c;
Specman E
initial
Interview Questions
repeat(100)begin
a =$random;//apply random stimulus
b =$random;
#10
$display(" a=%0d,b=%0d,c=%0d",a,b,c);
if(a +b !=c) // monitor logic.
$display(" *ERROR* ");
end
Constructs
http://testbench.in/TS_08_SELF_CHECKING_TESTBENCHS.html[9/26/2012 2:19:38 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
Self Checking
Testbenchs
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TOP
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TUTORIALS
HOW TO GET SCENARIOS WHICH WE NEVER THOUGHT
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
In Directed verification, the Verification Environment has mechanism to send the

Stimulus to DUT and collect the responses and check the responses. The Stimulus is
generated in Tests case.Directed testbenchs may also use a limited amount of
randomization, often by creating random data values rather than simply filling in
each data element with a predetermined value.Each test case verifies specific
feature of the design. This becomes tedious when the design complexity increases.As
circuit
complexity increases, it becomes more difficult to create patterns that fully exercise
the design.Test case maintenance become harder and time consuming.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
In Directed Verification, test writer has to list out each feature.Test writer can't
think of all possible potential bug scenarios and there are chances that Bugs will
escape.With these approaches, the bugs lurking in these corners hide until late in
the development cycle, or aren't found at all until product is taped out.
input is what keeps
Solution to the above problems is Constraint random verification. Using constraint
with time!
random verification, the stimulus required to verify test features are generated
RVM Ethernet sample automatically.Test writer specifies set of specification, and the TestBench
automatically creates solution space and picks up scenarios from the solution space.
Specman E
Interview Questions
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
Which We Never
Thought
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
Constraint random verification also reduces manual effort and code for individual
tests.As the scenarios are generated automatically by the TestBench, the number of
test case files gets reduced.In Directed verification, some of the tests share similar
logic, if the engineer has to change the logic which is common to certain group of
tests, then he has to edit all the test case files and it is time consuming.But in
Constraint random verification, the number of tests case files will be very less, so
changes will be mostly in environment and minimal.
Directed verification with a fairly simple TestBench, verification engineers can start
finding bugs in simulation almost immediately even before the TestBench is fully
completed.With a constrained-random verification environment, there is an up-front
cost that must be invested before the first test can be run. Constraint-based
generators can be easily converted into checkers if required.
http://testbench.in/TS_09_HOW_TO_GET_SCENARIOS_WHICH_WE_NEVER_THOUGHT.html[9/26/2012 2:19:47 PM]
Generating fully randomly is meaningless as it may generate invalid scenarios and it

may also regenerate the same scenario again and again wasting potential simulation
time. A User must define data structures, which represent stimulus applied to the DUT
input. Next, constraints must be defined to guide the random generator. Using
constraint, the solution space is defined, and randomization picks up scenarios
randomly from the solution space.Constraints act as knobs in the TestBench which
control the generator's randomness.
The main disadvantage of constraint random verification is we never know how well
the DUT is verified.If verification engineercan get the information about the logic in
DUT which is not verified, he can further constraint the randomization or write
directed testcases to exercise the unverified logic.
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TUTORIALS
SystemVerilog
HOW TO CHECK WHETHER THE TESTBENCH HAS SATISFACTORILY Index

Asic Design
EXERCISED THE DESIGN
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Code coverage is used to measure the efficiency of verification implementation. It

provides a quantitative measurement of the testing space. It describes the degree to
which the source code of a DUT has been tested. It is also referred as structural
coverage.
Code coverage answers the questions like
Have all the branches in " Case ", "if" have been entered?
Have all the conditions in "if","case" statement is simulated?
Have all the variables have been toggles?
Have all the statements of the RTL code have been exercised?
Have all the states in the FSM has been entered and all the legal transitions
exercised?
Have all the paths within a block have been exercised?
By applying code coverage analysis techniques to hardware description languages,
verification efficiency was improved by enabling a verification engineer to isolate
areas of un-tested HDL code. The verification engineerexamine a coverage report,
seeks out the low values and understands why that particular code hasn't been tested
fully and writes more tests or directs randomness to cover the untested areas where
there may be a possibility of bug hiding.
No additional coding is required to get 100 percent code coverage , the tool would
automatically
show
the
item
as
covered
if
the
required
test
scenario(s)/combination(s) is(are) exercised.
In unit level verification, a module by module is verified in its own test environment
to prove that the logic, control, and data paths are functionally correct. The goal of
module level verification is to ensure that the component/unit being tested conforms
to its specifications and is ready to be integrated with other subcomponents of the
product. Code coverage becomes a criterion for finishing unit level testing as it needs
to verify every feature of component/unit. In sub-system level /system level, the
goal is to ensure that the interfaces among the units are correct and the units work
together to execute the functionality correctly. In sub system level /system level
testing, code coverage may not be useful as the verification is not targeted at all the
features of the unit.
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_10_HOW_TO_CHECK_WHETHER_THE_TESTBENCH_HAS_SATISFACTORILY_EXERCISED_THE_DESIGN.html[9/26/2012 2:19:57 PM]
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Index
Asic Design
SystemVerilog
There are a number of coverage criteria, they are:
Verification
Need
Constructs
Testbench
Statement coverage /line coverage
Linear Testbench
Interface
Block/segment coverage
Linear Random
Conditional coverage
OOPS
Testbench
Branch coverage
How To Check The
Randomization
Toggle coverage
Results
Functional Coverage
Path coverage
Assertion
Fsm coverage
DPI
The following example is considered while explaining code coverage types in further How To Check Whether
The Testbench Has
UVM Tutorial
sections.
VMM Tutorial
The Design
Types Of Code
OVM Tutorial
EXAMPLE
Coverage
1
Easy Labs : SV
Statement Coverage
2moduledut();
Block Coverage
Easy Labs : UVM
3rega,b,c,d,e,f;
4
Easy Labs : OVM
Branch Coverage
5initial
Easy Labs : VMM
Path Coverage
6begin
Toggle Coverage
7#5a =0;
AVM Switch TB
Fsm Coverage
8#5a =1;
VMM Ethernet sample 9end
Make Your Goal 100
10
Nothing Less
11 always@(posedgea)
Functional Coverage
12 begin
Verilog
Coverage Driven
13c
=b
&&a;
Verification
Constraint Random
14if(c &&f)
Verilog Switch TB
15b =e;
16else
Basic Constructs
17e =b;
Verification Plan
18
19case(c)
OpenVera
201:f =1;
Constructs
210:f =0;
input is what keeps
22default:f
=0;
Switch TB
23endcase
RVM Switch TB
with time!
24
RVM Ethernet sample 25 end
26endmodule
TUTORIALS
TYPES OF CODE COVERAGE
Specman E
Interview Questions
http://testbench.in/TS_11_TYPES_OF_CODE_COVERAGE.html[9/26/2012 2:20:04 PM]
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TUTORIALS
STATEMENT COVERAGE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Statement coverage, also known as line coverage is the easiest understandable type
of coverage. This is required to be 100% for every project.From N lines of code and
according to the applied stimulus how many statements (lines) are covered in the
simulation is measured by statement coverage. If a DUT is 10 lines long and 8 lines of
them were exercised in a test run, then the DUT has line coverage of 80%. Line
coverage includes continuous assignment statements, Individual procedural
statements, Procedural statement blocks, Procedural statement block types,
Conditional statement and Branches for conditional statements. It considers only it
the executable statements and statements which are not executable like module,
endmodule, comments, timescale etc are not covered.
Statement coverage report of the above example:
VMM Tutorial
OVM Tutorial
There are total 12 statements at lines 5,7,8,11,13,14,15,17,19,20,21,22
Covered 9 statements. They are at lines

5,7,8,11,13,14,17,19,22
Uncovered 3 statements. They are at line

15,20,21
Coverage percentage: 75.00 (9/12)
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_12_STATEMENT_COVERAGE.html[9/26/2012 2:20:12 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
<< PREVIOUS PAGE
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Search
Index
Asic Design
SystemVerilog
The nature of the statement and block coverage looks somewhat same. The Functional Verification
Verification
difference is that block coverage considers branched blocks of if/else, case branches, Need
Constructs
Testbench
wait, while, for etc.Analysis of block coverage reveals the dead code in RTL.
Linear Testbench
Interface
Linear Random
Block coverage report of the above example:
OOPS
Testbench
How To Check The
Randomization
Results
Functional Coverage
There are total 9 blocks at lines
Assertion
5,7,8,11,15,17,20,21,22
DPI
Covered 6 blocks. They are at lines
The Testbench Has
UVM Tutorial
5,7,8,11,17,22
VMM Tutorial
The Design
Uncovered 3 blocks. They are at line
OVM Tutorial
15,20,21
Statement Coverage
Easy Labs : SV
Block Coverage
Easy Labs : UVM
Branch Coverage
Easy Labs : OVM
Path Coverage
Easy Labs : VMM
Toggle Coverage
Fsm Coverage
AVM Switch TB
Make Your Goal 100
VMM Ethernet sample
Nothing Less
Functional Coverage
Coverage Driven
Verilog
Constraint Random
Verification
Verilog Switch TB
Basic Constructs
Verification Plan
TUTORIALS
BLOCK COVERAGE
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_13_BLOCK_COVERAGE.html[9/26/2012 2:20:20 PM]

input is what keeps
with time!
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TUTORIALS
CONDITIONAL COVERAGE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Conditional coverage also called as expression coverage, will reveals how the
variables or sub-expressions in conditional statements are evaluated. Expressions with
logical operators are only considered.. The downside is that the conditional coverage
measure doesn't take into consideration how the Boolean value was gotten from the
conditions. Conditional coverage is the ratio of no. of cases checked to the total no.
of cases present. Suppose one expression having Boolean expression like AND or OR, so
entries which is given to that expression to the total possibilities is called expression
coverage.
Assertion
Conditional coverage report of the previous example:

AtLINE 13
UVM Tutorial
Combinations of STATEMENT c = (b && a)
B =0and a = 0isCovered
VMM Tutorial
B =0and a = 1isCovered
OVM Tutorial
B =1and a = 0isNot Covered
b =1and a = 1isNot Covered
Easy Labs : SV
Easy Labs : UVM

At LINE 14 combinations of STATEMENT if ((c && f))
C =0andf = 0is Covered
Easy Labs : OVM
C =0andf = 1is Not Covered
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample Total possible combinations: 8

Total combinations executed: 3
DPI
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_14_CONDITIONAL_COVERAGE.html[9/26/2012 2:20:28 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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Index
Asic Design
SystemVerilog
Branch coverage which is also called as Decision coverage report s the true or false of Functional Verification
Verification
the conditions like if-else, case and the ternary operator (? :) statements. For an "if" Need
Constructs
statement, decision coverage will report whether the "if" statement is evaluated in Testbench
Linear Testbench
both true and false cases, even if "else" statement doesn't exist.
Interface
Linear Random
OOPS
Testbench
How To Check The
Randomization
Results
Branch
coverage
report
of
the
example:
Functional Coverage

Assertion
At line 15 branch b = e;not covered
At
line
17
branch
e
=
b;covered
DPI
At line 20 branch 1: f = 1; not covered
The Testbench Has
UVM Tutorial
At line 21 branch 0: f = 0; covered
At line 22 branch default: f = 0; not covered
VMM Tutorial
The Design

OVM Tutorial
Statement Coverage
Easy Labs : SV
Block Coverage
Easy Labs : UVM
Branch Coverage
Easy Labs : OVM
Path Coverage
Easy Labs : VMM
Toggle Coverage
Fsm Coverage
AVM Switch TB
Make Your Goal 100
VMM Ethernet sample
Nothing Less
Functional Coverage
Coverage Driven
Verilog
Constraint Random
Verification
Verilog Switch TB
Basic Constructs
Verification Plan
TUTORIALS
BRANCH COVERAGE
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_15_BRANCH_COVERAGE.html[9/26/2012 2:20:37 PM]

input is what keeps
with time!
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TUTORIALS
PATH COVERAGE
SystemVerilog
Verification
Constructs
Interface
Path coverage represents yet another interesting measure. Due to conditional

statements like if-else, case in the design different path is created which diverts the
flow of stimulus to the specific path.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Path coverage is considered to be more complete than branch coverage because it

can detect the errors related to the sequence of operations. As mentioned in the
above figure path will be decided according to the if-else statement According to the
applied stimulus the condition which is satisfied only under those expressions will
execute, the path will be diverted according to that. Path coverage is possible in
always and function blocks . Path created by more than one block is not
covered.Analysis of path coverage report is not so easy task.
OpenVera
Constructs
Path coverage report of the example:
RVM Switch TB
Path 1 : 15,20Not Covered
RVM Ethernet sample Path 2 : 15,21Not Covered
Path 3:15,22Not Covered
Path 4:17,20Not Covered
Path 5 : 17,21Covered
Specman E
Path 6 : 17,22Not Covered
Interview Questions
Total possible paths : 6
Total covered path : 1
Path coverage Percentage : 16.67(1/6)
Switch TB
http://testbench.in/TS_16_PATH_COVERAGE.html[9/26/2012 2:20:44 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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Search
TUTORIALS
TOGGLE COVERAGE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
It makes assures that how many times variables and nets toggled? Toggle coverage
could be as simple as the ratio of nodes toggled to the total number of nodes.
X or Z --> 1 or H
X or Z --> 0 or L
1 or H --> X or Z
0 or L --> X or Z
Above example shows the signal changes from one level to another. All types of
transitions mentioned above are not interested. Only 1->0 and 0->1 are important.
Toggle coverage will show which signal did not change the state. Toggle coverage will
not consider zero-delay glitches. This is very useful in gate level simulation.
Toggle coverage report of the example:
Name Toggled 1->00->1
aNoNoYes
bNoNoNo
cNoNoNo
dNoNoNo
eNoNoNo
fNoNoNo
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_17_TOGGLE_COVERAGE.html[9/26/2012 2:20:52 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TUTORIALS
FSM COVERAGE
SystemVerilog
Verification
Constructs
Interface
It is the most complex type of code coverage, because it works on the behavior of the
design. Using Finite state machine coverage, all bugs related to finite state machine
design can be found. In this coverage we look for how many times states are visited,
transited and how many sequence are covered in a Finite state machine.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
State Coverage:
It gives the coverage of no. of states visited over the total no. of states. Suppose you
have N number of states and state machines transecting is in between only N-2 states
then coverage will give alert that some states are uncovered. It is advised that all the
states must be covered.
OVM Tutorial
Easy Labs : SV
Transition Coverage:
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
It will count the no. of transition from one state to another and it will compare it with
other total no. of transition. Total no. of transition is nothing but all possible no. of
transition which is present in the finite state machine. Possible transition = no. of
states * no. of inputs.
VMM Ethernet sample
EXAMPLE of FSM:
modulefsm (clk,reset,in);
inputclk,reset,in;
Verilog
reg[1:0]state;
Verification
Verilog Switch TB
parameters1 =2'b00;parameters2 =2'b01;
parameters3 =2'b10;parameters4 =2'b11;
Basic Constructs
always@(posedgeclk orposedgereset)
begin
OpenVera
if(reset)state <=s1;
Constructs
elsecase(state)
s1:if(in ==1'b1)state <=s2;
Switch TB
elsestate <=s3;
RVM Switch TB
s2:state <=s4;
RVM Ethernet sample s3:state <=s4;
s4:state <=s1;
endcase
end
Specman E
endmodule
Interview Questions
moduletestbench();
regclk,reset,in;
fsm dut(clk,reset,in);
initial
forever#5clk =~clk;
initial
begin
http://testbench.in/TS_18_FSM_COVERAGE.html[9/26/2012 2:20:59 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
clk =0;in =0;

#2reset =0;#2reset =1;
#21reset =0;#9in =0;
#9in =1;#10$finish;
end
endmodule
FSM coverage report for the above example:
// state coverage results

s1| Covered
s2| Not Covered
s3| Covered
s4| Covered
// state transition coverage results
s1->s2| Not Covered
s1->s3| Covered
s2->s1| Not Covered
s2->s4| Not Covered
s3->s1| Not Covered
s3->s4| Covered
s4->s1| Covered
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TUTORIALS
MAKE YOUR GOAL 100 PERCENT CODE COVERAGE NOTHING LESS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Never set your goal to anything less than 100% code coverage. Anything less than 100%
is a slippery slope. If you set your goal to 98% , may be the most important feature
like reset of the system may be in the untested part of2%.If the verification engineer
sets the code coverage goal to 95% to facilitate the 5% the unused untestable legacy
code, there are chances that the unused legacy code gets executed and the 5% holes
may be in the important code.100% code coverage provides advantages not only in
reducing the bug count but also in making it easier to make significant changes to
existing code base to remove uncover able areas like the unused legacy blocks in RTL
code.
Dont Be Fooled By The Code Coverage Report
UVM Tutorial
Highly covered code isn't necessarily free of defects, although it's certainly less likely
to contain them. By definition, code coverage is limited to the design code. It doesn't
know anything about what design supposed to do. Even If a feature is not
OVM Tutorial
implemented in design, code coverage can report 100% coverage.It is also impossible
to determine whether we tested all possible values of a feature using code coverage.
Easy Labs : SV
For example, randomization may not generate packets with all possible lengths, this
Easy Labs : UVM
cannot be reported by code coverage.. Code coverage is unable to tell much about
how well you have covered your logic -- only whether you've executed each line/block
Easy Labs : OVM
etc at least once. Code coverage does not provide information about your test bench
Easy Labs : VMM
randomization quality and it does not report what caused the line execution/state
transition etc.Analysis of code coverage require knowledge of design to find which
AVM Switch TB
features are not verified which is time consuming and out of scope of verification
VMM Ethernet sample engineer.If the analysis is done at higher level of abstraction, it would be easier for
the test writer to identify the missed serious which is not possible by code
coverage.So if the code coverage is less than 100%, it means there is more work to
do, if it is 100%, it doesn't mean that the verification is complete.
Verilog
VMM Tutorial
Verification
Verilog Switch TB
When To Stop Testing?
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
It's getting harder to figure out when to stop testing as the complexity of the protocol
is increasing. In directed test environment, for each point mentioned in test plan,
there will be a separate test case file. So if there are 100 points in test plan, then the
engineer has to write 100 test case files. After writing and executing the 100 test
case files, we can say that "all the points in test plan are verified" and we can stop
testing.
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TS_19_MAKE_YOUR_GOAL_100_PERCENT_CODE_COVERAGE_NOTHING_LESS.html[9/26/2012 2:21:07 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
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TUTORIALS
FUNCTIONAL COVERAGE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
In CRV, the each point in test plan is generated automatically. As there points are
generated automatically, we need a mechanism which tells us that all the points in
test plan are not exercised.When all the points in testplans are verified and the code
coverage is 100% we can stop verification.
What are the untested features?
In Directed verification, there will be a separate testcase file for each feature to be
verified. So to know how many features are verified, count the testcases.Verification
is done when all tests are coded and passing alone with 100% code coverage. In
constraint random verification all the features are generated randomly. Verification
engineer need a mechanism to know the information about the verified features of
DUT.
SystemVerilog provides a mechanism to know the untested feature using functional
coverage. Functional Coverage is "instrumentation" that is manually added to the
TestBench.This is a better approach then counting testcases.Functional coverage is
better than code coverage where the code coverage reports what was exercised
rather that what was tested.
Easy Labs : OVM
Functional coverage answers questions like

Have all the packets length between 64 to 1518 are used?
AVM Switch TB
Did the DUT got exercised with alternate packets with good and bad crc?
Did the monitor observe that the result comes with 4 clock cycles after read
VMM Ethernet sample
operation?
Did the fifos are filled completely?
Easy Labs : VMM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Summary of functional coverage advantages:

Functional coverage helps determine how much of your specification was covered.
Functional coverage qualifies the testbenchs.
Considered as stopping criteria for unit level verification.
Gives feedback about the untested features.
Givesthe information about the redundant tests which consume valuable cycle.
Guides to reach the goals earlier based on grading.
Introduction To Functional Coverage:
RVM Ethernet sample SystemVerilog provides 2 ways to mention coverage.Cover group which is uses
Specman E
Interview Questions
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
information from transactor, monitor and checker. Assertion coverage which is uses
temporal language which can be outside or inside RTL code.
Covergroup:
There are three types of cover group points:
1. item functional coverage point
2. cross functional coverage point
3. transitional functional coverage point
Item
"Item" is used to capture the information about the sclare value.A range of
interested values can also be observed.
For example, consider a packet protocol. The packet has a address field with possible
http://testbench.in/TS_20_FUNCTIONAL_COVERAGE.html[9/26/2012 2:21:17 PM]
input is what keeps

with time!
values of A0,A1 and data which can be 4 to 10 bytes. At the end of packet parity is
also attached for integrity checking.
The following table identifies these coverage points for the above packet:
Item_DL Data length 4 to 10
Item_ADDAddress A0,A1
Item_ParParityGood and Bad
Coverage engine collects item values are during simulation and reports.
Reports consists how many times
Packets with length 4,5,6,7,8,9,10 are generated.
Packets with good parity, bad parity are generated.
Packets with address A0, A1 are generated.
Cross
"cross" is used to examine the cross product of two or more item coverage points.
Example: verify DUT by sending both good parity and bad parity packets with all the
address.
Cross_ ADD_ParItem_ADD,Item_Par
Coverage report
Packets with
Packets with
Packets with
Packets with
consists
Address
Address
Address
Address
how many times

A0 with good parity are generated
A0 with bad parity are generated
A1 with good parity are generated
A1 with bad parity are generated
Transitional
Transitional functional point is used to examine the legal transitions of a value.
Example:
Verify the DUT with incremental packet length from 4 to 10.
Trans_length( 4=> 5=> 6 => 7 => 8 =>9 =>10)
Coverage engine reports whether this sequence is exercised or not.
Assertion Coverage:
Assertion coverage looks for the desired behavior in RTL. It uses assertion language
which is in temporal nature. It has direct access to design variables and designer can
add many points in RTL which he wants the verification engineer to cover.
Example:Verify by sending back-to-back packets.
Functional coverage will be discussed in more detail in later chapters.
Verification using functional coverage and randomization is called coverage driven
constraint random verification.
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TUTORIALS
SystemVerilog
COVERAGE
DRIVEN
ARCHITECTURE
CONSTRAINT
RANDOM
VERIFICATION Index
Verification
Constructs
Basic functionality of CDRV Environment:
Interface
Input side of DUT :

-- Generating traffic streams
-- Driving traffic into the design (stimuli)
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Output side of DUT:

-- Checking these data streams
-- Checking protocols and timing
Collecting both the functional coverage and code coverage information.
Writing deterministic tests and random tests to achieve 100% coverage.
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera

input is what keeps
with time!
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification
Architecture
Verification Plan
Verification Components Required For Cdcrv:

Stimulus
Stimulus generator
Transactor
Driver
Monitor
Assertion monitor
Checker
Scoreboard
Coverage
Utilities
Tests
http://testbench.in/TS_21_COVERAGE_DRIVEN_CONSTRAINT_RANDOM_VERIFICATION_ARCHITECTURE.html[9/26/2012 2:21:24 PM]
Stimulus:
When building a verification environment, the verification engineer often starts by
modeling the device input stimulus. In Verilog, the verification engineer is limited in
how to model this stimulus because of the lack of high-level data structures.
Typically, the verification engineer will create a array/memory to store the stimuli.
SystemVerilog provides high-level data structures and the notion of dynamic data
types for modeling stimulus. Using SystemVerilog randomization, stimulus is generated
automatically.Stimulus is also processed in other verification components.
SystemVerilog high-level data structures helps in storing and processing of stimulus in
an efficient way.
Stimulus Generator
The generator component generates stimulus which are sent to DUT by driver.
Stimulus generation is modeled to generate the stimulus based on the specification.
For simple memory stimulus generator generates read, write operations, address and
data to be stored in the address if its write operation.Scenarios like generate
alternate read/write operations are specified in scenario generator. SystemVerilog
provided construct to control the random generation distribution and
order.Constraints defined in stimulus are combinatioural in nature where as
constraints defined in stimulus generators are sequential in nature.
Stimulus generation can be directed or directed random or automatic and user should
have proper controllability from test case. It should also consider the generation of
stimulus which depends on the state of the DUT for example, Generating read cycle as
soon as interrupt is seen.Error injection is a mechanism in which the DUT is verified
by sending error input stimulus.Generally it is also taken care in this module.
Generally generator should be able to generate every possible scenario and the user
should be able to control the generation from directed and directed random testcases.
Transactor
Transactor does the high level operations like burst-operations into individual
commands, sub-layer protocol in layered protocol like PciExpress Transaction layer
over PciExpress Data Link Layer, TCP/IP over Ethernet etc. It also handles the DUT
configuration operations. This layer also provides necessary information to coverage
model about the stimulus generated. Stimulus generated in generator is high level like
Packet is with good crc, length is 5 and da is 8<92>h0.This high level stimulus is
converted into low level data using packing. This low level data is just a array of bits
or bytes. Packing is an operation in which the high level stimulus values scalars,
strings, array elements and struct are concatenated in the specified manner.
Driver
The drivers translate the operations produced by the generator into the actual inputs
for the design under verification. Generators create inputs at a high level of
abstraction namely, as transactions like read write operation. The drivers convert this
input into actual design inputs, as defined in the specification of the designs
interface. If the generator generates read operation, then read task is called, in that,
the DUT input pin "read_write" is asserted.
Monitor
Monitor reports the protocol violation and identifies all the transactions. Monitors are
two types, Passive and active. Passive monitors do not drive any signals.Active
monitors can drive the DUT signals. Sometimes this is also refered as
receiver.Monitor converts the state of the design and its outputs to a transaction
abstraction level so it can be stored in a 'score-boards' database to be checked later
on.Monitor converts the pin level activities in to high level.
Assertion Based Monitor
Assertions are used to check time based protocols, also known as temporal checks.
Assertions are a necessary compliment to transaction based testing as they describe
the pin level, cycle by cycle, protocols of the design. Assertions are also used for
functional coverage.
Data Checker
The monitor only monitors the interface protocol. It doesn't check the whether the
data is same as expected data or not, as interface has nothing to do with the date.
Checker converts the low level data to high level data and validated the data. This
operation of converting low level data to high level data is called Unpacking which is
reverse of packing operation. For example, if data is collected from all the commands
of the burst operation and then the data is converted in to raw data , and all the sub
fields information are extracted from the data and compared against the expected
values. The comparison state is sent to scoreboard.
Scoreboard
Scoreboard is sometimes referred as tracker. Scoreboard stores the expected DUT
output. Scoreboard in Verilog tends to be cumbersome, rigid, and may use up much
memory due to the lack of dynamic data types and memory allocation. Dynamic data
types and Dynamic memory allocation makes it much easier to write a scoreboard in
SystemVerilog.The stimulus generator generated the random vectors and is sent to
the DUT using drivers. These stimuli are stored in scoreboard until the output comes
out of the DUT. When a write operation is done on a memory with address 101 and
data 202, after some cycles, if a read is done at address 101, what should be the
data?.The score board recorded the address and data when write operation is done.
Get the data stored at address of 101 in scoreboard and compare with the output of
the DUT in checker module. Scoreboard also has expected logic if needed. Take a 2
inputs and gate. The expect logic does the "and " operation on the two inputs and
stores the output".
Coverage
This component has all the coverage related to the functional coverage groups.
Utilities
Utilities are set of global tasks which are not related to any protocol. So this module
can be reused across projects without any modification to code. Tasks such as global
timeout, printing messages control, seeding control, test pass/fail conditions, error
counters etc. The tasks defined in utilities are used by all other components of the
TestBench.
Environment:
Environment contains the instances of all the verification component and Component
connectivity is also done.Steps required for execution of each component is done in
this.
Tests
Tests contain the code to control the TestBench features. Tests can communicate with
all the TestBench components. Once the TestBench is in place, the verification
engineer now needs to focus on writing tests to verify that the device behaves
according to specification.
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Index
Asic Design
SystemVerilog
Verification
Need
Constructs
Testbench
Linear Testbench
Interface
Linear Random
OOPS
Testbench
How To Check The
Randomization
Results
Functional Coverage
Assertion
DPI
The Testbench Has
UVM Tutorial
VMM Tutorial
The Design
OVM Tutorial
Statement Coverage
Easy Labs : SV
Block Coverage
Easy Labs : UVM
Branch Coverage
Easy Labs : OVM
Path Coverage
Easy Labs : VMM
Toggle Coverage
Fsm Coverage
AVM Switch TB
Make Your Goal 100
VMM Ethernet sample
Nothing Less
Functional Coverage
Coverage Driven
Verilog
Constraint Random
Verification
Verification Plan
Verilog Switch TB
Basic Constructs
In test plan, we prepare a road map for how do achieve the goal, it is a living Verification Plan
document. Test plan includes, introduction, assumptions, list of test cases, list of
features to be tested, approach, deliverables, resources, risks and scheduling, entry Report a Bug or Comment
OpenVera
and exit criteria.Test plan helps verification engineer to understand how the on This section - Your
Constructs
verification should be done. A test plan could come in many forms, such as a input is what keeps
spreadsheet, a document or a simple text file. Sometimes, test plan simply reside in Testbench.in improving
Switch TB
the engineer's head which is dangerous in which the process cannot be properly with time!
RVM Switch TB
measured and controlled. Test plan also contains the descriptions of TestBench
RVM Ethernet sample architecture and description of each component and its functionality.
TUTORIALS
Specman E
Interview Questions
PHASES OF VERIFICATION
Building Testbench
In this phase, the verification environment is developed.Each verification component
can be developed one by one or if more than one engineer is working it can be
developed parallel.Writing the coverage module can be done at any time. It is
preffered to write down the coverage module first as it gives some idea of the
verification progress.
Writing Tests
http://testbench.in/TS_22_PHASES_OF_VERIFICATION.html[9/26/2012 2:21:32 PM]
After the TestBench is built and integrated to DUT, it's time for validating the
DUT.Initially in CDV, the test are ran randomly till some 70 % of coverage is reached
or no improvement in the coverage for 1 day simulation.By analyzing the coverage
reports, new tests are written to cover the holes. In these tests, randomization is
directed to cover the holes. Then finally, the hard to reach scenarios, called as corner
cases have to be written in directed verification fashion. Of course, debugging is
done in parallel and DUT fixes are done.
Integrating Code Coverage
Once you have achieved certain level of functional coverage, integrate the code
coverage.For doing code coverage, the code coverage tools have option to switch it
on. And then do the simulation, the tool will provide the report.
Analyze Coverage
Finally analyze both functional coverage and code coverage reports and take
necessary steps to achieve coverage goals.Run simulation again with a different
seed, all the while collecting functional coverage information.
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TUTORIALS
Ones Counter is a Counter which counts the number of one's coming in serial stream.
The Minimum value of the count is "0" and count starts by incriminating one till
"15".After "15" the counter rolls back to "0".Reset is also provided to reset the
counter value to "0". Reset signal is active negedge. Input is 1 bit port for which the
serial stream enters. Out bit is 4 bit port from where the count values can be taken.
Reset and clock pins also provided.
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
The following is the RTL code of onescounter with bugs.

input is what keeps
with time!
ONES COUNTER EXAMPLE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Following example is TestBench for ones counter. It has some verification components
which are required, but not all the verification components discussed earlier. All the
components implementation can be seen in further chapters with another protocol.
Description of the language construct is discussed in further chapters, so don't pay
attention to them. The intention of showing this example is to make you familiar with
some steps required while building verification environment and to help you to
understand the flow discussed above.
Functional Coverage
Assertion
Specification:
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
moduledff(clk,reset,din,dout);
RVM Ethernet sample inputclk,reset,din;
Specman E
Interview Questions
outputdout;
logicdout;
always@(posedgeclk,negedgereset)
if(!reset)
dout <=0;
else
dout <=din;
endmodule
moduleones_counter(clk,reset,data,count);
inputclk,reset,data;
output[0:3]count;
dff d1(clk,reset,data,count[0]);
http://testbench.in/TS_23_ONES_COUNTER_EXAMPLE.html[9/26/2012 2:21:40 PM]
dff d2(count[0],reset,~count[1],count[1]);
endmodule
Test Plan:
This is a simple testplan. Features to be verified are
1)Count should increment from "0" to "15".( Coverage item)
2)Count should roolover to "0" after "15".(Coverage transition)
3)Reset should make the output count to "0", when the count values is non "0". (
Assertion coverage)
Block Diagram:
Verification Environment Hierarchy

TOP
|-- Clock generator
|-- Dut Instance
|-- Interface
|-- Assertion block instance ( assertion coverage)
|-- Testcase instance
|-- Environment
|-- Driver
| |-- Stimulus
| |-- Covergroup
|-- Monitor
|-- Scoreboard
Testbench Components:
Stimulus
Stimulus is a single bit value.
classstimulus;
randbitvalue;
constraintdistribution {value dist{0:=1,1:=1};}
endclass
Driver
This driver consists of reset and drive method.Reset method resets the DUT and drive
method generates the stimulus and sends it to DUT. Driver also calculates the
expected DUT output and stores in scoreboard. Coverage is also sampled in this
component. Feature 1 and 2 which are mentioned in Testplan are covered in this
cover group.
classdriver;
stimulus sti;
Scoreboard sb;
covergroupcov;
Feature_1:coverpointsb.store ;
Feature_2 :coverpointsb.store{binstrans =(15=>0);}
endgroup
virtualintf_cnt intf;
functionnew(virtualintf_cnt intf,scoreboard sb);

this.intf =intf;
this.sb =sb;
cov =new();
endfunction
taskreset();// Reset method

intf.data=0;
@(negedgeintf.clk);
intf.reset =1;
@(negedgeintf.clk);
intf.reset =0;
@(negedgeintf.clk);
intf.reset =1;
endtask
taskdrive(inputintegeriteration);
repeat(iteration)
begin
sti =new();
@(negedgeintf.clk);
if(sti.randomize())// Generate stimulus
intf.data=sti.value;// Drive to DUT
sb.store =sb.store +sti.value;// Cal exp value and store in Scoreboard
if(sti.value)
cov.sample();
end
endtask
endclass
Monitor
The monitor collects the DUT output and then gets the expected value from the score
board and compares them.
classmonitor;
scoreboard sb;
functionnew(virtualintf_cnt intf,scoreboard sb);

this.intf =intf;
this.sb =sb;
endfunction
taskcheck();
forever
@(negedgeintf.clk)
if(sb.store !=intf.count)// Get expected value from scoreboard and
compare with DUT output
$display(" * ERROR * DUT count is %b :: SB count is %b
",intf.count,sb.store );
else
$display(" DUT count is %b :: SB count is %b ",intf.count,sb.store );
endtask
endclass
Assertion Coverage
This block contains the assertion coverage related to 3 rd feature mentioned in
testplan.
moduleassertion_cov(intf_cnt intf);
Feature_3 :coverproperty(@(posedgeintf.clk)(intf.count !=0)|->intf.reset
==0);
endmodule
Scoreboard
This scoreboard is a simple one which stores one expected value.
classscoreboard;
bit[0:3]store;
endclass
Environment:
Environment contains instances of driver, monitor and scoreboard.
classenvironment;
driver drvr;
scoreboard sb;
monitor mntr;
functionnew(virtualintf_cnt intf);
this.intf =intf;
sb =new();
drvr =new(intf,sb);
mntr =new(intf,sb);
fork
mntr.check();
join_none
endfunction
endclass
Top:
The interface is declared and the test bench and DUT instances are taken. Testbench
and DUT are connected using interfaces.Clock is also generated and connects it to
DUT and testbench.
interfaceintf_cnt(inputclk);
wireclk;
wirereset;
wiredata;
wire[0:3]count;
endinterface
moduletop();
regclk =0;
initial// clock generator
forever#5clk =~clk;
// DUT/assertion monitor/testcase instances

intf_cnt intf(clk);
ones_counter DUT(clk,intf.reset,intf.data,intf.count);
testcase test(intf);
assertion_cov acov(intf);
endmodule
Tests:
This is a simple test case.It does reset and then send 10 input values.
programtestcase(intf_cnt intf);
environment env =new(intf);
initial
begin
env.drvr.reset();
env.drvr.drive(10);
end
endprogram
After simulating with this testcase, the coverage report I got
Total Coverage Summary
SCORE ASSERTGROUP
9.380.00 18.75
Cover group report
VARIABLE EXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHT
Feature_1 1610637.501001
Feature_211 0 0.001001
Assertion coverage report:
COVERPROPERTIESCATEGORYSEVERITYATTEMPTSMATCHESINCOMPLETE
Feature_300 1300
This coverage report will be different if you simulate in your tool.

To improve the coverage, than the 1st testcase , I wrote 2nd testcase with more input
values and also logic related to 3 feature in the testplan.
programtestcase(intf_cnt intf);
environment env =new(intf);
initial
begin
env.drvr.reset();
env.drvr.drive(100);
env.drvr.reset();
env.drvr.drive(100);
end
endprogram
Download the phase 1 files:
ones_counter.tar
Browse the code in ones_counter.tar
Run the simulation:
your_tool_command -f filelist test_1.sv
your_tool_command -f filelist test_2.sv
Simulation Log Report:
DUTcount is 0xxx ::SBcount is 0000
DUTcount is 0xxx ::SBcount is 0000
DUTcount is 0000::SBcount is 0000
*ERROR*DUTcount is 1111::SBcount is 0001
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TUTORIALS
VERIFICATION PLAN
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
The Verification Plan is the focal point for defining exactly what needs to be tested,
and drives the coverage criteria.Success of a verification project relies heavily on
the completeness and accurate implementation of a verification plan. A good plan
contains detailed goals using measurable metrics, along with optimal resource usage
and realistic schedule estimates. Verification plan gives an opportunity to present and
review the strategy for functional verification before the verification engineer have
gone into detail to implement it. It also establishes proper communication. Just
imagine how it would be working with a multisite project and you have a query for
which you have to wait till the next day to see the answer in email and they just call
you while you are in sleep.It also gives an idea about the areas that are going to be
difficult to verify for taking necessary steps.It is used to determine the progress and
completion of the verification phase of verification.Verification Planning should start
early with system/architecture evaluation phase.Once the functional spec is given to
the verification team, they will start its development.
A verification plan could come in many forms, such as a spreadsheet, a document or a
simple text file. Templates are good if continually used in your company as it makes
common interface for information, reviewer know where to look for certain
information even in a huge document that he wants to know at this moment, because
different reviewers want different infomation in different moments.
Generally Verification plan development is divided in two steps: What to verify and
How to verify?
VMM Ethernet sample Step one:What to Verify?
list of clearly defined features-to-verify. This is called feature extraction phase.
Step two:How to Verify?
After defining what exactly need to be verified, define how to verify them.
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Verification Plan Contains The Following:

Overview
Resources, Budget and Schedule
Verification Environment
System Verilog Verification Flow
Feature Extraction
Stimulus Generation Plan
Checker Plan
Coverage Plan
Details of reusable components
Specman E
Interview Questions
http://testbench.in/TS_24_VERIFICATION_PLAN.html[9/26/2012 2:21:48 PM]
Index
Asic Design
Need
Testbench
Linear Testbench
Linear Random
Testbench
How To Check The
Results
The Testbench Has
The Design
Statement Coverage
Block Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100
Nothing Less
Functional Coverage
Coverage Driven
Constraint Random
Verification Plan
input is what keeps
with time!
Overview
This section contains description of the project, what specification is followed, what
languages and methodology are used. Information related to the HW blocks, SW
blocks and HW/SW interaction is outlined.
Feature Extraction
This section contains list of all the features to be verified.Generally each feature is
associated with
1.Unique Name Id
2.Description
3.Expected result
4.Pointer to the specification
5.priority.
The "Unique name ID" should be descriptive in nature to understand the nature of the
feature and should be unique.For example,<module name>_<sub module>_<feature
number>_<feature name>
Some points on how extraction the features:
Read the MRD, System Specification, Macro and Micro Hardware Specification.
Go through the designer notes/presentations.
Annotate each line/paragraph specifying a functional item e.g.,read/write a
register
Annotate each line/paragraph specifying a multiple-functional itemse.g.,
steps required to set and cause an interrupt .
Identify all RTL configurations
Identify interfaces and related protocols across interface.
Identify standards compliance requirements, list corner cases.
Create a list of illegal scenarios to verify.
Create a list of exceptions to verify.
Create a list of operation sequences to verify e.g., interrupt followed by
breakpoint etc.
Create a list of things to try and break the machine.
Take advantage of existing plans.
Use points from compliance checklist for standard protocols.
Get information about the Common tests for all chips.
Get review by a number of people, usually very experienced engineers. Better
if you get reviewed by Architects, micro Architects, Leads, verification engineers, RTL
Designers, software designers, marketing team and other team members.
Resources, Budget And Schedule

This section contains details of man power required and schedule for each phase of
the verification. Information about the tools which are used for simulation, debugger
and bug tracking are listed.
A detailed TestBench architecture is essential for a robust verification
environment.In this section describe the topology, about each component of the
TestBench, special techniques that are used, IPs, Reused blocks, new blocks, and
guidelines on how to reuse the TestBench components.For example if you think
upfront about error injection, configuration, component communication, callbacks
etc, you can provide hooks to do those.
System Verilog Verification Flow
Details about each level (block, sub-system, system) and phases (RTL, gate) of
verification are mentioned.
The stimulus generation section contains information about different types of
transactions, sequences of transactions and various scenarios generated as per the
specification.
Each point is associated with
1.Unique name ID
2.Stimulus to be generated for driving into the DUT
3.Configuration/constraints Information
Checker Plan
This section will explain the expected result checking's in the TestBench. This can be
done in monitor/checker.
Various fields associated with each of the point are:
1.Checker Unique name
2.Unique Feature ID(Defined in Feature plan)
3.Checker Description
Coverage Plan
The coverage section explains the functional coverage of the features. A functional
coverage plan should be built to help implement coverage points in the verification
environment.Genarally it would be better if the coverage block is brocken based on
the design logical blocks.It will list the various Coverage groups and assertion.
Various fields of the coverage plan section are:
1.Coverage Group
2.Coverage Description
3.Coverage name
4.Unique name ID (Defined in feature plan)
5.Cover point (Items/cross/transition/assertion)
6.Coverage goal
Details Of Reusable Components
This section contains the details of reusable components and the description about
their usage.
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TUTORIALS
INTRODUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
ahe UVM (Universal Verification Methodology) Class Library provides the building
blocks needed to quickly develop well-constructed and reusable verification
components and test environments in SystemVerilog.
UVM library contains:

Component
classes
for
building
testbench
components
like
generator/driver/monitor etc.
Reporting classes for logging,
Factory for object substitution.
Synchronization classes for managing concurrent process.
Policy classes for printing, comparing, recording, packing, and unpacking of
uvm_object based classes.
TLM Classes for transaction level interface.
Sequencer and Sequence classes for generating realistic stimulus.
input is what keeps
And Macros which can be used for shorthand notation of complex implementation.
with time!
Easy Labs : UVM

Easy Labs : OVM
In this tutorial, we will learn some of the UVM concepts with examples.
Easy Labs : VMM

AVM Switch TB
Installing Uvm Library
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
1)Go to http://www.accellera.org/activities/vip/
2)Download the uvm*.tar.gz file.
3)Untar the file.
4)Go to the extracted directory: cd uvm*\uvm\src
5)Set the UVM_HOME path:setenv UVM_HOME `pwd`
(This is required to run the examples which are downloaded from this site)
6)Go to examples :cd../examples/hello_world/uvm/
7)Compile the example using :
your_tool_compilation_command -fcompile_<toolname>.f
(example for questasim use :qverilog -f compile_questa.f)
8)Run the example.
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/UT_01_INTRODUCTION.html[9/26/2012 2:21:56 PM]
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http://testbench.in/UT_01_INTRODUCTION.html[9/26/2012 2:21:56 PM]
Search
TUTORIALS
UVM TESTBENCH
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Uvm components, uvm env and uvm test are the three main building blocks of a
testbench in uvm based verification.
Uvm_env
uvm_env is extended from uvm_component and does not contain any extra
functionality. uvm_env is used to create and connect the uvm_components like driver,
monitors ,sequeners etc.A environment class can also be used as sub-environment
in another environment.As there is no difference between uvm_env and
uvm_component , we will discuss about uvm_component, in the next section.
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
VMM Tutorial
Verification Components
OVM Tutorial
uvm verification component classes are derived from uvm_component class which on This section - Your
provides features like hierarchy searching, phasing, configuration , reporting , factory input is what keeps
and transaction recording.
Easy Labs : SV
Easy Labs : UVM
with time!
Following are some of the uvm component classes

Easy Labs : OVM
uvm_agent
Easy Labs : VMM
uvm_monitor
AVM Switch TB
uvm_scoreboard
uvm_driver
VMM Ethernet sample
uvm_sequencer
Verilog
Verification
Verilog Switch TB
NOTE: uvm_env and uvm_test are also extended from uvm_component.

A typical uvm verification environment:
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
An agent typically contains three subcomponents: a driver, sequencer, and
http://testbench.in/UT_02_UVM_TESTBENCH.html[9/26/2012 2:22:06 PM]
monitor.If the agent is active, subtypes should contain all three subcomponents.If
the agent is passive, subtypes should contain only the monitor.
About Uvm_component Class:
uvm_compoenent class is inherited from uvm_report_object which is inherited from
uvm_object.
As I mentioned previously, uvm_component class provides features like hierarchy
searching, phasing, configuration , reporting , factory and transaction recording.
We will discuss about phasing concept in this section and rest of the features will be
discussed as separate topics.
UVM phases
UVM Components execute their behavior in strictly ordered, pre-defined phases. Each
phase is defined by its own virtual method, which derived components can override to
incorporate component-specific behavior. By default , these methods do nothing.
-->virtualfunctionvoidbuild()
This phase is used to construct various child components/ports/exports and configures
them.
-->virtualfunctionvoidconnect()
This phase is used for connecting the ports/exports of the components.
-->virtualfunctionvoidend_of_elaboration()
This phase is used for configuring the components if required.
-->virtualfunctionvoidstart_of_simulation()
This phase is used to print the banners and topology.
-->virtualtaskrun()
In this phase , Main body of the test is executed where all threads are forked off.
-->virtualfunctionvoidextract()
In this phase, all the required information is gathered.
-->virtualfunctionvoidcheck()
In this phase, check the results of the extracted information such as un responded
requests in scoreboard, read statistics registers etc.
-->virtualfunctionvoidreport()
This phase is used for reporting the pass/fail status.

Onlybuild() method is executed in top down manner. i.e after executing
parentbuild() method, child objects build() methods are executed.All other
methods are executed in bottom-up manner.The run() method is the only method
which is time consuming. The run() method is forked, so the order in which all
components run() method are executed is undefined.
Uvm_test
uvm_test is derived from uvm_component class and there is no extra functionality is
added.The advantage of used uvm_test for defining the user defined test is that the
test
case
selection
can
be
done
from
command
line
option
+UVM_TESTNAME=<testcase_string> . User can also select the testcase by passing the
testcase name as string to uvm_root::run_test(<testcase_string>)method.
In the above <testcase_string> is theobject type of the testcase class.
Lets implement environment for the following topology. I will describe the
implementation of environment , testcase and top module. Agent, monitor and driver
are implemented similar to environment.
1)Extend uvm_env class and define user environment.

classenv extendsuvm_env;
2)Declare the utility macro. This utility macro provides the implementation of create()
and get_type_name() methods and all the requirements needed for factory.
ùvm_component_utils(env)
3)Declare the objects for agents.
agent ag1;
agent ag2;
4)Define the constructor. In the constructor, call the super methods and pass the
parent object. Parent is the object in which environment is instantiated.
functionnew(stringname,uvm_component parent =null);
super.new(name,parent);
endfunction:new
5)Define build method. In the build method, construct the agents.
To construct agents, usecreate() method.The advantage of create() over new() is
that when create() method is called, it will check if there is a factory override and
constructs the object of override type.
functionvoidbuild();
super.build();
uvm_report_info(get_full_name(),"Build",UVM_LOW);
ag1 =agent::type_id::create("ag1",this);
endfunction
6)Define
connect(),end_of_elaboration(),start_of_simulation(),run(),extract(),check(),report()
methods.
Just print a message from these methods, as we dont have any logic in this example
to define.
functionvoidconnect();
uvm_report_info(get_full_name(),"Connect",UVM_LOW);
endfunction
Complete code of environment class:
ùvm_component_utils(env)
agent ag1;
agent ag2;
functionnew(stringname,uvm_component parent);
endfunction
uvm_report_info(get_full_name(),"Build",UVM_LOW);
endfunction
uvm_report_info(get_full_name(),"Connect",UVM_LOW);
endfunction
functionvoidend_of_elaboration();
uvm_report_info(get_full_name(),"End_of_elaboration",UVM_LOW);
endfunction
functionvoidstart_of_simulation();
uvm_report_info(get_full_name(),"Start_of_simulation",UVM_LOW);
endfunction
taskrun();
uvm_report_info(get_full_name(),"Run",UVM_LOW);
endtask
functionvoidextract();
uvm_report_info(get_full_name(),"Extract",UVM_LOW);
endfunction
functionvoidcheck();
uvm_report_info(get_full_name(),"Check",UVM_LOW);
endfunction
functionvoidreport();
uvm_report_info(get_full_name(),"Report",UVM_LOW);
endfunction
endclass
Now we will implement the testcase.

1)Extend uvm_test and define the test case
classtest1 extendsuvm_test;
2)Declare component ustilits using utility macro.
ùvm_component_utils(test1)
2)Declare environment class handle.

env t_env;
3)Define constructor method. In the constructor, call the super method and construct
the environment object.
functionnew(stringname="test1",uvm_component parent=null);
t_env =new("t_env",this);
endfunction:new
4)Define the end_of_elaboration method. In this method, call the print() method. This
print() method will print the topology of the test.
print();
endfunction
4)Define the run method and call the global_stop_request() method.
taskrun ();
#1000;
global_stop_request();
endtask:run
Testcase source code:
env t_env;
endfunction:new
print();
endfunction
taskrun ();
#1000;
endtask:run
endclass
Top Module:
To start the testbench, run_test() method must be called from initial block.
Run_test() mthod Phases all components through all registered phases.
moduletop;
initial
run_test();
endmodule
Download the source code
uvm_phases.tar
Browse the code in uvm_phases.tar
Command to run the simulation
VCS Users : make vcs

Questa Users: make questa
Log file:
[RNTST] Running test test1...
uvm_test_top.t_env [uvm_test_top.t_env] Build
uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Build
uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Build
uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Build
uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Connect
uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Connect
uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Connect
uvm_test_top.t_env [uvm_test_top.t_env] Connect
uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] End_of_elaboration
uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] End_of_elaboration
uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] End_of_elaboration
uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] End_of_elaboration
uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] End_of_elaboration
uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] End_of_elaboration
uvm_test_top.t_env [uvm_test_top.t_env] End_of_elaboration
uvm_test_top [uvm_test_top] End_of_elaboration
---------------------------------------------------------------------Name TypeSizeValue
---------------------------------------------------------------------uvm_test_top test1 -uvm_test_top@2
t_envenv - t_env@4
ag1agent - ag1@6
drvdriver-drv@12
rsp_port uvm_analysis_port - rsp_port@16
sqr_pull_portuvm_seq_item_pull_+ -sqr_pull_port@14
monmonitor -mon@10
ag2agent - ag2@8
drvdriver-drv@20
monmonitor -mon@18
uvm_test_top.t_env.ag1.drv[uvm_test_top.t_env.ag1.drv]Start_of_simulation
uvm_test_top.t_env.ag1.mon[uvm_test_top.t_env.ag1.mon]Start_of_simulation
uvm_test_top.t_env.ag1[uvm_test_top.t_env.ag1]Start_of_simulation
uvm_test_top.t_env.ag2.drv[uvm_test_top.t_env.ag2.drv]Start_of_simulation
uvm_test_top.t_env.ag2.mon[uvm_test_top.t_env.ag2.mon]Start_of_simulatio
..
..
..
..
Observe the above log report:
1)Build method was called in top-down fashion. Look at the following part of message.
uvm_test_top.t_env [uvm_test_top.t_env] Build
2)Connect method was called in bottopm up fashion. Look at the below part of log
file,

uvm_test_top.t_env [uvm_test_top.t_env] Connect
3)Following part of log file shows the testcase topology.
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TUTORIALS
UVM REPORTING
SystemVerilog
The uvm_report_object provides an interface to the UVM reporting facility.Through

this interface, components issue the various messages with different severity levels
that occur during simulation. Users can configure what actions are taken and what
file(s) are output for individual messages from a particular component or for all
messages from all components in the environment.
Verification
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A report consists of an id string, severity, verbosity level, and the textual message
itself. If the verbosity level of a report is greater than the configured maximum
verbosity level of its report object, it is ignored.
Reporting Methods:
Following are the primary reporting methods in the UVM.
virtualfunctionvoiduvm_report_info
(stringid,stringmessage,intverbosity=UVM_MEDIUM,stringfilename="",intline=0)
virtualfunctionvoiduvm_report_warning
(stringid,stringmessage,intverbosity=UVM_MEDIUM,stringfilename="",intline=0)
virtualfunctionvoiduvm_report_error
(stringid,stringmessage,intverbosity=UVM_LOW, stringfilename="",intline=0)
virtualfunctionvoiduvm_report_fatal
(stringid,stringmessage,intverbosity=UVM_NONE,stringfilename="",intline=0)
Arguments description:
Verilog
Verification
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RVM Ethernet sample
id -- a unique id to form a group of messages.

message -- The message text
verbosity -- the verbosity of the message, indicating its relative importance. If this
number is less than or equal to the effective verbosity level, then the report is issued,
subject to the configured action and file descriptor settings.
filename/line -- If required to print filename and line number from where the
message is issued, use macros, `__FILE__ and `__LINE__.
Actions:
These methods associate the specified action or actions with reports of the given
severity, id, or severity-id pair.
Specman E
Interview Questions
Following are the actions defined:

UVM_NO_ACTION -- Do nothing
UVM_DISPLAY -- Display report to standard output
UVM_LOG-- Write to a file
UVM_COUNT -- Count up to a max_quit_count value before exiting
UVM_EXIT -- Terminates simulation immediately
UVM_CALL_HOOK -- Callback the hook method .
Configuration:
http://testbench.in/UT_03_UVM_REPORTING.html[9/26/2012 2:22:14 PM]
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
Using these methods, user can set the verbosity levels and set actions.
functionvoidset_report_verbosity_level
(intverbosity_level)
functionvoidset_report_severity_action
(uvm_severity severity,uvm_action action)
functionvoidset_report_id_action
(stringid,uvm_action action)
functionvoidset_report_severity_id_action
(uvm_severity severity,stringid,uvm_action action)
Example
Lets see an example:
In the following example, messages from rpting::run() method are of different
verbosity level. In the top module, 3 objects of rpting are created and different
verbosity levels are set using set_report_verbosity_level() method.
ìnclude"uvm.svh"
importuvm_pkg::*;
classrpting extendsuvm_component;
ùvm_component_utils(rpting)
endfunction
taskrun();
uvm_report_info(get_full_name(),
"Info Message : Verbo lvl - UVM_NONE",UVM_NONE,`__FILE__,`__LINE__);
"Info Message : Verbo lvl - UVM_LOW ",UVM_LOW);
"Info Message : Verbo lvl - 150 ",150);
"Info Message : Verbo lvl - UVM_MEDIUM",UVM_MEDIUM);
uvm_report_warning(get_full_name(),
"Warning Messgae from rpting",UVM_LOW);
uvm_report_error(get_full_name(),
"Error Message from rpting \n\n",UVM_LOW);
endtask
endclass
moduletop;
rpting rpt1;
rpting rpt2;
rpting rpt3;
initialbegin
rpt1 =new("rpt1",null);
rpt1.set_report_verbosity_level(UVM_MEDIUM);
rpt2.set_report_verbosity_level(UVM_LOW);
rpt3.set_report_verbosity_level(UVM_NONE);
run_test();
end
endmodule
uvm_reporting.tar
Browse the code in uvm_reporting.tar
Log file:
UVM_INFO reporting.sv(13)@0:rpt1[rpt1]Info Message:Verbo lvl - UVM_NONE
UVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - UVM_LOW
UVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - 150
UVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - UVM_MEDIUM
UVM_WARNIN@0:rpt[rpt1] Warning Messgae from rpting
UVM_ERROR @0:rpt1[rpt1] Error Message from rpting
UVM_INFOreporting.sv(13)@0:rpt2[rpt2]Info Message:Verbo lvl - UVM_NONE
UVM_INFO@ 0:rpt2[rpt2] Info Message : Verbo lvl - UVM_LOW
UVM_WARNING@0:rpt2[rpt2] Warning Messgae from rpting
UVM_ERROR@0:rpt2[rpt2] Error Message from rpting
UVM_INFOreporting.sv(13)@0:rpt3[rpt3]Info Message:Verbo lvl - UVM_NONE
UVM_ERROR @ 9200 [TIMOUT] Watchdog timeout of '23f0' expired.
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Index
Introduction
Uvm Testbench
A transaction is data item which is eventually or directly processed by the DUT. The Uvm Reporting
packets, instructions, pixels are data items. In uvm, transactions are extended from Uvm Transaction
uvm_transactions class oruvm_sequence_item class. uvm_transaction is a typedef of Uvm Configuration
Uvm Factory
uvm_sequence_item.
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Example of a transaction:
Uvm Sequence 4
Uvm Sequence 5
classPacket extendsuvm_transaction;
Uvm Sequence 6
randbit[7:0]da;
Uvm Tlm 1
randbit[7:0]sa;
Uvm Tlm 2
randbit[7:0]length;
Uvm Callback
randbit[7:0]data[];
randbytefcs;
endclass
UVM TRANSACTION
Core Utilities:
uvm_transaction class is extended from uvm_object.uvm_transaction adds more
features line transaction recording , transaction idand timings of the transaction.
The methods used to model, transform or operate on transactions like print, copying,
cloning, comparing, recording, packing and unpacking are already defined in
VMM Ethernet sample uvm_object.
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FIG:UVM OBJECT UTILITIES

User Defined Implementations:
User should define these methods in the transaction using do_<method_name> and
call them using <method_name>.Following table shows calling methods and userdefined hook do_<method_name> methods.Clone and create methods, does not
usehook methods concepts.
http://testbench.in/UT_04_UVM_TRANSACTION.html[9/26/2012 2:22:22 PM]

input is what keeps
with time!
Shorthand Macros:
Using the field automation concept of uvm, all the above defines methods can be
defined automatically.
To use these field automation macros, first declare all the data fields, then place the
field
automation
macros
between
the
ùvm_object_utils_begin
and
ùvm_object_utils_end macros.
Example of field automation macros:
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]length;
randbit[7:0]data[];
randbytefcs;
ùvm_object_utils_begin(Packet)
ùvm_field_int(da,UVM_ALL_ON|UVM_NOPACK)
ùvm_field_int(sa,UVM_ALL_ON|UVM_NOPACK)
ùvm_field_int(length,UVM_ALL_ON|UVM_NOPACK)
ùvm_field_array_int(data,UVM_ALL_ON|UVM_NOPACK)
ùvm_field_int(fcs,UVM_ALL_ON|UVM_NOPACK)
ùvm_object_utils_end
endclass.
For most of the data types in systemverilog, uvm defined corresponding field
automation macros. Following table shows all the field automation macros.
Each ùvm_field_* macro has at least two arguments: ARG and FLAG.
ARG is the instance name of the variable and FLAG is used to control the field usage in
core utilities operation.
Following table shows uvm field automation flags:
By default, FLAG is set to UVM_ALL_ON. All these flags can be ored. Using NO_* flags,
can turn of particular field usage in a paerticuler method. NO_* flags takes
precedency over other flags.
Example of Flags:
The above macro will use the field "da" in all utilities methods except Packing and
unpacking methods.
Lets see a example:
In the following example, all the utility methods are defined using field automation
macros except Packing and unpacking methods.Packing and unpacking methods are
donein do_pack() amd do_unpack() method.
ìnclude"uvm.svh"
importuvm_pkg::*;
//Define the enumerated types for packet types
typedefenum{GOOD_FCS,BAD_FCS}fcs_kind_t;
randfcs_kind_t fcs_kind;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
constraintpayload_size_c {data.sizeinside{[1:6]};}
constraintlength_c {length ==data.size;}
functionnew(stringname="");
super.new(name);
endfunction:new
if(fcs_kind ==GOOD_FCS)
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();
endfunction:post_randomize
///// method to calculate the fcs /////

virtualfunctionbytecal_fcs;
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
result =result ^length;
for(i =0;i<data.size;i++)
result =result ^data[i];
result =fcs ^result;
returnresult;
endfunction:cal_fcs
functionvoiddo_pack(uvm_packer packer);
super.do_pack(packer);
packer.pack_field_int(da,$bits(da));
packer.pack_field_int(sa,$bits(sa));
packer.pack_field_int(length,$bits(length));
foreach(data[i])
packer.pack_field_int(data[i],8);
packer.pack_field_int(fcs,$bits(fcs));
endfunction:do_pack
functionvoiddo_unpack(uvm_packer packer);
intsz;
da =packer.unpack_field_int($bits(da));
sa =packer.unpack_field_int($bits(sa));
length =packer.unpack_field_int($bits(length));
data.delete();
data=new[length];
foreach(data[i])
data[i]=packer.unpack_field_int(8);
fcs =packer.unpack_field_int($bits(fcs));
endfunction:do_unpack
endclass:Packet
/////////////////////////////////////////////////////////
////Test to check the packet implementation////
/////////////////////////////////////////////////////////
moduletest;
Packet pkt1 =new("pkt1");
byteunsignedpkdbytes[];
initial
repeat(10)
if(pkt1.randomize)
begin
$display(" Randomization Sucessesfull.");
pkt1.print();
uvm_default_packer.use_metadata =1;
void'(pkt1.pack_bytes(pkdbytes));
$display("Size of pkd bits %d",pkdbytes.size());
pkt2.unpack_bytes(pkdbytes);
pkt2.print();
if(pkt2.compare(pkt1))
$display(" Packing,Unpacking and compare worked");
else
$display(" *** Something went wrong in Packing or Unpacking or compare ***
\n \n");
end
else
$display(" *** Randomization Failed ***");
endmodule
uvm_transaction.tar
Browse the code in uvm_transaction.tar
Log report:
Randomization Sucessesfull.
--------------------------------------------------------------------Name TypeSizeValue
--------------------------------------------------------------------pkt1 Packet-pkt1@3
da integral8'h1d
sa integral8'h26
length integral8 'h5
data da(integral)5 [0]integral8'hb1
[1]integral8'h3f
[2]integral8'h9e
[3]integral8'h38
[4]integral8'h8d
fcsintegral8'h9b
--------------------------------------------------------------------Size of pkd bits 9
--------------------------------------------------------------------pkt2 Packet-pkt2@5
da integral8'h1d
sa integral8'h26
[1]integral8'h3f
[2]integral8'h9e
[3]integral8'h38
[4]integral8'h8d
fcsintegral8'h9b
--------------------------------------------------------------------Packing,Unpacking and compare worked
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TUTORIALS
UVM CONFIGURATION
SystemVerilog
Verification
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Interface
OOPS
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UVM Tutorial
Configuration is amechanism in UVM that higher level components in a hierarchy can

configure the lower level components variables. Using set_config_* methods, user can
configure integer, string and objects of lower level components. Without this
mechanism, user should access the lower level component using hierarchy paths,
which restricts reusability. This mechanism can be used only with components.
Sequences and transactions cannot be configured using this mechanism. When
set_config_* method is called, the data is stored w.r.t strings in a table. There is also
a global configuration table.
Higher level component can set the configuration data in level component table. It is
the responsibility of the lower level component to get the data from the component
table and update the appropriate table.
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
VMM Tutorial
Set_config_* Methods:
OVM Tutorial
Following are the method to configure integer , string and object of uvm_object on This section - Your
input is what keeps
based class respectively.
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functionvoidset_config_int (stringinst_name,
stringfield_name,
uvm_bitstream_t value)
functionvoidset_config_string (stringinst_name,
stringfield_name,
VMM Ethernet sample stringvalue)
AVM Switch TB
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Verification
functionvoidset_config_object (stringinst_name,
stringfield_name,
uvm_object value,bitclone =1)
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string inst_name: Hierarchical string path.
string field_name: Name of the field in the table.
bitstream_t value: In set_config_int, a integral value that can be anything from 1
bit to 4096 bits.
bit clone : If this bit is set then object is cloned.
inst_name and field_name are strings of hierarchal path. They can include wile card
RVM Ethernet sample "*" and "?" characters. These methods must be called in build phase of the component.
Specman E
Interview Questions
"*"matches zero or more characters

"?"matches exactly one character
Some examples:
"*" -All the lower level components.
"*abc"-All the lower level components which ends with "abc".
Example: "xabc","xyabc","xyzabc" ....
http://testbench.in/UT_05_UVM_CONFIGURATION.html[9/26/2012 2:22:30 PM]

with time!
"abc*"-All the lower level components which startswith "abc".

Example: "abcx","abcxy","abcxyz" ....
"ab?" -All the lower level components which start with "ab" , then followed by one
more character.
Example: "abc","abb","abx" ....
"?bc" -All the lower level components which start with any one character,then
followed by "c".
Example: "abc","xbc","bbc" ....
"a?c" -All the lower level components which start with "a" , then followed by one
more character and then followed by "c".
Example: "abc","aac","axc" ..
There are two ways to get the configuration data:

1)Automatic : Using Field macros
2)Manual : using gte_config_* methods.
Automatic Configuration:
To use the atomic configuration, all the configurable fields should be defined using
uvm component field macros and uvm component utilities macros.
uvm component utility macros:
For non parameterized classes
ùvm_component_utils_begin(TYPE)
ùvm_field_*macro invocations here
ùvm_component_utils_end
For parameterized classes.
ùvm_component_param_utils_begin(TYPE)
For UVM Field macros, Refer to link
UVM_TRANSACTION
Example:
Following example is from link
UVM_TESTBENCH
2 Configurable fields, a integer and a string are defined in env, agent, monitor and
driver classes. Topology of the environment using these classes is
Driver class Source Code:

Similar to driver class, all other components env, agent and monitor are define.
classdriver extendsuvm_driver;
integerint_cfg;
stringstr_cfg;
ùvm_component_utils_begin(driver)
ùvm_field_int(int_cfg,UVM_DEFAULT)
ùvm_field_string(str_cfg,UVM_DEFAULT)
endfunction
super.build();
endfunction
endclass
Testcase:
Using set_config_int() and set_config_string() configure variables at various hierarchal
locations.
//t_env.ag1.drv.int_cfg
//t_env.ag1.mon.int_cfg
set_config_int("*.ag1.*","int_cfg",32);
//t_env.ag2.drv
set_config_int("t_env.ag2.drv","int_cfg",32);
//t_env.ag2.mon
set_config_int("t_env.ag2.mon","int_cfg",32);
//t_env.ag1.mon.str_cfg
//t_env.ag1.drv.str_cfg
set_config_string("*.ag?.*","str_cfg","pars");
//t_env.str_cfg
set_config_string("t_env","str_cfg","abcd");
uvm_configuration_1.tar
Browse the code in uvm_configuration_1.tar

From the above log report of th example, we can see the variables int_cfg and str_cfg
of all the components and they are as per the configuration setting from the testcase.
Manual Configurations:
Using get_config_* methods, user can get the required data if the data is available in
the table.
Following are the method to get configure data of type integer , string and object of
uvm_object based class respectively.
functionbitget_config_int (stringfield_name,
inoutuvm_bitstream_t value)
functionbitget_config_string (stringfield_name,
inoutstringvalue)
functionbitget_config_object (stringfield_name,
inoutuvm_object value,
inputbitclone =1)
If a entry is found in the table with "field_name" then data will be updated to "value"
argument . If entry is not found, then the function returns "0". So when these
methods are called, check the return value.
Example:
Driver class code:
classdriver extendsuvm_driver;
integerint_cfg;
stringstr_cfg;
ùvm_component_utils(driver)
endfunction
super.build();
void'(get_config_int("int_cfg",int_cfg));
void'(get_config_string("str_cfg",str_cfg));
$psprintf("int_cfg %0d : str_cfg %0s ",int_cfg,str_cfg),UVM_LOW);
endfunction
endclass
Log file
UVM_INFO @ 0: uvm_test_top.t_env
int_cfg x : str_cfg abcd
UVM_INFO @ 0: uvm_test_top.t_env.ag1
int_cfg x : str_cfg
UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv
int_cfg 32 : str_cfg pars
UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon
UVM_INFO @ 0: uvm_test_top.t_env.ag2
int_cfg x : str_cfg
UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv
UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon
Configuration Setting Members:

print_config_settings
functionvoidprint_config_settings
(stringfield="",
uvm_componentcomp=null,
bitrecurse=0)
This method prints all configuration information for this component.
If "field" is specified and non-empty, then only configuration settings matching that
field, if any, are printed.The field may not contain wildcards. If "recurse" is set, then
information for all children components are printed recursively.
print_config_matches
staticbitprint_config_matches =0
Setting this static variable causes get_config_* to print info about matching
configuration settings as they are being applied. These two members will be helpful
to know while debugging.
Log file
When print_config_settings method is called
uvm_test_top.t_env.ag1.drv
uvm_test_top.*.ag1.* int_cfg int 32
uvm_test_top.t_env.ag1.drv.rsp_port
uvm_test_top.*.ag?.* str_cfg stringpars
uvm_test_top.t_env.ag1.drv.rsp_port
uvm_test_top.t_env.ag1.drv.sqr_pull_port
uvm_test_top.*.ag?.* str_cfg stringpars
uvm_test_top.t_env.ag1.drv.sqr_pull_port
When print_config_matches is set to 1.
UVM_INFO @ 0: uvm_test_top.t_env [auto-configuration]
Auto-configuration matches for component uvm_test_top.t_env (env).
Last entry for a given field takes precedence.
Config set fromInstance Path Field name TypeValue
-----------------------------------------------------------------------------uvm_test_top(test1) uvm_test_top.t_env str_cfgstringabcd
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The factory pattern is an well known object-oriented design pattern. The factory
method design pattern defining a separate method for creating the objects. ,whose
subclasses can then override to specify the derived type of object that will be
created.
Using this method, objects are constructed dynamically based on the specification
type of the object. User can alter the behavior of the pre-build code without
modifying the code. From the testcase, user from environment or testcase can replace
any object which is at any hierarchy level with the user defined object.
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
For example: In your environment, you have a driver component. You would like the
extend the driver component for error injection scenario. After defining the extended
driver classwith error injection,how will youreplace the base driver component
which is deep in the hierarchy of your environment ? Using hierarchical path, you
could replace the driver object with the extended driver. This could not be easy if Report a Bug or Comment
there are many driver objects. Then you should also take care of its connections with on This section - Your
input is what keeps
the other components of testbenchs like scoreboard etc.
Easy Labs : UVM
One more example: In your Ethernet verification environment, you have different with time!
drivers to support different interfaces for 10mbps,100mps and 1G. Now you want to
Easy Labs : OVM
reuse the same environment for 10G verification.Inside somewhere deep in the
Easy Labs : VMM
hierarchy, while building the components, as a driver components ,your current
environment can only select 10mmps/100mps/1G drivers using configuration
AVM Switch TB
settings.How to add one more driver to the current drivers list of drivers so that
VMM Ethernet sample from the testcase you could configure the environment to work for 10G.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Using the uvm fatroy, it is very easy to solve the above two requirements.Only classs
extended from uvm_object and uvm_component are supported for this.
There are three basic steps to be followed for using uvm factory.
1) Registration
2) Construction
3) Overriding
The factory makes it is possible to override the type of uvm component /objector
instance of a uvm component/objectin2 ways. They are based on uvm
component/object type oruvm compoenent/objectname.
Registration:
While defining a class , its type has to be registered with the uvm factory. To do this
job easier, uvm has predefined macros.
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ùvm_component_utils(class_type_name)
ùvm_component_param_utils(class_type_name #(params))
ùvm_object_utils(class_type_name)
ùvm_object_param_utils(class_type_name #(params))
For uvm_*_param_utils are used for parameterized classes and other two macros for
non-parameterized class.Registration is required for name-based overriding , it is
not required for type-based overriding.
EXAMPLE: Example of above macros
http://testbench.in/UT_06_UVM_FACTORY.html[9/26/2012 2:22:39 PM]
classpacket extendsuvm_object;
ùvm_object_utils(packet)
endclass
classpacket #(typeT=int,intmode=0)extendsuvm_object;
ùvm_object_param_utils(packet #(T,mode))
endclass
classdriver extendsuvm_component;
ùvm_component_utils(driver)
endclass
classmonitor #(typeT=int,intmode=0)extendsuvm_component;
ùvm_component_param_utils(driver#(T,mode))
endclass
Construction:
To construct a uvm based component or uvm based objects, static method create()
should be used. This function constructs the appropriate object based on the
overrides and constructs the object and returns it. So while constructing the uvm
based components or uvm based objects , do not use new() constructor.
Syntax :
staticfunctionT create(stringname,
uvm_component parent,
stringcontext=" ")
The Create() function returns an instance of the component type, T, represented by
this proxy, subject to any factory overrides based on the context provided by the
parents full name.The context argument, if supplied, supersedes the parents
context.The new instance will have the given leaf name and parent.
EXAMPLE:
class_type object_name;
object_name =clss_type::type_id::creat("object_name",this);
For uvm_object based classes, doesnt need the parent handle as second argument.
Overriding:
If required, user could override the registered classes or objects. User can override
based of name string or class-type.
There are 4 methods defined for overriding:
functionvoidset_inst_override_by_type
(uvm_object_wrapper original_type,
uvm_object_wrapper override_type,
stringfull_inst_path )
The above method is used to override the object instances of "original_type" with
"override_type" . "override_type" is extended from"original_type".
functionvoidset_inst_override_by_name
(stringoriginal_type_name,
stringoverride_type_name,
Original_type_name and override_type_name are the class names which are registered
in the factory. All the instances of objects with name "Original_type_name" will be
overriden
with
objects
of
name
"override_type_name"
using
set_inst_override_by_name() method.
functionvoidset_type_override_by_type
(uvm_object_wrapper original_type,
uvm_object_wrapper override_type,
bitreplace =1)
Using the above method, request to create an object oforiginal_type can be
overriden with override_type.
functionvoidset_type_override_by_name
bitreplace =1)
Using the above method, request to create an object oforiginal_type_name can be
overriden with override_type_name.
When multiple overrides are done , then using the argument "replace" , we can
control whether to override the previous override or not. If argument "replace" is 1,
then previous overrides will be replaced otherwise, previous overrides will remain.
print() method, prints the state of the uvm_factory, registered types, instance
overrides, and type overrides.
Now we will see a complete example. This example is based on the environment build
in topic UVM TESTBENCH . Refer to that section for more information about this
example.
Lets look at the 3 steps which I discussed above using the example defined in UVM
TESTBENCH
1) Registration
In all the class, you can see the macroùvm_component_utils(type_name)
2) Construction
In file agant.sv file,monitor and driver are constructed using create() method.
mon =monitor::type_id::create("mon",this);
drv =driver::type_id::create("drv",this);
3)In this example, a one testcase is already developed in topic UVM_TESTBENCH.
There are no over rides in this test case.
Topology of this test environment is shown below.
In this example, there is one driver class and one monitor class.In this testcase , By
extending driver class , we will define driver_2 class and by extending monitor class,
we will define monitor_2 class.
From the testcase , Using set_type_override_by_type, we will override driver with
driver_2 and Using set_type_override_by_name, we will override monitor with
monitor_2.
To know about the overrides which are done, call factory.print() method of factory
class.
classdriver_2 extendsdriver;
ùvm_component_utils(driver_2)
endfunction
endclass
classmonitor_2 extendsmonitor;
ùvm_component_utils(monitor_2)
endfunction
endclass
classtest_factory extendsuvm_test;
ùvm_component_utils(test_factory)
env t_env;
factory.set_type_override_by_type(driver::get_type(),driver_2::get_type(),"*");
factory.set_type_override_by_name("monitor","monitor_2","*");
factory.print();
endfunction:new
print();
endfunction:end_of_elaboration
taskrun ();
#1000;
endtask:run
endclass
Download the example:
uvm_factory.tar
Browse the code in uvm_factory.tar
Command to simulate
Command to run the example with the testcase which is defined above:
Method factory.print() displayed all the overrides as shown below in the log file.
#### Factory Configuration (*)

No instance overrides are registered with this factory
Type Overrides:
Requested TypeOverride Type
--------------------------driverdriver_2
monitor monitor_2
In the below text printed by print_topology() method ,we can see overridden driver
and monitor.
--------------------------------------------------------------------uvm_test_top test_factory-uvm_test_top@2
t_envenv - t_env@4
ag1agent - ag1@6
drvdriver_2-drv@12
monmonitor_2 -mon@10
ag2agent - ag2@8
drvdriver_2-drv@20
---------------------------------------------------------------------
In the below text printed by print_topology() method ,with testcase test1 which does
note have overrides.
Command to run this example with test1 is
--------------------------------------------------------------------uvm_test_top test1 -uvm_test_top@2
t_envenv - t_env@4
ag1agent - ag1@6
drvdriver-drv@12

monmonitor -mon@10
ag2agent - ag2@8
drvdriver-drv@20
monmonitor -mon@18
---------------------------------------------------------------------
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TUTORIALS
UVM SEQUENCE 1
SystemVerilog
Introduction
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
A sequence is a series of transaction.User can define the complex stimulus.

sequences can be reused, extended, randomized, and combined sequentially and
hierarchically in various ways.
For example, for a processor, lets say PUSH_A,PUSH_B,ADD,SUB,MUL,DIV and POP_C

are the instructions. If the instructions are generated randomly, then to excursing a
meaningful operation like "adding 2 variables" which requires a series of transaction
"PUSH_APUSH_BADDPOP_C " will take longer time. By defining these series of
"PUSH_APUSH_BADDPOP_C ", it would be easy to exercise the DUT.
Advantages of uvm sequences :
Sequences can be reused.
Stimulus generation is independent of testbench.
Easy to control the generation of transaction.
Sequences can be combined sequentially and hierarchically.
A complete sequence generation requires following 4 classes.
1- Sequence item.
2- Sequence
3- Sequencer
4- Driver
uvm_sequence_item :
User
has
to
define
a
transaction
by
extending
uvm_sequence_item.uvm_sequence_item class provides the basic functionality for
objects, both sequence items and sequences, to operate in the sequence mechanism.
For more information aboutuvm_sequence_itemRefer to link
UVM_TRANSACTION
uvm_sequence:
User should extend uvm_sequence class and define the construction of sequence of
transactions. These transactions can be directed, constrained randomized or fully
randomized. The uvm_sequence class provides the interfaces necessary in order to
create streams of sequence items and/or other sequences.
virtualclassuvm_sequence #(
typeREQ=uvm_sequence_item,
typeRSP=REQ
)
Interview Questions
uvm_sequencer:
uvm_sequencer is responsible for the coordination between sequence and driver.
Sequencer sends the transaction to driver and gets the response from the driver. The
response transaction from the driver is optional. When multiple sequences are running
in parallel, then sequencer is responsible for arbitrating between the parallel
sequences. There are two types of sequencers : uvm_sequencer and
uvm_push_sequencer
http://testbench.in/UT_07_UVM_SEQUENCE_1.html[9/26/2012 2:22:50 PM]
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
classuvm_sequencer #(
typeRSP=REQ
)
classuvm_push_sequencer #(
typeRSP=REQ
)
uvm driver:
User should extend uvm_driver class to define driver component. uvm driver is a
component that initiate requests for new transactions and drives it to lower level
components. There are two types of drivers: uvm_driver and uvm_push_driver.
classuvm_driver #(
typeRSP=REQ
)
classuvm_push_driver #(
typeRSP=REQ
)
In pull mode , uvm_sequencer is connected to uvm_driver
modeuvm_push_sequencer is connectd to uvm_push_driver.
in push
uvm_sequencer and uvm_driver are parameterized components with request and

response transaction types. REQ and RSP types by default are uvm_sequence_type
types. User can specify REQ and RSP of different transaction types. If user specifies
only REQ type, then RSP will be REQ type.
Sequence And Driver Communication:
The above image shows how a transaction from a sequence is sent to driver and the
response from the driver is sent to sequencer.There are multiple methods called
during this operation.
First when the body() method is called
1) A transaction is created using "create()" method. If a transaction is created using
"create()" method, then it can be overridden if required using uvm factory.
2) After a transaction is created, wait_for_grant() method is called. This method is
blocking method.
3) In the run task of the driver, when "seq_item_port.get_next_item()" is called, then

the sequencer un blocks wait_for_grant() method. If more than one sequence is
getting executed by sequencer, then based on arbitration rules, un blocks the
wait_for_grant() method.
4) After the wait_for_grant() un blocks, then transaction can be randomized, or its
properties can be filled directly. Then using the send_request() method, send the
transaction to the driver.
5) After calling the send_request() method, "wait_for_item_done()" method is called.
This is a blocking method and execution gets blocks at this method call.
6) The transaction which is sent from sequence , in the driver this transaction is
available as "seq_item_port.get_next_item(req)" method argument. Then driver can
drive this transaction to bus or lower level.
7) Once the driver operations are completed, thenby calling
"seq_item_port.put(rsp)", wait_for_item_done() method of sequence gest unblocked.
Using get_responce(res), the response transaction from driver is taken by sequence
and processes it.
After this step, again the steps 1 to 7 are repeated five times.
If a response from driver is not required, then steps 5,6,7 can be skipped and
item_done() method from driver should be called as shown in above image.
Simple Example
Lest write an example: This is a simple example ofprocessor instruction. Various
instructions
which
are
supported
by
the
processor
are
PUSH_A,PUSH_B,ADD,SUB,MUL,DIV and POP_C.
Sequence Item
1) Extend uvm_sequence_item and define instruction class.
classinstruction extendsuvm_sequence_item;
2) Define the instruction as enumerated types and declare a variable of instruction
enumerated type.
typedefenum{PUSH_A,PUSH_B,ADD,SUB,MUL,DIV,POP_C}inst_t;
randinst_t inst;
3) Define operational method using uvm_field_* macros.
ùvm_object_utils_begin(instruction)
ùvm_field_enum(inst_t,inst,UVM_ALL_ON)
4) Define the constructor.
functionnew(stringname="instruction");
super.new(name);
endfunction
Sequence item code:
randinst_t inst;
super.new(name);
endfunction
endclass
Sequence
We will define a operation addition using uvm_sequence. The instruction sequence
should be "PUSH APUSH BADDPOP C".
1) Define a sequence by extending uvm_sequence. Set REQ parameter to "instruction"

type.
classoperation_addition extendsuvm_sequence #(instruction);
functionnew(stringname="operation_addition");
super.new(name);
endfunction
3) Lets name the sequencer which we will develop is "instruction_sequencer".
Using the ùvm_sequence_utils macro, register the "operation_addition" sequence
with "instruction_sequencer" sequencer. This macro adds the sequence to the
sequencer list. This macro will also register the sequence for factory overrides.
ùvm_sequence_utils(operation_addition,instruction_sequencer)
4)
In the body() method, first call wait_for_grant(), then construct a transaction and set
the instruction enum to PUSH_A . Then send the transaction to driver using
send_request() method. Then call the wait_for_item_done() method. Repeat the
above steps for other instructions PUSH_B, ADD and POP_C.
For construction of a transaction, we will use the create() method.

virtualtaskbody();
req =instruction::type_id::create("req");
wait_for_grant();
assert(req.randomize()with{
inst ==instruction::PUSH_A;
});
send_request(req);
wait_for_item_done();
//get_response(res); This is optional. Not using in this example.
wait_for_grant();
req.inst =instruction::PUSH_B;
send_request(req);
//get_response(res);
wait_for_grant();
req.inst =instruction::ADD;
send_request(req);
wait_for_grant();
req.inst =instruction::POP_C;
send_request(req);
endtask
Sequence code
classoperation_addition extendsuvm_sequence #(instruction);
instruction req;
super.new(name);
endfunction
ùvm_sequence_utils(operation_addition,instruction_sequencer)
virtualtaskbody();
wait_for_grant();
});
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
endtask
endclass
Sequencer:
uvm_sequence hasa property called default_sequence. Default sequence is a
sequence which will be started automatically. Using set_config_string, user can
override the default sequence to any user defined sequence, so that when a
sequencer is started, automatically a user defined sequence will be started.If over
rides are not done with user defined sequence, then a random transaction are
generated.Using "start_default_sequence()" method, "default_sequence" can also be
started.
uvm sequencer has seq_item_export and res_export tlm ports for connecting to uvm
driver.
1) Define instruction_sequencer by extending uvm_sequencer.
classinstruction_sequencer extendsuvm_sequencer #(instruction);
Inside the constructor, place the macro ùvm_update_sequence_lib_and_item().
This macro creates 3 predefined sequences. We will discuss about the predefined
sequences in next section.

ùvm_update_sequence_lib_and_item(instruction)
endfunction
3) Place the uvm_sequencer_utils macro. This macro registers the sequencer for
factory overrides.
ùvm_sequencer_utils(instruction_sequencer)
Sequencer Code;
endfunction
endclass
Driver:
uvm_driver is a class which is extended from uvm_componenet. This driver is used in
pull mode. Pull mode means, driver pulls the transaction from the sequencer when it
requires.
uvm driver has 2 TLM ports.
1) Seq_item_port: To get a item from sequencer, driver uses this port. Driver can also
send response back using this port.
2) Rsp_port :This can also be used to send response back to sequencer.
Seq_item_port methods:
Lets implement a driver:

1) Define a driver which takes the instruction from the sequencer and does the
processing. In this example we will just print the instruction type and wait for some
delay.
classinstruction_driver extendsuvm_driver #(instruction);
2) Place the uvm_component_utils
get_type_name and create.
macro
ùvm_component_utils(instruction_driver)
3) DefineConstructor method.
to
define
virtual
methods like
endfunction
4) Define the run() method. Run() method is executed in the "run phase". In this
methods, transactions are taken from the sequencer and drive them on to dut
interface or to other components.
Driver
class
has
a
port
"seq_item_port".
Using
the
method
seq_item_port.get_next_item(), get the transaction from the sequencer and process
it.Once the processing is done, using the item_done() method, indicate to the
sequencer that the request is completed. In this example, after taking the
transaction, we will print the transaction and wait for 10 units time.
taskrun ();
while(1)begin
seq_item_port.get_next_item(req);
$display("%0d: Driving Instruction%s",$time,req.inst.name());
#10;
seq_item_port.item_done();
end
endtask
endclass
Driver class code:
// Provide implementations of virtual methods such as get_type_name and create
// Constructor
endfunction
taskrun ();
foreverbegin
#10;
// rsp.set_id_info(req); These two steps are required only if
// seq_item_port.put(esp); responce needs to be sent back to sequence
end
endtask
endclass
Driver And Sequencer Connectivity:
Deriver and sequencer are connected using TLM. uvm_driver has seq_item_port which
is used to get the transaction from uvm sequencer. This port is connected to
uvm_sequencer
seq_item_exportUsing
"<driver>.seq_item_port.connect(<sequencer>.seq_item_export);"
driver
and
sequencer can be connected. Simillarly"res_port" of driver which is used to send
response from driver to sequencer is connected to "res_export" of the sequencer using
""<driver>.res_port.connect(<sequencer>.res_export);".
Testcase:
This testcase is used only for the demo purpose of this tutorial session. Actually, the
sequencer and the driver and instantiated and their ports are connected in a agent
component and used.Lets implement a testcase
1) Take instances of sequencer and driver and construct both components.
sequencer =new("sequencer",null);
sequencer.build();
driver =new("driver",null);
driver.build();
2)
Connect the seq_item_export to the drivers seq_item_port.
driver.seq_item_port.connect(sequencer.seq_item_export);
3) Using set_confg_string() method, set the default sequence of the sequencer to
"operation_addition". Operation_addition is the sequence which we defined previous.
set_config_string("sequencer","default_sequence","operation_addition");
4) Using the start_default_sequence() method of the sequencer, start the default
sequence of the sequencer. In the previous step we configured the addition operation
as default sequene. When you run the simulation, you will see the PUSH_A,PUSH_B
ADD and POP_C series of transaction.
sequencer.start_default_sequence();
Testcase Code:
moduletest;
instruction_sequencer sequencer;
instruction_driver driver;
initialbegin
sequencer.build();
driver.build();
sequencer.print();
fork
begin
run_test();
end
#2000global_stop_request();
join
end
endmodule
uvm_basic_sequence.tar
Browse the code in uvm_basic_sequence.tar
Command to simulate
Log file Output
UVM_INFO @ 0 [RNTST] Running test ...
0: Driving InstructionPUSH_A
10: Driving InstructionPUSH_B
20: Driving InstructionADD
30: Driving InstructionPOP_C
From the above log , we can see that transactions are generates as we defined in uvm
sequence.
<< PREVIOUS PAGE
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Index
Introduction
Uvm Testbench
Uvm Reporting
Pre Defined Sequences:
Uvm Transaction
Uvm Configuration
Every sequencer in uvm has 3 pre defined sequences. They are
Uvm Factory
Uvm Sequence 1
1)uvm_random_sequence
Uvm Sequence 2
2)uvm_exhaustive_sequence.
Uvm Sequence 3
3)uvm_simple_sequence
Uvm Sequence 4
All the user defined sequences which are registered by user and the above three Uvm Sequence 5
predefined sequences are stored in sequencer queue.
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
UVM SEQUENCE 2
VMM Tutorial

input is what keeps
with time!
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
uvm_random_sequence :
This sequence randomly selects and executes a sequence from the sequencer
sequence
library,
excluding
uvm_random_sequence
itself,
and
uvm_exhaustive_sequence. From the above image, from sequence id 2 to till the last
sequence, all the sequences are executed randomly.If the "count" variable of the
sequencer is set to 0, then non of the sequence is executed. If the "count" variable of
the sequencer is set to -1, then some random number of sequences from 0 to
"max_random_count" are executed. By default "max_random_count" is set to
10."Count" and "max_random_count" can be changed using set_config_int().
The sequencer when automatically started executes the sequence which is point by
By
defaultdefault_sequence
variable
points to
uvm_random_sequence.
RVM Ethernet sample default_sequence.
Specman E
uvm_exhaustive_sequence:
Interview Questions
This sequence randomly selects and executes each sequence from the sequencers
sequence library once in a randc style, excluding itself and uvm_random_sequence.
uvm_simple_sequence:
This sequence simply executes a single sequence item.
In the previous example from UVM_SEQUENCE_1 section.
The print() method of the sequencer in that example printed the following
--------------------------------------------------------------------sequencerinstruction_sequen+ - sequencer@2
rsp_export uvm_analysis_export -rsp_export@4
seq_item_exportuvm_seq_item_pull_+ -seq_item_export@28
default_sequence string18 operation_addition
countintegral32 -1
max_random_count integral32 'd10
sequencesarray 4 [0]string19uvm_random_sequence
[1]string23 uvm_exhaustive_sequ+
[2]string19uvm_simple_sequence
[3]string18 operation_addition
max_random_depth integral32'd4
num_last_reqsintegral32'd1
num_last_rspsintegral32'd1
---------------------------------------------------------------------
Some observations from the above log:

The countis set to -1.The default sequencer is set to operations_addition. There
are 3 predefined sequences and 1 user defined sequence.
Lets look at a example: In the attached example, in file sequence.sv file, there are 4
seuqneces,
they
are
operation_addition,
operation_subtraction,
operation_multiplication.
In the testcase.sv file, the "default_seuence" is set to "uvm_exhaustive_sequence"
using the set_config_string.
set_config_string("sequencer", "default_sequence", "uvm_exhaustive_sequence");
Download the example
uvm_sequence_1.tar
Browse the code in uvm_sequence_1.tar
Command to run the summation
Log File
10: Driving
20: Driving
30: Driving
40: Driving
InstructionPUSH_A
InstructionPUSH_B
InstructionSUB
InstructionPOP_C
50: Driving
60: Driving
70: Driving
80: Driving
InstructionPUSH_A
InstructionPUSH_B
InstructionMUL
InstructionPOP_C

From the above log , we can see that all the 3 user defined sequences and predefined
uvm_simple_sequence are executed.
Sequence Action Macro:

In the previous sections, we have seen the implementation of body() method of
sequence. The body() method implementation requires some steps.We have seen
these steps asCreation of item, wait for grant, randomize the item, send the item.
All these steps have be automated using "sequence action macros". There are some
more additional steps added in these macros. Following are the steps defined with the
"sequence action macro".
Pre_do(), mid_do() and post_do() are callback methods which are in uvm sequence.If
user is interested , he can use these methods. For example, inmid_do() method, user
can print the transaction orthe randomized transaction can be fined tuned.These
methods should not be clled by user directly.
Syntax:
virtualtaskpre_do(bitis_item)
virtualfunctionvoidmid_do(uvm_sequence_item this_item)
virtualfunctionvoidpost_do(uvm_sequence_item this_item)
Pre_do() is a task , ifthe method consumes simulation cycles, the behavior may be
unexpected.
Example Of Pre_do,Mid_do And Post_do
Lets look at a example: We will define a sequence using ùvm_do macro. This macro
has all the above defined phases.
1)Define the body method using the ùvm_do() macro. Before and after this macro,
just call messages.
virtualtaskbody();
"Seuqnce Action Macro Phase: Before uvm_do macro ",UVM_LOW);
ùvm_do(req);
"Seuqnce Action Macro Phase: After uvm_do macro ",UVM_LOW);
endtask
2)Define pre_do() method. Lets just print a message from this method.
virtualtaskpre_do(bitis_item);
"Seuqnce Action Macro Phase: PRE_DO ",UVM_LOW);
endtask
3)Define mid_do() method. Lets just print a message from this method.
virtualfunctionvoidmid_do(uvm_sequence_item this_item);
"Seuqnce Action Macro Phase: MID_DO ",UVM_LOW);
endfunction
4)Define post_do() method. Lets just print a message from this method.
virtualfunctionvoidpost_do(uvm_sequence_item this_item);
"Seuqnce Action Macro Phase: POST_DO ",UVM_LOW);
endfunction
Complet sequence code:
classdemo_uvm_do extendsuvm_sequence #(instruction);
instruction req;
functionnew(stringname="demo_uvm_do");
super.new(name);
endfunction
ùvm_sequence_utils(demo_uvm_do,instruction_sequencer)
"Seuqnce Action Macro Phase: PRE_DO ",UVM_LOW);
endtask
virtualfunctionvoidmid_do(uvm_sequence_item this_item);
"Seuqnce Action Macro Phase: MID_DO ",UVM_LOW);
endfunction
virtualfunctionvoidpost_do(uvm_sequence_item this_item);
"Seuqnce Action Macro Phase: POST_DO ",UVM_LOW);
endfunction
virtualtaskbody();
"Seuqnce Action Macro Phase: Before uvm_do macro ",UVM_LOW);
ùvm_do(req);
"Seuqnce Action Macro Phase: After uvm_do macro ",UVM_LOW);
endtask
endclass
uvm_sequence_2.tar
Log file report:
UVM_INFO@0:reporter[sequencer.demo_uvm_do]
Seuqnce Action Macro Phase: Before uvm_do macro
Seuqnce Action Macro Phase: PRE_DO
Seuqnce Action Macro Phase: MID_DO
0: Driving InstructionMUL
Seuqnce Action Macro Phase: POST_DO
Seuqnce Action Macro Phase: After uvm_do macro
The above log file shows themessages from pre_do,mid_do and post_do methods.
List Of Sequence Action Macros:
These macros are used to start sequences and sequence items that were either
registered with a <ùvm-sequence_utils> macro or whose associated sequencer was
already set using the <set_sequencer> method.
ùvm_create(item/sequence)
This action creates the item or sequence using the factory. Only the create phase will
be executed.
ùvm_do(item/sequence)
This macro takes as an argument a uvm_sequence_item variable or sequence . All the
above defined 7 phases will be executed.
ùvm_do_with(item/sequence, Constraint block)
This is the same as ùvm_do except that the constraint block in the 2nd argument is
applied to the item or sequence in a randomize with statement before execution.
ùvm_send(item/sequence)
Create phase and randomize phases are skipped, rest all the phases will be executed.
Using ùvm_create, create phase can be executed.Essentially, an ùvm_do without
the create or randomization.
ùvm_rand_send(item/sequence)
Only create phase is skipped. rest of all the phases will be executed. User should use
ùvm_create to create the sequence or item.
ùvm_rand_send_with(item/sequence , Constraint block)
ùvm_create to create the sequence or item.Constraint block will be applied which
randomization.
ùvm_do_pri(item/sequence, priority )
This is the same as ùvm_do except that the sequence item or sequence is executed
with the priority specified in the argument.
ùvm_do_pri_with(item/sequence , constraint block , priority)
This is the same as ùvm_do_pri except that the given constraint block is applied to
the item or sequence in a randomize with statementbefore execution.
ùvm_send_pri(item/sequence,priority)
This is the same as ùvm_send except that the sequence item or sequence is executed
ùvm_rand_send_pri(item/sequence,priority)
This is the same as ùvm_rand_send except that the sequence item or sequence is
executed with the priority specified in the argument.
ùvm_rand_send_pri_with(item/sequence,priority,constraint block)
This is the same as ùvm_rand_send_pri except that the given constraint block is
Followingmacros are used on sequence or sequence items on a different sequencer.
ùvm_create_on(item/sequence,sequencer)
This is the same as ùvm_create except that it also sets the parent sequence to the
sequence in which the macro is invoked, and it sets the sequencer to the specified
sequencer argument.
ùvm_do_on(item/sequence,sequencer)
This is the same as ùvm_do except that it also sets the parent sequence to the
sequencerargument.
ùvm_do_on_pri(item/sequence,sequencer, priority)
This is the same as ùvm_do_pri except that it also sets the parent sequence to the
sequencerargument.
ùvm_do_on_with(item/sequence,sequencer, constraint block)
This is the same as ùvm_do_with except that it also sets the parent sequence to the
sequence in which the macro is invoked, and it sets thesequencer to the specified
sequencerargument.The user must supply brackets around the constraints.
ùvm_do_on_pri_with(item/sequence,sequencer,priority,constraint block)
This is the same as ùvm_do_pri_with except that it also sets the parent sequence to
the sequence in which the macro is invoked, and it sets the sequencer to the specified
sequencer argument.
Examples With Sequence Action Macros:
virtualtaskbody();
"Executing Sequence Action Macro uvm_do",UVM_LOW);
ùvm_do(req)
endtask
virtualtaskbody();
"Executing Sequence Action Macro uvm_do_with ",UVM_LOW);
ùvm_do_with(req,{inst ==ADD;})
endtask
virtualtaskbody();
"Executing Sequence Action Macro uvm_create and uvm_send",UVM_LOW);
ùvm_create(req)
ùvm_send(req)
endtask
virtualtaskbody();
"Executing
Sequence
Action
Macro
uvm_create
and
uvm_rand_send",UVM_LOW);
ùvm_create(req)
ùvm_rand_send(req)
endtask

uvm_sequence_3.tar
Command to sun the simulation

Log file report
UVM_INFO@10:reporter[***]Executing Sequence Action Macro uvm_do_with
UVM_INFO@20:reporter[***]Executing Sequence Action Macro uvm_create
uvm_send
UVM_INFO@30:reporter[***]Executing Sequence Action Macro uvm_do
30: Driving InstructionDIV
UVM_INFO@40:reporter[***]Executing Sequence Action Macro uvm_create
uvm_rand_send
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and
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TUTORIALS
UVM SEQUENCE 3
SystemVerilog
Body Callbacks:
Verification
Constructs
Interface
OOPS
Randomization
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Assertion
DPI
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VMM Tutorial
OVM Tutorial
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uvm sequences has two callback methods pre_body() and post_body(), which are
executed before and after the sequence body() method execution. These callbacks
are called only when start_sequence() of sequencer or start() method of the sequence
is called. User should not call these methods.
virtualtaskpre_body()
virtualtaskpost_body()
Example
In this example, I just printed messages from pre_body() and post_body() methods.
These methods can be used for initialization, synchronization with some events or
cleanup.
classdemo_pre_body_post_body extendsuvm_sequence #(instruction);
instruction req;
Easy Labs : VMM

functionnew(stringname="demo_pre_body_post_body");
super.new(name);
AVM Switch TB
endfunction
VMM Ethernet sample
ùvm_sequence_utils(demo_pre_body_post_body,instruction_sequencer)
Easy Labs : OVM
Verilog
Verification
Verilog Switch TB
Basic Constructs
virtualtaskpre_body();
uvm_report_info(get_full_name()," pre_body() callback ",UVM_LOW);
endtask
virtualtaskpost_body();
uvm_report_info(get_full_name()," post_body() callback ",UVM_LOW);
endtask
OpenVera
virtualtaskbody();
"body() method: Before uvm_do macro ",UVM_LOW);
Switch TB
ùvm_do(req);
RVM Switch TB
RVM Ethernet sample "body() method: After uvm_do macro ",UVM_LOW);
endtask
endclass
Constructs
Specman E
Interview Questions
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback

uvm_sequence_4.tar

input is what keeps
with time!
Log file report

UVM_INFO @ 0: reporter [***]pre_body() callback
UVM_INFO @ 0: reporter [***] body() method: Before uvm_do macro
0: Driving InstructionSUB
UVM_INFO @ 10: reporter [***] body() method: After uvm_do macro
UVM_INFO @ 10: reporter [***]post_body() callback
Hierarchical Sequences
One main advantage of sequences is smaller sequences can be used to create
sequences to generate stimulus required for todays complex protocol.
To create a sequence using another sequence, following steps has to be done
1)Extend the uvm_sequence class and define a new class.
2)Declare instances of child sequences which will be used to create new sequence.
3)Start the child sequence using <instance>.start() method in body() method.
Sequential Sequences
To executes child sequences sequentially, child sequence start() method should be
called sequentially in body method.
In the below example you can see all the 3 steps mentioned above.
In this example, I have defined 2 child sequences. These child sequences can be used
as normal sequences.
Sequence 1 code:
This sequence generates 4 PUSH_A instructions.
virtualtaskbody();
repeat(4)begin
ùvm_do_with(req,{inst ==PUSH_A;});
end
endtask
Sequence 2 code:
This sequence generates 4 PUSH_B instructions.
virtualtaskbody();
repeat(4)begin
ùvm_do_with(req,{inst ==PUSH_B;});
end
endtask
Sequential Sequence code:
This sequence first calls sequence 1 and then calls sequence 2.
classsequential_sequence extendsuvm_sequence #(instruction);
seq_a s_a;
seq_b s_b;
functionnew(stringname="sequential_sequence");
super.new(name);
endfunction
ùvm_sequence_utils(sequential_sequence,instruction_sequencer)
virtualtaskbody();
ùvm_do(s_a);
ùvm_do(s_b);
endtask
endclass
From the testcase,"sequential_sequence"is selected as "default_sequence".
uvm_sequence_5.tar
Log file report
If you observe the above log, you can see sequence seq_a is executed first and then
sequene seq_b is executed.
Parallelsequences
To executes child sequences Parallel, child sequence start() method should be called
parallel using fork/joinin body method.
Parallel Sequence code:
classparallel_sequence extendsuvm_sequence #(instruction);
seq_a s_a;
seq_b s_b;
functionnew(stringname="parallel_sequence");
super.new(name);
endfunction
ùvm_sequence_utils(parallel_sequence,instruction_sequencer)
virtualtaskbody();
fork
ùvm_do(s_a)
ùvm_do(s_b)
join
endtask
endclass
uvm_sequence_6.tar
Log file report

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TUTORIALS
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Verification
Constructs
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OOPS
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UVM Tutorial
Index
Introduction
Uvm Testbench
Sequencer Arbitration:
Uvm Reporting
When sequences are executed parallel, sequencer will arbitrate among the parallel Uvm Transaction
sequence. When all the parallel sequences are waiting for a grant from sequencer Uvm Configuration
using wait_for_grant() method, then the sequencer, using the arbitration mechanism, Uvm Factory
Uvm Sequence 1
sequencer grants to one of the sequencer.
Uvm Sequence 2
Uvm Sequence 3
There are 6 different arbitration algorithms, they are
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
UVM SEQUENCE 4
VMM Tutorial

input is what keeps
with time!
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
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Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
To set the arbitaration, use the set_arbitration() method of the sequencer. By default
, the arbitration algorithms is set to SEQ_ARB_FIFO.
functionvoidset_arbitration(SEQ_ARB_TYPEval)
Lets look at a example.
In this example, I have 3 child sequences seq_mul seq_add and seq_sub each of them
generates 3 transactions.
Sequence code 1:
virtualtaskbody();
repeat(3)begin
ùvm_do_with(req,{inst ==MUL;});
end
endtask
Sequence code 2:
virtualtaskbody();
repeat(3)begin
ùvm_do_with(req,{inst ==ADD;});
end
endtask
Sequence code 3:
virtualtaskbody();
repeat(3)begin
ùvm_do_with(req,{inst ==SUB;});
end
endtask
Parallel sequence code:
In the body method, before starting child sequences, set the arbitration using
set_arbitration(). In this code, im setting it to SEQ_ARB_RANDOM.
seq_add add;
seq_sub sub;
seq_mul mul;
super.new(name);
endfunction
virtualtaskbody();
m_sequencer.set_arbitration(SEQ_ARB_RANDOM);
fork
ùvm_do(add)
ùvm_do(sub)
ùvm_do(mul)
join
endtask
endclass
uvm_sequence_7.tar
Log file report for when SEQ_ARB_RANDOM is set.

Log file report for when SEQ_ARB_FIFO is set.
If you observe the first log report, all the transaction of the sequences are generated
in random order. In the second log file, the transactions are given equal priority and
are in fifo order.
Setting The Sequence Priority:
There are two ways to set the priority of a sequence. One is using the start method of
the sequence and other using the set_priority() method of the sequence. By default,
the priority of a sequence is 100. Higher numbers indicate higher priority.
virtualtaskstart(uvm_sequencer_base sequencer,
uvm_sequence_base parent_sequence =null,
integerthis_priority =100,
bitcall_pre_post =1)
functionvoidset_priority (intvalue)
Lets look a example with SEQ_ARB_WEIGHTED.
For sequence seq_mul set the weight to 200.
For sequence seq_add set the weight to 300.
For sequence seq_sub set the weight to 400.
In the below example, start() method is used to override the default priority value.
Code :
seq_add add;
seq_sub sub;
seq_mul mul;
super.new(name);
endfunction
virtualtaskbody();
m_sequencer.set_arbitration(SEQ_ARB_WEIGHTED);
add =new("add");
sub =new("sub");
mul =new("mul");
fork
sub.start(m_sequencer,this,400);
add.start(m_sequencer,this,300);
mul.start(m_sequencer,this,200);
join
endtask
endclass
uvm_sequence_8.tar
Log file report

20: Driving
30: Driving
40: Driving
50: Driving
60: Driving
70: Driving
80: Driving
InstructionSUB
InstructionSUB
InstructionADD
InstructionADD
InstructionADD
InstructionMUL
InstructionSUB
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TUTORIALS
UVM SEQUENCE 5
SystemVerilog
Sequencer Registration Macros
Verification
Constructs
DPI
Sequence Registration Macros does the following

1) Implements get_type_name method.
2) Implements create() method.
3) Registers with the factory.
4) Implements the static get_type() method.
5) Implements the virtual get_object_type() method.
6) Registers the sequence type with the sequencer type.
7) Defines p_sequencer variable. p_sequencer is a handle to its sequencer.
8) Implements m_set_p_sequencer() method.
UVM Tutorial
If there are no local variables, then use following macro
Interface
OOPS
Randomization
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Assertion
VMM Tutorial
OVM Tutorial
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ùvm_sequence_utils(TYPE_NAME,SQR_TYPE_NAME)
If there are local variables in sequence, then use macro
ùvm_sequence_utils_begin(TYPE_NAME,SQR_TYPE_NAME)
ùvm_sequence_utils_end
AVM Switch TB
VMM Ethernet sample Macros ùvm_field_* are used for define utility methods.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
These ùvm_field_* macrosare discussed in

UVM_TRANSACTION
Example to demonstrate the usage of the above macros:

classseq_mul extendsuvm_sequence #(instruction);
randintegernum_inst ;
instruction req;
Switch TB
constraintnum_c {num_inst inside{3,5,7};};
RVM Switch TB
ùvm_sequence_utils_begin(seq_mul,instruction_sequencer)
RVM Ethernet sample ùvm_field_int(num_inst,UVM_ALL_ON)
Specman E
Interview Questions
functionnew(stringname="seq_mul");
super.new(name);
endfunction
virtualtaskbody();
$psprintf("Num of transactions %d",num_inst),UVM_LOW);
repeat(num_inst)begin
end
endtask
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
endclass
uvm_sequence_9.tar
Log
UVM_INFO @ 0: reporter [RNTST] Running test ...
UVM_INFO @ 0: reporter [sequencer.seq_mul] Num of transactions 5
Setting Sequence Members:
set_config_*can be used only for the components not for the sequences.
By using configuration you can change the variables inside components only not in
sequences.
But there is a workaround to this problem.
Sequence has handle name called p_sequencer which is pointing the Sequencer on
which it is running.
Sequencer is a component , so get_config_* methods are implemented for it.
So from the sequence, using the sequencer get_config_* methods, sequence members
can be updated if the variable is configured.
When using set_config_* , path to the variable should be sequencer name, as we are
using the sequencer get_config_* method.
Following method demonstrates how this can be done:
Sequence:
1) num_inst is a integer variables which can be updated.
2) In the body method, call the get_config_int() method to get the integer value if
num_inst is configured from testcase.
integernum_inst =4;
instruction req;
ùvm_field_int(num_inst,UVM_ALL_ON)
super.new(name);
endfunction
virtualtaskbody();
void'(p_sequencer.get_config_int("num_inst",num_inst));
$psprintf("Num of transactions %d",num_inst),UVM_LOW);
end
endtask
endclass
Testcase:
From the testcase, using the set_config_int() method, configure the num_inst to 3.
The instance path argument should be the sequencer path name.
moduletest;
initialbegin
set_config_string("sequencer","default_sequence","seq_mul");
set_config_int("sequencer","num_inst",3);
sequencer.build();
driver.build();
sequencer.print();
fork
begin
run_test();
end
join
end
endmodule

uvm_sequence_10.tar
Log
UVM_INFO @ 0: reporter [sequencer.seq_mul] Num of transactions 3
From the above log we can see that seq_mul.num_inst value is 3.
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TUTORIALS
SystemVerilog
UVM SEQUENCE 6
Verification
Exclusive Access
Constructs
A sequence may need exclusive access to the driver which sequencer is arbitrating
among multiple sequence. Some operations require that a series of transaction needs
to be driven without any other transaction in between them. Then a exclusive access
to the driver will allow to a sequence to complete its operation with out any other
sequence operations in between them.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
There are 2 mechanisms to get exclusive access:

Lock-unlcok
Grab-ungrab
UVM Tutorial
VMM Tutorial
Lock-Unlock
OVM Tutorial
tasklock(uvm_sequencer_base sequencer =Null)

functionvoidunlock(uvm_sequencer_base sequencer =Null)
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Easy Labs : UVM
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Using lock() method , a sequence can requests for exclusive access.A lock request
will be arbitrated the same as any other request.A lock is granted after all earlier
requests are completed and no other locks or grabs are blocking this sequence. A
AVM Switch TB
lock() is blocking task and when access is granted, it will unblock.
VMM Ethernet sample
Using unlock(), removes any locks or grabs obtained by this sequence on the specified
sequencer.
Easy Labs : VMM
Verilog
Verification
Verilog Switch TB
Basic Constructs
If sequencer is null, the lock/unlock will be applied on the current default sequencer.
Lets see an example,
In this example there are 3 sequences with each sequence generating 4 transactions.
All these 3 sequences will be called in parallel in another sequence.
Sequence 1 code:
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Specman E
Interview Questions
virtualtaskbody();
repeat(4)begin
end
endtask
Sequence 2 code:
virtualtaskbody();
repeat(4)begin
ùvm_do_with(req,{inst ==POP_C;});
end
endtask
Sequence 3 code:
In this sequence , call the lock() method to get the exclusive access to driver.
After completing all the transaction driving, then call the unclock() method.
virtualtaskbody();
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
lock();
repeat(4)begin
end
unlock();
endtask
virtualtaskbody();
fork
ùvm_do(s_a)
ùvm_do(s_b)
ùvm_do(s_c)
join
endtask
uvm_sequence_11.tar
Log file:
From the above log file, we can observe that , when seq_b sequence got the access,
then transactions from seq_a and seq_c are not generated.
Lock() will be arbitrated before giving the access. To get the exclusive access without
arbitration, grab() method should be used.
Grab-Ungrab
taskgrab(uvm_sequencer_base sequencer =null)
functionvoidungrab(uvm_sequencer_base sequencer =null)
grab() method requests a lock on the specified sequencer. A grab() request is put in
front of the arbitration queue.It will be arbitrated before any other requests.A
grab() is granted when no other grabs or locks are blocking this sequence.
A grab() is blocking task and when access is granted, it will unblock.
Ungrab() method removes any locks or grabs obtained by this sequence on the
specified sequencer.
If no argument is supplied, then current default sequencer is chosen.
Example:
virtualtaskbody();
#25;
grab();
repeat(4)begin
end
ungrab();
endtask
uvm_sequence_12.tar
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TUTORIALS
UVM TLM 1
SystemVerilog
Before going into the TLM interface concepts, lets see why we need TLM interface
Verification
Constructs
Interface
Port Based Data Transfer:

Following is a simple verification environment.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial

input is what keeps
with time!
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
Components generator and driver are implemented as modules.These modules are

connected using module ports or SV interfaces.The advantage of this methodology is,
the two above mentioned components are independent. Instead of consumer module,
any other component which can understand producer interface can be connected,
which gives a great reusability.
The disadvantage of this methodology is , data transfer is done at lower lever
abstraction.
Task Based Data Transfer:
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/UT_13_UVM_TLM_1.html[9/26/2012 2:23:43 PM]
In the above environment, methods are used to transfer the data between
components. So, this gives a better control and data transfer is done at high level.
The disadvantage is, components are using hierarchal paths which do not allow the
reusability.
TLM interfaces:
UVM has TLM interfaces which provide the advantages which we saw in the above two
data transfer styles.
Data is transferred at high level.Transactions which are developed by extending the
uvm_sequence_item can be transferred between components using method calls.
These methods are not hierarchal fixed, so that components can be reused.
The advantages of TLM interfaces are
1) Higher level abstraction
2) Reusable. Plug and play connections.
3) Maintainability
4) Less code.
5) Easy to implement.
6) Faster simulation.
7) Connect to Systemc.
8) Can be used for reference model development.
Operation Supported By Tlm Interface:
Putting:
Producer transfers a value to Consumer.
Getting:
Consumer requires a data value from producer.
Peeking:
Copies data from a producer without consuming the data.
Broadcasting:
Transaction is broadcasted to none or one or multiple consumers.
Methods
BLOCKING:
virtualtaskput(inputT1t)
virtualtaskget(outputT2t)
virtualtaskpeek(outputT2t)
NON-BLOCKIN:
virtualfunctionbittry_put(inputT1t)
virtualfunctionbitcan_put()
virtualfunctionbittry_get(outputT2t)
virtualfunctionbitcan_get()
virtualfunctionbittry_peek(outputT2t)
virtualfunctionbitcan_peek()
BLOCKING TRANSPORT:
virtualtasktransport(inputT1req,outputT2rsp)
NON-BLOCKING TRANSPORT:
virtualfunctionbitnb_transport(inputT1req,outputT2rsp)
ANALYSIS:
virtualfunctionvoidwrite(inputT1t)
Tlm Terminology :
Producer:
A component which
Consumer:
A component which
Initiator:
A component which
Target:
A component which
generates a transaction.
consumes the transaction.
initiates process.
responded to initiator.
Tlm Interface Compilation Models:

Blocking:
A blocking interface conveys transactions in blocking fashion; its methods do not
return until the transaction has been successfully sent or retrieved.Its methods are
defined as tasks.
Non-blocking:
A non-blocking interface attempts to convey a transaction without consuming
simulation time.Its methods are declared as functions.Because delivery may fail
(e.g. the target component is busy and can not accept the request), the methods may
return with failed status.
Combined:
A combination interface contains both the blocking and non-blocking variants.
Interfaces:
The UVM provides ports, exports and implementation and analysis ports for connecting
your components via the TLM interfaces. Port, Export, implementation terminology
applies to control flow not to data flow.
Port:
Interface that requires an implementation is port.
Import:
Interface that provides an implementation is import ot implementation port.
Export:
Interface used to route transaction interfaces to other layers of the hierarchy.
Analysis:
Interface used to distribute transactions to passive components.
Direction:
Unidirectional:
Data transfer is done in a single direction and flow of control is in either or both
direction.
Bidirectional:
Data transfer is done in both directions and flow of control is in either or both
directions.
Examples:
A readoperation is a bidirectional.
A write operation is unidirectional.
Lets look at a example:
In this example, we will use *_put_* interface.
There are 2 components, producer and consumer.

Producer generates the transaction and Consumers consumes it.
In this example, producer calls the put() method to send transaction to consumer i.e
producer is initiator and consumer is target.
When the put() method in the producer is called, it actually executes the put()
method which is defined in consumer component.
Transaction
We will use the below transaction in this example.
randinst_t inst;
super.new(name);
endfunction
endclass
Producer:
1) Define producer component by extending uvm_component.
classproducer extendsuvm_component;
endclass:producer
2) Declare uvm_blocking_put_port port.
uvm_blocking_put_port#(instruction)put_port;
3) In the constructor, construct the port.
functionnew(stringname,uvm_component p =null);
super.new(name,p);
put_port =new("put_port",this);
endfunction
4) Define the run() method. In this method, randomize the transaction.
Then call the put() of the put_port and pass the randomized transaction.
taskrun;
begin
instruction ints;
#10;
ints =new();
if(ints.randomize())begin
ùvm_info("producer",$sformatf("sending
%s",ints.inst.name()),UVM_MEDIUM)
put_port.put(ints);
end
end
endtask
Producer source code
uvm_blocking_put_port#(instruction)put_port;
super.new(name,p);
endfunction
taskrun;
begin
instruction ints;
#10;
ints =new();
if(ints.randomize())begin
ùvm_info("producer",$sformatf("sending
%s",ints.inst.name()),UVM_MEDIUM)
put_port.put(ints);
end
end
endtask
endclass:producer
Consumer:
1) Define a consumer component by extending uvm_component.
classconsumer extendsuvm_component;
endclass:consumer
2) Declareuvm_blocking_put_imp import. The parameters to this port are transaction
and the consumer component itself.
uvm_blocking_put_imp#(instruction,consumer)put_port;
3) In the construct , construct the port.
super.new(name,p);
endfunction
4) Define put() method. When the producer calls "put_port.put(ints);", thenthis
method will be called. Arguments to this method is transaction type "instruction".
In this method, we will just print the transaction.
taskput(instruction t);
ùvm_info("consumer",$sformatf("receiving %s",t.inst.name()),UVM_MEDIUM)
endtask
Consumer source code
uvm_blocking_put_imp#(instruction,consumer)put_port;
super.new(name,p);
endfunction
taskput(instruction t);
ùvm_info("consumer",$sformatf("receiving %s",t.inst.name()),UVM_MEDIUM)
//push the transaction into queue or array
//or drive the transaction to next level
//or drive to interface
endtask
endclass:consumer
Connecting producer and consumer
In the env class, take the instance of producer and consumer components.
In the connect method, connect the producer put_port to consumer put_port using
p.put_port.connect(c.put_port);
Env Source code
producer p;
consumer c;
functionnew(stringname="env");
super.new(name);
p =new("producer",this);
c =new("consumer",this);
endfunction
p.put_port.connect(c.put_port);
endfunction
taskrun();
#1000;
endtask
endclass
Testcase
moduletest;
env e;
initialbegin
e =new();
run_test();
end
endmodule
uvm_tlm_1.tar
Browse the code in uvm_tlm_1.tar
Log
UVM_INFO producer.sv(26) @ 10:
env.producer [producer] sending PUSH_A
UVM_INFO consumer.sv(20) @ 10:
env.consumer [consumer] receiving PUSH_A
UVM_INFO producer.sv(26) @ 20:
env.producer [producer] sending PUSH_B
UVM_INFO consumer.sv(20) @ 20:
env.consumer [consumer] receiving PUSH_B
One more example using*_get_* interface as per the belowtopology.
uvm_tlm_2.tar
All Interfaces In Uvm:
uvm_blocking_put_port #(T)
uvm_nonblocking_put_port #(T)
uvm_put_port #(T)
uvm_blocking_get_port #(T)
uvm_nonblocking_get_port #(T)
uvm_get_port #(T)
uvm_blocking_peek_port #(T)
uvm_nonblocking_peek_port #(T)
uvm_peek_port #(T)
uvm_blocking_get_peek_port #(T)
uvm_nonblocking_get_peek_port #(T)
uvm_get_peek_port #(T)
uvm_analysis_port #(T)
uvm_transport_port #(REQ,RSP)
uvm_blocking_transport_port #(REQ,RSP)
uvm_nonblocking_transport_port #(REQ,RSP)
uvm_master_port #(REQ,RSP)
uvm_blocking_master_port #(REQ,RSP)
uvm_nonblocking_master_port #(REQ,RSP)
uvm_slave_port #(REQ,RSP)
uvm_blocking_slave_port #(REQ,RSP)
uvm_nonblocking_slave_port #(REQ,RSP)
uvm_put_export #(T)
uvm_blocking_put_export #(T)
uvm_nonblocking_put_export #(T)
uvm_get_export #(T)
uvm_blocking_get_export #(T)
uvm_nonblocking_get_export #(T)
uvm_peek_export #(T)
uvm_blocking_peek_export #(T)
uvm_nonblocking_peek_export #(T)
uvm_get_peek_export #(T)
uvm_blocking_get_peek_export #(T)
uvm_nonblocking_get_peek_export #(T)
uvm_analysis_export #(T)
uvm_transport_export #(REQ,RSP)
uvm_nonblocking_transport_export #(REQ,RSP)
uvm_master_export #(REQ,RSP)
uvm_blocking_master_export #(REQ,RSP)
uvm_nonblocking_master_export #(REQ,RSP)
uvm_slave_export #(REQ,RSP)
uvm_blocking_slave_export #(REQ,RSP)
uvm_nonblocking_slave_export #(REQ,RSP)
uvm_put_imp #(T,IMP)
uvm_blocking_put_imp #(T,IMP)
uvm_nonblocking_put_imp #(T,IMP)
uvm_get_imp #(T,IMP)
uvm_blocking_get_imp #(T,IMP)
uvm_nonblocking_get_imp #(T,IMP)
uvm_peek_imp #(T,IMP)
uvm_blocking_peek_imp #(T,IMP)
uvm_nonblocking_peek_imp #(T,IMP)
uvm_get_peek_imp #(T,IMP)
uvm_blocking_get_peek_imp #(T,IMP)
uvm_nonblocking_get_peek_imp #(T,IMP)
uvm_analysis_imp #(T,IMP)
uvm_transport_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_blocking_transport_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_nonblocking_transport_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_master_imp #(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_blocking_master_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_nonblocking_master_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_slave_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_blocking_slave_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
uvm_nonblocking_slave_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
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TUTORIALS
UVM TLM 2
SystemVerilog
Analysis
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
The analysis portis used to perform non-blocking broadcasts of transactions.It is by

components like monitors/drivers to publish transactions to its subscribers, which are
typically scoreboards and response/coverage collectors. For each port, more than one
component can be connected. Even if a component is not connected to the port,
simulation can continue, unlike put/get ports where simulation is not continued.
The uvm_analysis_port consists of a single function, write().Subscriber component
should provide an implementation of write()method. UVM provides the
uvm_subscriber base component to simplify this operation, so a typical analysis
component would extend uvm_subscriber and its export is analysis_export.
UVM Tutorial
VMM Tutorial
OVM Tutorial
Lets write a example.

In the example, we will define a monitor component and a subscriber.
Easy Labs : SV
Monitor source code:
Easy Labs : UVM
In monitor, call the function write() pass the transaction.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
classmonitor extendsuvm_monitor;
uvm_analysis_port #(instruction)anls_port;
VMM Ethernet sample super.new(name,p);
Verilog
anls_port =new("anls_port",this);
endfunction
taskrun;
instruction inst;
Verilog Switch TB
inst =new();
#10ns;
Basic Constructs
inst.inst =instruction::MUL;
anls_port.write(inst);
#10ns;
OpenVera
inst.inst =instruction::ADD;
Constructs
#10ns;
Switch TB
inst.inst =instruction::SUB;
RVM Switch TB
RVM Ethernet sample endtask
Verification
endclass
Specman E
Interview Questions
Subscriber source code:

In Subscriber, define the write() method.
classsubscriber extendsuvm_subscriber#(instruction);
super.new(name,p);
endfunction
functionvoidwrite(instruction t);
ùvm_info(get_full_name(),
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
$sformatf("receiving %s",t.inst.name()),UVM_MEDIUM)
endfunction
endclass:subscriber
Env source code:
monitor mon;
subscriber sb,cov;
super.new(name);
mon =new("mon",this);
sb=new("sb",this);
cov =new("cov",this);
endfunction
mon.anls_port.connect(sb.analysis_export);
mon.anls_port.connect(cov.analysis_export);
endfunction
taskrun();
#1000;
endtask
endclass
moduletest;
env e;
initialbegin
e =new();
run_test();
end
endmodule
uvm_tlm_3.tar
From the below log, you see that transaction is sent to both the components cov and
sb.
Log
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
subscriber.sv(18)
subscriber.sv(18)
subscriber.sv(18)
subscriber.sv(18)
subscriber.sv(18)
subscriber.sv(18)
@
@
@
@
@
@
0:
0:
0:
0:
0:
0:
env.cov [env.cov] receiving MUL

env.sb [env.sb] receiving MUL
env.cov [env.cov] receiving ADD
env.sb [env.sb] receiving ADD
env.cov [env.cov] receiving SUB
env.sb [env.sb] receiving SUB
Tlm Fifo
Tlm_fifo provides storage of transactions between two independently running
processes just like mailbox.Transactions are put into the FIFO via the put_export and
fetched from the get_export.
Methods
Following are the methods defined for tlm fifo.
functionnew(stringname,
uvm_component parent =null,
intsize=1)
The size indicates the maximum size of the FIFO; a value of zero indicates no upper
bound.
virtualfunctionintsize()
Returns the capacity of the FIFO. 0 indicates the FIFO capacity has no limit.
virtualfunctionintused()
Returns the number of entries put into the FIFO.
virtualfunctionbitis_empty()
Returns 1 when there are no entries in the FIFO, 0 otherwise.
virtualfunctionbitis_full()
Returns 1 when the number of entries in the FIFO is equal to its size, 0 otherwise.
virtualfunctionvoidflush()
Removes all entries from the FIFO, after which used returns 0 and is_empty returns 1.
Example
Lets implement a example.
In this example, we will use a tlm_fifo to connectproducer and consumer.
The producer component generates the transaction and using its put_portpot()
method, sends transaction out.The consumer component, to get the transaction
from outside, uses get() method of get_port.These two ports are connected to
tlm_fifo in the env class. In this example, producer and consumer are initiators as
both components are calling the methods.
Producer source code:

uvm_blocking_put_port#(int)put_port;
super.new(name,p);
endfunction
taskrun;
intrandval;
begin
#10;
randval =$urandom_range(4,10);
ùvm_info("producer",
$sformatf("sending %d",randval),UVM_MEDIUM)
put_port.put(randval);
end
endtask
endclass:producer
Consumer source code:
uvm_blocking_get_port#(int)get_port;
super.new(name,p);
get_port =new("get_port",this);
endfunction
taskrun;
intval;
forever
begin
get_port.get(val);
ùvm_info("consumer",
$sformatf("receiving %d",val),UVM_MEDIUM)
end
endtask
endclass:consumer
Env source code:
producer p;
consumer c;
tlm_fifo #(int)f;
super.new(name);
p =new("producer",this);
c =new("consumer",this);
f =new("fifo",this);
endfunction
p.put_port.connect(f.put_export);
c.get_port.connect(f.get_export);
endfunction
taskrun();
endtask
endclass
uvm_tlm_4.tar
Log
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
producer.sv(28) @ 10: env.producer [producer] sending 7

consumer.sv(26) @ 10: env.consumer [consumer] receiving 7
producer.sv(28) @ 20: env.producer [producer] sending 4
consumer.sv(26) @ 20: env.consumer [consumer] receiving 4
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TUTORIALS
UVM CALLBACK
SystemVerilog
Callback mechanism is used for altering the behavior of the transactor without
modifying the transactor. One of the many promises of Object-Oriented programming
is that it will allow for plug-and-play re-usable verification components. Verification
Designers will hook the transactors together to make a verification environment. In
SystemVerilog, this hooking together of transactors can be tricky. Callbacks provide a
mechanism whereby independently developed objects may be connected together in
simple steps.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
This article describes uvm callbacks. uvm callback might be used for simple
notification, two-way communication, or to distribute work in a process. Some
requirements are often unpredictable when the transactor is first written. So a
transactor should provide some kind of hooks for executing the code which is defined
afterwards. In uvm, these hooks are created using callback methods. For instance, a
driver is developed and an empty method is called before driving the transaction to
the DUT. Initially this empty method does nothing. As the implementation goes, user
may realize that he needs to print the state of the transaction or to delay the
transaction driving to DUT or inject an error into transaction. Callback mechanism
allows executing the user defined code in place of the empty callback method.Other
example of callback usage is in monitor. Callbacks can be used in a monitor for
collecting coverage information or for hooking up to scoreboard to pass transactions
for self checking. With this, user is able to control the behavior of the transactor in
verification environment and individual testcases without doing any modifications to
the transactor itself.
Following are the steps to be followed to create a transactor with callbacks. We will
VMM Ethernet sample see simple example of creating a Driver transactor to support callback mechanism.
Verilog
Stpe 1) Define a facade class.
Verification
1) Extend the uvm_callback class to create a faced class.
Verilog Switch TB
classDriver_callback extendsuvm_callback;
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
endclass:Driver_callback
2)Define required callback methods. All the callback methods must be virtual.
In this example, we will create callback methods which will be called before driving
the packet and after driving the packet to DUT.
virtualtaskpre_send();endtask
virtualtaskpost_send();endtask
3)Define the constructor and get_type_name methods and define type_name.
functionnew(stringname="Driver_callback");
super.new(name);
endfunction
staticstringtype_name ="Driver_callback";
virtualfunctionstringget_type_name();
returntype_name;
endfunction
Step 2) Register the facade class with driver and call the callback methods.
http://testbench.in/UT_15_UVM_CALLBACK.html[9/26/2012 2:24:10 PM]
Index
Introduction
Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback
input is what keeps
with time!
1)In the driver class, using ùvm_register_cb() macro, register the facade class.
classDriver extendsuvm_component;
ùvm_component_utils(Driver)
ùvm_register_cb(Driver,Driver_callback)
functionnew(stringname,uvm_component parent=null);
endfunction
endclass
2)Calling callback method.
Inside the transactor, callback methods should be called whenever something
interesting happens.
We will call the callback method before driving the packet and after driving the
packet. We defined 2 methods in facade class. We will call pre_send() method before
sending the packet and post_send() method after sending the packet.
Using a ùvm_do_callbacks() macro, callback methods are called.
There are 3 argumentd to ùvm_do_callbacks(,) macro.
First argument must be the driver class and second argument is facade class.
Third argument must be the callback method in the facade class.
To call pre_send() method , use macro

ùvm_do_callbacks(Driver,Driver_callback,pre_send());
and similarly to call post_send() method,
ùvm_do_callbacks(Driver,Driver_callback,post_send());
Place the above macros before and after driving the packet.
virtualtaskrun();
repeat(2)begin
ùvm_do_callbacks(Driver,Driver_callback,pre_send())
$display(" Driver: Started Driving the packet ...... %d",$time);
// Logic to drive the packet goes hear
// let's consider that it takes 40 time units to drive a packet.
#40;
$display(" Driver: Finished Driving the packet ...... %d",$time);
ùvm_do_callbacks(Driver,Driver_callback,post_send())
end
endtask
With this, the Driver implementation is completed with callback support.

Driver And Driver Callback Class Source Code
classDriver_callback extendsuvm_callback;
super.new(name);
endfunction
staticstringtype_name ="Driver_callback";
virtualfunctionstringget_type_name();
returntype_name;
endfunction
endclass:Driver_callback
classDriver extendsuvm_component;
ùvm_register_cb(Driver,Driver_callback)
functionnew(stringname,uvm_component parent=null);
endfunction
virtualtaskrun();
repeat(2)begin
ùvm_do_callbacks(Driver,Driver_callback,pre_send())
#40;
ùvm_do_callbacks(Driver,Driver_callback,post_send())
end
endtask
endclass
Let's run the driver in simple testcase. In this testcase, we are not changing any
callback methods definitions.
Testcase Source Code
moduletest;
Driver drvr;
initialbegin
drvr =new("drvr");
run_test();
end
endmodule
Download files
uvm_callback_1.tar
Browse the code in uvm_callback_1.tar
Log report
Driver: Started Driving the packet ......0
Driver: Finished Driving the packet ...... 40
Driver: Started Driving the packet ...... 40
UVM_ERROR @ 9200: reporter [TIMOUT] Watchdog timeout of '9200' expired.
Following steps are to be performed for using callback mechanism to do required
functionality.
We will see how to use the callbacks which are implemented in the above defined
driver in a testcase.
1) Implement the user defined callback method by extending facade class of the
driver class.
We will delay the driving of packet be 20 time units using the pre_send() call back
method.
We will just print a message from post_send() callback method.

classCustom_Driver_callbacks_1 extendsDriver_callback;
super.new(name);
endfunction
virtualtaskpre_send();
$display("CB_1:pre_send: Delaying the packet driving by 20 time units.
%d",$time);
#20;
endtask
virtualtaskpost_send();
$display("CB_1:post_send: Just a message frompost send callback method \n");
endtask
endclass
2) Construct the user defined facade class object.
Custom_Driver_callbacks_1 cb_1;
cb_1 =new("cb_1");
3) Register the callback method with the driver component. uvm_callback class has
static method add() which is used to register the callback.
uvm_callbacks #(Driver,Driver_callback)::add(drvr,cb_1);
Testcase 2 Source Code

super.new(name);
endfunction
%d",$time);
#20;
endtask
endtask
endclass
moduletest;
initialbegin
Driver drvr;
drvr =new("drvr");
cb_1 =new("cb_1");
uvm_callbacks #(Driver,Driver_callback)::display();
run_test();
end
endmodule
uvm_callback_2.tar
Simulation Command
Run the testcase. See the log results; We delayed the driving of packet by 20 time
units using callback mechanism. See the difference between the previous testcase log
and this log.
Log report
cb_1 on drvrON
CB_1:pre_send: Delaying the packet driving by 20 time units.0
CB_1:post_send: Just a message frompost send callback method
CB_1:pre_send: Delaying the packet driving by 20 time units. 60
Driver: Finished Driving the packet ......120
Now we will see registering 2 callback methods.

1) Define another user defined callback methods by extending facade class.
super.new(name);
endfunction
$display("CB_2:pre_send: Hai .... this is from Second callback %d",$time);
endtask
endclass
cb_2 =new("cb_2");
3) Register the object
super.new(name);
endfunction
%d",$time);
#20;
endtask
endtask
endclass
super.new(name);
endfunction
endtask
endclass
moduletest;
initialbegin
Driver drvr;
drvr =new("drvr");
cb_1 =new("cb_1");
cb_2 =new("cb_2");
run_test();
end
endmodule
Download source code
uvm_callback_3.tar
Run the testcase and analyze the result.
Log report
CB_2:pre_send: Hai .... this is from Second callback 20
The log results show that pre_send() method of CDc_1 is called first and then
pre_send() method of Cdc_2. This is because of the order of the registering callbacks.
Now we will see how to change the order of the callback method calls.
By changing the sequence of calls to add() method, order of callback method calling
can be changed.
moduletest;
initialbegin
Driver drvr;
drvr =new("drvr");
cb_1 =new("cb_1");
cb_2 =new("cb_2");
run_test();
end
endmodule
uvm_callback_4.tar
Run and analyze the results.
Log results show that, pre_send() method of CDs_1 is called after calling
CDs_2pre_send() method.
Log file report
CB_2:pre_send: Hai .... this is from Second callback0
Methods:
add_by_name:
We have seen, the usage of add() method which requires object.
Using add_by_name() method, callback can be registered with object name.
staticfunctionvoidadd_by_name(stringname,
uvm_callback cb,
uvm_component root,
uvm_apprepend ordering =UVM_APPEND)
delete:
uvm also provides uvm_callbacks::delete() method to remove the callback methods
which are registered.
Similar to delete, delete_by_name() method is used to remove the callback using the
object name.
staticfunctionvoiddelete_by_name(stringname,
uvm_callback cb,
uvm_component root )
Macros:
ùvm_register_cb
Registers the given CB callback type with the given T object type.
ùvm_set_super_type
Defines the super type of T to be ST.

ùvm_do_callbacks
Calls the given METHOD of all callbacks of type CB registered with the calling object
ùvm_do_obj_callbacks
Calls the given METHOD of all callbacks based on type CB registered with the given
object, OBJ, which is or is based on type T.
ùvm_do_callbacks_exit_on
Calls the given METHOD of all callbacks of type CB registered with the calling object
ùvm_do_obj_callbacks_exit_on
Calls the given METHOD of all callbacks of type CB registered with the given object
OBJ, which must be or be based on type T, and returns upon the first callback that
returns the bit value given by VAL.
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TUTORIALS
INTRODUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Verification methodological manual (VMM) , co-authored by verification experts from

ARM and Synopsys, describes how to use SystemVerilog to develop scalable,
predictable and reusableverification environments. VMM has become important
factor in increasing verification reuse, improved verification productivity and
timeliness.
VMM consists coding guide lines and base classes. VMM is focused on Coverage driven
verification methodology. VMM supports both the top-down and bottom-up
approaches. VMM follows layered test bench architecture to take the full advantage of
the automation. The VMM for SystemVerilog TestBench architecture comprises five
layers.
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts

input is what keeps
signal layer:
This layer connects the TestBench to the RTL design. It consists of interface, clocking, with time!
The layered TestBench is the heart of the verification environment in VMM:
and modport constructs.
command layer:
This layer contains lower-level driver and monitor components, as well as the
assertions. This layer provides a transaction-level interface to the layer above and
drives the physical pins via the signal layer.
functional layer:
This layer contains higher-level driver and monitor components, as well as the selfchecking structure (scoreboard/tracker).
scenario layer:
This layer uses generators to produce streams or sequences of transactions that are
applied to the functional layer. The generators have a set of weights, constraints or
scenarios specified by the test layer. The randomness of constrained-random testing is
introduced within this layer.
test layer:
Tests are located in this layer. Test layer can interact with all the layers. This layer
allows to pass directed commands to functional and command layer.
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/VM_01_INTRODUCTION.html[9/26/2012 2:24:18 PM]
VMM libraries consists following sub libraries

VMM
VMM
VMM
VMM
Standard Library
Register Abstraction Layer (RAL)
Hardware Abstraction Layer (HAL)
Scoreboarding
The VMM Standard Library provides base classes for key aspects of the verification
environment, transaction generation, notification service and a message logging
service.
These libraries can be downloaded from http://www.vmmcentral.org
Following are some of the classes and macros defined in the VMM Standard Library
vmm_env :
The class is a base class used to implement verification environments.
vmm_xactor :
This base class is to be used as the basis for all transactors, including bus-functional
models, monitors and generators. It provides a standard control mechanism expected
to be found in all transactors.
vmm_channel :
This class implements a generic transaction-level interface mechanism. Transactionlevel interfaces remove the higher-level layers from the physical interface details.
Using channels, transactors pass transactions from one to other.
vmm_data :
This base class is to be used as the basis for all transaction descriptors and data
models. It provides a standard set of methods expected to be found in all descriptors.
User must extend vmm_data to create a custom transaction.
vmm_log :
The vmm_log class used implements an interface to the message service. These
classes provide a mechanism for reporting simulation activity to a file or a terminal.
To ensure a consistent look and feel to the messages issued from different sources,
vmm_log is used.
vmm_atomic_gen :
This is a macro. This macro defines a atomic generator for generating transaction
which are derived from vmm_data.
vmm_scenario_gen :
Defines a scenario generator class to generate sequences of related instances of the
specified class.
vmm_notify :
The vmm_notify class implements an interface to the notification service. The
notification service provides a synchronization mechanism for concurrent threads or
transactors.
vmm_test :
This class will be useful for runtime selection of testcases to run on an environment.
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The vmm_log class provides an interface to the VMM message service so that all
messages, regardless of their sources, can have a common "look and feel".Not always
we require all type of messages. During normal simulation, we need only note, error
and warning messages. While you are debugging, you may need debug messages and
trace messages. vmm_log allows you to control the messages. This helps in debugging.
vmm_log has a uniform message format which helps for post processing the log file
using scripts if needed. You can also convert a error message to warning message
which is required in some specific testcases. The message service describes and
controls messages based on several concepts:
Message source:
A message source can be any component of a TestBench. They can be Transactors,
scoreboards, assertions, environment or a testcase.
input is what keeps

Message filters:
Filters can prevent or allow a message from being issued. They can be promoted or Testbench.in improving
with time!
demoted based on the identifier, type, severity or content.
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Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
Vmm Message Type

Individual messages are categorized into different types.
FAILURE_TYP: For reporting error messages.
NOTE_TYP : Normal message used to indicate the simulation progress.
DEBUG_TYP: Message useful for debugging purpose.
TIMING_TYP : For reporting timing errors.
XHANDLING_TYP: For reporting X or Z on signals
INTERNAL_TYP : Messages from the VMM base classes.
REPORT_TYP,PROTOCOL_TYP,TRANSACTION_TYP,COMMAND_TYP,CYCLE_TYP :
Additional message types that can be used by transactors.
Message Severity
Individual messages are categorized into different severities
FATAL_SEV: An error which causes a program to abort.
ERROR_SEV: Simulation aborts after a certain number of errors are observed.
WARNING_SEV: Simulation can proceed and still produce useful result.
NORMAL_SEV : This message indicates the state of simulation.
TRACE_SEV: This message identifies high-level internal information that is not
normally issued.
DEBUG_SEV: This message identifies medium-level internal information that is not
normally issued.
VERBOSE_SEV: This message identifies low-level internal information that is not
normally issued.
Vmm Log Macros
We can use the following predefined macros to select the message severity.
http://testbench.in/VM_02_VMM_LOG.html[9/26/2012 2:24:29 PM]
`vmm_fatal(vmm_log log,stringmsg);
`vmm_error(vmm_log log,stringmsg);
`vmm_warning(vmm_log log,stringmsg);
`vmm_note(vmm_log log,stringmsg);
`vmm_trace(vmm_log log,stringmsg);
`vmm_debug(vmm_log log,stringmsg);
`vmm_verbose(vmm_log log,stringmsg);
The second argument in the above macro can accept only a string. So if we want to
pass a complex message, then convert it to string using a $psprintf() system task.
These macros are simple to use and the macro expansion is easy to understand.
Following is a expansion of `vmm_not macro. Other macros also have same logic with
different Message severity levels.
`definevmm_note (log,msg )
do
if(log.start_msg(vmm_log::NOTE_TYP))begin
void'(log.text(msg));
log.end_msg();
end
while(0)
To change the severity and verbosity of the messages services at simulation time , use
+vmm_log_default=SEVERITY TYPE. Where SEVERITY TYPE can be ERROR, WARNING,
NORMAL, TRACE, DEBUG OR VERBOSE.We will see the demo of this service in the
example.
Message Handling
Different messages require different action by the simulator once the message has
been issued.
ABORT_SIM: Aborts the simulation.
COUNT_ERROR: Count the message as an error.
STOP_PROMPT: Stop the simulation immediately and return to the simulation
runtime-control command prompt.
DEBUGGER : Stop the simulation immediately and start the graphical debugging
environment.
DUMP_STACK : Dump the call stack or any other context status information and
continue the simulation.
CONTINUE : Continue the simulation normally.
To use this vmm feature, take the instance of vmm_log and use the message macros.
For most of the vmm classes like vmm_env,vmm_xactor,vmm_data etc, this
instantiation is already done internally, so user dont need to take a separate instance
of vmm_log.
vmm_log log =new("test_log","log");
Following is a simple program which demonstrates the usages of different severity
levels.
This program creates the object of a vmm_log class and uses log macros to define
various messages. You can also see the usage of $psprintf() system task.
programtest_log();
initialbegin
`vmm_error(log,"This is a ERROR Message");

`vmm_warning(log,"This is a WARNING Message");
`vmm_note(log,$psprintf("This is a NOTE Message at time %d",$time));
`vmm_trace(log,"This is a TRACE Message");
`vmm_debug(log,"This is a DEBUG Message");
`vmm_verbose(log,"This is a VERBOSE Message");
`vmm_fatal(log,"This is a FATAL Message");
end
endprogram
vmm_log.tar
Browse the code in vmm_log.tar
Simulation commands
vcs -sverilog -f filelist -R -ntb_opts rvm -ntb_opts dtm
You can see the following messages on the terminal. You can only see Normal, Error,
warning and fatal messages.
Log file report:
!ERROR![FAILURE] on test_log(log) at0:
This is a ERROR Message
WARNING[FAILURE] on test_log(log) at0:
This is a WARNING Message
Normal[NOTE] on test_log(log) at0:
This is a NOTE Message at time0
*FATAL*[FAILURE] on test_log(log) at0:
This is a FATAL Message
Run the simulation with command option +vmm_log_default=DEBUG
You can see the following messages on the terminal. You can see that Debug and trace
message is also coming.
Log file report:
Trace[DEBUG] on test_log(log) at0:
This is a TRACE Message
Debug[DEBUG] on test_log(log) at0:
This is a DEBUG Message
Run the simulation with command option +vmm_log_default=VERBOSE
You can see the following messages on the terminal. You can see that Trace, Debug
and Verbose messages are also coming.
Log file report:
Trace[DEBUG] on test_log(log) at0:
This is a TRACE Message
Debug[DEBUG] on test_log(log) at0:
This is a DEBUG Message
Verbose[DEBUG] on test_log(log) at0:
This is a VERBOSE Message
Counting Number Of Messages Based Of Message Severity

Some time we need to count the number of messages executed based of the severity
type. vmm_log has get_message_count() function which returns the message count
based on severity type, source and message string.
user dont need to implement a logic to print the state of test i.e TEST PASSED or TEST
FAILED, vmm_env has already implemented this in the report() method. We will see
this in next topic.
virtualfunctionintget_message_count(intseverity =ALL_SEVS,
stringname="",
stringinstance="",
bitrecurse =0);
Following is a example which demonstrations theget_message_count() function. The

following example , also demonstrates the use of $psprintf which will be use full to
print message when there are variable arguments to print.
programtest_log();
intfatal_cnt ;
interror_cnt ;
intwarn_cnt ;
initialbegin
`vmm_note(log,$psprintf("This is a NOTE Message at time %d",$time));
`vmm_error(log,"This is a ERROR Message 1 ");

`vmm_warning(log,"This is a WARNING Message 1 ");

`vmm_warning(log,"This is a WARNING Message 2 ");
fatal_cnt =log.get_message_count(vmm_log::FATAL_SEV,"/./","/./",1);
error_cnt =log.get_message_count(vmm_log::ERROR_SEV,"/./","/./",1);
warn_cnt=log.get_message_count(vmm_log::WARNING_SEV,"/./","/./",1);
$display("\n\n");
$display(" Number of Fatal messages : %0d ",fatal_cnt);
$display(" Number of Error messages : %0d ",error_cnt);
$display(" Number of Warning messages : %0d ",warn_cnt);
$display("\n\n");
end
endprogram
vmm_log_1.tar
Browse the code in vmm_log_1.tar
Simulation commands
Log file report:


This is a ERROR Message 1
This is a WARNING Message 1
This is a WARNING Message 2
Number of Fatal messages : 0
Number of Error messages : 3
Number of Warning messages : 2
Sometimes we would like to wait for a specific message and execute some logic. For
example, you want to count number of crc error packets transmitted by dut in some
special testcase or you want to stop the simulation after a specific series of messages
are received. vmm_log has a method to wait for a specific message.
virtualtaskwait_for_msg(stringname="",
stringinstance="",
bitrecurse =0,
inttyps =ALL_TYPS,
intseverity =ALL_SEVS,
stringtext ="",
logicissued =1'bx,
refvmm_log_msg msg);
Following is a simple example which demonstrates the use of above method. In this
example, wait_for_msg() method wait for a specific string.
programtest_log();
vmm_log_msg msg =new(log);
/* This logic is some where in the monitor */
initial
repeat(4)begin
#($urandom()%10)
`vmm_error(log,"Packet with CRC ERROR is received");
end
/* In testcase you are counting the error messages */
initial
foreverbegin
log.wait_for_msg("/./","/./",-1,vmm_log::ALL_TYPS,vmm_log::ERROR_SEV,"Packet
with CRC ERROR is received",1'bx,msg);
// You can count number of crc errored pkts rcvd.
// or do whatever you want.
$display(" -- Rcvd CRC ERROR message at %d --",$time);
end
endprogram
vmm_log_2.tar
Browse the code in vmm_log_2.tar
Simulation commands
Log file report:

Packet with CRC ERROR is received
-- Rcvd CRC ERROR message at8 -!ERROR![FAILURE] on test_log(log) at8:
-- Rcvd CRC ERROR message at8 -!ERROR![FAILURE] on test_log(log) at 11:
-- Rcvd CRC ERROR message at 11 -!ERROR![FAILURE] on test_log(log) at 11:
-- Rcvd CRC ERROR message at 11 --
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Verification environment is developed by extending vmm_env class.The TestBench

simulation needs some systematic flow like reset, initialize etc. vmm_env base class
has methods formalize the simulation steps. All methods are declared as virtual
methods. All the Verification components and instantiated, connected and component
activities starting is done in this class. As it contains all verification components
instances, the environment class affects the entire test environment.
The vmm_env class divides a simulation into the following steps, with corresponding
methods:
gen_cfg() :
Randomize test configuration parameters.
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts

build() :
Creates the instances of channels and transactors. Transactors are connected using input is what keeps
channels. DUT is also connected to TestBench using the interfaces.
with time!
reset_dut() :
Reset the DUT using the interface signals.
cfg_dut() :
Configures the DUT configuration parameters.
start() :
Starts all the components of the verification environment to start component activity.
All the transactors (atomic_gen, senario_gen, vmm_xactor....) have start method,
which starts their activities. All the components start() methods are called in this
method.
wait_for_end() :
This method waits till the test is done.
stop() :
Stops all the components of the verification environment to terminate the simulation
cleanly. Stop data generators.
cleanup() :
Performs clean-up operations to let the simulation terminate gracefully.Itwaits for
DUT to drain all the data it has.
report() :
The report method in vmm_env collects error and warning metrics from all the log
objects and reports a summary of the results.
To create a user environment, define a new class extended from vmm_env and extend
the above methods. To retain the core functionality of the base class methods, each
extended method must call super. as the first line of code.
In The following example, we are defining a new class Custom_env from vmm_env and
extending all the vmm_env class methods. All the methods are extended and
`vmm_note() message is included to understand the simulation flow.
classCustom_env extendsvmm_env;
http://testbench.in/VM_03_VMM_ENV.html[9/26/2012 2:24:38 PM]
functionnew();
super.new("Custom_env");
endfunction
virtualfunctionvoidgen_cfg();
super.gen_cfg();
`vmm_note(this.log,"Start of gen_cfg() method ");
`vmm_note(this.log,"End of gen_cfg() method ");
endfunction
virtualfunctionvoidbuild();
super.build();
`vmm_note(this.log,"Start of build() method ");
`vmm_note(this.log,"End of build() method ");
endfunction
virtualtaskreset_dut();
super.reset_dut();
`vmm_note(this.log,"Start of reset_dut() method ");
`vmm_note(this.log,"End of reset_dut() method ");
endtask
virtualtaskcfg_dut();
super.cfg_dut();
`vmm_note(this.log,"Start of cfg_dut() method ");
`vmm_note(this.log,"End of cfg_dut() method ");
endtask
virtualtaskstart();
super.start();
`vmm_note(this.log,"Start of start() method ");
`vmm_note(this.log,"End of start() method ");
endtask
virtualtaskwait_for_end();
super.wait_for_end();
`vmm_note(this.log,"Start ofwait_for_end() method ");
`vmm_note(this.log,"End ofwait_for_end() method ");
endtask
virtualtaskstop();
super.stop();
`vmm_note(this.log,"Start of stop() method ");
`vmm_note(this.log,"End of stop() method ");
endtask
virtualtaskcleanup();
super.cleanup();
`vmm_note(this.log,"Start of cleanup() method ");
`vmm_note(this.log,"End of cleanup() method ");
endtask
virtualtaskreport();
super.report();
`vmm_note(this.log,"Start of report() method \n\n\n");
`vmm_note(this.log,"End of report() method");
endtask
endclass
In addition to the methods that have already been discussed earlier, vmm_env also
contains a run() method which does not require any user extension. This method is
called from the testcase. When this method is called, individual steps in vmm_env are
called in a sequence in the following order:
gen_cfg => build => cfg_dut_t => start_t => wait_for_end_t => stop_t => cleanup_t =>
report
Now we will see the testcase implementation. VMM recommends the TestBench to be
implemented in program block. In a program block, create an object of the
Custom_env class and call the run() method.
programtest();
Custom_env env =new();
initial
env.run();
endprogram
Download the files
vmm_env_1.tar
Browse the code in vmm_env_1.tar
Simulation commands
Log file report:
Normal[NOTE] on Custom_env()
Start of gen_cfg() method
End of gen_cfg() method
Start of build() method
End of build() method
Start of reset_dut() method
End of reset_dut() method
Start of cfg_dut() method
at0:
at0:
at0:
at0:
at0:
at0:
at0:
Normal[NOTE] on Custom_env() at0:

End of cfg_dut() method
Start of start() method
End of start() method
Start ofwait_for_end() method
End ofwait_for_end() method
Start of stop() method
End of stop() method
Start of cleanup() method
End of cleanup() method
Simulation PASSED on /./ (/./) at0 (0 warnings, 0 demoted errors & 0
demoted warnings)
Start of report() method

End of report() method
$finish at simulation time0
Log file report shows that individual methods in vmm_env are called in a ordered
sequence upon calling run() method.
When you call build() and if gen_cfg() is not called before that, gen_cfg() will be
called first then build will execute.
Same way, if you call gen_cfg() followed by cfg_dut() followed by run(), then
cfg_dut() will make sure to call build() followed by reset_dut() first before executing
its user defined logic, run() will make sure to call start(), wait_for_end(), stop(),
clean(), report()in the order given.
programtest();
vmm_env env =new();
initial
begin
$display("*************** Before Calling env.gen_cfg() ***************");
env.gen_cfg();
$display("*************** Before Calling env.cfg_dut() ***************");
env.cfg_dut();
$display("*************** Before Calling env.run() ***************");
env.run();
end
endprogram
Download the files
vmm_env_2.tar
Browse the code in vmm_env_2.tar
Simulation commands
vcs -sverilog -f filelist -R -ntb_opts rvm -ntb_opts dtm +vmm_log_default=VERBOSE
Log file report:
*************** Before Calling env.gen_cfg() ***************

Trace[INTERNAL] on Verif Env() at0:
Generating test configuration...
*************** Before Calling env.cfg_dut() ***************
Building verification environment...
Reseting DUT...
Configuring...
*************** Before Calling env.run() ***************
Starting verification environment...
Saving RNG state information...
Waiting for end of test...
Stopping verification environment...
Cleaning up...
demoted warnings)
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OOPS
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Functional Coverage
vmm_data class is to be used to model all transactions in the infrastructure . It

provides a standard set of methods expected to be found in all transactions. All
transactions in the verification environment inherit this object and override its main
generic virtual tasks such as copy(), byte_pack(), byte_unpack(), compare() and
psdisplay().
vmm_data has 3 unique identifiers for identifying transaction instance.
DPI
int stream_id;// Stream identifier

int scenario_id;// Sequence identifier within stream
int data_id;// instance identifier within sequence
UVM Tutorial
This class is used to generate random, constraint random and directed transactions.
Assertion
VMM Tutorial
OVM Tutorial
We will see the implementation of some methods.
Easy Labs : SV
Let us implement a simple packet using vmm_data.
Easy Labs : UVM
Packet Specification
------------------------------Packet has DA,SA,Len and ..... few more feilds.
All the feilds are 8 bit.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
1) Define a packet class by extending vmm_data

classPacket extendsvmm_data;
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
2) Define all the packet fields as rand variables

randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]length;
....
....
3) Constraint the rand variables based on the specification.
constraintaddress_c {da inside{`P0,`P1,`P2,`P3};}
....
.....
4) Define psdisplay() method.
psdisplay() method displays the current value of the transaction or data described by
this instance in a human-readable format on the standard output.
virtualfunctionstringpsdisplay(stringprefix ="");
inti;
$write(psdisplay," %s%s da:0x%h\n",psdisplay,prefix,this.da);

$write(psdisplay," %s%s sa:0x%h\n",psdisplay,prefix,this.sa);
$write(psdisplay,"
%s%s
(data.size=%0d)\n",psdisplay,prefix,this.length,this.data.size());
.........
endfunction
http://testbench.in/VM_04_VMM_DATA.html[9/26/2012 2:24:48 PM]
length:0x%h
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
input is what keeps
with time!
5) Define copy() method.
copy() method copies the current value of the object instance to the specified object
instance.
virtualfunctionvmm_data copy(vmm_data to =null);

Packet cpy;
cpy =new;
super.copy_data(cpy);
cpy.da =this.da;
cpy.sa =this.sa;
cpy.length =this.length;
...........
6) Define compare() method.
Compare method compares the current value of the object instance with the current
value of the specified object instance.
virtualfunctionbitcompare(inputvmm_data to,outputstringdiff,inputint
kind =-1);
Packet cmp;
compare=1;// Assume success by default.

diff="No differences found";
// data types are the same, do comparison:

if(this.da !=cmp.da)
begin
diff =$psprintf("Different DA values: %b != %b",this.da,cmp.da);
compare=0;
end
if(this.sa !=cmp.sa)
begin
diff =$psprintf("Different SA values: %b != %b",this.sa,cmp.sa);
compare=0;
end
........
........
7) Define byte_pack() method.
byte_pack() method Packs the content of the transaction or data into the specified
dynamic array of bytes.
virtualfunctionintunsignedbyte_pack(
reflogic[7:0]bytes[],
inputintunsignedoffset =0,
inputint kind =-1);
byte_pack =0;
bytes =new[this.data.size()+4];
bytes[0]=this.da;
bytes[1]=this.sa;
bytes[2]=this.length;
........
........
8) Define byte_unpack() method.
byte_unpack() method unpacket the array in to different data feilds.
virtualfunctionintunsignedbyte_unpack(
constreflogic[7:0]bytes[],
inputintlen=-1,
inputintkind =-1);
this.da =bytes[0];
this.sa =bytes[1];
this.length =bytes[2];
.........
.........
Complete Packet Class
staticvmm_log log =new("Packet","Class");
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];//Payload using Dynamic array,size is generated on the fly
randbytefcs;
functionnew();
super.new(this.log);
endfunction:new
virtualfunctionvmm_data allocate();
Packet pkt;
pkt =new();
returnpkt;
endfunction:allocate
inti;
$write(psdisplay,"
%s
packet
#%0d.%0d.%0d\n",prefix,this.stream_id,this.scenario_id,this.data_id);
$write(psdisplay,"
%s%s
length:0x%h
$write(psdisplay," %s%s data[%0d]:0x%h",psdisplay,prefix,0,data[0]);
if(data.size()>1)
$write(psdisplay," data[%0d]:0x%h",1,data[1]);
if(data.size()>4)
$write(psdisplay,"....");
if(data.size()>2)
$write(psdisplay," data[%0d]:0x%h",data.size()-2,data[data.size()-2]);
if(data.size()>3)
$write(psdisplay,"\n %s%s fcs:0x%h \n",psdisplay,prefix,this.fcs);
endfunction

Packet cpy;
// Copying to a new instance?

if(to ==null)
cpy =new;
else
// Copying to an existing instance. Correct type?

if(!$cast(cpy,to))
begin
`vmm_fatal(this.log,"Attempting to copy to a non packet instance");
copy =null;
returncopy;
end
cpy.da =this.da;
cpy.sa =this.sa;
cpy.data=new[this.data.size()];
foreach(data[i])
begin
cpy.data[i]=this.data[i];
end
cpy.fcs =this.fcs;
copy =cpy;
endfunction:copy
virtualfunctionbitcompare(inputvmm_data to,outputstringdiff,inputint kind

=-1);
Packet cmp;

if(!$cast(cmp,to))
begin
`vmm_fatal(this.log,"Attempting to compare to a non packet instance");
compare=0;
diff ="Cannot compare non packets";
returncompare;
end

begin
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
if(this.length !=cmp.length)
begin
diff =$psprintf("Different LEN values: %b != %b",this.length,cmp.length);
compare=0;
returncompare;
end
foreach(data[i])
if(this.data[i]!=cmp.data[i])
begin
diff =$psprintf("Different
data[%0d]
values:
0x%h
!=
0x%h",i,this.data[i],cmp.data[i]);
compare=0;
returncompare;
end
if(this.fcs !=cmp.fcs)
begin
diff =$psprintf("Different FCS values: %b != %b",this.fcs,cmp.fcs);
compare=0;
returncompare;
end
endfunction:compare
inputint kind =-1);
byte_pack =0;
bytes[0]=this.da;
bytes[1]=this.sa;
foreach(data[i])
bytes[3+i]=data[i];
bytes[this.data.size()+3]=fcs;
byte_pack =this.data.size()+4;
endfunction:byte_pack
inputintlen=-1,
inputintkind =-1);
this.da =bytes[0];
this.sa =bytes[1];
this.fcs =bytes[bytes.size()-1];
this.data=new[bytes.size()-4];
foreach(data[i])
this.data[i]=bytes[i+3];
returnbytes.size();
endfunction:byte_unpack
endclass
Vmm_data Methods
virtualfunctionstringpsdisplay (stringprefix ="");

virtualfunctionbitis_valid (bitsilent =1,intkind =-1);
virtualfunctionvmm_data allocate ();
virtualfunctionvmm_data copy (vmm_data to =null);
virtualfunctionbitcompare(
inputvmm_data to,outputstringdiff,inputintkind =-1);
functionvoiddisplay(stringprefix ="");
virtualprotectedfunctionvoidcopy_data (vmm_data to );
virtualfunctionintunsignedbyte_pack (
reflogic[7:0]bytes [],intunsignedoffset =0,intkind =-1);
virtualfunctionintunsignedbyte_unpack (
constreflogic[7:0]bytes [],inputintunsignedoffset =0,
inputintlen=-1,inputintkind =-1);
virtualfunctionintunsignedbyte_size (intkind =-1);
virtualfunctionintunsignedmax_byte_size (intkind =-1);
virtualfunctionvoidsave (intfile );
virtualfunctionbitload (intfile );
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TUTORIALS
VMM CHANNEL
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
The channel is the interface mechanism used by transactors to transfer transactions.

Transaction objects are produced or consumed by a transactor. Transactor can be a
generator or a driver or a scoreboard. In Transaction-level modeling multiple
processes communicate with each other by sending transactions through channels. For
example, to transfer a transaction from generator to a driver, we don't need to send
at signal level. To transfer a transaction from Driver to DUT, physical signals are used.
The channel transfers transactions between the verification components, and it serves
as a synchronizing agent between them.
Assertion
DPI

input is what keeps
with time!
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
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RVM Ethernet sample
Specman E
Interview Questions
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
Channels are similar to SystemVerilog mailboxes with advanced features. Vmm

Channels provides much richer feature functionality than a SV mailbox. vmm channels
are superset of mailboxs.
Some of the the benefits of channels over mailboxes:
Dynamic reconfiguration
Inbuilt notifications
Strict type checking
Out of order usage
task tee() for easy scoreboarding
Record and playback
task sneak() for monitors
Using `vmm_channel() macro , channels can be created.
`vmm_channel(Custom_vmm_data)
The above macro creates a channel Custom_vmm_data_channel . There are various
methods to access the channels.
In the following example, we will see
1) Channel creation using macros.
2) Constructing a channel.
3) Pushing a transaction in to channel.
4) Popping out a transaction from the channel.
We will create a channel for vmm_data for this example. Users can create a channel
for any transaction which is derived from the vmm_data class. You can try this
http://testbench.in/VM_05_VMM_CHANNEL.html[9/26/2012 2:24:58 PM]
example by creating channel for Packet class which is discussed in previous section.
1) Define a channel using macro
`vmm_channel(vmm_data)
2) Construct an object of channel which is defined by the above macro.
vmm_data_channel p_c =new("p_c","chan",10);
3) Push a packet p_put in to p_c channel.
p_c.put(p_put);
4) Get a packet from p_c channel.
p_c.get(p_put);
Complete Example
`vmm_channel(vmm_data)
programtest_channel();
vmm_data p_put,p_get;
vmm_data_channel p_c =new("p_c","chan",10);
inti;
initial
repeat(10)
begin
#($urandom()%10);
p_put =new(null);
p_put.stream_id =i++;
$display(" Pushed a packet in to channel with id %d",p_put.stream_id);
p_c.put(p_put);// Pushing a transaction in to channel
end
initial
forever
begin
p_c.get(p_get);// popping a transaction from channel.
$display(" Popped a packet from channel with id %d",p_get.stream_id);
end
endprogram
Download the file
vmm_channel.tar
Browse the code in vmm_channel.tar
Log report
Pushed a packet in to channel with id 0
Popped a packet from channel with id 0

Vmm Channel Methods.
functionnew(stringname,stringinstance,
intunsignedfull =1,intunsignedempty=0,bitfill_as_bytes =0);
functionvoidreconfigure (intfull =-1,intempty=-1,logicfill_as_bytes =1'bx);
functionintunsignedfull_level ();
functionintunsignedempty_level ();
functionintunsignedlevel ();
functionintunsignedsize();
functionbitis_full ();
functionvoidflush ();
functionvoidsink ();
functionvoidflow ();
functionvoidlock (bit[1:0]who );
functionvoidunlock (bit[1:0]who );
functionbitis_locked (bit[1:0]who );
taskput(class_name obj,intoffset =-1);
functionvoidsneak (class_name obj,intoffset =-1);
functionclass_name unput (intoffset =-1);
taskget(outputclass_name obj,inputintoffset =0);
taskpeek(outputclass_name obj,inputintoffset =0);
taskactivate (outputclass_name obj,inputintoffset =0);
functionclass_name active_slot ();
functionclass_name start();
functionclass_name complete (vmm_data status=null);
functionclass_name remove ();
functionactive_status_e status();
tasktee (outputclass_name obj );
functionbittee_mode (bitis_on );
functionvoidconnect (vmm_channel downstream );
functionclass_name for_each (bitreset =0);
functionintunsignedfor_each_offset ();
functionbitrecord (stringfilename );
taskbitplayback (outputbitsuccess,inputstringfilename,
inputvmm_data loader,inputbitmetered =0);
Refer to VMM book for details of each method.
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Index
Introduction
Vmm Log
Vmm Env
VMM has two types of generators. Atomic generator and Scenario generator.
Vmm Data
Vmm Channel
Atomic generator is a simple generator which generates transactions randomly.
`vmm_atomic_gen is a macro which is used to define a class named Vmm Xactor
<class_name>_atomic_gen for any user-specified class derived from vmm_data, using Vmm Callback
Vmm Test
a process similar to the `vmm_channel macro.
Vmm Channel Record
And Playback
Vmm Opts
VMM ATOMIC GENERATOR

input is what keeps
with time!
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Verilog
Verification
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Basic Constructs
To use <class_name>_atomic_gen class, a <class_name>_channel must exist.

<class_name>_atomic_gen
generates
transactions
and
pushes
it
to
<class_name>_channel. A <class_name>_channel object can be passed to generator
while constructing.
functionnew(stringinstance,
intstream_id =-1,
<class_name>_channel out_chan =null);
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
The generator will stop generating the transaction after generating

stop_after_n_insts.User can set the stop_after_n_insts to any unsigned int value. By
default this values is 0.
If stop_after_n_insts is 0, then generator generates infinite number of transactions.
If stop_after_n_insts is non zero positive number, then generator generates
stop_after_n_insts transactions.
We will see an example of creating a atomic generator for a packet class. Packet class
is in file Packet.sv .
1) define `vmm_atomic_gen macro for packet class. This macro creates a
packet_atomic_gen class creates and randomizes packet transactions.
`vmm_atomic_gen(packet,"packet atomic generator")
2) define `vmm_channel for the packet class. This macro creates a packet_channel
which will be used by the packet_atomic_gen to store the transactions. Any other
component can take the transactions from this channel.
http://testbench.in/VM_06_VMM_ATOMIC_GENERATOR.html[9/26/2012 2:25:08 PM]
`vmm_channel(packet)
3) Create an object of pcakt_atomic_gen.
packet_atomic_gen pkt_gen =new("Atomic Gen","test");
4) Set the number of transactions to be generated to 4
pkt_gen.stop_after_n_insts =4;
5) Start the generator to generate transactions. These transactions are available to
access through pkt_chan as soon as they are generated.
pkt_gen.start_xator();
6) Collect the packets from the pkt_chan and display the packet content to terminal.
pkt_gen.out_chan.get(pkt);
pkt.display();
Completed Example
`vmm_channel(Packet)
`vmm_atomic_gen(Packet,"Atomic Packet Generator")
programtest_atomic_gen();
Packet_atomic_gen pkt_gen =new("Atomic Gen","test");

Packet pkt;
initial
begin
pkt_gen.stop_after_n_insts =4;
#100;pkt_gen.start_xactor();
end
initial
#200forever
begin
pkt_gen.out_chan.get(pkt);
pkt.display();
end
endprogram
vmm_atomic_gen.tar
Browse the code in vmm_atomic_gen.tar
Commands to run the simulation
Log file report
packet #1952805748.0.0
da:0xdb
sa:0x71
length:0x0e (data.size=1)
data[0]:0x63
fcs:0xe9
packet #1952805748.0.1
da:0xa7
sa:0x45
length:0xa4 (data.size=5)
data[0]:0x00 data[1]:0x4f.... data[3]:0xe7 data[4]:0xd8
fcs:0x31
packet #1952805748.0.2
da:0x15
sa:0xe6
length:0xa1 (data.size=1)
data[0]:0x80
fcs:0x01
packet #1952805748.0.3
da:0xd7
sa:0xa9
length:0xdc (data.size=3)
data[0]:0xcc data[1]:0x7c data[1]:0x7c
fcs:0x67
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Index
Introduction
Vmm Log
Vmm Env
This base class is to be used as the basis for all transactors, including bus-functional Vmm Data
models, monitors and generators. It provides a standard control mechanism expected Vmm Channel
to be found in all transactors.
Vmm Xactor
Vmm Callback
virtual function void start_xactor();
Starts the execution threads in this transactor instance. This method is called by Vmm Test
Vmm Channel Record
Environment class which is extended from vmm_env start() method.
And Playback
virtual function void stop_xactor();
Vmm Opts
Stops the execution threads in this transactor instance. This method is called by
Environment class which is extended from vmm_env stop() method.
VMM XACTOR

protected task wait_if_stopped()
input is what keeps
protected task wait_if_stopped_or_empty(vmm_channel chan)
Blocks the thread execution if the transactor has been stopped via the stop_xactor() with time!
method or if the specified input channel is currently empty.
protected virtual task main();

This task is forked off whenever the start_xactor() method is called. It is terminated
whenever the reset_xactor() method is called. The functionality of a user-defined
transactor must be implemented in this method.
VMM Ethernet sample Let us see an example of using vmm_xactor.
1) Extend vmm_xactor to create a custom_xtor.
Verilog
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Basic Constructs
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Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
classDriver extendsvmm_xactor;
2) Define constructor. In this example, we don't have any interfaces of channels, we
will not implement them.
Call the super.new() method.
functionnew();
super.new("Driver Transactor","inst",0);
endfunction:new
3) Define main() method.
First call the super.main() method.
Then define the activity which you want to do.
taskmain();
super.main();
Specman E
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foreverbegin
#100;
$display(" Driver : %d",$time);
end
endtask:main
Now we will see how to use the above defined Custom_xtor class.
1) Create a object of Custom_xtor.
Driver drvr =new();
http://testbench.in/VM_07_VMM_XACTOR.html[9/26/2012 2:25:17 PM]
2) Call the start_xactor() methods of Custom_xtor object.

Now the main() method which is defined starts gets executed.
#100drvr.start_xactor();
3) Call the stop_xactor() methos.
This will stop the execution of main() method.
#1000drvr.stop_xactor();
Complete Vmm_xactor Example
functionnew();
super.new("Driver Transactor","inst",0);
endfunction:new
taskmain();
super.main();
foreverbegin
#100;
$display(" Driver : %d",$time);
end
endtask:main
endclass:Driver
programtest();
Driver drvr =new();
initial
fork
join
endprogram
Download the files
vmm_xactor.tar
Browse the code in vmm_xactor.tar
Log file report
Driver :200
Driver :300
Driver :400
Driver :500
Driver :600
Driver :700
Driver :800
Driver :900
Driver : 1000
$finish at simulation time 1000
Vmm_xactor Members
functionnew(stringname,stringinstance,intstream_id =-1);
virtualfunctionstringget_name ();
virtualfunctionstringget_instance ();
vmm_log log;
intstream_id;
virtualfunctionvoidprepend_callback (vmm_xactor_callbacks cb );
virtualfunctionvoidappend_callback (vmm_xactor_callbacks cb );
virtualfunctionvoidunregister_callback (vmm_xactor_callbacks cb );
vmm_notify notify;
// Enumeration values for the state of the transactor:
enum{XACTOR_IDLE,XACTOR_BUSY,
XACTOR_STARTED,XACTOR_STOPPED,XACTOR_RESET};
virtualfunctionvoidstart_xactor ();
virtualfunctionvoidstop_xactor ();
virtualfunctionvoidreset_xactor (reset_e rst_typ =SOFT_RST);
protectedtaskwait_if_stopped ();
protectedtaskwait_if_stopped_or_empty (vmm_channel chan );
protectedvirtualtaskmain ();
virtualfunctionvoidsave_rng_state ();
virtualfunctionvoidrestore_rng_state ();
virtualfunctionvoidxactor_status (stringprefix ="");
// Macro to simplify the calling of callback methods:
`vmm_callback(callback_class_name,method (args ))
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TUTORIALS
VMM CALLBACK
SystemVerilog
Callback mechanism is used for altering the behavior of the transactor without
modifying the transactor. One of the many promises of Object-Oriented programming
is that it will allow for plug-and-play re-usable verification components. Verification
Designers will hook the transactors together to make a verification environment. In
SystemVerilog, this hooking together of transactors can be tricky. Callbacks provide a
mechanism whereby independently developed objects may be connected together in
simple steps.
Verification
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This article describes vmm callbacks. Vmm callback might be used for simple
notification, two-way communication, or to distribute work in a process. Some
requirements are often unpredictable when the transactor is first written. So a
transactor should provide some kind of hooks for executing the code which is defined
afterwards. In vmm, these hooks are created using callback methods. For instance, a
driver is developed and an empty method is called before driving the transaction to
the DUT. Initially this empty method does nothing. As the implementation goes, user
may realize that he needs to print the state of the transaction or to delay the
transaction driving to DUT or inject an error into transaction. Callback mechanism
allows executing the user defined code in place of the empty callback method.Other
example of callback usage is in monitor. Callbacks can be used in a monitor for
collecting coverage information or for hooking up to scoreboard to pass transactions
for self checking. With this, user is able to control the behavior of the transactor in
verification environment and individual testcases without doing any modifications to
the transactor itself.
Following are the steps to be followed to create a transactor with callbacks. We will
VMM Ethernet sample see simple example of creating a Driver transactor to support callback mechanism.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
1) Define a facade class.

Extend the vmm_xactor_callbacks class to create a faced class.
Define required callback methods. All the callback methods must be virtual.
In this example, we will create callback methods which will be called before driving
the packet and after driving the packet to DUT.
classDriver_callbacks extendsvmm_xactor_callbacks;
Switch TB
endclass
RVM Switch TB
2) Calling callback method.
RVM Ethernet sample Inside the transactor, callback methods should be called whenever something
Specman E
Interview Questions
interesting happens.
We will call the callback method before driving the packet and after driving the
packet. We defined 2 methods in facade class. We will call pre_send() method before
sending the packet and post_send() method after sending the packet.
Using a `vmm_callback(,) macro, callback methods are called.
There are 2 argumentd to `vmm_callback(,) macro.
First argument must be the facade class.
Second argument must be the callback method in the facade class.
To call pre_send() method , use macro

`vmm_callback(Driver_callbacks,pre_send());
and simillary to call post_send() method,
`vmm_callback(Driver_callbacks,post_send());
http://testbench.in/VM_08_VMM_CALLBACK.html[9/26/2012 2:25:28 PM]
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
input is what keeps
with time!
Place the above macros before and after driving the packet.
virtualtaskmain();
super.main();
foreverbegin
#40;
end
endtask
With this, the Driver implementation is completed with callback support.
Complete Source Code
endclass
functionnew();
super.new("Driver","class");
endfunction
virtualtaskmain();
super.main();
foreverbegin
#40;
end
endtask
endclass
Let's run the driver in simple testcase. In this testcase, we are not changing any
callback methods definitions.
programtesting_callbacks();
Driver drvr =new();
initial
begin
end
endprogram
Download files
vmm_callback.tar
Browse the code in vmm_callback.tar
Log report
Following steps are to be performed for using callback mechanism to do required
functionality.
We will see how to use the callbacks which are implemented in the above defined
driver in a testcase.
1) Implement the user defined callback method by extending facade class of the
driver class.
We will delay the driving of packet be 20 time units using the pre_send() call back
method.
We will just print a message from post_send() callback method.
classCustom_Driver_callbacks_1 extendsDriver_callbacks;
%d",$time);
#20;
endtask
endtask
Custom_Driver_callbacks CDc =new();
3) Register the callback method. vmm_xactor class has append_callback() which is
used to register the callback.
drvr.append_callback(CDc_1);
Driver drvr =new();
%d",$time);
#20;
endtask
endtask
endclass
Custom_Driver_callbacks_1 CDc_1 =new();
initial
begin
end
endprogram
vmm_callback_1.tar
Browse the code in vmm_callback_1.tar
Simulation Command
Run the testcase. See the log results; We delayed the driving of packet by 20 time
units using callback mechanism. See the difference between the previous testcase log
and this log.
Log report
Now we will see registering 2 callback methods.

1) Define another user defined callback methods by extending facade class.
endtask
endclass
3) Register the object
Driver drvr =new();
%d",$time);
#20;
endtask
endtask
endclass
endtask
endclass
initial
begin
end
endprogram
Download source code
vmm_callback_2.tar
Run the testcase and analyze the result.
Log report
The log results show that pre_send() method of CDc_1 is called first and then
pre_send() method of Cdc_2. This is beacuse of the order of the registering callbacks.
Now we will see how to change the order of the callback method calls.
Use prepend_callback() method for registering instead of append_callback() method.
Driver drvr =new();
%d",$time);
#20;
endtask
endtask
endclass
endtask
endclass
initial
begin
drvr.prepend_callback(CDc_2);
end
endprogram
vmm_callback_3.tar
Run and analyze the results.
Log results show that, pre_send() method of CDs_1 is called after calling CDs_2
pre_send() method.
Log file report

Vmm also provides method to remove the callback methods which are registered.
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Index
Introduction
Vmm Log
Vmm Env
vmm_test is introduced in vmm 1.1.
Vmm Data
Vmm Channel
To know the vmm version which you are using, use this command
vcs -R -sverilog -ntb_opts dtm
Vmm Xactor
+incdir+$VMM_HOME/sv $VMM_HOME/sv/vmm_versions.sv
Vmm Callback
Vmm Test
vmm_test is used for compiling all the testcases in one compilation. The simulation of Vmm Channel Record
each testcase is done individually. Traditionally for each testcase, compile and And Playback
simulation are done per testcase file. With this new approach, which dose compilation Vmm Scenario Generator
Vmm Opts
only once, will save lot of cup.
VMM TEST
VMM Tutorial
Generally each testcase can be divided into two parts.
OVM Tutorial
Procedural code part.
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The procedural code part (like passing the above new constrained transaction
definition to some atomic generator, calling the env methods etc) has to be defined
between these macros. vmm provides 2 macros to define testcase procedural part.
`vmm_test_begin(testcase_name,vmm_env,"Test Case Name String")
`vmm_test_env(testcase_name)
VMM Ethernet sample Declarative code part.
Verilog
The declarative part( like new constrained transacting definition) is defined outside
these macros.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Writing A Testcase
Let us see an example of writing a testcase.
Inside the testcase, we will define a new transaction and pass this transaction to the
atomic generator.
Switch TB
Declarative part:
RVM Switch TB
1) Define all the declarative code.
RVM Ethernet sample
Specman E
Interview Questions
classconstrained_tran extendspcie_transaction;
// Add some constraints

// Change some method definitions
endclass
2) Define a handle to the above object.
constrained_tran c_tran_obj;
Procedural part:
Use a `vmm_test_begin . There are 3 arguments to macro.
http://testbench.in/VM_09_VMM_TEST.html[9/26/2012 2:25:39 PM]

input is what keeps
with time!
The first argument is the name of the testcase class and will also be used as the name
of the testcase in the global testcase registry.
The second argument is the name of the environment class that will be used to
execute the testcase. A data member of that type named "env" will be defined and
assigned, ready to be used.
The third argument is a string documenting the purpose of the test.
`vmm_test_begin(test_1,vmm_env,"Test_1")
In this testcase, we want to pass the c_tran_obj object. The steps t pass the
c_tran_obj as per the vmm_env is
env.build();
c_tran_obj =new(" ");
env.atomic_gen.randomized_obj =c_tran_obj;
Start the vmm_env execution.
env.run();
Now use `vmm_test_end to define the end of the testcase. The argument to this is
the testcase name.
`vmm_test_end(test_1)
Following is the full testcase source code which we discussed above.
Testcase source code
classconstrained_tran extendspcie_transaction;
endclass
constrained_tran c_tran_obj
$display(" Start of Testcase :Test_1 ");
env.build();
c_tran_obj =new(" ");
env.atomic_gen.randomized_obj =c_tran_obj;
env.run();
$display(" End of Testcase : Test_1 ");
Like this you can write many testcases in separate file or single file.
Example Of Using Vmm_test
Now we will implement 3 simple testcases and a main testcase which will be used for
selecting any one of the 3 testcases.
testcase_1
Write this testcase in a testcase_1.sv file
// Define all the declarative code hear. I done have anything to show you.
//
//class constrained_tran extends pcie_transaction;
//
//end class
//
//constrained_tran c_tran_obj
// This is procedural part. You can call build method.
env.build();
// You can pass the above created transaction to atomic gen.

// c_tran_obj = new(" ");
// env.atomic_gen.randomized_obj = c_tran_obj;
//
//
env.run();
testcase_2
// Do something like this ....
env.build();
// like this ....
env.run();
testcase_3
// Do something like this ....
env.build();
// like this ....
env.run();
main testcase
Now we will write the main testcase. This doesn't have any test scenario, it is only
used for handling the above 3 testcases.
This should be written in program block.
1)First include all the above testcases inside the program block.
ìnclude"testcase_1.sv"
2)Define env class object.
vmm_env env =new();
As I dont have a custom env class to show, I used vmm_env. You can use your custom
defined env.
3)In the initial block call the run() method of vmm_test_registry class and pass the
above env object as argument. This run method of vmm_test_registry is a static
method, so there is no need to create an object of this class.
vmm_test_registry::run(env);
Main testcase source code
ìnclude"vmm.sv"
programmain();
vmm_env env;
initial
begin
$display(" START OF TEST CASE ");
env =new();
vmm_test_registry::run(env);
$display(" START OF TEST CASE ");
end
endprogram
Now compile the above code using command.
vcs -sverilog main_testcase.sv +incdir+$VMM_HOME/sv

Now simulate the above compiled code.
To simulate , just do ./simv and see the log.
You can see the list of the testcases. This simulation will not ececute any testcase.
LOG
START OF TEST CASE
*FATAL*[FAILURE] on vmm_test_registry(class) at0:
No test was selected at runtime using +vmm_test=<test>.
Available tests are:
0) Default : Default testcase that simply calls env::run()
1) test_1: Test_1
2) test_2: Test_2
3) test_3: Test_3
To run testcase_1 use ./simv +vmm_test=test_1
LOG
START OF TEST CASE
Normal[NOTE] on vmm_test_registry(class) at0:
Running test "test_1"...
Start of Testcase :Test_1
demoted warnings)
End of Testcase : Test_1
START OF TEST CASE
Simillarly to run testcase_2 ./simv +vmm_test=test_2
LOG
START OF TEST CASE
Running test "test_2"...
Start of Testcase :Test_2
demoted warnings)
End of Testcase : Test_2
START OF TEST CASE
You can also call the Default testcase, which just calls theenv::run()
./simv +vmm_test=Default
LOG
START OF TEST CASE
Running test "Default"...
demoted warnings)
START OF TEST CASE

vmm_test.tar
Browse the code in vmm_test.tar
Command to compile
vcs -sverilog -ntb_opts dtm +incdir+$VMM_HOME/sv main_testcase.sv
Commands to simulate testcases
./simv
./simv
./simv
./simv
./simv
+vmm_test=Default
+vmm_test=test_1
+vmm_test=test_2
+vmm_test=test_3
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TUTORIALS
VMM CHANNEL RECORD AND PLAYBACK
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The purpose of this channel feature is to save all the incoming transaction to the
specified file and play back the transaction from the file.
This will be useful when we want to recreate a random scenario in different
environment. For example, you found a very interesting random scenario in 10G speed
Ethernet. Now you want to use the same random scenario on 1G Ethernet. It may not
be possible to reproduce the same scenario at 1G speed even with the SV random
stability. The other way is to write a directed testcase to recreate the same scenario.
Using this Record/playback feature, we can record the transaction in the 10G speed
Ethernet and then play this scenario at 1G speed Ethernet.
One more advantage of this feature is, it allows us to shutdown the activities of some
components. For Example, consider a layered protocol, the Ethernet. The Verification
environment can be developed with layers of transactors corresponding to each
protocol layer like, TCP over IP laver, IP fragment and reassembly layer, IP fragment
over Ethernet and Ethernet layer. All these layers will be connected using channels.
With record/playback feature, the input transaction to Ethernet layer can be
recorded and in the next simulation, we can shutdown the TCP over IP laver, IP
fragment and reassembly layer, IP fragment over Ethernet layers transactors and by
playing back the recorded transactions. This will improve the memory consumption
and execution speed.
Record/Playback is independent of Random stability. Changing the seed value will not
affect the playback. This will give us an opportunity to test the DUT using a specific
VMM Ethernet sample scenario of the high layer (Consider the previous example: Some interested scenario
in IP fragment over Ethernet) with lot of different randomization using different seeds
of lower layer protocol (Ethernet layer).
Verilog
This will also help, when we cannot reproduce the random scenario using Seed. If you
Verification
found a Bug in the DUT, and still you are in the development stage of your
Verilog Switch TB
environment, you cannot stop the development in the environment till the bug is
fixed. There are chances that the changes in the environment will not allow you to
Basic Constructs
reproduce the same scenario even with the same seed. In this case, if you have stored
the transactions, you can playback the transaction.
AVM Switch TB
OpenVera
Constructs
Switch TB
RVM Switch TB
Now we will learn about the implementation.

Recording
RVM Ethernet sample To record the flow of transaction descriptors added through the channel instance, call
the record method of that instance.
Specman E
Interview Questions
functionbitrecord(stringfilename);
The vmm_data::save() method must be implemented for recording.All the
transaction which are added to channel using the vmm_channel::put() method are
recorded and are avilabe for playback. A null filename stops the recording process.
vmm_channel::record() method returns TRUE if the specified file was successfully
opened.
RECORDING notification is indicated by vmm_channel::notify, when recording.
Playing Back
To playback the transactions in the recorded file, use the vmm_channel::playback()
http://testbench.in/VM_10_VMM_CHANNEL_RECORD_AND_PLAYBACK.html[9/26/2012 2:25:48 PM]
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
input is what keeps
with time!
method.
taskplayback(outputbitsuccess,
inputstringfilename,
inputvmm_datafactory,
inputbit metered =0,
inputvmm_scenario grabber =null);
This method will block the sources of the current channel like vmm_channl::put()
method till the playback is completed. The vmm_data::load() method must be
implemented for playback. The order of the transaction will be same as the order
while recording. If the metered argument is TRUE, the transaction descriptors are
added to the channel with the same relative time interval as they were originally put
in when the file was recorded.
The success argument is set to TRUE if the playback was successful. If the playback
process encounters an error condition such as a NULL (empty string) filename, a
corrupt file or an empty file, then success is set to FALSE.
PLAYBACK_DONE notification is indicated by vmm_channel::notify, when playback is
completed.
EXAMPLE
Let us write an example to see how the record and playback works.
Record & Playback of channels can be used with atomic generator and scenario
generators. Here is a simple transaction with its channel and atomic generator. We
will use this atomic generator to generate transaction. The atomic generator has
out_chan channel, this channel is used send the generated transaction. We will record
and playback the transaction in the out_chan. I used Vmm_data macros for
implementing all the required methods.
classtrans extendsvmm_data;
typedefenumbit{BAD_FCS=1'b0,GOOD_FCS=1'b1}kind_e;
randbit[47:0]DA;
randbit[47:0]SA;
randintlength;
randkind_e kind;
`vmm_data_member_begin(trans)
`vmm_data_member_scalar(DA,DO_ALL)
`vmm_data_member_scalar(SA,DO_ALL)
`vmm_data_member_scalar(length,DO_ALL)
`vmm_data_member_enum(kind,DO_ALL)
`vmm_data_member_end(trans)
endclass
// for declaring trans_channel

`vmm_channel(trans)
// for declaring trans_atomic_gen

`vmm_atomic_gen(trans,"Gen")
Now we will write a simple program to record and play back the above defined
transaction.
Use the trans_atomic_gen to generate the transactions. This also the put the
transactions in to out_chan channel. Call the start_xactor() method of the generator
to start the generator of transaction. Call the record() method of out_chan to record
the incoming transactions.
gen.stop_after_n_insts =3;
gen.start_xactor();
gen.out_chan.record("Trans_recordes.tr");
To play back the recorded transactions, call the playback method. Then check if the
playback is fine.
tr =new();
gen.out_chan.playback(success,"Trans_recordes.tr",tr);
if(!success)
$display(" Failed to playback Trans_recordes.tr"); ]
Now we will write a logic which gets the transaction from the channel and prints the
content to terminal, so that we can observe the results.
The above the logic generates 3 transactions. Get the 3 transaction from the channel
and print the content.
initial
repeat(3)
begin
#10;
gen.out_chan.get(tr);
tr.display();
end
Complete source code
programmain();
trans tr;
trans_atomic_gen gen =new("Atomic Gen",1);
bitsuccess;
// This is the producer logic.

// Transactions are produced from Atomic generator in RECORD mode.
// Transactions are produced from recorded file in PLAYBACK mode.
initial
begin
if($test$plusargs("RECORD"))
begin
$display(" RECORDING started ");
gen.start_xactor();
end
elseif($test$plusargs("PLAYBACK"))
begin
$display(" PLAYBACK started ");
tr =new();
if(!success)
$display(" Failed to playback Trans_recordes.tr");
end
else
$display(" give +RECORD or +PLAYBACK with simulation command");
end
// This is consumer logic.

initial
repeat(3)
begin
#10;
tr.display();
end
endprogram
This works with vmm 1.1 and above.

vmm_record_playback.tar
Browse the code in vmm_record_playback.tar
Command to record the transaction
vcs -R -sverilog +incdir+$VMM_HOME/sv record_playback.sv +RECORD
Log file
RECORDING started
trans (1.0.0):
DA='haecd55f5b651
SA='h13db0b1a590e
length='hd8a7d371
kind=GOOD_FCS
trans (1.0.1):
DA='h5e980e9b7ce9
SA='h44a4bbdaf703
length='h5714c3a7
kind=GOOD_FCS
trans (1.0.2):
DA='hba4f5a021300
SA='h2de750b6cc3e
length='h22ca2bd8
kind=GOOD_FCS
You can also see a file named "Trans_recordes.tr" in your simulation directory.
Command to playback the transaction
vcs -R -sverilog +incdir+$VMM_HOME/sv trans.sv +PLAYBACK
Log File
PLAYBACK started
trans (0.0.0):
DA='haecd55f5b651
SA='h13db0b1a590e
length='hd8a7d371
kind=GOOD_FCS
trans (0.0.0):
DA='h5e980e9b7ce9
SA='h44a4bbdaf703
length='h5714c3a7
kind=GOOD_FCS
trans (0.0.0):
DA='hba4f5a021300
SA='h2de750b6cc3e
length='h22ca2bd8
kind=GOOD_FCS
Look, the same transactions which were generated while RECORDING are played
back.
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Easy Labs : SV
Index
Introduction
Vmm Log
Atomic generator generates individual data items or transaction descriptors. Each Vmm Env
item is generated independently of other items in a random fashion. Atomic generator Vmm Data
Vmm Channel
is simple to describe and use.
Vmm Xactor
Unlike atomic generator, a scenario generator generates a sequence of transaction.
Vmm Callback
Vmm Test
Example of sequence of transaction:
Vmm Channel Record
And Playback
CPU instructions like LOAD__A,LOAD__B,ADD_A_B,STORE_C.
Vmm Scenario
Packets with incrementing length.
Generator
Do write operation to address "123" and then do the read to address "123".
Vmm Opts
It is very unlikely that atomic generator to generate transaction in the above ordered Report a Bug or Comment
sequence. With scenario generator, we can generate these sequence of transaction.
VMM SCENARIO GENERATOR
VMM provides `vmm_scenario_gen() macro for quickly creating a scenario generator.
Easy Labs : UVM
`vmm_scenario_gen(class_name,"Class Description");
Easy Labs : OVM
The
macro
defines
classes
named
<class_name>_scenario_gen,
<class_name>_scenario,
<class_name>_scenario_election
,
<class_name>_scenario_gen_callbacks and <class_name>_atomic_scenario.
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample classcustom_scenario_gen extendsvmm_xactor;
Verilog
Verification
classcustom_scenario extendsvmm_data;
classcustom_atomic_scenario extendscustom_scenario;
classcustom_scenario_election;
classcustom_scenario_gen_callbacks extendsvmm_xactor_callbacks
Verilog Switch TB
<class_name>_scenario:
Basic Constructs
This scenario generator can generate more than one scenario. Each scenario which
can contain more than one transaction is described in a class which is extended from
<class_name>_scenario.
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
For each scenario, following variables must be constraint.

Length: number of transactions in an array.
Repeated: number of times to repeat this scenario.
<class_name>_atomic_scenario:
This class is a atomic scenario. This is the default scenario. This scenario is a random
transactions.
Specman E
Interview Questions
<class_name>_scenario_election:
This class is the arbiter which determines the order that the known scenarios are
applied. By default, scenarios are elected atomically. User can extend this class to
define an order in which the scenarios should be picked.
<class_name>_scenario_gen:
This class is the scenario generator which generates the transactions and sends out
using output channel. This class has a queue of scenario objects. Each scenario
contains transaction instances in an array.
http://testbench.in/VM_11_VMM_SCENARIO_GENERATOR.html[9/26/2012 2:25:58 PM]
input is what keeps

with time!
<class_name>_scenario_gen_callbacks:
This class provides callback mechanism. There are two callback methods define.
pre_scenario_randomize() and post_scenario_gen() which are called at prerandomization of the scenario and post-generation of the scenario respectively.
Example
Let us write an example.
Following is the transaction class which we will use to write a scenario generator.
classinstruction extendsvmm_data;
vmm_log log;
typedefenum{LOAD__A,LOAD__B,ADD_A_B,SUB_A_B,STORE_C}kinds_e;
randkinds_e inst;
functionnew();
endfunction:new
psdisplay =$psprintf("Instruction : %s | stream_id : %0d | scenario_id : %0d
",inst.name(),stream_id,scenario_id);
endfunction:psdisplay
instruction tr =new;
allocate =tr;
virtualfunctionvmm_data copy(vmm_data cpy =null);
instruction to;
if(cpy ==null)
to =new;
else
if(!$cast(to,cpy))begin
`vmm_fatal(this.log,"Attempting to copy to a non instruction instance");
returnnull;
end
super.copy_data(to);
to.inst =this.inst;
copy =to;
endfunction:copy
endclass
The above transaction crests CPU instructions.

Let us consider that sequence of instruction LOAD__A,LOAD__B,ADD_A_B,STORE_Cis
a interesting scenario and LOAD__A,LOAD__B,SUB_A_B,STORE_C is also an interesting
scenario.
When instructions are generated, we want to generate these 2 sequences of
instruction. Let us see how to generate these 2 sequence of instructions .
As we have already discussed, `vmm_scenario_gen() creates use full class for
cscenario generation.
1) Use`vmm_scenario_gen() macro to declare the scenario classes.
`vmm_scenario_gen(instruction,"Instruction Scenario Generator")
This macro will create following classs
instruction_scenario_gen
instruction_scenario
instruction_atomic_scenario
instruction_scenario_election
instruction_scenario_gen_callbacks
2) Define interesting scenarios by extending inst_scenario;
classinstruction_scenario_add_sub extendsinstruction_scenario;
3) Define the first scenario. It is sequence of instructions for addition operation.
a) Declare a variable for identifying the scenario.
intaddition_scenario_id;
Each scenario has more than one inductions. All these instructions are in a queue
"items" which is already defined in"instruction_scenario".
The rand varible "scenario_kind", which pre defined in the vmm_scenario class, will
randomly select one of the defined scenarios. "scenario_kind" varible has the id of the
current scenario. So we have to define the addition scenario, when the
"scenario_kind" value is addition_scenario_id.
b) Constrain the scenario kind,
constraintaddition_scenario_items {
if($void(scenario_kind)==addition_scenario_id){
c)The number of instructions define in a scenario is specified by the predefined
variable "length". In our example, we have 4 instructions. So constrain the length to 4.
length ==4;
d) The predefined variable "repeated" used to control if the VMM scenario generator
would run the scenario more than once each time it is created. We are not interested
in repeating so, constrain it to 0
repeated ==0;
e) Constrain the individual items based on the requirements if this scenario is
selected. Our requirement in this example is that "inst" should follow the sequence
LOAD__A,LOAD__B,ADD_A_B,STORE_C
foreach(items[i])
if(i ==0)
this.items[i].inst ==instruction::LOAD__A;
elseif(i ==1)
this.items[i].inst ==instruction::LOAD__B;
elseif(i ==2)
this.items[i].inst ==instruction::ADD_A_B;
elseif(i ==3)
this.items[i].inst ==instruction::STORE_C;
4)Define second scenario. It is Sequence of instructions for subtraction operation.
a) Declare a variable for identifying the scenario.
intsubtraction_scenario_id ;
b) Constrain the scenario kind,
constraintsubtraction_scenario_items {
if($void(scenario_kind)==subtraction_scenario_id){
c) Constrain the length
length ==4;
d) Constrain the repeated
repeated ==0;
e) Constrain the items
foreach(items[i])
if(i ==0)
elseif(i ==1)
elseif(i ==2)
this.items[i].inst ==instruction::SUB_A_B;
elseif(i ==3)
5)Define constructor method.
a) call the super.new() method.
Get a unique Ids from the define_scenario() method for each scenario.
define_scenario() is predefined in*_scenario class.
functionnew();
this.addition_scenario_id =define_scenario(" ADDITION ",4);
this.subtraction_scenario_id =define_scenario(" SUBSTRACTION ",4);
endfunction
With this, we completed the implementation of scenarios.
Scenario Code
`vmm_scenario_gen(instruction,"Instruction Scenario Generator")
classinstruction_scenario_add_sub extendsinstruction_scenario;
///////////////////////////////////////////////////////////////
//////ADDITION SCENARIO//////////
///////////////////////////////////////////////////////////////
intaddition_scenario_id;
constraintaddition_scenario_items {
if($void(scenario_kind)==addition_scenario_id){
repeated ==0;
length ==4;
foreach(items[i])
if(i ==0)
elseif(i ==1)
elseif(i ==2)
this.items[i].inst ==instruction::ADD_A_B;
elseif(i ==3)
}
}
///////////////////////////////////////////////////////////////
//////ASUBTRACTION SCENARIO//////////
///////////////////////////////////////////////////////////////
intsubtraction_scenario_id ;
constraintsubtraction_scenario_items {
if($void(scenario_kind)==subtraction_scenario_id){
repeated ==0;
length ==4;
foreach(items[i])
if(i ==0)
elseif(i ==1)
elseif(i ==2)
this.items[i].inst ==instruction::SUB_A_B;
elseif(i ==3)
}
}
functionnew();
this.addition_scenario_id =define_scenario(" ADDITION ",4);
this.subtraction_scenario_id =define_scenario(" SUBSTRACTION ",4);
endfunction
endclass
Testcase
Now we will write a test case to see how to above defined scenario works.
1) Declare scenario generator
instruction_scenario_gen gen;
2) Declare the scenario which we defined earlier.
instruction_scenario_add_sub sce_add_sub;
3) Construct the generator and scenarios.
gen =new("gen",0);
sce_add_sub =new();
4) set the number of instances and scenarios generated by generator to 20 and 4
respectevy.
gen.stop_after_n_scenarios =4;
5) Scenario generators store all the scenarios in scenario_set queue. So, we have to
add the scenario which we constructed above to the queue.
gen.scenario_set[0]=sce_add_sub;
6) Start the generator
gen.start_xactor();
7) Similar t the Atomic generator, the transactionscreated by the scenario generator
are sent to out_chan channel.
Get the instructions from the out_chan channel and print the content.
repeat(20)begin
gen.out_chan.get(inst);
inst.display();
Testcase code
programtest();
instruction_scenario_gen gen;
instruction_scenario_add_sub sce_add_sub;
instruction inst;
initial
begin
gen =new("gen",0);
sce_add_sub =new();
//gen.log.set_verbosity(vmm_log::DEBUG_SEV,"/./","/./");
gen.stop_after_n_scenarios =4;
gen.scenario_set[0]=sce_add_sub;
gen.start_xactor();
repeat(20)begin
gen.out_chan.get(inst);
inst.display();
end
end
endprogram
Down load the source code
vmm_scenario.tar
Browse the code in vmm_scenario.tar
Command to simulate
vcs -sverilog -ntb_opts rvm -f filelist -R
Observe the log file,you can see the both the scenarios.
Logfile
Instruction
Instruction
Instruction
Instruction
:
:
:
:
LOAD__A | stream_id : 0 | scenario_id : 0

LOAD__B | stream_id : 0 | scenario_id : 0
ADD_A_B | stream_id : 0 | scenario_id : 0
STORE_C | stream_id : 0 | scenario_id : 0
Instruction
Instruction
Instruction
Instruction
:
:
:
:

Instruction
Instruction
Instruction
Instruction
:
:
:
:

SUB_A_B | stream_id : 0 | scenario_id : 2
Instruction
Instruction
Instruction
Instruction
:
:
:
:

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AVM Switch TB
Some of the test parameters in functional verification are passed from the command
line. Passing Parameters from the command line allows simulating the same testcase
file with different scenario. For example, let say you are verifying Ethernet protocol.
Insert_crc_error.sv is a testcase file which verifies the DUT by sending CRC error
packets. Now you can use the same testcase file to verify the DUT in 3 different
modes , 10G 1000M and 100M modes by passing these parameters from the command
prompt, this increases the testcase reusability.
As parameters became one of the most important techniques in reusing the testcases,
vmm has added vmm_opts class to manage parameters efficiently.
vmm_opts captures parameter from run time options.

input is what keeps
1) Command line
vmm_opts internally uses $plusargs to recognize the options specified on command Testbench.in improving
with time!
line.
There are 2 ways to specify the parameters during runtime.
2) text file
If you have lot of parameters to mentions, then you can also mention all the
parameters in a text file and pass it as command line options.
vmm_opts can recognize 3 types of parameters. They are
String type parameters
Integer type parameters
Bit type parameters
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Following are the 3 static methods which are defined in vmm_opts to get the
parameter values.
Static functionbitget_bit(stringname,stringdoc ="");
Static functionintget_int(stringname,intdflt =0,stringdoc ="");
OpenVera
Constructs
Switch TB
RVM Switch TB
Static functionstringget_string(stringname,stringdflt ="",stringdoc ="");

The first argument is the name of the parameter and the argument "doc" is description
of the runtime argument that will be displayed by the vmm_opts::get_help() method.
as these methods are static, user dont need to construct the object of vmm_opts.
RVM Ethernet sample Argument "dflt" is the default value.
How to give options

Specman E
Interview Questions
Index
Introduction
Vmm Log
Vmm Env
Vmm Data
Vmm Channel
Vmm Xactor
Vmm Callback
Vmm Test
Vmm Channel Record
And Playback
Vmm Opts
To supply a Boolean runtime option "foo" , use "+vmm_opts+...+foo+..." command-line

option, or "+vmm_foo" command-line option, or the line "+foo" in the option file.
To supply a integer value "5" for runtime option "foo", use the
"+vmm_opts+...+foo=5+..." command-line option, or "+vmm_foo=5" command-line
option, or the line "+foo=5" in the option file.
To supply a string value "bar" for runtime option "foo" , use the
"+vmm_opts+...+foo=bar+..." command-line option, or "+vmm_foo=bar" command-line
option, or the line "+foo=bar" in the option file.
To
supply
textfile
http://testbench.in/VM_12_VMM_OPTS.html[9/26/2012 2:26:08 PM]
which
contains
the
runtime
options,
use
"+vmm_opts_file=finename.txt"
+vmm_help command line option will print the run time options help. This option will
call the vmm_opts::get_help() method.
The following is a basic example of how these parameters could be received using
vmm_opts
EXAMPLE
ìnclude"vmm.sv"
classmy_env extendsvmm_env;
integerfoo1;
stringfoo2;
bitfoo3;
super.gen_cfg();
`vmm_note(log,"START OF GEN_CFG ");
foo1 =vmm_opts::get_int("foo1",10,"Help for the option foo1: pass any integer
between 0 to 100");
foo2 =vmm_opts::get_string("foo2","default_string","Help for the option foo2:
pass any string");
foo3 =vmm_opts::get_int("foo3","Help for the option foo3: just use foo3 to
enable ");
`vmm_note(log,$psprintf("\n Run time Options\n foo1 : %0d \n foo2 : %s
\n foo3 : %b \n",foo1,foo2,foo3));
`vmm_note(log,"END OF GEN_CFG ");
endfunction
endclass
programmain();
initial
begin
my_env env;
env =new();
env.run();
end
endprogram
vmm_opts.tar
Browse the code in vmm_opts.tar
Commands to complie
This works with vmm 1.1 and above.
vcs -sverilog -ntb_opts dtm +incdir+$VMM_HOME/sv main_testcase.sv
Commands to complie
./simv
./simv +vmm_foo1=101
./simv +vmm_opts+foo1=101+foo2=Testbench.in
Following is log file
+vmm_foo2=Testbench.in
generated
using
runtime
option+vmm_foo1=101
Log
Normal[NOTE] on Verif Env() at0:
START OF GEN_CFG
WARNING[FAILURE] on vmm_opts(class) at0:
No documentation specified for option "foo3".
Run time Options

foo1 : 101
foo2 : Testbench.in
foo3 : 0

END OF GEN_CFG
demoted warnings)
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Index
Introduction
Ovm Testbench
Ovm Reporting
The OVM Class Library provides the building blocks needed to quickly develop well- Ovm Transaction
constructed and reusable verification components and test environments in Ovm Factory
Ovm Sequence 1
SystemVerilog.
Ovm Sequence 2
Ovm Sequence 3
OVM library contains:
Component
classes
for
building
testbench
components
like Ovm Sequence 4
Ovm Sequence 5
generator/driver/monitor etc.
Ovm Sequence 6
Reporting classes for logging,
Ovm Configuration
Factory for object substitution.
Synchronization classes for managing concurrent process.
Policy classes for printing, comparing, recording, packing, and unpacking of on This section - Your
ovm_object based classes.
input is what keeps
TLM Classes for transaction level interface.
with time!
Sequencer and Sequence classes for generating realistic stimulus.
And Macros which can be used for shorthand notation of complex implementation.
INTRODUCTION
Easy Labs : UVM

Easy Labs : OVM
In this tutorial, we will learn some of the OVM concepts with examples.
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OT_01_INTRODUCTION.html[9/26/2012 2:26:16 PM]
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TUTORIALS
OVM TESTBENCH
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Ovm components, ovm env and ovm test are the three main building blocks of a
testbench in ovm based verification.
Ovm_env
Ovm_env is extended from ovm_componented and does not contain any extra
functionality. Ovm_env is used to create and connect the ovm_components like
driver, monitors ,sequeners etc.A environment class can also be used as subenvironment in another environment.As there is no difference between ovm_env and
ovm_component , we will discuss about ovm_component, in the next section.

input is what keeps
Verification Components
Ovm verification component classes are derived from ovm_component class which with time!
provides features like hierarchy searching, phasing, configuration , reporting , factory

and transaction recording.
Following are some of the ovm component classes

Ovm_agent
Easy Labs : VMM
Ovm_monitor
AVM Switch TB
Ovm_scoreboard
Ovm_driver
VMM Ethernet sample
Ovm_sequencer
Easy Labs : OVM
Verilog
Verification
Verilog Switch TB
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
NOTE: ovm_env and ovm_test are also extended from ovm_component.

A typical ovm verification environment:
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OT_02_OVM_TESTBENCH.html[9/26/2012 2:26:24 PM]
An agent typically contains three subcomponents: a driver, sequencer, and

monitor.If the agent is active, subtypes should contain all three subcomponents.If
the agent is passive, subtypes should contain only the monitor.
About Ovm_component Class:
Ovm_compoenent class is inherited from ovm_report_object which is inherited from
ovm_object.
As I mentioned previously, ovm_component class provides features like hierarchy
searching, phasing, configuration , reporting , factory and transaction recording.
We will discuss about phasing concept in this section and rest of the features will be
discussed as separate topics.
OVM phases
OVM Components execute their behavior in strictly ordered, pre-defined phases. Each
phase is defined by its own virtual method, which derived components can override to
incorporate component-specific behavior. By default , these methods do nothing.
-->virtualfunctionvoidbuild()
This phase is used to construct various child components/ports/exports and configures
them.
-->virtualfunctionvoidconnect()
This phase is used for connecting the ports/exports of the components.
-->virtualfunctionvoidend_of_elaboration()
This phase is used for configuring the components if required.
-->virtualfunctionvoidstart_of_simulation()
This phase is used to print the banners and topology.
-->virtualtaskrun()
In this phase , Main body of the test is executed where all threads are forked off.
-->virtualfunctionvoidextract()
In this phase, all the required information is gathered.
-->virtualfunctionvoidcheck()
In this phase, check the results of the extracted information such as un responded
requests in scoreboard, read statistics registers etc.
-->virtualfunctionvoidreport()
This phase is used for reporting the pass/fail status.
Onlybuild() method is executed in top down manner. i.e after executing
parentbuild() method, child objects build() methods are executed.All other
methods are executed in bottom-up manner.The run() method is the only method
which is time consuming. The run() method is forked, so the order in which all
components run() method are executed is undefined.
Ovm_test
Ovm_test is derived from ovm_component class and there is no extra functionality is
added.The advantage of used ovm_test for defining the user defined test is that the
test
case
selection
can
be
done
from
command
line
option
+OVM_TESTNAME=<testcase_string> . User can also select the testcase by passing the
testcase name as string to ovm_root::run_test(<testcase_string>)method.
In the above <testcase_string> is theobject type of the testcase class.
Lets implement environment for the following topology. I will describe the
implementation of environment , testcase and top module. Agent, monitor and driver
are implemented similar to environment.
1)Extend ovm_env class and define user environment.

classenv extendsovm_env;
2)Declare the utility macro. This utility macro provides the implementation of create()
and get_type_name() methods and all the requirements needed for factory.
òvm_component_utils(env)
3)Declare the objects for agents.
agent ag1;
agent ag2;
4)Define the constructor. In the constructor, call the super methods and pass the
functionnew(stringname,ovm_component parent =null);
endfunction:new
5)Define build method. In the build method, construct the agents.
To construct agents, usecreate() method.The advantage of create() over new() is
that when create() method is called, it will check if there is a factory override and
constructs the object of override type.
super.build();
ovm_report_info(get_full_name(),"Build",OVM_LOG);
endfunction
6)Define
connect(),end_of_elaboration(),start_of_simulation(),run(),extract(),check(),report()
methods.
Just print a message from these methods, as we dont have any logic in this example
to define.
ovm_report_info(get_full_name(),"Connect",OVM_LOG);
endfunction
Complete code of environment class:
classenv extendsovm_env;
òvm_component_utils(env)
agent ag1;
agent ag2;
functionnew(stringname,ovm_component parent);
endfunction
ovm_report_info(get_full_name(),"Build",OVM_LOG);
endfunction
ovm_report_info(get_full_name(),"Connect",OVM_LOG);
endfunction
ovm_report_info(get_full_name(),"End_of_elaboration",OVM_LOG);
endfunction
functionvoidstart_of_simulation();
ovm_report_info(get_full_name(),"Start_of_simulation",OVM_LOG);
endfunction
taskrun();
ovm_report_info(get_full_name(),"Run",OVM_LOG);
endtask
functionvoidextract();
ovm_report_info(get_full_name(),"Extract",OVM_LOG);
endfunction
functionvoidcheck();
ovm_report_info(get_full_name(),"Check",OVM_LOG);
endfunction
functionvoidreport();
ovm_report_info(get_full_name(),"Report",OVM_LOG);
endfunction
endclass
Now we will implement the testcase.

1)Extend ovm_test and define the test case
classtest1 extendsovm_test;
2)Declare component ustilits using utility macro.
òvm_component_utils(test1)
2)Declare environment class handle.
env t_env;
3)Define constructor method. In the constructor, call the super method and construct
the environment object.
functionnew(stringname="test1",ovm_component parent=null);
endfunction:new
4)Define the end_of_elaboration method. In this method, call the print() method. This
print() method will print the topology of the test.
print();
endfunction
4)Define the run method and call the global_stop_request() method.
taskrun ();
#1000;
endtask:run
Testcase source code:
env t_env;
endfunction:new
print();
endfunction
taskrun ();
#1000;
endtask:run
endclass
Top Module:
To start the testbench, run_test() method must be called from initial block.
Run_test() mthod Phases all components through all registered phases.
moduletop;
initial
run_test();
endmodule
ovm_phases.tar
Browse the code in ovm_phases.tar
your_tool_simulation_command +path_to_ovm_pkg -f filelist +OVM_TESTNAME=test1
Log file:
[RNTST] Running test test1...
ovm_test_top.t_env [ovm_test_top.t_env] Build
ovm_test_top.t_env.ag1 [ovm_test_top.t_env.ag1] Build
ovm_test_top.t_env.ag1.drv [ovm_test_top.t_env.ag1.drv] Build
ovm_test_top.t_env.ag1.mon [ovm_test_top.t_env.ag1.mon] Build
ovm_test_top.t_env.ag1.drv [ovm_test_top.t_env.ag1.drv] Connect
ovm_test_top.t_env.ag1.mon [ovm_test_top.t_env.ag1.mon] Connect
ovm_test_top.t_env.ag1 [ovm_test_top.t_env.ag1] Connect
ovm_test_top.t_env [ovm_test_top.t_env] Connect
ovm_test_top.t_env.ag1.drv [ovm_test_top.t_env.ag1.drv] End_of_elaboration
ovm_test_top.t_env.ag1.mon [ovm_test_top.t_env.ag1.mon] End_of_elaboration
ovm_test_top.t_env.ag1 [ovm_test_top.t_env.ag1] End_of_elaboration
ovm_test_top.t_env.ag2.drv [ovm_test_top.t_env.ag2.drv] End_of_elaboration
ovm_test_top.t_env.ag2.mon [ovm_test_top.t_env.ag2.mon] End_of_elaboration
ovm_test_top.t_env.ag2 [ovm_test_top.t_env.ag2] End_of_elaboration
ovm_test_top.t_env [ovm_test_top.t_env] End_of_elaboration
ovm_test_top [ovm_test_top] End_of_elaboration
---------------------------------------------------------------------ovm_test_top test1 -ovm_test_top@2
t_envenv - t_env@4
ag1agent - ag1@6
drvdriver-drv@12
rsp_port ovm_analysis_port - rsp_port@16
sqr_pull_portovm_seq_item_pull_+ -sqr_pull_port@14
monmonitor -mon@10
ag2agent - ag2@8
drvdriver-drv@20
monmonitor -mon@18
ovm_test_top.t_env.ag1.drv[ovm_test_top.t_env.ag1.drv]Start_of_simulation
ovm_test_top.t_env.ag1.mon[ovm_test_top.t_env.ag1.mon]Start_of_simulation
ovm_test_top.t_env.ag1[ovm_test_top.t_env.ag1]Start_of_simulation
ovm_test_top.t_env.ag2.drv[ovm_test_top.t_env.ag2.drv]Start_of_simulation
ovm_test_top.t_env.ag2.mon[ovm_test_top.t_env.ag2.mon]Start_of_simulatio
..
..
..
..
Observe the above log report:
1)Build method was called in top-down fashion. Look at the following part of message.
ovm_test_top.t_env [ovm_test_top.t_env] Build
2)Connect method was called in bottopm up fashion. Look at the below part of log
file,
ovm_test_top.t_env [ovm_test_top.t_env] Connect
3)Following part of log file shows the testcase topology.
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TUTORIALS
OVM REPORTING
SystemVerilog
The ovm_report_object provides an interface to the OVM reporting facility.Through

this interface, components issue the various messages with different severity levels
that occur during simulation. Users can configure what actions are taken and what
file(s) are output for individual messages from a particular component or for all
messages from all components in the environment.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
A report consists of an id string, severity, verbosity level, and the textual message
itself. If the verbosity level of a report is greater than the configured maximum
verbosity level of its report object, it is ignored.
Reporting Methods:
Following are the primary reporting methods in the OVM.
virtualfunctionvoidovm_report_info
(stringid,stringmessage,intverbosity=OVM_MEDIUM,stringfilename="",intline=0)
virtualfunctionvoidovm_report_warning
(stringid,stringmessage,intverbosity=OVM_MEDIUM,stringfilename="",intline=0)
virtualfunctionvoidovm_report_error
(stringid,stringmessage,intverbosity=OVM_LOW, stringfilename="",intline=0)
virtualfunctionvoidovm_report_fatal
(stringid,stringmessage,intverbosity=OVM_NONE,stringfilename="",intline=0)
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
id -- a unique id to form a group of messages.

message -- The message text
verbosity -- the verbosity of the message, indicating its relative importance. If this
number is less than or equal to the effective verbosity level, then the report is issued,
subject to the configured action and file descriptor settings.
filename/line -- If required to print filename and line number from where the
message is issued, use macros, `__FILE__ and `__LINE__.
Actions:
These methods associate the specified action or actions with reports of the
givenseverity, id, or severity-id pair.
Specman E
Interview Questions
Following are the actions defined:

OVM_NO_ACTION -- Do nothing
OVM_DISPLAY -- Display report to standard output
OVM_LOG-- Write to a file
OVM_COUNT -- Count up to a max_quit_count value before exiting
OVM_EXIT -- Terminates simulation immediately
OVM_CALL_HOOK -- Callback the hook method .
Configuration:
http://testbench.in/OT_03_OVM_REPORTING.html[9/26/2012 2:26:32 PM]
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
Using these methods, user can set the verbosity levels and set actions.
functionvoidset_report_verbosity_level
(intverbosity_level)
functionvoidset_report_severity_action
(ovm_severity severity,ovm_action action)
functionvoidset_report_id_action
(stringid,ovm_action action)
functionvoidset_report_severity_id_action
(ovm_severity severity,stringid,ovm_action action)
Example
Lets see an example:
In the following example, messages from rpting::run() method are of different
verbosity level. In the top module, 3 objects of rpting are created and different
verbosity levels are set using set_report_verbosity_level() method.
ìnclude"ovm.svh"
importovm_pkg::*;
classrpting extendsovm_threaded_component;
òvm_component_utils(rpting)
endfunction
taskrun();
ovm_report_info(get_full_name(),
"Info Message : Verbo lvl - OVM_NONE",OVM_NONE,`__FILE__,`__LINE__);
"Info Message : Verbo lvl - OVM_LOW ",OVM_LOW);
"Info Message : Verbo lvl - 150 ",150);
"Info Message : Verbo lvl - OVM_MEDIUM",OVM_MEDIUM);
ovm_report_warning(get_full_name(),
"Warning Messgae from rpting",OVM_LOW);
ovm_report_error(get_full_name(),
"Error Message from rpting \n\n",OVM_LOG);
endtask
endclass
moduletop;
rpting rpt1;
rpting rpt2;
rpting rpt3;
initialbegin
rpt1.set_report_verbosity_level(OVM_MEDIUM);
rpt2.set_report_verbosity_level(OVM_LOW);
rpt3.set_report_verbosity_level(OVM_NONE);
run_test();
end
endmodule
ovm_reporting.tar
Browse the code in ovm_reporting.tar
your_tool_simulation_command +path_to_ovm_pkg ovm_log_example.sv
Log file:
OVM_INFO reporting.sv(13)@0:rpt1[rpt1]Info Message:Verbo lvl - OVM_NONE
OVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - OVM_LOW
OVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - 150
OVM_INFO @0:rpt1[rpt1] Info Message : Verbo lvl - OVM_MEDIUM
OVM_WARNIN@0:rpt[rpt1] Warning Messgae from rpting
OVM_ERROR @0:rpt1[rpt1] Error Message from rpting
OVM_INFOreporting.sv(13)@0:rpt2[rpt2]Info Message:Verbo lvl - OVM_NONE
OVM_INFO@ 0:rpt2[rpt2] Info Message : Verbo lvl - OVM_LOW
OVM_WARNING@0:rpt2[rpt2] Warning Messgae from rpting
OVM_ERROR@0:rpt2[rpt2] Error Message from rpting
OVM_INFOreporting.sv(13)@0:rpt3[rpt3]Info Message:Verbo lvl - OVM_NONE
OVM_ERROR @ 9200 [TIMOUT] Watchdog timeout of '23f0' expired.
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TUTORIALS
OVM TRANSACTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
A transaction is data item which is eventually or directly processed by the DUT. The
packets, instructions, pixels are data items. In ovm, transactions are extended from
ovm_transactions class orovm_sequence_item class. Generally transactions are
extended from ovm_transactionif randomization is not done in sequence and
transactions are extended from ovm_sequence_item if the randomization is done in
sequence. In this section, we will see ovm_transaction only, ovm_sequence_item will
be addressed in another section.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Example of a transaction:
classPacket extendsovm_transaction;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]length;
randbit[7:0]data[];
randbytefcs;
endclass
Core Utilities:
ovm_transaction class is extended from ovm_object.Ovm_transaction adds more
features line transaction recording , transaction idand timings of the transaction.
The methods used to model, transform or operate on transactions like print, copying,
cloning, comparing, recording, packing and unpacking are already defined in
ovm_object.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
FIG:OVM OBJECT UTILITIES
http://testbench.in/OT_04_OVM_TRANSACTION.html[9/26/2012 2:26:41 PM]
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
User Defined Implementations:

User should define these methods in the transaction using do_<method_name> and
call them using <method_name>.Following table shows calling methods and userdefined hook do_<method_name> methods.Clone and create methods, does not
usehook methods concepts.
Shorthand Macros:
Using the field automation concept of ovm, all the above defines methods can be
defined automatically.
To use these field automation macros, first declare all the data fields, then place the
field
automation
macros
between
the
òvm_object_utils_begin
and
òvm_object_utils_end macros.
Example of field automation macros:
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]length;
randbit[7:0]data[];
randbytefcs;
òvm_object_utils_begin(Packet)
òvm_field_int(da,OVM_ALL_ON|OVM_NOPACK)
òvm_field_int(sa,OVM_ALL_ON|OVM_NOPACK)
òvm_field_int(length,OVM_ALL_ON|OVM_NOPACK)
òvm_field_array_int(data,OVM_ALL_ON|OVM_NOPACK)
òvm_field_int(fcs,OVM_ALL_ON|OVM_NOPACK)
òvm_object_utils_end
endclass.
For most of the data types in systemverilog, ovm defined corresponding field
automation macros. Following table shows all the field automation macros.
Each òvm_field_* macro has at least two arguments: ARG and FLAG.
ARG is the instance name of the variable and FLAG is used to control the field usage in
core utilities operation.
Following table shows ovm field automation flags:
By default, FLAG is set to OVM_ALL_ON. All these flags can be ored. Using NO_* flags,
can turn of particular field usage in a paerticuler method. NO_* flags takes
precedency over other flags.
Example of Flags:
The above macro will use the field "da" in all utilities methods except Packing and
unpacking methods.
Lets see a example:
In the following example, all the utility methods are defined using field automation
macros except Packing and unpacking methods.Packing and unpacking methods are
donein do_pack() amd do_unpack() method.
ìnclude"ovm.svh"
importovm_pkg::*;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
constraintsolve_size_length {solvedata.sizebeforelength;}
super.new(name);
endfunction:new
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();

integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
functionvoiddo_pack(ovm_packer packer);
foreach(data[i])
endfunction:do_pack
functionvoiddo_unpack(ovm_packer packer);
intsz;
data.delete();
data=new[length];
foreach(data[i])
endclass:Packet
/////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
moduletest;
initial
repeat(10)
if(pkt1.randomize)
begin
pkt1.print();
ovm_default_packer.use_metadata =1;
pkt2.print();
else
\n \n");
end
else
endmodule
ovm_transaction.tar
Browse the code in ovm_transaction.tar
your_tool_simulation_command +path_to_ovm_pkg -packet.sv
Log report:
--------------------------------------------------------------------pkt1 Packet-pkt1@3
da integral8'h1d
sa integral8'h26
[1]integral8'h3f
[2]integral8'h9e
[3]integral8'h38
[4]integral8'h8d
fcsintegral8'h9b
--------------------------------------------------------------------Size of pkd bits 9
--------------------------------------------------------------------pkt2 Packet-pkt2@5
da integral8'h1d
sa integral8'h26
[1]integral8'h3f
[2]integral8'h9e
[3]integral8'h38
[4]integral8'h8d
fcsintegral8'h9b
--------------------------------------------------------------------Packing,Unpacking and compare worked
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TUTORIALS
OVM FACTORY
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
The factory pattern is an well known object-oriented design pattern. The factory
method design pattern defining a separate method for creating the objects. ,whose
subclasses can then override to specify the derived type of object that will be
created.
Using this method, objects are constructed dynamically based on the specification
type of the object. User can alter the behavior of the pre-build code without
modifying the code. From the testcase, user from environment or testcase can replace
any object which is at any hierarchy level with the user defined object.
For example: In your environment, you have a driver component. You would like the
extend the driver component for error injection scenario. After defining the extended
driver classwith error injection,how will youreplace the base driver component
which is deep in the hierarchy of your environment ? Using hierarchical path, you
could replace the driver object with the extended driver. This could not be easy if
there are many driver objects. Then you should also take care of its connections with
the other components of testbenchs like scoreboard etc.
Easy Labs : UVM
One more example: In your Ethernet verification environment, you have different
drivers to support different interfaces for 10mbps,100mps and 1G. Now you want to
reuse the same environment for 10G verification.Inside somewhere deep in the
Easy Labs : VMM
hierarchy, while building the components, as a driver components ,your current
environment can only select 10mmps/100mps/1G drivers using configuration
AVM Switch TB
settings.How to add one more driver to the current drivers list of drivers so that
VMM Ethernet sample from the testcase you could configure the environment to work for 10G.
Easy Labs : OVM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Using the ovm fatroy, it is very easy to solve the above two requirements.Only classs
extended from ovm_object and ovm_component are supported for this.
There are three basic steps to be followed for using ovm factory.
1) Registration
2) Construction
3) Overriding
The factory makes it is possible to override the type of ovm component /objector
instance of a ovm component/objectin2 ways. They are based on ovm
component/object type orovm compoenent/objectname.
Registration:
While defining a class , its type has to be registered with the ovm factory. To do this
job easier, ovm has predefined macros.
Specman E
Interview Questions
òvm_component_utils(class_type_name)
òvm_component_param_utils(class_type_name #(params))
òvm_object_utils(class_type_name)
òvm_object_param_utils(class_type_name #(params))
For ovm_*_param_utils are used for parameterized classes and other two macros for
non-parameterized class.Registration is required for name-based overriding , it is
not required for type-based overriding.
EXAMPLE: Example of above macros
http://testbench.in/OT_05_OVM_FACTORY.html[9/26/2012 2:26:49 PM]
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
classpacket extendsovm_object;
òvm_object_utils(packet)
endclass
classpacket #(typeT=int,intmode=0)extendsovm_object;
òvm_object_param_utils(packet #(T,mode))
endclass
classdriver extendsovm_component;
òvm_component_utils(driver)
endclass
classmonitor #(typeT=int,intmode=0)extendsovm_component;
òvm_component_param_utils(driver#(T,mode))
endclass
Construction:
To construct a ovm based component or ovm based objects, static method create()
should be used. This function constructs the appropriate object based on the
overrides and constructs the object and returns it. So while constructing the ovm
based components or ovm based objects , do not use new() constructor.
Syntax :
staticfunctionT create(stringname,
ovm_component parent,
stringcontext=" ")
The Create() function returns an instance of the component type, T, represented by
this proxy, subject to any factory overrides based on the context provided by the
parents full name.The context argument, if supplied, supersedes the parents
context.The new instance will have the given leaf name and parent.
EXAMPLE:
class_type object_name;
object_name =class_type::type_id::creat("object_name",this);
For ovm_object based classes, doesnt need the parent handle as second argument.
Overriding:
If required, user could override the registered classes or objects. User can override
based of name string or class-type.
There are 4 methods defined for overriding:
functionvoidset_inst_override_by_type
(ovm_object_wrapper original_type,
ovm_object_wrapper override_type,
The above method is used to override the object instances of "original_type" with
"override_type" . "override_type" is extended from"original_type".
functionvoidset_inst_override_by_name
Original_type_name and override_type_name are the class names which are registered
in the factory. All the instances of objects with name "Original_type_name" will be
overriden
with
objects
of
name
"override_type_name"
using
set_inst_override_by_name() method.
functionvoidset_type_override_by_type
(ovm_object_wrapper original_type,
ovm_object_wrapper override_type,
bitreplace =1)
Using the above method, request to create an object oforiginal_type can be
overriden with override_type.
functionvoidset_type_override_by_name
bitreplace =1)
Using the above method, request to create an object oforiginal_type_name can be
overriden with override_type_name.
When multiple overrides are done , then using the argument "replace" , we can
control whether to override the previous override or not. If argument "replace" is 1,
then previous overrides will be replaced otherwise, previous overrides will remain.
print() method, prints the state of the ovm_factory, registered types, instance
overrides, and type overrides.
Now we will see a complete example. This example is based on the environment build
in topic OVM TESTBENCH . Refer to that section for more information about this
example.
Lets look at the 3 steps which I discussed above using the example defined in OVM
TESTBENCH
1) Registration
In all the class, you can see the macroòvm_component_utils(type_name)
2) Construction
In file agant.sv file,monitor and driver are constructed using create() method.
mon =monitor::type_id::create("mon",this);
drv =driver::type_id::create("drv",this);
3)In this example, a one testcase is already developed in topic OVM_TESTBENCH.
There are no over rides in this test case.
Topology of this test environment is shown below.
In this example, there is one driver class and one monitor class.In this testcase , By
extending driver class , we will define driver_2 class and by extending monitor class,
we will define monitor_2 class.
From the testcase , Using set_type_override_by_type, we will override driver with
driver_2 and Using set_type_override_by_name, we will override monitor with
monitor_2.
To know about the overrides which are done, call print_all_overrides() method of
factory class.
classdriver_2 extendsdriver;
òvm_component_utils(driver_2)
endfunction
endclass
classmonitor_2 extendsmonitor;
òvm_component_utils(monitor_2)
endfunction
endclass
classtest_factory extendsovm_test;
òvm_component_utils(test_factory)
env t_env;
factory.set_type_override_by_type(driver::get_type(),driver_2::get_type(),"*");
factory.set_type_override_by_name("monitor","monitor_2","*");
factory.print_all_overrides();
endfunction:new
print();
taskrun ();
#1000;
endtask:run
endclass
ovm_factory.tar
Browse the code in ovm_factory.tar
Command to simulate
Command to run the example with the testcase which is defined above:
Your_tool_simulation_command
+incdir+path_to_ovm
-f
+OVM_TESTNAME=test_factory
filelist
Method factory.print_all_overrides() displayed all the overrides as shown below in the

log file.
#### Factory Configuration (*)

No instance overrides are registered with this factory
Type Overrides:
Requested TypeOverride Type
--------------------------driverdriver_2
monitor monitor_2
In the below text printed by print_topology() method ,we can see overridden driver
and monitor.
--------------------------------------------------------------------ovm_test_top test_factory-ovm_test_top@2
t_envenv - t_env@4
ag1agent - ag1@6
drvdriver_2-drv@12
ag2agent - ag2@8
drvdriver_2-drv@20
---------------------------------------------------------------------
In the below text printed by print_topology() method ,with testcase test1 which does
note have overrides.
Command to run this example with test1 is
your_tool_simulation_command +incdir+path_to_ovm -f filelist +OVM_TESTNAME=test1
--------------------------------------------------------------------ovm_test_top test1 -ovm_test_top@2

t_envenv - t_env@4
ag1agent - ag1@6
drvdriver-drv@12
monmonitor -mon@10
ag2agent - ag2@8
drvdriver-drv@20
monmonitor -mon@18
---------------------------------------------------------------------
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TUTORIALS
OVM SEQUENCE 1
SystemVerilog
Introduction
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
A sequence is a series of transaction.User can define the complex stimulus.

sequences can be reused, extended, randomized, and combined sequentially and
hierarchically in various ways.
For example, for a processor, lets say PUSH_A,PUSH_B,ADD,SUB,MUL,DIV and POP_C

are the instructions. If the instructions are generated randomly, then to excursing a
meaningful operation like "adding 2 variables" which requires a series of transaction
"PUSH_APUSH_BADDPOP_C " will take longer time. By defining these series of
"PUSH_APUSH_BADDPOP_C ", it would be easy to exercise the DUT.
Advantages of ovm sequences :
Sequences can be reused.
Stimulus generation is independent of testbench.
Easy to control the generation of transaction.
Sequences can be combined sequentially and hierarchically.
A complete sequence generation requires following 4 classes.
1- Sequence item.
2- Sequence
3- Sequencer
4- Driver
Ovm_sequence_item :
User
has
to
define
a
transaction
by
extending
ovm_sequence_item.ovm_sequence_item class provides the basic functionality for
objects, both sequence items and sequences, to operate in the sequence mechanism.
For more information aboutovm_sequence_itemRefer to link
OVM_TRANSACTION
Ovm_sequence:
User should extend ovm_sequence class and define the construction of sequence of
transactions. These transactions can be directed, constrained randomized or fully
randomized. The ovm_sequence class provides the interfaces necessary in order to
create streams of sequence items and/or other sequences.
virtualclassovm_sequence #(
typeREQ=ovm_sequence_item,
typeRSP=REQ
)
Interview Questions
Ovm_sequencer:
Ovm_sequencer is responsible for the coordination between sequence and driver.
Sequencer sends the transaction to driver and gets the response from the driver. The
response transaction from the driver is optional. When multiple sequences are running
in parallel, then sequencer is responsible for arbitrating between the parallel
sequences. There are two types of sequencers : ovm_sequencer and
ovm_push_sequencer
http://testbench.in/OT_06_OVM_SEQUENCE_1.html[9/26/2012 2:26:58 PM]
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
classovm_sequencer #(
typeRSP=REQ
)
classovm_push_sequencer #(
typeRSP=REQ
)
Ovm driver:
User should extend ovm_driver class to define driver component. ovm driver is a
component that initiate requests for new transactions and drives it to lower level
components. There are two types of drivers: ovm_driver and ovm_push_driver.
classovm_driver #(
typeRSP=REQ
)
classovm_push_driver #(
typeRSP=REQ
)
In pull mode , ovm_sequencer is connected to ovm_driver
modeovm_push_sequencer is connectd to ovm_push_driver.
in push
Ovm_sequencer and ovm_driver are parameterized components with request and

response transaction types. REQ and RSP types by default are ovm_sequence_type
types. User can specify REQ and RSP of different transaction types. If user specifies
only REQ type, then RSP will be REQ type.
Sequence And Driver Communication:
The above image shows how a transaction from a sequence is sent to driver and the
response from the driver is sent to sequencer.There are multiple methods called
during this operation.
First when the body() method is called
1) A transaction is created using "create()" method. If a transaction is created using

"create()" method, then it can be overridden if required using ovm factory.
2) After a transaction is created, wait_for_grant() method is called. This method is
blocking method.
3) In the run task of the driver, when "seq_item_port.get_next_item()" is called, then
the sequencer un blocks wait_for_grant() method. If more than one sequence is
getting executed by sequencer, then based on arbitration rules, un blocks the
wait_for_grant() method.
4) After the wait_for_grant() un blocks, then transaction can be randomized, or its
properties can be filled directly. Then using the send_request() method, send the
transaction to the driver.
5) After calling the send_request() method, "wait_for_item_done()" method is called.
This is a blocking method and execution gets blocks at this method call.
6) The transaction which is sent from sequence , in the driver this transaction is
available as "seq_item_port.get_next_item(req)" method argument. Then driver can
drive this transaction to bus or lower level.
7) Once the driver operations are completed, thenby calling
"seq_item_port.put(rsp)", wait_for_item_done() method of sequence gest unblocked.
Using get_responce(res), the response transaction from driver is taken by sequence
and processes it.
After this step, again the steps 1 to 7 are repeated five times.
If a response from driver is not required, then steps 5,6,7 can be skipped and
item_done() method from driver should be called as shown in above image.
Simple Example
Lest write an example: This is a simple example ofprocessor instruction. Various
instructions
which
are
supported
by
the
processor
are
PUSH_A,PUSH_B,ADD,SUB,MUL,DIV and POP_C.
Sequence Item
1) Extend ovm_sequence_item and define instruction class.
classinstruction extendsovm_sequence_item;
2) Define the instruction as enumerated types and declare a variable of instruction
enumerated type.
randinst_t inst;
3) Define operational method using ovm_field_* macros.
òvm_object_utils_begin(instruction)
òvm_field_enum(inst_t,inst,OVM_ALL_ON)
super.new(name);
endfunction
Sequence item code:
classinstruction extendsovm_sequence_item;
randinst_t inst;
òvm_object_utils_begin(instruction)
òvm_field_enum(inst_t,inst,OVM_ALL_ON)
super.new(name);
endfunction
endclass
Sequence
We will define a operation addition using ovm_sequence. The instruction sequence
should be "PUSH APUSH BADDPOP C".
1) Define a sequence by extending ovm_sequence. Set REQ parameter to "instruction"

type.
classoperation_addition extendsovm_sequence #(instruction);
super.new(name);
endfunction
3) Lets name the sequencer which we will develop is "instruction_sequencer".
Using the òvm_sequence_utils macro, register the "operation_addition" sequence
with "instruction_sequencer" sequencer. This macro adds the sequence to the
sequencer list. This macro will also register the sequence for factory overrides.
òvm_sequence_utils(operation_addition,instruction_sequencer)
4)
In the body() method, first call wait_for_grant(), then construct a transaction and set
the instruction enum to PUSH_A . Then send the transaction to driver using
send_request() method. Then call the wait_for_item_done() method. Repeat the
above steps for other instructions PUSH_B, ADD and POP_C.
For construction of a transaction, we will use the create() method.

virtualtaskbody();
wait_for_grant();
});
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
endtask
Sequence code
classoperation_addition extendsovm_sequence #(instruction);
instruction req;
super.new(name);
endfunction
òvm_sequence_utils(operation_addition,instruction_sequencer)
virtualtaskbody();
wait_for_grant();
});
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
wait_for_grant();
send_request(req);
endtask
endclass
Sequencer:
Ovm_sequence hasa property called default_sequence. Default sequence is a
sequence which will be started automatically. Using set_config_string, user can
override the default sequence to any user defined sequence, so that when a
sequencer is started, automatically a user defined sequence will be started.If over
rides are not done with user defined sequence, then a random transaction are
generated.Using "start_default_sequence()" method, "default_sequence" can also be
started.
Ovm sequencer has seq_item_export and res_export tlm ports for connecting to ovm
driver.
1) Define instruction_sequencer by extending ovm_sequencer.
classinstruction_sequencer extendsovm_sequencer #(instruction);
Inside the constructor, place the macro òvm_update_sequence_lib_and_item().
This macro creates 3 predefined sequences. We will discuss about the predefined
sequences in next section.
òvm_update_sequence_lib_and_item(instruction)
endfunction
3) Place the ovm_sequencer_utils macro. This macro registers the sequencer for
factory overrides.
òvm_sequencer_utils(instruction_sequencer)
Sequencer Code;
classinstruction_sequencer extendsovm_sequencer #(instruction);
òvm_update_sequence_lib_and_item(instruction)
endfunction
òvm_sequencer_utils(instruction_sequencer)
endclass
Driver:
ovm_driver is a class which is extended from ovm_componenet. This driver is used in
pull mode. Pull mode means, driver pulls the transaction from the sequencer when it
requires.
Ovm driver has 2 TLM ports.
1) Seq_item_port: To get a item from sequencer, driver uses this port. Driver can also
send response back using this port.
2) Rsp_port :This can also be used to send response back to sequencer.
Seq_item_port methods:
Lets implement a driver:

1) Define a driver which takes the instruction from the sequencer and does the
processing. In this example we will just print the instruction type and wait for some
delay.
classinstruction_driver extendsovm_driver #(instruction);
2) Place the ovm_component_utils
get_type_name and create.
macro
to
define
virtual
methods like
òvm_component_utils(instruction_driver)
3) DefineConstructor method.
endfunction
4) Define the run() method. Run() method is executed in the "run phase". In this
methods, transactions are taken from the sequencer and drive them on to dut
interface or to other components.
Driver
class
has
a
port
"seq_item_port".
Using
the
method
seq_item_port.get_next_item(), get the transaction from the sequencer and process
it.Once the processing is done, using the item_done() method, indicate to the
sequencer that the request is completed. In this example, after taking the
transaction, we will print the transaction and wait for 10 units time.
taskrun ();
while(1)begin
#10;
end
endtask
endclass
Driver class code:
classinstruction_driver extendsovm_driver #(instruction);
// Provide implementations of virtual methods such as get_type_name and create
òvm_component_utils(instruction_driver)
// Constructor
endfunction
taskrun ();
foreverbegin
#10;
// seq_item_port.put(esp); responce needs to be sent back to sequence
end
endtask
endclass
Driver And Sequencer Connectivity:
Deriver and sequencer are connected using TLM. Ovm_driver has seq_item_port which
is used to get the transaction from ovm sequencer. This port is connected to
ovm_sequencer
seq_item_exportUsing
"<driver>.seq_item_port.connect(<sequencer>.seq_item_export);"
driver
and
sequencer can be connected. Simillarly"res_port" of driver which is used to send
response from driver to sequencer is connected to "res_export" of the sequencer using
""<driver>.res_port.connect(<sequencer>.res_export);".
Testcase:
This testcase is used only for the demo purpose of this tutorial session. Actually, the
sequencer and the driver and instantiated and their ports are connected in a agent
component and used.Lets implement a testcase
1) Take instances of sequencer and driver and construct both components.
sequencer.build();
driver.build();
2)
Connect the seq_item_export to the drivers seq_item_port.
3) Using set_confg_string() method, set the default sequence of the sequencer to
"operation_addition". Operation_addition is the sequence which we defined previous.
4) Using the start_default_sequence() method of the sequencer, start the default
sequence of the sequencer. In the previous step we configured the addition operation
as default sequene. When you run the simulation, you will see the PUSH_A,PUSH_B
ADD and POP_C series of transaction.
Testcase Code:
moduletest;
initialbegin
sequencer.build();
driver.build();
sequencer.print();
fork
begin
run_test();
end
join
end
endmodule
ovm_basic_sequence.tar
Browse the code in ovm_basic_sequence.tar
Command to simulate
Your_tool_simulation_command +incdir+path_to_ovm testcase.sv
Log file Output
OVM_INFO @ 0 [RNTST] Running test ...
From the above log , we can see that transactions are generates as we defined in ovm
sequence.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Ovm Testbench
Ovm Reporting
Pre Defined Sequences:
Ovm Transaction
Ovm Factory
Every sequencer in ovm has 3 pre defined sequences. They are
Ovm Sequence 1
Ovm Sequence 2
1)Ovm_random_sequence
Ovm Sequence 3
2)Ovm_exhaustive_sequence.
Ovm Sequence 4
3)Ovm_simple_sequence
Ovm Sequence 5
All the user defined sequences which are registered by user and the above three Ovm Sequence 6
predefined sequences are stored in sequencer queue.
Ovm Configuration
OVM SEQUENCE 2
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Ovm_random_sequence :
This sequence randomly selects and executes a sequence from the sequencer
sequence
library,
excluding
ovm_random_sequence
itself,
and
ovm_exhaustive_sequence. From the above image, from sequence id 2 to till the last
sequence, all the sequences are executed randomly.If the "count" variable of the
sequencer is set to 0, then non of the sequence is executed. If the "count" variable of
the sequencer is set to -1, then some random number of sequences from 0 to
"max_random_count" are executed. By default "mac_random_count" is set to
10."Count" and "mac_random_count" can be changed using set_config_int().
The sequencer when automatically started executes the sequence which is point by
default_sequence.
By
defaultdefault_sequence
variable
points to
ovm_random_sequence.
ovm_exaustive_sequence:
This sequence randomly selects and executes each sequence from the sequencers
sequence library once in a randc style, excluding itself and ovm_random_sequence.
ovm_simple_sequence:
This sequence simply executes a single sequence item.
In the previous example from OVM_SEQUENCE_1 section.
The print() method of the sequencer in that example printed the following
--------------------------------------------------------------------sequencerinstruction_sequen+ - sequencer@2
rsp_export ovm_analysis_export -rsp_export@4
seq_item_exportovm_seq_item_pull_+ -seq_item_export@28
default_sequence string18 operation_addition
countintegral32 -1
sequencesarray 4 [0]string19ovm_random_sequence
[1]string23 ovm_exhaustive_sequ+
[2]string19ovm_simple_sequence
[3]string18 operation_addition
---------------------------------------------------------------------
Some observations from the above log:

The countis set to -1.The default sequencer is set to operations_addition. There
are 3 predefined sequences and 1 user defined sequence.
Lets look at a example: In the attached example, in file sequence.sv file, there are 4
seuqneces,
they
are
operation_addition,
operation_subtraction,
operation_multiplication.
In the testcase.sv file, the "default_seuence" is set to "ovm_exhaustive_sequence"
using the set_config_string.
set_config_string("sequencer", "default_sequence", "ovm_exhaustive_sequence");
ovm_sequence_1.tar
Browse the code in ovm_sequence_1.tar
Command to run the summation
Log File
10: Driving
20: Driving
30: Driving
40: Driving
InstructionPUSH_A
InstructionPUSH_B
InstructionSUB
InstructionPOP_C
50: Driving
60: Driving
70: Driving
80: Driving
InstructionPUSH_A
InstructionPUSH_B
InstructionMUL
InstructionPOP_C

From the above log , we can see that all the 3 user defined sequences and predefined
ovm_simple_sequence are executed.
Sequence Action Macro:

In the previous sections, we have seen the implementation of body() method of
sequence. The body() method implementation requires some steps.We have seen
these steps asCreation of item, wait for grant, randomize the item, send the item.
All these steps have be automated using "sequence action macros". There are some
more additional steps added in these macros. Following are the steps defined with the
"sequence action macro".
Pre_do(), mid_do() and post_do() are callback methods which are in ovm sequence.If
user is interested , he can use these methods. For example, inmid_do() method, user
can print the transaction orthe randomized transaction can be fined tuned.These
methods should not be clled by user directly.
Syntax:
virtualtaskpre_do(bitis_item)
virtualfunctionvoidmid_do(ovm_sequence_item this_item)
virtualfunctionvoidpost_do(ovm_sequence_item this_item)
Pre_do() is a task , ifthe method consumes simulation cycles, the behavior may be
unexpected.
Example Of Pre_do,Mid_do And Post_do
Lets look at a example: We will define a sequence using òvm_do macro. This macro
has all the above defined phases.
1)Define the body method using the òvm_do() macro. Before and after this macro,
just call messages.
virtualtaskbody();
"Seuqnce Action Macro Phase: Before ovm_do macro ",OVM_LOW);
òvm_do(req);
"Seuqnce Action Macro Phase: After ovm_do macro ",OVM_LOW);
endtask
2)Define pre_do() method. Lets just print a message from this method.
"Seuqnce Action Macro Phase: PRE_DO ",OVM_LOW);
endtask
3)Define mid_do() method. Lets just print a message from this method.
virtualfunctionvoidmid_do(ovm_sequence_item this_item);
"Seuqnce Action Macro Phase: MID_DO ",OVM_LOW);
endfunction
4)Define post_do() method. Lets just print a message from this method.
virtualfunctionvoidpost_do(ovm_sequence_item this_item);
"Seuqnce Action Macro Phase: POST_DO ",OVM_LOW);
endfunction
Complet sequence code:
classdemo_ovm_do extendsovm_sequence #(instruction);
instruction req;
functionnew(stringname="demo_ovm_do");
super.new(name);
endfunction
òvm_sequence_utils(demo_ovm_do,instruction_sequencer)
"Seuqnce Action Macro Phase: PRE_DO ",OVM_LOW);
endtask
virtualfunctionvoidmid_do(ovm_sequence_item this_item);
"Seuqnce Action Macro Phase: MID_DO ",OVM_LOW);
endfunction
virtualfunctionvoidpost_do(ovm_sequence_item this_item);
"Seuqnce Action Macro Phase: POST_DO ",OVM_LOW);
endfunction
virtualtaskbody();
"Seuqnce Action Macro Phase: Before ovm_do macro ",OVM_LOW);
òvm_do(req);
"Seuqnce Action Macro Phase: After ovm_do macro ",OVM_LOW);
endtask
endclass
ovm_sequence_2.tar
Log file report:
OVM_INFO@0:reporter[sequencer.demo_ovm_do]
Seuqnce Action Macro Phase: Before ovm_do macro
Seuqnce Action Macro Phase: PRE_DO
Seuqnce Action Macro Phase: MID_DO
Seuqnce Action Macro Phase: POST_DO

Seuqnce Action Macro Phase: After ovm_do macro
The above log file shows themessages from pre_do,mid_do and post_do methods.
List Of Sequence Action Macros:
These macros are used to start sequences and sequence items that were either
registered with a <òvm-sequence_utils> macro or whose associated sequencer was
already set using the <set_sequencer> method.
òvm_create(item/sequence)
This action creates the item or sequence using the factory. Only the create phase will
be executed.
òvm_do(item/sequence)
This macro takes as an argument a ovm_sequence_item variable or sequence . All the
above defined 7 phases will be executed.
òvm_do_with(item/sequence, Constraint block)
This is the same as òvm_do except that the constraint block in the 2nd argument is
òvm_send(item/sequence)
Create phase and randomize phases are skipped, rest all the phases will be executed.
Using òvm_create, create phase can be executed.Essentially, an òvm_do without
the create or randomization.
òvm_rand_send(item/sequence)
òvm_create to create the sequence or item.
òvm_rand_send_with(item/sequence , Constraint block)
òvm_create to create the sequence or item.Constraint block will be applied which
randomization.
òvm_do_pri(item/sequence, priority )
This is the same as òvm_do except that the sequence item or sequence is executed
òvm_do_pri_with(item/sequence , constraint block , priority)
This is the same as òvm_do_pri except that the given constraint block is applied to
the item or sequence in a randomize with statementbefore execution.
òvm_send_pri(item/sequence,priority)
This is the same as òvm_send except that the sequence item or sequence is executed
òvm_rand_send_pri(item/sequence,priority)
This is the same as òvm_rand_send except that the sequence item or sequence is
executed with the priority specified in the argument.
òvm_rand_send_pri_with(item/sequence,priority,constraint block)
This is the same as òvm_rand_send_pri except that the given constraint block is
Followingmacros are used on sequence or sequence items on a different sequencer.
òvm_create_on(item/sequence,sequencer)
This is the same as òvm_create except that it also sets the parent sequence to the
sequencer argument.
òvm_do_on(item/sequence,sequencer)
This is the same as òvm_do except that it also sets the parent sequence to the
sequencerargument.
òvm_do_on_pri(item/sequence,sequencer, priority)
This is the same as òvm_do_pri except that it also sets the parent sequence to the
sequencerargument.
òvm_do_on_with(item/sequence,sequencer, constraint block)
This is the same as òvm_do_with except that it also sets the parent sequence to the
sequence in which the macro is invoked, and it sets thesequencer to the specified
sequencerargument.The user must supply brackets around the constraints.
òvm_do_on_pri_with(item/sequence,sequencer,priority,constraint block)
This is the same as òvm_do_pri_with except that it also sets the parent sequence to
the sequence in which the macro is invoked, and it sets the sequencer to the specified
sequencer argument.
Examples With Sequence Action Macros:
virtualtaskbody();
"Executing Sequence Action Macro ovm_do",OVM_LOW);
òvm_do(req)
endtask
virtualtaskbody();
"Executing Sequence Action Macro ovm_do_with ",OVM_LOW);
òvm_do_with(req,{inst ==ADD;})
endtask
virtualtaskbody();
"Executing Sequence Action Macro ovm_create and ovm_send",OVM_LOW);
òvm_create(req)
òvm_send(req)
endtask
virtualtaskbody();
"Executing
Sequence
Action
Macro
ovm_create
and
ovm_rand_send",OVM_LOW);
òvm_create(req)
òvm_rand_send(req)
endtask

ovm_sequence_3.tar
Log file report

OVM_INFO@10:reporter[***]Executing Sequence Action Macro ovm_do_with
OVM_INFO@20:reporter[***]Executing Sequence Action Macro ovm_create
ovm_send
OVM_INFO@30:reporter[***]Executing Sequence Action Macro ovm_do
30: Driving InstructionDIV
OVM_INFO@40:reporter[***]Executing Sequence Action Macro ovm_create
ovm_rand_send
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Index
Introduction
Ovm Testbench
Body Callbacks:
Ovm Reporting
Ovm sequences has two callback methods pre_body() and post_body(), which are Ovm Transaction
executed before and after the sequence body() method execution. These callbacks Ovm Factory
are called only when start_sequence() of sequencer or start() method of the sequence Ovm Sequence 1
Ovm Sequence 2
is called. User should not call these methods.
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
virtualtaskpre_body()
Ovm Sequence 6
virtualtaskpost_body()
Ovm Configuration
Example
OVM SEQUENCE 3
In this example, I just printed messages from pre_body() and post_body() methods. on This section - Your
These methods can be used for initialization, synchronization with some events or input is what keeps
cleanup.
with time!
classdemo_pre_body_post_body extendsovm_sequence #(instruction);
instruction req;
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functionnew(stringname="demo_pre_body_post_body");
super.new(name);
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endfunction
VMM Ethernet sample
òvm_sequence_utils(demo_pre_body_post_body,instruction_sequencer)
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Verilog
Verification
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Basic Constructs
virtualtaskpre_body();
ovm_report_info(get_full_name()," pre_body() callback ",OVM_LOW);
endtask
virtualtaskpost_body();
ovm_report_info(get_full_name()," post_body() callback ",OVM_LOW);
endtask
OpenVera
virtualtaskbody();
"body() method: Before ovm_do macro ",OVM_LOW);
Switch TB
òvm_do(req);
RVM Switch TB
RVM Ethernet sample "body() method: After ovm_do macro ",OVM_LOW);
endtask
endclass
Constructs
Specman E
Interview Questions

ovm_sequence_4.tar
Log file report

OVM_INFO @ 0: reporter [***]pre_body() callback
OVM_INFO @ 0: reporter [***] body() method: Before ovm_do macro
OVM_INFO @ 10: reporter [***] body() method: After ovm_do macro
OVM_INFO @ 10: reporter [***]post_body() callback
Hierarchical Sequences
One main advantage of sequences is smaller sequences can be used to create
sequences to generate stimulus required for todays complex protocol.
To create a sequence using another sequence, following steps has to be done
1)Extend the ovm_sequence class and define a new class.
2)Declare instances of child sequences which will be used to create new sequence.
3)Start the child sequence using <instance>.start() method in body() method.
Sequential Sequences
To executes child sequences sequentially, child sequence start() method should be
called sequentially in body method.
In the below example you can see all the 3 steps mentioned above.
In this example, I have defined 2 child sequences. These child sequences can be used
as normal sequences.
Sequence 1 code:
This sequence generates 4 PUSH_A instructions.
virtualtaskbody();
repeat(4)begin
òvm_do_with(req,{inst ==PUSH_A;});
end
endtask
Sequence 2 code:
This sequence generates 4 PUSH_B instructions.
virtualtaskbody();
repeat(4)begin
òvm_do_with(req,{inst ==PUSH_B;});
end
endtask
Sequential Sequence code:
This sequence first calls sequence 1 and then calls sequence 2.
classsequential_sequence extendsovm_sequence #(instruction);
seq_a s_a;
seq_b s_b;
functionnew(stringname="sequential_sequence");
super.new(name);
endfunction
òvm_sequence_utils(sequential_sequence,instruction_sequencer)
virtualtaskbody();
òvm_do(s_a);
òvm_do(s_b);
endtask
endclass
From the testcase,"sequential_sequence"is selected as "default_sequence".
ovm_sequence_5.tar
Log file report
If you observe the above log, you can see sequence seq_a is executed first and then
sequene seq_b is executed.
Parallelsequences
To executes child sequences Parallel, child sequence start() method should be called
parallel using fork/joinin body method.
Parallel Sequence code:
classparallel_sequence extendsovm_sequence #(instruction);
seq_a s_a;
seq_b s_b;
super.new(name);
endfunction
òvm_sequence_utils(parallel_sequence,instruction_sequencer)
virtualtaskbody();
fork
òvm_do(s_a)
òvm_do(s_b)
join
endtask
endclass
ovm_sequence_6.tar
Log file report
10: Driving
20: Driving
30: Driving
40: Driving
50: Driving
60: Driving
70: Driving
InstructionPUSH_B
InstructionPUSH_A
InstructionPUSH_B
InstructionPUSH_A
InstructionPUSH_B
InstructionPUSH_A
InstructionPUSH_B
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Ovm Testbench
Sequencer Arbitration:
Ovm Reporting
When sequencers are executed parallel, sequencer will arbitrate among the parallel Ovm Transaction
sequence. When all the parallel sequences are waiting for a grant from sequencer Ovm Factory
using wait_for_grant() method, then the sequencer, using the arbitration mechanism, Ovm Sequence 1
Ovm Sequence 2
sequencer grants to one of the sequencer.
Ovm Sequence 3
Ovm Sequence 4
There are 6 different arbitration algorithms, they are
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
OVM SEQUENCE 4
DPI

input is what keeps
with time!
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OVM Tutorial
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VMM Ethernet sample
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To set the arbitaration, use the set_arbitration() method of the sequencer. By default
, the arbitration algorithms is set to SEQ_ARB_FIFO.
functionvoidset_arbitration(SEQ_ARB_TYPEval)
Lets look at a example.
In this example, I have 3 child sequences seq_mul seq_add and seq_sub each of them
generates 3 transactions.
Sequence code 1:
virtualtaskbody();
repeat(3)begin
òvm_do_with(req,{inst ==MUL;});
end
endtask
Sequence code 2:
virtualtaskbody();
repeat(3)begin
òvm_do_with(req,{inst ==ADD;});
end
endtask
Sequence code 3:
virtualtaskbody();
repeat(3)begin
òvm_do_with(req,{inst ==SUB;});
end
endtask
In the body method, before starting child sequences, set the arbitration using
set_arbitration(). In this code, im setting it to SEQ_ARB_RANDOM.
seq_add add;
seq_sub sub;
seq_mul mul;
super.new(name);
endfunction
virtualtaskbody();
m_sequencer.set_arbitration(SEQ_ARB_RANDOM);
fork
òvm_do(add)
òvm_do(sub)
òvm_do(mul)
join
endtask
endclass
ovm_sequence_7.tar
Log file report for when SEQ_ARB_RANDOM is set.

Log file report for when SEQ_ARB_FIFO is set.
If you observe the first log report, all the transaction of the sequences are generated
in random order. In the second log file, the transactions are given equal priority and
are in fifo order.
Setting The Sequence Priority:
There are two ways to set the priority of a sequence. One is using the start method of
the sequence and other using the set_priority() method of the sequence. By default,
the priority of a sequence is 100. Higher numbers indicate higher priority.
virtualtaskstart(ovm_sequencer_base sequencer,
ovm_sequence_base parent_sequence =null,
integerthis_priority =100,
bitcall_pre_post =1)
functionvoidset_priority (intvalue)
Lets look a example with SEQ_ARB_WEIGHTED.
For sequence seq_mul set the weight to 200.
For sequence seq_add set the weight to 300.
For sequence seq_sub set the weight to 400.
In the below example, start() method is used to override the default priority value.
Code :
seq_add add;
seq_sub sub;
seq_mul mul;
super.new(name);
endfunction
virtualtaskbody();
m_sequencer.set_arbitration(SEQ_ARB_WEIGHTED);
add =new("add");
sub =new("sub");
mul =new("mul");
fork
sub.start(m_sequencer,this,400);
add.start(m_sequencer,this,300);
mul.start(m_sequencer,this,200);
join
endtask
endclass
ovm_sequence_8.tar
Log file report

40: Driving
50: Driving
60: Driving
70: Driving
80: Driving
InstructionADD
InstructionADD
InstructionADD
InstructionMUL
InstructionSUB
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OVM SEQUENCE 5
SystemVerilog
Sequencer Registration Macros
Verification
Constructs
DPI
Sequence Registration Macros does the following

1) Implements get_type_name method.
2) Implements create() method.
3) Registers with the factory.
4) Implements the static get_type() method.
5) Implements the virtual get_object_type() method.
6) Registers the sequence type with the sequencer type.
7) Defines p_sequencer variable. p_sequencer is a handle to its sequencer.
8) Implements m_set_p_sequencer() method.
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If there are no local variables, then use following macro
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òvm_sequence_utils(TYPE_NAME,SQR_TYPE_NAME)
If there are local variables in sequence, then use macro
òvm_sequence_utils_begin(TYPE_NAME,SQR_TYPE_NAME)
òvm_field_*macro invocations here
òvm_sequence_utils_end
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VMM Ethernet sample Macros òvm_field_* are used for define utility methods.
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Verification
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OpenVera
Constructs
These òvm_field_* macrosare discussed in

OVM_TRANSACTION
Example to demonstrate the usage of the above macros:

classseq_mul extendsovm_sequence #(instruction);
randintegernum_inst ;
instruction req;
Switch TB
constraintnum_c {num_inst inside{3,5,7};};
RVM Switch TB
òvm_sequence_utils_begin(seq_mul,instruction_sequencer)
RVM Ethernet sample òvm_field_int(num_inst,OVM_ALL_ON)
Specman E
Interview Questions
super.new(name);
endfunction
virtualtaskbody();
$psprintf("Num of transactions %d",num_inst),OVM_LOW);
end
endtask
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
endclass
ovm_sequence_9.tar
Log
OVM_INFO @ 0: reporter [RNTST] Running test ...
OVM_INFO @ 0: reporter [sequencer.seq_mul] Num of transactions 5
Setting Sequence Members:
set_config_*can be used only for the components not for the sequences.
By using configuration you can change the variables inside components only not in
sequences.
But there is a workaround to this problem.
Sequence has handle name called p_sequencer which is pointing the Sequencer on
which it is running.
Sequencer is a component , so get_config_* methods are implemented for it.
So from the sequence, using the sequencer get_config_* methods, sequence members
can be updated if the variable is configured.
When using set_config_* , path to the variable should be sequencer name, as we are
using the sequencer get_config_* method.
Following method demonstrates how this can be done:
Sequence:
1) num_inst is a integer variables which can be updated.
2) In the body method, call the get_config_int() method to get the integer value if
num_inst is configured from testcase.
classseq_mul extendsovm_sequence #(instruction);
integernum_inst =4;
instruction req;
òvm_sequence_utils_begin(seq_mul,instruction_sequencer)
òvm_field_int(num_inst,OVM_ALL_ON)
super.new(name);
endfunction
virtualtaskbody();
$psprintf("Num of transactions %d",num_inst),OVM_LOW);
end
endtask
endclass
Testcase:
From the testcase, using the set_config_int() method, configure the num_inst to 3.
The instance path argument should be the sequencer path name.
moduletest;
initialbegin
sequencer.build();
driver.build();
sequencer.print();
fork
begin
run_test();
end
join
end
endmodule

ovm_sequence_10.tar
Log
OVM_INFO @ 0: reporter [RNTST] Running test ...
OVM_INFO @ 0: reporter [sequencer.seq_mul] Num of transactions 3
From the above log we can see that seq_mul.num_inst value is 3.
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SystemVerilog
OVM SEQUENCE 6
Verification
Exclusive Access
Constructs
A sequence may need exclusive access to the driver which sequencer is arbitrating
among multiple sequence. Some operations require that a series of transaction needs
to be driven without any other transaction in between them. Then a exclusive access
to the driver will allow to a sequence to complete its operation with out any other
sequence operations in between them.
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There are 2 mechanisms to get exclusive access:

Lock-unlcok
Grab-ungrab
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Lock-Unlock
OVM Tutorial
tasklock(ovm_sequencer_base sequencer =Null)

functionvoidunlock(ovm_sequencer_base sequencer =Null)
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Using lock() method , a sequence can requests for exclusive access.A lock request
will be arbitrated the same as any other request.A lock is granted after all earlier
requests are completed and no other locks or grabs are blocking this sequence. A
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lock() is blocking task and when access is granted, it will unblock.
VMM Ethernet sample
Using unlock(), removes any locks or grabs obtained by this sequence on the specified
sequencer.
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If sequencer is null, the lock/unlock will be applied on the current default sequencer.
Lets see an example,
In this example there are 3 sequences with each sequence generating 4 transactions.
All these 3 sequences will be called in parallel in another sequence.
Sequence 1 code:
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virtualtaskbody();
repeat(4)begin
òvm_do_with(req,{inst ==PUSH_A;});
end
endtask
Sequence 2 code:
virtualtaskbody();
repeat(4)begin
òvm_do_with(req,{inst ==POP_C;});
end
endtask
Sequence 3 code:
In this sequence , call the lock() method to get the exclusive access to driver.
After completing all the transaction driving, then call the unclock() method.
virtualtaskbody();
Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
input is what keeps
with time!
lock();
repeat(4)begin
end
unlock();
endtask
virtualtaskbody();
fork
òvm_do(s_a)
òvm_do(s_b)
òvm_do(s_c)
join
endtask
ovm_sequence_11.tar
Log file:
From the above log file, we can observe that , when seq_b sequence got the access,
then transactions from seq_a and seq_c are not generated.
Lock() will be arbitrated before giving the access. To get the exclusive access without
arbitration, grab() method should be used.
Grab-Ungrab
taskgrab(ovm_sequencer_base sequencer =null)
functionvoidungrab(ovm_sequencer_base sequencer =null)
grab() method requests a lock on the specified sequencer. A grab() request is put in
front of the arbitration queue.It will be arbitrated before any other requests.A
grab() is granted when no other grabs or locks are blocking this sequence.
A grab() is blocking task and when access is granted, it will unblock.
Ungrab() method removes any locks or grabs obtained by this sequence on the
specified sequencer.
If no argument is supplied, then current default sequencer is chosen.
Example:
virtualtaskbody();
#25;
grab();
repeat(4)begin
end
ungrab();
endtask
ovm_sequence_12.tar
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OVM CONFIGURATION
SystemVerilog
Verification
Constructs
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Functional Coverage
Assertion
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UVM Tutorial
VMM Tutorial
OVM Tutorial
Configuration is amechanism in OVM that higher level components in a hierarchy can

configure the lower level components variables. Using set_config_* methods, user can
configure integer, string and objects of lower level components. Without this
mechanism, user should access the lower level component using hierarchy paths,
which restricts reusability. This mechanism can be used only with components.
Sequences and transactions cannot be configured using this mechanism. When
set_config_* method is called, the data is stored w.r.t strings in a table. There is also
a global configuration table.
Higher level component can set the configuration data in level component table. It is
the responsibility of the lower level component to get the data from the component
table and update the appropriate table.

input is what keeps
Set_config_* Methods:
Following are the method to configure integer , string and object of ovm_object with time!
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based class respectively.
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functionvoidset_config_int (stringinst_name,
stringfield_name,
ovm_bitstream_t value)
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functionvoidset_config_string (stringinst_name,
stringfield_name,
VMM Ethernet sample stringvalue)
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Verilog
Verification
functionvoidset_config_object (stringinst_name,
stringfield_name,
ovm_object value,bitclone =1)
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string inst_name: Hierarchical string path.
string field_name: Name of the field in the table.
bitstream_t value: In set_config_int, a integral value that can be anything from 1
bit to 4096 bits.
bit clone : If this bit is set then object is cloned.
inst_name and field_name are strings of hierarchal path. They can include wile card
RVM Ethernet sample "*" and "?" characters. These methods must be called in build phase of the component.
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Index
Introduction
Ovm Testbench
Ovm Reporting
Ovm Transaction
Ovm Factory
Ovm Sequence 1
Ovm Sequence 2
Ovm Sequence 3
Ovm Sequence 4
Ovm Sequence 5
Ovm Sequence 6
Ovm Configuration
"*"matches zero or more characters

"?"matches exactly one character
Some examples:
"*" -All the lower level components.
"*abc"-All the lower level components which ends with "abc".
Example: "xabc","xyabc","xyzabc" ....
http://testbench.in/OT_12_OVM_CONFIGURATION.html[9/26/2012 2:27:52 PM]
"abc*"-All the lower level components which startswith "abc".

Example: "abcx","abcxy","abcxyz" ....
"ab?" -All the lower level components which start with "ab" , then followed by one
more character.
Example: "abc","abb","abx" ....
"?bc" -All the lower level components which start with any one character,then
followed by "c".
Example: "abc","xbc","bbc" ....
"a?c" -All the lower level components which start with "a" , then followed by one
more character and then followed by "c".
Example: "abc","aac","axc" ..
There are two ways to get the configuration data:

1)Automatic : Using Field macros
2)Manual : using gte_config_* methods.
Automatic Configuration:
To use the atomic configuration, all the configurable fields should be defined using
ovm component field macros and ovm component utilities macros.
Ovm component utility macros:
For non parameterized classes
òvm_component_utils_begin(TYPE)
òvm_component_utils_end
For parameterized classes.
òvm_component_param_utils_begin(TYPE)
For OVM Field macros, Refer to link
OVM_TRANSACTION
Example:
Following example is from link
OVM_TESTBENCH
2 Configurable fields, a integer and a string are defined in env, agent, monitor and
driver classes. Topology of the environment using these classes is
Driver class Source Code:

Similar to driver class, all other components env, agent and monitor are define.
classdriver extendsovm_driver;
integerint_cfg;
stringstr_cfg;
òvm_component_utils_begin(driver)
òvm_field_int(int_cfg,OVM_DEFAULT)
òvm_field_string(str_cfg,OVM_DEFAULT)
endfunction
super.build();
endfunction
endclass
Testcase:
Using set_config_int() and set_config_string() configure variables at various hierarchal
locations.
//t_env.ag1.drv.int_cfg
//t_env.ag1.mon.int_cfg
set_config_int("*.ag1.*","int_cfg",32);
//t_env.ag2.drv
set_config_int("t_env.ag2.drv","int_cfg",32);
//t_env.ag2.mon
set_config_int("t_env.ag2.mon","int_cfg",32);
set_config_string("*.ag?.*","str_cfg","pars");
//t_env.str_cfg
set_config_string("t_env","str_cfg","abcd");
ovm_configuration_1.tar
Browse the code in ovm_configuration_1.tar

From the above log report of th example, we can see the variables int_cfg and str_cfg
of all the components and they are as per the configuration setting from the testcase.
Manual Configurations:
Using get_config_* methods, user can get the required data if the data is available in
the table.
Following are the method to get configure data of type integer , string and object of
ovm_object based class respectively.
functionbitget_config_int (stringfield_name,
inoutovm_bitstream_t value)
functionbitget_config_string (stringfield_name,
inoutstringvalue)
functionbitget_config_object (stringfield_name,
inoutovm_object value,
inputbitclone =1)
If a entry is found in the table with "field_name" then data will be updated to "value"
argument . If entry is not found, then the function returns "0". So when these
methods are called, check the return value.
Example:
Driver class code:
classdriver extendsovm_driver;
integerint_cfg;
stringstr_cfg;
òvm_component_utils(driver)
endfunction
super.build();
void'(get_config_int("int_cfg",int_cfg));
void'(get_config_string("str_cfg",str_cfg));
$psprintf("int_cfg %0d : str_cfg %0s ",int_cfg,str_cfg),OVM_LOW);
endfunction
endclass
Log file
OVM_INFO @ 0: ovm_test_top.t_env
int_cfg x : str_cfg abcd
OVM_INFO @ 0: ovm_test_top.t_env.ag1
int_cfg x : str_cfg
OVM_INFO @ 0: ovm_test_top.t_env.ag1.drv
OVM_INFO @ 0: ovm_test_top.t_env.ag1.mon
OVM_INFO @ 0: ovm_test_top.t_env.ag2
int_cfg x : str_cfg
OVM_INFO @ 0: ovm_test_top.t_env.ag2.drv
OVM_INFO @ 0: ovm_test_top.t_env.ag2.mon
Configuration Setting Members:

print_config_settings
functionvoidprint_config_settings
(stringfield="",
ovm_componentcomp=null,
bitrecurse=0)
This method prints all configuration information for this component.
If "field" is specified and non-empty, then only configuration settings matching that
field, if any, are printed.The field may not contain wildcards. If "recurse" is set, then
information for all children components are printed recursively.
print_config_matches
staticbitprint_config_matches =0
Setting this static variable causes get_config_* to print info about matching
configuration settings as they are being applied. These two members will be helpful
to know while debugging.
Log file
When print_config_settings method is called
ovm_test_top.t_env.ag1.drv
ovm_test_top.*.ag1.* int_cfg int 32
ovm_test_top.t_env.ag1.drv.rsp_port
ovm_test_top.*.ag?.* str_cfg stringpars
ovm_test_top.t_env.ag1.drv.rsp_port
ovm_test_top.t_env.ag1.drv.sqr_pull_port
ovm_test_top.*.ag?.* str_cfg stringpars
ovm_test_top.t_env.ag1.drv.sqr_pull_port
When print_config_matches is set to 1.
OVM_INFO @ 0: ovm_test_top.t_env [auto-configuration]
Auto-configuration matches for component ovm_test_top.t_env (env).
Last entry for a given field takes precedence.
Config set fromInstance Path Field name TypeValue
-----------------------------------------------------------------------------ovm_test_top(test1) ovm_test_top.t_env str_cfgstringabcd
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Index
Introduction
Specification
In this tutorial, we will verify the Switch RTL core. Following are the steps we follow Verification Plan
Phase 1 Top
to verify the Switch RTL core.
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
1) Understand the specification
Phase 5 Driver
Phase 6 Receiver
2) Developing Verification Plan
Phase 7 Scoreboard
3) Building the Verification Environment. We will build the Environment in Multiple Phase 8 Coverage
Phase 9 Testcase
phases, so it will be easy for you to lean step by step.
INTRODUCTION

Phase 1) We will develop the testcase and interfaces, and integrate them in these on This section - Your
input is what keeps
with the DUT in top module.
with time!
Phase 2) We will Develop the Environment class.
Phase 3) We will develop reset and configuration methods in Environment class.

Then using these methods, we will reset the DUT and configure the port address.
Phase 4) We will develop a packet class based on the stimulus plan. We will also
write a small code to test the packet class implementation.
Phase 5) We will develop a driver class. Packets are generated and sent to dut
using driver.
Phase 6) We will develop receiver class. Receiver collects the packets coming from
the output port of the DUT.
Phase 7) We will develop scoreboard class which does the comparison of the
expected packet with the actual packet received from the DUT.
Phase 8) We will develop coverage class based on the coverage plan.
OpenVera
Constructs
Phase 9) In this phase , we will write testcases and analyze the coverage report.
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SL_01_INTRODUCTION.html[9/26/2012 2:28:00 PM]
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Introduction
Specification
Switch Specification:
Verification Plan
This is a simple switch. Switch is a packet based protocol. Switch drives the incoming Phase 1 Top
packet which comes from the input port to output ports based on the address Phase 2 Environment
Phase 3 Reset
contained in the packet.
Phase 4 Packet
The switch has a one input port from which the packet enters. It has four output ports Phase 5 Driver
Phase 6 Receiver
where the packet is driven out.
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
SPECIFICATION
DPI

input is what keeps
with time!
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Packet Format:
Packet contains 3 parts. They are Header, data and frame check sequence.
Packet width is 8 bits and the length of the packet can be between 4 bytes to 259
bytes.
Packet Header:
Packet header contains three fields DA, SA and length.
DA: Destination address of the packet is of 8 bits. The switch drives the packet to
respective ports based on this destination address of the packets. Each output port
has 8-bit unique port address.If the destination address of the packet matches the
port address, then switch drives the packet to the output port.
SA: Source address of the packet from where it originate. It is 8 bits.
Length: Length of the data is of 8 bits andfrom 0 to 255. Length is measured in terms
of bytes.
If Length = 0, it means data length is 0 bytes
http://testbench.in/SL_02_SPECIFICATION.html[9/26/2012 2:28:08 PM]

Data: Data should be in terms of bytes and can take anything.
FCS: Frame check sequence
This field contains the security check of the packet. It is calculated over the header
and data.
Configuration:
Switch has four output ports. These output ports address have to be configured to a
unique address. Switch matches the DA field of the packet with this configured port
address and sends the packet on to that port. Switch contains a memory. This
memory has 4 locations, each can store 8 bits. To configure the switch port address,
memory write operation has to be done using memory interface. Memory address
(0,1,2,3) contains the address of port(0,1,2,3) respectively.
Interface Specification:
The Switch has one input Interface, from where the packet enters and 4 output
interfaces from where the packet comes out and one memory interface, through the
port address can be configured.Switch also has a clock and asynchronous reset
signal.
Memory Interface:
Through memory interfaced output port address are configured. It accepts 8 bit data
to be written to memory. It has 8 bit address inputs. Address 0,1,2,3 contains the
address of the port 0,1,2,3 respectively.
There are 4 input signals to memory interface. They are
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
All the signals are active high and are synchronous to the positive edge of clock
signal.
To configure a port address,
1.Assert the mem_en signal.
2.Asser the mem_rd_wr signal.

3.Drive the port number (0 or 1 or 2 or 3) on the mem_add signal
4.Drive the 8 bit port address on to mem_data signal.
Input Port
Packets are sent into the switch using input port.
signal.
inputport has 2inputsignals.They are
input[7:0]data;
inputdata_status;
To send the packet in to switch,
1.
2.
3.
4.
Assert the data_status signal.

Send the packet on the data signal byte by byte.
After sending all the data bytes, deassert the data_status signal.
There should be at least 3 clock cycles difference between packets.
Output Port
Switch sends the packets out using the output ports.There are 4 ports, each having
data, ready and read signals.All the signals are active high and are synchronous to
the positive edge of clock signal.
Signal list is
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
When the data is ready to be sent out from the port, switch asserts ready_* signal
high indicating that data is ready to be sent.
If the read_* signal is asserted, when ready_* is high, then the data comes out of the
port_* signal after one clock cycle.
RTLcode:
RTL code is attached with the tar files. From the Phase 1, you can download the tar
files.
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Index
Introduction
Specification
Overview
Verification Plan
This Document describes the Verification Plan for Switch. The Verification Plan is Phase 1 Top
based on System Verilog Hardware Verification Language. The methodology used for Phase 2 Environment
Phase 3 Reset
Verification is Constraint random coverage driven verification.
Phase 4 Packet
Phase 5 Driver
Phase 6 Receiver
Feature Extraction
Phase 7 Scoreboard
Phase 8 Coverage
This section contains list of all the features to be verified.
Phase 9 Testcase
1)
ID:Configuration
Description: Configure all the 4 port address with unique values.
VERIFICATION PLAN
input is what keeps

2)
ID: Packet DA
Description: DA field of packet should be any of the port address. All the 4 port with time!
address should be used.
3)
ID : Packet payload
Description: Length can be from 0 to 255. Send packets with all the lengths.
4)
ID: Length
VMM Ethernet sample Description:
Length field contains length of the payload.
Send Packet with correct length field and incorrect length fields.
Verilog
5)
Verification
ID: FCS
Verilog Switch TB
Description:
Good FCS:Send packet with good FCS.
Basic Constructs
Bad FCS: Send packet with corrupted FCS.
AVM Switch TB
OpenVera
Constructs
1)
2)
RVM Switch TB
3)
RVM Ethernet sample 4)
Switch TB
Specman E
Interview Questions
Packet DA: Generate packet DA with the configured address.

Payload length: generate payload length ranging from 2 to 255.
Correct or Incorrect Length field.
Generate good and bad FCS.
Coverage Plan
1)Cover all the port address configurations.
2)Cover all the packet lengths.
3)Cover all correct and incorrect length fields.
4)Cover good and bad FCS.
5)Cover all the above combinations.
http://testbench.in/SL_03_VERIFICATION_PLAN.html[9/26/2012 2:28:17 PM]
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Index
Introduction
Specification
Verification Plan
In phase 1,
Phase 1 Top
1) We will write SystemVerilog Interfaces for input port, output port and memory Phase 2 Environment
Phase 3 Reset
port.
Phase 4 Packet
2) We will write Top module where testcase and DUT instances are done.
Phase 5 Driver
3) DUT and TestBench interfaces are connected in top module.
Phase 6 Receiver
4) Clock is generator in top module.
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
NOTE:In every file you will see the syntax
ìfndefGUARD_*
èndifGUARD_*
PHASE 1 TOP
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Interfaces
In the interface.sv file, declare the 3 interfaces in the following way.
All the interfaces has clock as input.
All the signals in interface are logic type.
All the signals are synchronized to clock except reset in clocking block.
Signal directional w.r.t TestBench is specified with modport.
ìfndefGUARD_INTERFACE
`defineGUARD_INTERFACE
//////////////////////////////////////////
// Interface declaration for the memory///
//////////////////////////////////////////
Basic Constructs
interfacemem_interface(inputbitclock);
logic[7:0]mem_data;
logic[1:0]mem_add;
logic mem_en;
OpenVera
logic
mem_rd_wr;
Constructs
Switch TB
clockingcb@(posedgeclock);
defaultinput#1output#1;
RVM Switch TB
output mem_data;
RVM Ethernet sample outputmem_add;
outputmem_en;
outputmem_rd_wr;
endclocking
Specman E
Interview Questions
modportMEM(clockingcb,inputclock);
endinterface
////////////////////////////////////////////
// Interface for the input side of switch.//
// Reset signal is also passed hear.//
////////////////////////////////////////////
interfaceinput_interface(inputbitclock);
logic data_status;
logic [7:0]data_in;
http://testbench.in/SL_04_PHASE_1_TOP.html[9/26/2012 2:28:27 PM]

input is what keeps
with time!
logic reset;
outputdata_status;
outputdata_in;
endclocking
modportIP(clockingcb,outputreset,inputclock);
endinterface
/////////////////////////////////////////////////
// Interface for the output side of the switch.//
// output_interface is for only one output port//
/////////////////////////////////////////////////
interfaceoutput_interface(inputbitclock);
logic[7:0]data_out;
logicready;
logicread;
input data_out;
input ready;
outputread;
endclocking
modportOP(clockingcb,inputclock);
endinterface
//////////////////////////////////////////////////
èndif
Testcase
Testcase is a program block which provides an entry point for the test and creates a
scope that encapsulates program-wide data. Currently this is an empty testcase which
just ends the simulation after 100 time units.Program block contains all the above
declared interfaces as arguments. This testcase has initial and final blocks.
ìfndefGUARD_TESTCASE
`defineGUARD_TESTCASE
programtestcase(mem_interface.MEMmem_intf,input_interface.IPinput_intf,output_interface.OPoutput_intf[4
]);
initial
begin
$display(" ******************* Start of testcase ****************");
#1000;
end
final
$display(" ******************** End of testcase *****************");
endprogram
èndif
Top Module
The modules that are included in the source text but are not instantiated are called
top modules. This module is the highest scope of modules. Generally this module is
named as "top" and referenced as "top module".Module name can be anything.
Do the following in the top module:
1)Generate the clock signal.
bitClock;
initial
forever#10Clock =~Clock;
2)Do the instances of memory interface.
mem_interface mem_intf(Clock);
3)Do the instances of input interface.
input_interface input_intf(Clock);
4)There are 4 output ports. So do 4 instances of output_interface.
output_interface output_intf[4](Clock);
5)Do the instance of testcase and pass all the above declared interfaces.
testcase TC(mem_intf,input_intf,output_intf);
6)Do the instance of DUT.
switch DUT(.
7)Connect all the interfaces and DUT.The design which we have taken is in
verilog.So Verilog DUT instance is connected signal by signal.
switch DUT(.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.ready_0(output_intf[0].ready),
.read_0(output_intf[0].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));
Top Module Source Code:

ìfndefGUARD_TOP
`defineGUARD_TOP
moduletop();
/////////////////////////////////////////////////////
// Clock Declaration and Generation//
/////////////////////////////////////////////////////
bitClock;
initial
/////////////////////////////////////////////////////
//Memory interface instance//
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//Input interface instance //
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//output interface instance//
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//Program block Testcase instance//
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//DUT instance and signal connection //
/////////////////////////////////////////////////////
endmodule
èndif
switch_1.tar
Browse the code in switch_1.tar
Run the simulation:
vcs -sverilog -f filelist -R -ntb_opts dtm
Log file after simulation:
******************* Start of testcase ****************
******************** End of testcase *****************
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Assertion
Index
Introduction
Specification
Verification Plan
In this phase, we will write
Phase 1 Top
Phase 2 Environment
Environment class.
Phase 3 Reset
Virtual interface declaration.
Phase 4 Packet
Defining Environment class constructor.
Phase 5 Driver
Defining required methods for execution. Currently these methods will not be Phase 6 Receiver
implemented in this phase.
Phase 7 Scoreboard
Phase 8 Coverage
All the above are done in Environment.sv file.
Phase 9 Testcase
DPI
We will write a testcase using the above define environment class in testcase.sv file.
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PHASE 2 ENVIRONMENT
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Environment Class:
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The class is a base class used to implement verification environments. Testcase

contains the instance of the environment class and has access to all the public
declaration of environment class.
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All methods are declared as virtual methods. In environment class, we will formalize
the simulation steps using virtual methods.The methods are used to control the
VMM Ethernet sample execution of the simulation.
AVM Switch TB
Following are the methods which are going to be defined in environment class.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
1) new() : In constructor method, we will connect the virtual interfaces which are
passed as argument to the virtual interfaces to those which are declared in
environment class.
2) build(): In this method , all the objects like driver, monitor etc are constructed.
Currently this method is empty as we did not develop any other component.
3) reset(): in this method we will reset the DUT.
4) cfg_dut(): In this method, we will configure the DUT output port address.
5) start(): in this method, we will call the methods which are declared in the other
components like driver and monitor.
6) wait_for_end(): this method is used to wait for the end of the simulation.Waits
until all the required operations in other components are done.
Specman E
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7) report(): This method is used to print the TestPass and TestFail status of the
simulation, based on the error count..
8) run(): This method calls all the above declared methods in a sequence order. The
testcase calls this method, to start the simulation.
We are not implementing build(), reset(), cfg_dut() , strat() and report() methodsin
this phase.
Connecting the virtual interfaces of Environment class to the physical interfaces of
http://testbench.in/SL_05_PHASE_2_ENVIRONMENT.html[9/26/2012 2:28:38 PM]

input is what keeps
with time!
top module.
Verification environment contains the declarations of the virtual interfaces. Virtual
interfaces are just a handles(like pointers). When a virtual interface is declared, it
only creats a handle. It doesnot creat a real interface.
Constructor method should be declared with virtual interface as arguments, so that
when the object is created in testcase, new() method can pass the interfaces in to
environment class where they are assigned to the local virtual interface handle. With
this, the Environment classvirtual interfaces are pointed to the physical interfaces
which are declared in the top module.
Declare virtual interfaces in Environmentclass.

virtualmem_interface.MEMmem_intf;
virtualinput_interface.IPinput_intf ;
virtualoutput_interface.OPoutput_intf[4];
The construction of Environment class is declared with virtual interface as arguments.
functionnew(virtualmem_interface.MEMmem_intf_new ,
virtualinput_interface.IPinput_intf_new ,
virtualoutput_interface.OPoutput_intf_new[4]);
In constructor methods, the interfaces which are arguments are connected to the
virtual interfaces of environment class.
this.mem_intf=mem_intf_new;
this.input_intf=input_intf_new;
this.output_intf =output_intf_new ;
Run :
The run() method is called from the testcase to start the simulation. run() method
calls all the methods which are defined in the Environment class.
taskrun();
$display(" %0d : Environment: start of run() method",$time);
build();
reset();
cfg_dut();
start();
wait_for_end();
report();
$display(" %0d : Environment: end of run() method",$time);

endtask:run
Environment Class Source Code:

ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment ;
$display(" %0d : Environment: created env object",$time);

endfunction:new
$display(" %0d : Environment: start of build() method",$time);
$display(" %0d : Environment: end of build() method",$time);
endfunction:build
taskreset();
$display(" %0d : Environment: start of reset() method",$time);
$display(" %0d : Environment: end of reset() method",$time);
endtask:reset
taskcfg_dut();
$display(" %0d : Environment: start of cfg_dut() method",$time);
$display(" %0d : Environment: end of cfg_dut() method",$time);
endtask:cfg_dut
taskstart();
$display(" %0d : Environment: start of start() method",$time);
$display(" %0d : Environment: end of start() method",$time);
endtask:start
taskwait_for_end();
$display(" %0d : Environment: start of wait_for_end() method",$time);

$display(" %0d : Environment: end of wait_for_end() method",$time);
endtask:wait_for_end
taskrun();
build();
reset();
cfg_dut();
start();
wait_for_end();
report();
endtask:run
taskreport();
endtask:report
endclass
èndif
We will create a file Global.sv for global requirement. In this file,define all the port
address as macros in this file. Define a variable error as integer to keep track the
number of errors occurred during the simulation.
ìfndefGUARD_GLOBALS
`defineGUARD_GLOBALS
`defineP08'h00
`defineP18'h11
`defineP28'h22
`defineP38'h33
interror =0;
intnum_of_pkts =10;
èndif
Now we will update the testcase. Take an instance of the Environment class and call
the run method of the Environment class.
ìfndef GUARD_TESTCASE
`define GUARD_TESTCASE
program
testcase(mem_interface.MEM
input_intf,output_interface.OP output_intf[4]);
mem_intf,input_interface.IP
Environment env;
initial
begin
env =new(mem_intf,input_intf,output_intf);
env.run();
#1000;
end
final
endprogram
èndif
Download the phase 2 source code:
switch_2.tar
Run the simulation:

Log report after the simulation:
0 : Environemnt : created env object
0 : Environemnt : start of run() method
0 : Environemnt : start of build() method
0 : Environemnt : end of build() method
0 : Environemnt : start of reset() method
0 : Environemnt : end of reset() method
0 : Environemnt : start of cfg_dut() method
0 : Environemnt : end of cfg_dut() method
0 : Environemnt : start of start() method
0 : Environemnt : end of start() method
0 : Environemnt : start of wait_for_end() method
0 : Environemnt : end of wait_for_end() method
0 : Environemnt : end of run() method
******************** End of testcase *****************
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Verification Plan
In this phase we will reset and configure the DUT.
Phase 1 Top
The Environment class has reset() method which contains the logic to reset the DUT Phase 2 Environment
Phase 3 Reset
and cfg_dut() method which contains the logic to configure the DUT port address.
Phase 4 Packet
Phase 5 Driver
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
PHASE 3 RESET
DPI

input is what keeps
with time!
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Verilog Switch TB
Basic Constructs
NOTE:Clocking block signals can be driven only using a non-blocking assignment.

Define the reset() method.
1) Set all the DUT input signals to a known state.
mem_intf.cb.mem_data<=0;
mem_intf.cb.mem_add <=0;
mem_intf.cb.mem_en<=0;
Constructs
mem_intf.cb.mem_rd_wr <=0;
input_intf.cb.data_in <=0;
Switch TB
input_intf.cb.data_status <=0;
RVM Switch TB
output_intf[0].cb.read<=0;
RVM Ethernet sample output_intf[1].cb.read<=0;
OpenVera
Specman E
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2) Reset the DUT.

// Reset the DUT
input_intf.reset <=1;
repeat(4)@input_intf.clock;
3) Updated the cfg_dut method.
taskcfg_dut();
http://testbench.in/SL_06_PHASE_3_RESET.html[9/26/2012 2:28:48 PM]
mem_intf.cb.mem_en <=1;
@(posedgemem_intf.clock);
mem_intf.cb.mem_add<=8'h0;
mem_intf.cb.mem_data <=`P0;
$display(" %0d : Environment: Port 0 Address %h ",$time,`P0);

endtask:cfg_dut
(4) In wait_for_end method, wait for some clock cycles.

taskwait_for_end();
repeat(10000)@(input_intf.clock);
endtask:wait_for_end
Download the Phase 3 source code:
switch_3.tar
Run the simulation:
Log File report
0 : Environment : created env object
0 : Environment : start of run() method
0 : Environment : start of build() method
0 : Environment : end of build() method
0 : Environment : start of reset() method
40 : Environment : end of reset() method
40 : Environment : start of cfg_dut() method
70 : Environment : Port 0 Address 00
150 : Environment : end of cfg_dut() method
150 : Environment : start of start() method

150 : Environment : end of start() method
150 : Environment : start of wait_for_end() method
100150 : Environment : end of wait_for_end() method
100150 : Environment : end of run() method
******************** End of testcase *****************
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In this Phase, We will define a packet and then test it whether it is generating as
expected.
Packet is modeled using class. Packet class should be able to generate all possible
packet types randomly. Packet class should also implement required methods like
packing(), unpacking(), compare() and display() methods.
We will write the packet class in packet.sv file. Packet class variables and constraints
have been derived from stimulus generation plan.
Revisit Stimulus Generation Plan
1) Packet DA: Generate packet DA with the configured address.
2) Payload length: generate payload length ranging from 2 to 255.
3) Correct or Incorrect Length field.
4) Generate good and bad FCS.
1) Declare FCS types as enumerated data types. Name members as GOOD_FCS and
BAD_FCS.
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2) Declare the length type as enumerated data type. Name members as

GOOD_LENGTH and BAD_LENGTH.
AVM Switch TB
VMM Ethernet sample typedefenum{GOOD_LENGTH,BAD_LENGTH}length_kind_t;
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
3) Declare the length type and fcs type variables as rand.

randlength_kind_tlength_kind;
4) Declare the packet field as rand. All fields are bit data types. All fields are 8 bit
packet array. Declare the payload as dynamic array.
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbytedata[];//Payload using Dynamic array,size is generated on the fly
randbytefcs;
RVM Ethernet sample 5) Constraint the DA field to be any one of the configured address.

Specman E
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6) Constrain the payload dynamic array size to between 1 to 255.

7) Constrain the payload length to the length field based on the length type.
constraintlength_kind_c {
(length_kind ==GOOD_LENGTH)->length ==data.size;
(length_kind ==BAD_LENGTH)->length ==data.size+2;}
Use solve before to direct the randomization to generate first the payload dynamic
http://testbench.in/SL_07_PHASE_4_PACKET.html[9/26/2012 2:28:58 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Driver
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
input is what keeps
with time!
array size and then randomize length field.

8) Constrain the FCS field initial value based on the fcs kind field.
constraintfcs_kind_c {
(fcs_kind ==GOOD_FCS)->fcs ==8'b0;
(fcs_kind ==BAD_FCS)->fcs ==8'b1;}
9) Define the FCS method.
functionbytecal_fcs;
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
10) Define display methods:
Display method displays the current value of the packet fields to standard output.
virtualfunctionvoiddisplay();
$display("\n---------------------- PACKETKIND ------------------------- ");
$display("fcs_kind : %s ",fcs_kind.name());
$display("length_kind: %s ",length_kind.name());
$display("-------- PACKET ---------- ");
$display("0 : %h ",da);
$display("1 : %h ",sa);
$display("2 : %h ",length);
foreach(data[i])
$write("%3d : %0h ",i +3,data[i]);
$display("\n %2d : %h ",data.size()+3,cal_fcs);
$display("----------------------------------------------------------- \n");
endfunction:display
11) Define pack method:
Packing is commonly used to convert the high level data to low level data that can be
applied to DUT.In packet class various fields are generated. Required fields are
concatenated to form a stream of bytes which can be driven conveniently to DUT
interface by the driver.
virtualfunctionintunsignedbyte_pack(reflogic[7:0]bytes[]);
bytes =new[data.size+4];
bytes[0]=da;
bytes[1]=sa;
bytes[2]=length;
foreach(data[i])
bytes[3+i]=data[i];
bytes[data.size()+3]=cal_fcs;
byte_pack =bytes.size;
12) Define unpack method:
The unpack() method does exactly the opposite of pack method. Unpacking is
commonly used to convert a data stream coming from DUT to high level data packet
object.
virtualfunctionvoidbyte_unpack(constreflogic[7:0]bytes[]);
this.da =bytes[0];
this.sa =bytes[1];
this.fcs =bytes[bytes.size-1];
this.data=new[bytes.size-4];
foreach(data[i])
data[i]=bytes[i +3];
this.fcs =0;
if(bytes[bytes.size-1]!=cal_fcs)
this.fcs =1;
14) Define a compare method.
Compares the current value of the object instance with the current value of the
specified object instance.
If the value is different, FALSE is returned.
virtualfunctionbitcompare(packet pkt);
compare=1;
if(pkt ==null)
begin
$display(" ** ERROR ** : pkt : received a null object ");
compare=0;
end
else
begin
if(pkt.da !==this.da)
begin
$display(" ** ERROR **: pkt : Da field did not match");
compare=0;
end
if(pkt.sa !==this.sa)
begin
$display(" ** ERROR **: pkt : Sa field did not match");
compare=0;
end
if(pkt.length !==this.length)
begin
$display(" ** ERROR **: pkt : Length field did not match");

compare=0;
end
foreach(this.data[i])
if(pkt.data[i]!==this.data[i])
begin
$display(" ** ERROR **: pkt : Data[%0d] field did not match",i);
compare=0;
end
if(pkt.fcs !==this.fcs)
begin
$display(" ** ERROR **: pkt : fcs field did not match %h %h",pkt.fcs ,this.fcs);
compare=0;
end
end
endfunction:compare
Packet Class Source Code
ìfndefGUARD_PACKET
`defineGUARD_PACKET
typedefenum{GOOD_LENGTH,BAD_LENGTH}length_kind_t;
classpacket;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbytefcs;
constraintfcs_kind_c {
(fcs_kind ==GOOD_FCS)->fcs ==8'b0;
(fcs_kind ==BAD_FCS)->fcs ==8'b1;}
functionbytecal_fcs;
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
///// method to print the packet fields ////
virtualfunctionvoiddisplay();
$display("\n---------------------- PACKETKIND ------------------------- ");
$display("fcs_kind : %s ",fcs_kind.name());
$display("length_kind: %s ",length_kind.name());
$display("-------- PACKET ---------- ");
$display("0 : %h ",da);
$display("1 : %h ",sa);
$display("2 : %h ",length);
foreach(data[i])
$write("%3d : %0h ",i +3,data[i]);
$display("\n %2d : %h ",data.size()+3,cal_fcs);
$display("----------------------------------------------------------- \n");
endfunction:display
///// method to pack the packet into bytes/////
virtualfunctionintunsignedbyte_pack(reflogic[7:0]bytes[]);
bytes =new[data.size+4];
bytes[0]=da;
bytes[1]=sa;
bytes[2]=length;
foreach(data[i])
bytes[3+i]=data[i];
bytes[data.size()+3]=cal_fcs;
byte_pack =bytes.size;
////method to unpack the bytes in to packet /////
virtualfunctionvoidbyte_unpack(constreflogic[7:0]bytes[]);
this.da =bytes[0];
this.sa =bytes[1];
this.fcs =bytes[bytes.size-1];
this.data=new[bytes.size-4];
foreach(data[i])
data[i]=bytes[i +3];
this.fcs =0;
if(bytes[bytes.size-1]!=cal_fcs)
this.fcs =1;
//// method to compare the packets /////
virtualfunctionbitcompare(packet pkt);
compare=1;
if(pkt ==null)
begin
$display(" ** ERROR ** : pkt : received a null object ");
compare=0;
end
else
begin
if(pkt.da !==this.da)
begin
$display(" ** ERROR **: pkt : Da field did not match");
compare=0;
end
if(pkt.sa !==this.sa)
begin
$display(" ** ERROR **: pkt : Sa field did not match");
compare=0;
end
if(pkt.length !==this.length)
begin
$display(" ** ERROR **: pkt : Length field did not match");
compare=0;
end
foreach(this.data[i])
if(pkt.data[i]!==this.data[i])
begin
$display(" ** ERROR **: pkt : Data[%0d] field did not match",i);
compare=0;
end
if(pkt.fcs !==this.fcs)
begin
$display(" ** ERROR **: pkt : fcs field did not match %h %h",pkt.fcs ,this.fcs);
compare=0;
end
end
endfunction:compare
endclass
Now we will write a small program to test our packet implantation. This program
block is not used to verify the DUT.
Write a simple program block and do the instance of packet class. Randomize the
packet and call the display method to analyze the generation. Then pack the packet
in to bytes and then unpack bytes and then call compare method to check all the
methods.
Program Block Source Code
programtest;
packet pkt1 =new();
packet pkt2 =new();
logic[7:0]bytes[];
initial
repeat(10)
if(pkt1.randomize)
begin
$display(" Randomization Successes full.");
pkt1.display();
void'(pkt1.byte_pack(bytes));
pkt2 =new();
pkt2.byte_unpack(bytes);
else
$display(" *** Something went wrong in Packing or Unpacking or compare ***");
end
else
endprogram
Download the packet class with program block.
switch_4.tar
Run the simulation
Log file report:
---------------------- PACKETKIND ------------------------fcs_kind : BAD_FCS
length_kind: GOOD_LENGTH
-------- PACKET ---------0 : 00
1 : f7
2 : be
3 : a6 4 : 1b 5 : b5 6 : fa 7 : 4e 8 : 15 9 : 7d10 : 7211 : 9612 : 3113 :
c414 : aa15 : c416 : cf17 : 4f18 : f419 : 1720 : 8821 : f122 : 2c23 : ce24
: 525 : cb26 : 8c27 : 1a28 : 3729 : 6030 : 5f31 : 7a32 : a233 : f034 :
c935 : dc36 : 4137 : 3f38 : 1239 : f440 : df41 : c542 : d743 : 9444 :
8845 : 146 : 3147 : 2948 : d649 : f450 : d951 : 4f52 : 053 : dd54 : d255
: a656 : 5957 : 4358 : 4559 : f260 : a261 : a162 : fd63 : ea64 : c165 :
2066 : c767 : 2068 : e169 : 9770 : c671 : cf72 : cd73 : 1774 : 9975 :
4976 : b877 : 1c78 : df79 : e680 : 1a81 : ce82 : 8c83 : ec84 : b685 :
bb86 : a587 : 1788 : cb89 : 3290 : e191 : 8392 : 9693 : e94 : ee95 :
5796 : 3397 : cd98 : 6299 : 88 100 : 7b 101 : e6 102 : 41 103 : ad 104 : 26 105 :
ee 106 : 9c 107 : 95 108 : a7 109 : b8 110 : 83 111 : f 112 : ca 113 : ec 114 : b5 115 :
8d 116 : d8 117 : 2f 118 : 6f 119 : ea 120 : 4c 121 : 35 122 : 41 123 : f2 124 : 4e 125
: 89 126 : d8 127 : 78 128 : f1 129 : d 130 : d6 131 : d5 132 : 8 133 : c 134 : de 135 :
a9 136 : 1d 137 : a0 138 : ae 139 : 99 140 : f5 141 : 53 142 : d8 143 : 7a 144 : 4c 145
: d4 146 : b8 147 : 54 148 : b7 149 : c3 150 : c9 151 : 7b 152 : a3 153 : 71 154 : 2b
155 : b4 156 : 50 157 : 54 158 : 22 159 : 95 160 : df 161 : 17 162 : c9 163 : 41 164 :
80 165 : 2b 166 : f0 167 : ba 168 : 4a 169 : a9 170 : 7f 171 : 13 172 : 1e 173 : 12 174
: a8 175 : 2 176 : 3 177 : 3d 178 : 71 179 : e6 180 : 96 181 : 89 182 : c6 183 : 46 184
: d6 185 : 1b 186 : 5f 187 : 20 188 : a0 189 : a3 190 : 49 191 : 79 192 : 9
193 : 53
----------------------------------------------------------Packing,Unpacking and compare worked
..............
..............
..............
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TUTORIALS
SystemVerilog
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Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Specification
In phase 5 we will write a driver and then instantiatethe driver in environment and Verification Plan
Phase 1 Top
send packet in to DUT. Driver class is defined in Driver.sv file.
Phase 2 Environment
Driver is class which generates the packets and then drives it to the DUT input Phase 3 Reset
Phase 4 Packet
interface and pushes the packet in to mailbox.
Phase 5 Driver
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
PHASE 5 DRIVER
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
1) Declare a packet.
Basic Constructs
packet gpkt;
OpenVera
Constructs
Switch TB
RVM Switch TB
2) Declare a virtual input_interface of the switch. We will connect this to the Physical
interface of the top module same as what we did in environment class.
virtualinput_interface.IPinput_intf;
3) Define a mailbox "drvr2sb" which is used to send the packets to the score board.
RVM Ethernet sample mailboxdrvr2sb;
Specman E
Interview Questions
4) Define new constructor with arguments, virtual input interface and a mail box
which is used to send packets from the driver to scoreboard.
functionnew(virtualinput_interface.IPinput_intf_new,mailboxdrvr2sb);
if(drvr2sb ==null)
begin
$display(" **ERROR**: drvr2sb is null");
$finish;
end
else
this.drvr2sb =drvr2sb;
5) Construct the packet in the driver constructor.
http://testbench.in/SL_08_PHASE_5_DRIVER.html[9/26/2012 2:29:08 PM]
gpkt =new();
6) Define the start method.
In start method, do the following
Repeat the following steps for num_of_pkts times.
repeat($root.num_of_pkts)
Randomize the packet and check if the randomization is successes full.
if(pkt.randomize())
begin
$display(" %0d : Driver : Randomization Successes full.",$time);
...........
...........
else
begin
$display(" %0d Driver : ** Randomization failed. **",$time);
............
...........
Display the packet content.
pkt.display();
Then pack the packet in to bytes.
length =pkt.byte_pack(bytes);
Then send the packet byte in to the switch by asserting data_status of the input
interface signal and driving the data bytes on to the data_in signal.
foreach(bytes[i])
begin
@(posedgeinput_intf.clock);
input_intf.cb.data_in <=bytes[i];
end
After driving all the data bytes, deassert data_status signal of the input interface.
Send the packet in to mail "drvr2sb" box for scoreboard.
drvr2sb.put(pkt);
If randomization fails, increment the error counter which is defined in Globals.sv file
$root.error++;
Driver Class Source Code:
ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
classDriver;
mailboxdrvr2sb;
packet gpkt;
//// constructor method ////
functionnew(virtualinput_interface.IPinput_intf_new,mailboxdrvr2sb);
if(drvr2sb ==null)
begin
$display(" **ERROR**: drvr2sb is null");
$finish;
end
else
gpkt =new();
endfunction:new
/// method to send the packet to DUT ////////
taskstart();
packet pkt;
intlength;
logic[7:0]bytes[];
repeat($root.num_of_pkts)
begin
repeat(3)@(posedgeinput_intf.clock);
pkt =newgpkt;
//// Randomize the packet /////
if(pkt.randomize())
begin
$display(" %0d : Driver : Randomization Successes full. ",$time);
//// display the packet content ///////
pkt.display();
//// Pack the packet in tp stream of bytes //////

length =pkt.byte_pack(bytes);
///// assert the data_status signal and send the packed bytes //////
foreach(bytes[i])
begin
input_intf.cb.data_in <=bytes[i];
end
//// deassert the data_status singal //////

//// Push the packet in to mailbox for scoreboard /////

drvr2sb.put(pkt);
$display(" %0d : Driver : Finished Driving the packet with length

%0d",$time,length);
end
else
begin
$display(" %0d Driver : ** Randomization failed. **",$time);
////// Increment the error count in randomization fails ////////
$root.error++;
end
end
endtask:start
endclass
èndif
Now we will take the instance of the driver in the environment class.
1) Declare a mailbox "drvr2sb" which will be used to connect the scoreboard and
driver.
mailboxdrvr2sb;
2) Declare a driver object "drvr".
Driver drvr;
3) In build method, construct the mail box.
drvr2sb =new();
4) In build method, construct the driver object. Pass the input_intf and "drvr2sb" mail
box.
drvr=new(input_intf,drvr2sb);
5) To start sending the packets to the DUT, call the start method of "drvr" in the start
method of Environment class.
drvr.start();
ìfndef GUARD_ENV
`define GUARD_ENV
class Environment ;
virtual mem_interface.MEMmem_intf ;
virtual input_interface.IPinput_intf ;
virtual output_interface.OP output_intf[4] ;
Driver drvr;
mailboxdrvr2sb;
function new(virtual mem_interface.MEMmem_intf_new ,
virtual input_interface.IPinput_intf_new ,
virtual output_interface.OP output_intf_new[4] );
this.mem_intf= mem_intf_new;
this.input_intf= input_intf_new;
this.output_intf = output_intf_new ;

endfunction : new
function void build();
drvr2sb =new();
drvr=new(input_intf,drvr2sb);
endfunction : build
task reset();
// Drive all DUT inputs to a known state
mem_intf.cb.mem_data<= 0;
mem_intf.cb.mem_add <= 0;
mem_intf.cb.mem_en<= 0;
mem_intf.cb.mem_rd_wr <= 0;
input_intf.cb.data_in <= 0;
input_intf.cb.data_status <= 0;
output_intf[0].cb.read<= 0;
// Reset the DUT

input_intf.reset <= 1;
repeat (4) @ input_intf.clock;

endtask : reset
task cfg_dut();
mem_intf.cb.mem_en <= 1;
@(posedge mem_intf.clock);
mem_intf.cb.mem_add<= 8'h0;
mem_intf.cb.mem_data <= `P0;

endtask :cfg_dut
task start();
drvr.start();
endtask : start
task wait_for_end();
repeat(10000) @(input_intf.clock);
endtask : wait_for_end
task run();
build();
reset();
cfg_dut();
start();
wait_for_end();
report();
endtask : run
task report();
endtask : report
endclass
èndif
switch_5.tar
Run the command:
Log file report.
0 : Environment : created env object
0 : Environment : start of run() method
0 : Environment : start of build() method
0 : Environment : end of build() method
0 : Environment : start of reset() method
40 : Environment : end of reset() method
40 : Environment : start of cfg_dut() method
150 : Environment : end of cfg_dut() method
150 : Environment : start of start() method
210 : Driver : Randomization Successes full.
---------------------- PACKETKIND ------------------------fcs_kind : BAD_FCS
length_kind: GOOD_LENGTH
-------- PACKET ---------0 : 22
1 : 11
2 : 2d
3 : 63 4 : 2a 5 : 2e 6 : c 7 : a 8 : 14 9 : c110 : 1411 : 8f12 : 5413 :
5d14 : da15 : 2216 : 2c17 : ac18 : 1c19 : 4820 : 3c21 : 7e22 : f323 :
ed24 : 2425 : d126 : 3e27 : 3828 : aa29 : 5430 : 1931 : 8932 : aa33 :
cf34 : 6735 : 1936 : 9a37 : 1d38 : 9639 : 840 : 1541 : 6642 : 5543 : b44
: 7045 : 3546 : fc47 : 8f
48 : cd
----------------------------------------------------------1210 : Driver : Finished Driving the packet with length 49
1270 : Driver : Randomization Successes full.
..................
..................
..................
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Specification
In this phase, we will write a receiver and use the receiver in environment class to Verification Plan
Phase 1 Top
collect the packets coming from the switch output_interface.
Phase 2 Environment
Receiver collects the data bytes from the interface signal. And then unpacks the bytes Phase 3 Reset
Phase 4 Packet
in to packet and pushes it into mailbox.
Phase 5 Driver
Phase 6 Receiver
Receiver class is written in reveicer.sv file.
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
PHASE 6 RECEIVER
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) Declare a virtual output_interface. We will connect this to the Physical interface of

the top module, same as what we did in environment class.
virtualoutput_interface.OPoutput_intf;
OpenVera
Constructs
Switch TB
RVM Switch TB
2) Declare a mailbox"rcvr2sb" which is used to send the packets to the score board
mailboxrcvr2sb;
3) Define new constructor with arguments, virtual input interface and a mail box
RVM Ethernet sample which is used to send packets from the receiver to scoreboard.
Specman E
Interview Questions
functionnew(virtualoutput_interface.OPoutput_intf_new,mailboxrcvr2sb);
this.output_intf=output_intf_new;
if(rcvr2sb ==null)
begin
$display(" **ERROR**: rcvr2sb is null");
$finish;
end
else
this.rcvr2sb =rcvr2sb;
endfunction:new
4) Define the start method.
http://testbench.in/SL_09_PHASE_6_RECEIVER.html[9/26/2012 2:29:17 PM]

Wait for the ready signal to be asserted by the DUT.
wait(output_intf.cb.ready)
If the ready signal is asserted, then request the DUT to send the data out from the
data_out signal by asserting the read signal. When the data to be sent is finished by
the DUT, it will deassert the ready signal. Once the ready signal is deasserted, stop
collecting the data bytes and deasseart the read signal.
output_intf.cb.read <=1;
repeat(2)@(posedgeoutput_intf.clock);
while(output_intf.cb.ready)
begin
bytes =new[bytes.size+1](bytes);
bytes[bytes.size-1]=output_intf.cb.data_out;
@(posedgeoutput_intf.clock);
end
$display(" %0d : Receiver : Received a packet of length %0d",$time,bytes.size);
Create a new packet object of packet.
pkt =new();
Then call the unpack method of the packet to unpacked the bytes and then display
the packet content.
pkt.byte_unpack(bytes);
pkt.display();
Then send the packet to scoreboard.
rcvr2sb.put(pkt);
Delete the dynamic array bytes.
bytes.delete();
Receiver Class Source Code:
ìfndefGUARD_RECEIVER
`defineGUARD_RECEIVER
classReceiver;
mailboxrcvr2sb;
//// constructor method ////
functionnew(virtualoutput_interface.OPoutput_intf_new,mailboxrcvr2sb);
if(rcvr2sb ==null)
begin
$display(" **ERROR**: rcvr2sb is null");
$finish;
end
else
endfunction:new
taskstart();
logic[7:0]bytes[];
packet pkt;
forever
begin
begin
end
$display(" %0d : Receiver : Received a packet of length %0d",$time,bytes.size);
pkt =new();
pkt.display();
rcvr2sb.put(pkt);
bytes.delete();
end
endtask:start
endclass
èndif
Now we will take the instance of the receiver in the environment class.
1) Declare a mailbox "rcvr2sb" which will be used to connect the scoreboard and
receiver.
mailboxrcvr2sb;
2) Declare 4 receiver object "rcvr".
Receiver rcvr[4];
3) In build method, construct the mail box.
rcvr2sb =new();
4) In build method, construct the receiver object. Pass the output_intf and "rcvr2sb"
mail box. There are 4 output interfaces and receiver objects. We will connect one
receiver for one output interface.
foreach(rcvr[i])
rcvr[i]=new(output_intf[i],rcvr2sb);
5) To start collecting the packets from the DUT, call the "start" method of "rcvr" in the
"start" method of Environment class.
taskstart();
fork
drvr.start();
rcvr[0].start();
rcvr[1].start();
rcvr[2].start();
rcvr[3].start();
join_any
endtask:start
ìfndef GUARD_ENV
`define GUARD_ENV
class Environment ;
Driver drvr;
Receiver rcvr[4];
mailbox drvr2sb;
mailboxrcvr2sb;

endfunction : new
drvr2sb = new();
rcvr2sb =new();
drvr= new(input_intf,drvr2sb);
foreach(rcvr[i])
rcvr[i]=new(output_intf[i],rcvr2sb);
endfunction : build
task reset();
// Reset the DUT


endtask : reset
task cfg_dut();

endtask :cfg_dut
task start();
fork
drvr.start();
rcvr[0].start();
rcvr[1].start();
rcvr[2].start();
rcvr[3].start();
join_any
endtask : start
task run();
build();
reset();
cfg_dut();
start();
wait_for_end();
report();
endtask : run
task report();
endtask: report
endclass
èndif
switch_6.tar
Run the command:
<< PREVIOUS PAGE
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Specification
Verification Plan
In this phase we will see the scoreboard implementation.
Phase 1 Top
Scoreboard has 2 mailboxes. One is used to for getting the packets from the driver Phase 2 Environment
and other from the receiver.Then the packets are compared and if they don't match, Phase 3 Reset
Phase 4 Packet
then error is asserted.
Phase 5 Driver
Scoreboard in implemented in file Scoreboard.sv.
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
Phase 9 Testcase
PHASE 7 SCOREBOARD
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
1) Declare 2 mailboxes drvr2sb and rcvr2sb.

mailboxdrvr2sb;
mailboxrcvr2sb;
2) Declare a constructor method with "drvr2sb" and "rcvr2sb" mailboxes as arguments.
functionnew(mailboxdrvr2sb,mailboxrcvr2sb);
RVM Ethernet sample 3) Connect the mailboxes of the constructor to the mail boxes of the scoreboard.
Specman E
Interview Questions
4) Define a start method.
Do the following steps forever.
Wait until there is a packet is in "rcvr2sb". Then pop the packet from the mail box.
rcvr2sb.get(pkt_rcv);
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time);
Then pop the packet from drvr2sb.
drvr2sb.get(pkt_exp);
http://testbench.in/SL_10_PHASE_7_SCOREBOARD.html[9/26/2012 2:29:27 PM]
Compare both packets and increment an error counter if they are not equal.
if(pkt_rcv.compare(pkt_exp))
$display(" %0d : Scoreboardd :Packet Matched ",$time);
else
$root.error++;
Scoreboard Class Source Code:
ìfndefGUARD_SCOREBOARD
`defineGUARD_SCOREBOARD
classScoreboard;
mailboxdrvr2sb;
mailboxrcvr2sb;
functionnew(mailboxdrvr2sb,mailboxrcvr2sb);
endfunction:new
taskstart();
packet pkt_rcv,pkt_exp;
forever
begin
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver
",$time);
else
$root.error++;
end
endtask:start
endclass
èndif
Now we will see how to connect the scoreboard in the Environment class.
1) Declare a scoreboard.
Scoreboard sb;
2) Construct the scoreboard in the build method. Pass the drvr2sb and rcvr2sb
mailboxes to the score board constructor.
sb =new(drvr2sb,rcvr2sb);
3) Start the scoreboard method in the start method.
sb.start();
4) Now we are to the end of building the verification environment.
In the report() method of environment class, print the TEST PASS or TEST FAILstatus
based on the error count.
taskreport();
$display("\n\n*************************************************");
if(0==$root.error)
$display("********TEST PASSED *********");
else
$display("********TEST Failed with %0d errors *********",$root.error);
$display("*************************************************\n\n");
endtask:report
Source Code Of The Environment Class:
ìfndef GUARD_ENV
`define GUARD_ENV
class Environment ;
Driver drvr;
Receiver rcvr[4];
Scoreboard sb;
mailbox drvr2sb ;
mailbox rcvr2sb ;
endfunction : new
drvr2sb = new();
rcvr2sb = new();
sb =new(drvr2sb,rcvr2sb);
drvr= new(input_intf,drvr2sb);
foreach(rcvr[i])
rcvr[i]= new(output_intf[i],rcvr2sb);
endfunction : build
task reset();
// Reset the DUT


endtask : reset
task cfg_dut();

endtask :cfg_dut
task start();
fork
drvr.start();
rcvr[0].start();
rcvr[1].start();
rcvr[2].start();
rcvr[3].start();
sb.start();
join_any
endtask : start
task run();
build();
reset();
cfg_dut();
start();
wait_for_end();
report();
endtask: run
task report();
$display("\n\n*************************************************");
if(0==$root.error)
$display("********TEST PASSED *********");
else
$display("********TEST Failed with %0d errors *********",$root.error);
$display("*************************************************\n\n");
endtask : report
endclass
èndif
Download the phase 7 score code:
switch_7.tar
Run the simulation:
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DPI
Index
Introduction
Specification
In this phase we will write the functional coverage for switch protocol. Functional Verification Plan
coverage is written in Coverage.sv file. After running simulation, you will analyze the Phase 1 Top
coverage results and find out if some test scenarios have not been exercised and write Phase 2 Environment
Phase 3 Reset
tests to exercise them.
Phase 4 Packet
Phase 5 Driver
The points which we need to cover are
Phase 6 Receiver
1) Cover all the port address configurations.
Phase 7 Scoreboard
2) Cover all the packet lengths.
Phase 8 Coverage
3) Cover all correct and incorrect length fields.
Phase 9 Testcase
4) Cover good and bad FCS.
5) Cover all the above combinations.
UVM Tutorial
1) Define a cover group with following cover points.
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PHASE 8 COVERAGE
a) All packet lengths:
Easy Labs : SV
length :coverpointpkt.length;
Easy Labs : UVM
b) All port address:
Easy Labs : OVM
da :coverpointpkt.da {
binsp0 ={`P0};
binsp1 ={`P1};
AVM Switch TB
binsp2 ={`P2};
VMM Ethernet sample binsp3 ={`P3};}
Easy Labs : VMM
Verilog
c) Correct and incorrect Length field types:
Verification
length_kind :coverpointpkt.length_kind;
Verilog Switch TB
d) Good and Bad FCS:
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
fcs_kind :coverpointpkt.fcs_kind;
5) Cross product of all the above cover points:
all_cross:crosslength,da,length_kind,fcs_kind;
2) In constructor method, construct the cover group
RVM Ethernet sample functionnew();
switch_coverage =new();
endfunction:new
Specman E
Interview Questions
3) Write task which calls the sample method to cover the points.
tasksample(packet pkt);
this.pkt =pkt;
switch_coverage.sample();
endtask:sample
Source Code Of Coverage Class:
ìfndefGUARD_COVERAGE
`defineGUARD_COVERAGE
http://testbench.in/SL_11_PHASE_8_COVERAGE.html[9/26/2012 2:29:37 PM]

input is what keeps
with time!
classcoverage;
packet pkt;
covergroupswitch_coverage;
binsp0 ={`P0};
binsp1 ={`P1};
binsp2 ={`P2};
binsp3 ={`P3};}
endgroup
functionnew();
endfunction:new
this.pkt =pkt;
endtask:sample
endclass
èndif
Now we will use this coverage class instance in scoreboard.
1) Take an instance of coverage class and construct it in scoreboard class.
coverage cov =new();
2) Call the sample method and pass the exp_pkt to the sample method.
cov.sample(pkt_exp);
Source Code Of The Scoreboard Class:
ìfndef GUARD_SCOREBOARD
`define GUARD_SCOREBOARD
class Scoreboard;
mailbox drvr2sb;
mailbox rcvr2sb;
coverage cov =new();
function new(mailbox drvr2sb,mailbox rcvr2sb);
this.drvr2sb = drvr2sb;
this.rcvr2sb = rcvr2sb;
endfunction:new
task start();
packet pkt_rcv,pkt_exp;
forever
begin
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver ",$time);
begin

cov.sample(pkt_exp);
end
else
$root.error++;
end
endtask : start
endclass
èndif
switch_8.tar
Run the simulation:
urg -dir simv.cm
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Verification Plan
In this phase we will write a constraint random testcase.
Phase 1 Top
Lets verify the DUT by sending large packets of length above 200.
Phase 2 Environment
Phase 3 Reset
1) In testcase file, define a small_packet class.
This calls is inherited from the packet class and data.size() field is constraint to Phase 4 Packet
Phase 5 Driver
generate the packet with size greater than 200.
Phase 6 Receiver
Phase 7 Scoreboard
Phase 8 Coverage
classsmall_packet extendspacket;
Phase 9 Testcase
constraintsmall_c {data.size>200;}

endclass
PHASE 9 TESTCASE
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Easy Labs : SV
2) In program block, create an object of the small_packet class.

Then call the build method of env.
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small_packet spkt;
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AVM Switch TB
input is what keeps

with time!
3) Pass the object of the small_packet to the packet handle which is in driver.
env.drvr.gpkt =spkt;
VMM Ethernet sample Then call the reset(),cfg_dut(),start(),wait_for_end() and report() methods as in the
run method.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
env.reset();
env.cfg_dut();
env.start();
env.wait_for_end();
env.report();
Source Code Of Constraint Testcase:

RVM Ethernet sample classsmall_packet extendspacket;
Specman E
Interview Questions
constraintsmall_c {data.size>200;}
endclass
]);
Environment env;
small_packet spkt;
initial
begin
spkt =new();
http://testbench.in/SL_12_PHASE_9_TESTCASE.html[9/26/2012 2:29:48 PM]
env.build();
env.drvr.gpkt =spkt;
env.reset();
env.cfg_dut();
env.start();
env.wait_for_end();
env.report();
#1000;
end
final
endprogram
èndif
switch_9.tar
Run the simulation:
urg -dir simv.cm
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Search
DPI
Index
Introduction
Specification
In this tutorial, we will verify the Switch RTL core using UVM in SystemVerilog. Verification Plan
Phase 1 Top
Following are the steps we follow to verify the Switch RTL core.
Testcase
Phase 4 Packet
Phase 5 Sequencer N
3) Building the Verification Environment. We will build the Environment in Multiple Sequence
Phase 6 Driver
In this verification environment, I will not use agents and monitors to make this Phase 7 Receiver
Phase 8 Scoreboard
tutorial simple and easy.
UVM Tutorial
Phase 1) We will develop the interfaces, and connect it to DUT in top module.
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AVM Switch TB
INTRODUCTION

input is what keeps
Phase 2) We will develop the Configuration class.
Phase 3) We will develop the Environment class and Simple testcase and simulate with time!
them.
Phase 4) We will develop packet class based on the stimulus plan. We will also write
a small code to test the packet class implementation.
Phase 5) We will develop sequencer and a sample sequences.
VMM Ethernet sample Phase 6) We will develop driver and connect it to the Sequencer in to environment.
Verilog
Verification
Verilog Switch TB
Phase 7) We will develop receiver and instantiate in environment.

Phase 8) We will develop scoreboard which does the comparison of the expected
packet with the actual packet received from the DUT and connect it to driver and
receiver in Environment class.
Basic Constructs
OpenVera
Constructs
Installing Uvm Library
Switch TB
RVM Switch TB
RVM Ethernet sample 1)Go tohttp://www.accellera.org/activities/vip/
Specman E
Interview Questions
2)Download the uvm*.tar.gz file.

3)Untar the file.
4)Go to the extracted directory: cd uvm*\uvm\src
5)Set the UVM_HOME path:setenv UVM_HOME `pwd`
(This is required to run the examples which are downloaded from this site)
6)Go to examples :cd../examples/hello_world/uvm/
7)Compile the example using:
your_tool_compilation_command -f compile_<toolname>.f
(example for questasim use :qverilog -f compile_questa.f)
8)Run the example.
http://testbench.in/UL_01_INTRODUCTION.html[9/26/2012 2:29:56 PM]
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packet which comes from the input port to output ports based on the address Phase 2 Configuration
Testcase
The switch has a one input port from which the packet enters. It has four output ports Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
SPECIFICATION

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
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Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
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Packet Format:
bytes.
Packet header:
Length: Length of the data is of 8 bits and from 0 to 255. Length is measured in
terms of bytes.
http://testbench.in/UL_02_SPECIFICATION.html[9/26/2012 2:30:04 PM]

and data.
Configuration:
signal.
MEMORY INTERFACE:
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
signal.

INPUT PORT
signal.
input[7:0]data;
inputdata_status;
1.
2.
3.
4.

OUTPUT PORT
Signal list is
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
outputready_0;
outputready_1;
outputready_2;
outputready_3;
input read_0;
input read_1;
input read_2;
input read_3;
RTLcode:
files.
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Index
Introduction
Specification
Overview
Verification Plan
based on System Verilog Hardware Verification Language. The methodology used for Phase 2 Configuration
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Feature Extraction
Sequence
Phase 6 Driver
Phase 7 Receiver
1)
Phase 8 Scoreboard
ID:Configuration
VERIFICATION PLAN

2)
input is what keeps
ID: Packet DA
Description: DA field of packet should be any of the port address. All the 4 port Testbench.in improving
with time!
3)
ID : Packet payload
4)
ID: Length
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
5)
ID: FCS
Description:
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/UL_03_VERIFICATION_PLAN.html[9/26/2012 2:30:16 PM]
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Index
Introduction
Specification
In phase 1,
Verification Plan
1) We will write SystemVerilog Interfaces for input port, output port and memory Phase 1 Top
port.
Testcase
3) DUT and interfaces are connected in top module.
Phase 4 Packet
4) We will implement Clock generator in top module.
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Interface
Phase 8 Scoreboard
All the signals in interface are wire type.
input is what keeps
PHASE 1 TOP
This approach will avoid race conditions between the design and the verification with time!
environment.
Define the set-up and hold time using parameters.
Easy Labs : VMM

AVM Switch TB
Interface Source Code
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
//////////////////////////////////////////
//////////////////////////////////////////
OpenVera
Constructs
parametersetup_time =5ns;
parameterhold_time =3ns;
Switch TB
wire[7:0]mem_data;
wire[1:0]mem_add;
RVM Ethernet sample wire mem_en;
wire mem_rd_wr;
Specman E
defaultinput#setup_time output#hold_time;
output mem_data;
Interview Questions
outputmem_add;
outputmem_en;
outputmem_rd_wr;
endclocking:cb
RVM Switch TB
endinterface:mem_interface
////////////////////////////////////////////
http://testbench.in/UL_04_PHASE_1_TOP.html[9/26/2012 2:30:26 PM]

////////////////////////////////////////////
wire data_status;
wire [7:0]data_in;
reg reset;
outputdata_status;
outputdata_in;
endclocking:cb
endinterface:input_interface
/////////////////////////////////////////////////
/////////////////////////////////////////////////
wire[7:0]data_out;
wireready;
wireread;
input data_out;
input ready;
outputread;
endclocking:cb
endinterface:output_interface
//////////////////////////////////////////////////
èndif
Top Module
This top-level module will contain the design portion of the simulation.
1) The first step is to import the uvm packages
ìnclude"uvm.svh"
importuvm_pkg::*;
bitClock;
initial
begin
#20;
end
5) Connect all the interfaces and DUT.The design which we have taken is in
Top module Scource Code
ìfndefGUARD_TOP
`defineGUARD_TOP
/////////////////////////////////////////////////////
// Importing UVM Packages//
/////////////////////////////////////////////////////
ìnclude"uvm.svh"
importuvm_pkg::*;
moduletop();
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
bitClock;
initial
begin
#20;
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////

/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
endmodule:top
èndif
Download the files:
uvm_switch_1.tar
Browse the code in uvm_switch_1.tar
Command to compile
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PHASE 2 CONFIGURATION
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In this phase we will implement the configuration class. All the requirements of the
testbench configurations will be declared inside this class. Virtual interfaces required
by verification components driver and receiver for connecting to DUT are declared in
this class. We will also declare 4 variables which will hold the port address of the
DUT.
uvm_object does not have the simulation phases and can be used in get_config_object
and set_config_object method. So we will implement the configuration class by
extending uvm_object.
Configuration
VMM Tutorial
1) Define configuration class by extending uvm_object
OVM Tutorial
Easy Labs : SV
ìfndefGUARD_CONFIGURATION
`defineGUARD_CONFIGURATION
Easy Labs : UVM
classConfiguration extendsuvm_object;
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
endclass:Configuration
èndif
VMM Ethernet sample 2) Declare All the interfaces which are required in this verification environment.
Verification
virtualinput_interface.IP input_intf;
Verilog Switch TB
3) Declare 4 variables which holds the device port address.
Verilog
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
bit[7:0]device_add[4];
4) uvm_object required to define the uvm_object::creat() method.
uvm_object::create method allocates a new object of the same type as this object
and returns it via a base uvm_object handle.
In create method, we have to construct a new object of configuration class and
update all the important fields and return it.
virtualfunctionuvm_object create(stringname="");
Configuration t =new();
t.device_add= this.device_add;
t.input_intf= this.input_intf;
t.mem_intf= this.mem_intf;
t.output_intf = this.output_intf;
returnt;
endfunction:create
Configuration class source code
http://testbench.in/UL_05_PHASE_2_CONFIGURATION.html[9/26/2012 2:30:34 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
classConfiguration extendsuvm_object;
bit[7:0]device_add[4];
virtualfunctionuvm_object create(stringname="");
t.device_add= this.device_add;
returnt;
endfunction:create
èndif
Updates To Top Module
In top module we will create an object of the above defined configuration class and
update the interfaces so that all the verification components can access to physical
interfaces in top module using configuration class object.
1) Declare a Configuration class object
Configuration cfg;
2) Construct the configuration object and update the interfaces.
initialbegin
cfg =new();
cfg.input_intf =input_intf;
cfg.mem_intf =mem_intf;
cfg.output_intf =output_intf;
3) In top module , we have to call the run_test() method.
run_test();
Top module updates
typedef class Configuration;
module top();
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
bit Clock;
initial
begin
#20;
forever #10 Clock = ~Clock;
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////

/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Creat Configuration and Strart the run_test//
/////////////////////////////////////////////////////
Configuration cfg;
initialbegin
cfg =new();
run_test();
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
endmodule : top
èndif
uvm_switch_2.tar
Command to compile
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PHASE 3 ENVIRONMENT N TESTCASE
SystemVerilog
Verification
Constructs
Interface
In the phase we will implement the skeleton for environment class.

We will declare virtual interfaces and Extend Required Environment class virtual
methods.
We will also implement a simple testcase and run the simulation.
OOPS
Randomization
Functional Coverage
Assertion
DPI
Environment class is used to implement verification environments in UVM. It is

extension on uvm_env class.The testbench simulation needs some systematic flow
like building the components, connection the components, starting the components
etc. uvm_env base class has methods formalize the simulation steps. All methods are
declared as virtual methods.

input is what keeps
with time!
UVM Tutorial
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
We will not implement all the uvm_env virtual methods in this phase but will we print
messages from these methods which are required for this example to understand the
simulation execution.
Testcase contains the instance of the environment class. This testcase Creates a
Environment object and defines the required test specific functionality.
Verification environment contains the declarations of the virtual interfaces. These

virtual interfaces are pointed to the physical interfaces which are declared in the top
RVM Ethernet sample module. These virtual interfaces are made to point to physical interface in the
testcase.
RVM Switch TB
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Environment
1) Extend uvm_env class to define Environment class.
ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsuvm_env;
endclass:Environment
èndif
http://testbench.in/UL_06_PHASE_3_ENVIRONMENT_N_TESTCASE.html[9/26/2012 2:30:42 PM]
2)Declare the utility macro. This utility macro provides the implementation of
create() and get_type_name() methods.
ùvm_component_utils(Environment)
3) Define the constructor. In the constructor, call the super methods and pass the
endfunction:new
4) Define build method. In build method, just print messages and super.build() must
be called. This method is automatically called.
Build is the first phase in simulation. This phase is used to construct the child
components of the current class.
super.build();
uvm_report_info(get_full_name(),"START of build ",UVM_LOW);
uvm_report_info(get_full_name(),"END of build ",UVM_LOW);
endfunction
5) Define connect method. In connect method, just print messages and
super.connect() must be called.
This method is called automatically after the build() method is called. This method is
used for connecting port and exports.
virtualfunctionvoidconnect();
super.connect();
uvm_report_info(get_full_name(),"START of connect ",UVM_LOW);
uvm_report_info(get_full_name(),"END of connect ",UVM_LOW);

endfunction
Environment class Source Code
ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsuvm_env;
endfunction:new
super.build();
endfunction
virtualfunctionvoidconnect();
super.connect();

endfunction
èndif
Testcase
Now we will implement testcase. In UVM, testcases are implemented by extending
uvm_test. Using uvm_test , provides the ability to select which test to execute using
the UVM_TESTNAME command line option or argument to the uvm_root::run_test task.
We will use UVM_TESTNAME command line argument.
1) Define a testcase by extending uvm_test class.
endclass
2)Declare the utility macro.
3) Take the instance of Environemtn.
Environment t_env ;
4) Define the constructor method.
In this method, construct the environment class object and dont forget to pass the
parent argument.
endfunction:new
5) Define run() method.
run() method is the only task which is time consuming. After completing the
start_of_simulation() phase , this method is called.
To terminate this task, we will use global_stop_request().
As we dont have anything now to write in this testcase, just call the
global_stop_request() after some delay.
virtualtaskrun ();
#3000ns;
endtask:run
With this, for the first time, we can do the simulation.
Testcase Source code
Environment t_env ;
endfunction:new
virtualtaskrun ();
#3000ns;
endtask:run
endclass:test1
Download the Source Code
uvm_switch_3.tar

Log report after simulation
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
UVM_INFO
@
@
@
@
@
0 [RNTST] Running test test1...

0: uvm_test_top.t_env [uvm_test_top.t_env]
START of build
END of build
START of connect
END of connect
--- UVM Report Summary --** Report counts by severity

UVM_INFO :5
UVM_WARNING :0
UVM_ERROR :0
UVM_FATAL :0
** Report counts by id
[RNTST ] 1
[uvm_test_top.t_env] 4
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PHASE 4 PACKET
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Verification
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In this Phase, we will develop Transaction as per the verification plan. We will define
required methods and constraints. We will also develop a small logic to test our
implementation of this class.
Packet
We will write the packet class in Packet.sv file. Packet class variables and constraints
One way to model Packet is by extending uvm_sequence_item. uvm_sequence_item
provides basic functionality for sequence items and sequences to operate in a
sequence mechanism. Packet class should be able to generate all possible packet
types randomly. To define copy, compare, record, print and sprint methods, we will
use UVM field macros. For packing and Unpacking, we will define the logic and not use
the fieldmacros.
Easy Labs : SV
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AVM Switch TB
VMM Ethernet sample
1) Define enumerated type data for fcs.

Verilog
Verification
Verilog Switch TB
Basic Constructs
2) Define transaction by extending uvm_sequence_item.
classPacket extendsuvm_sequence_item;
endclass:Packet
OpenVera
Constructs
3) Define all the fields as rand variables.
RVM Switch TB
randbit[7:0]length;
RVM Ethernet sample randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
Specman E
Switch TB
Interview Questions
4) Define constraints to constraint payload size of data.


http://testbench.in/UL_07_PHASE_4_PACKET.html[9/26/2012 2:30:50 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
super.new(name);
endfunction:new
6) In post_randomize() , define the fcs value based on fcs_kind.
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();
7) Define cal_fcs() method which computes the fcs value.
returnda ^sa ^length ^data.xor()^fcs;
endfunction:cal_fcs
8) Using uvm_field_* macros, define transaction required method.
We will define packing and unpacking methods manually, so use UVM_NOPACK for
excluding atomic creation of packing and un packing method.
9) Define do_pack() method which does the packing operation.
foreach(data[i])
endfunction:do_pack
10) Define do_unpack() method which does the unpacking operation.
intsz;
data.delete();
data=new[length];
foreach(data[i])
Packet class source code
ìfndefGUARD_PACKET
`defineGUARD_PACKET
ìnclude"uvm.svh"
importuvm_pkg::*;
classPacket extendsuvm_sequence_item;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
super.new(name);
endfunction:new
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();

returnda ^sa ^length ^data.xor()^fcs;
endfunction:cal_fcs
foreach(data[i])
endfunction:do_pack
intsz;
data.delete();
data=new[length];
foreach(data[i])
endclass:Packet
Test The Transaction Implementation
Now we will write a small logic to test our packet implantation. This module is not
used in normal verification.
Define a module and take the instance of packet class. Randomize the packet and call
the print method to analyze the generation. Then pack the packet in to bytes and
then unpack bytes and then call compare method to check all the method
implementation.
1) Declare Packet objects and dynamic arrays.

2) In a initial block, randomize the packet, pack the packet in to pkdbytes and then
unpack it and compare the packets.
if(pkt1.randomize)
begin
pkt1.print();
pkt2.print();
else
\n \n");
Logic to test the transaction implementation
moduletest;
initial
repeat(10)
if(pkt1.randomize)
begin
$display(" Randomization Successesfull.");
pkt1.print();
pkt2.print();
else
\n \n");
end
else
endmodule
uvm_switch_4.tar

---------------------------------------------------------------------pkt1 Packet-pkt1@3
--da integral8'ha5
--sa integral8'ha1
--length integral8 'h6
--data da(integral)6 ----[0]integral8'h58
----[1]integral8'h60
----[3]integral8'hdd
----[4]integral8 'h9
----[5]integral8'haf
--fcsintegral8'h75
---------------------------------------------------------------------Size of pkd bits10
---------------------------------------------------------------------pkt2 Packet-pkt2@5
--da integral8'ha5
--sa integral8'ha1
--fcsintegral8'h75
---------------------------------------------------------------------Packing,Unpacking and compare worked
....
....
....
....
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TUTORIALS
PHASE 5 SEQUENCER N SEQUENCE
SystemVerilog
In this phase we will develop Sequence and Sequencer.
Verification
Constructs
Interface
OOPS
Randomization
A sequence is series of transaction and sequencer is used to for controlling the flow of
transaction generation.
A sequence of transaction (which we already developed in previous phase) is defined
by extending uvm_sequence class. uvm_sequencer does the generation of this
sequence of transaction, uvm_driver takes the transaction from Sequencer and
processes the packet/ drives to other component or to DUT.
Functional Coverage
Assertion
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample Sequencer
Verilog
A Sequencer is defined by extending uvm_sequencer. uvm_sequencer has a port

seq_item_export which is used to connect to uvm_driver for transaction transfer.
Verification
Verilog Switch TB
1) Define a sequencer by extending uvm_sequence.
Basic Constructs
ìfndefGUARD_SEQUENCER
`defineGUARD_SEQUENCER
OpenVera
Constructs
Switch TB
RVM Switch TB
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
classSequencer extendsuvm_sequencer #(Packet);

endclass:Sequencer
èndif
RVM Ethernet sample 2) We need Device port address, which are in configuration class. So declare a
configuration class object.
Specman E
Configuration cfg;
Interview Questions
3) Declare Sequencer utility macros.

ùvm_sequencer_utils(Sequencer)
ùvm_update_sequence_lib_and_item(Packet)
endfunction:new
http://testbench.in/UL_08_PHASE_5_SEQUENCER_N_SEQUENCE.html[9/26/2012 2:30:58 PM]
5) In end_of_elaboration() method, using get_config_object(), get the configuration

object which will be passed from testcase.
get_config_object() returns object of type uvm_object, so using a temporary
uvm_object and cast it to configuration object.
virtualfunctionvoidend_of_elaboration();
uvm_object tmp;
assert(get_config_object("Configuration",tmp));
$cast(cfg,tmp);
endfunction
Sequencer source code
classSequencer extendsuvm_sequencer #(Packet);
Configuration cfg;
ùvm_sequencer_utils(Sequencer)
ùvm_update_sequence_lib_and_item(Packet)
endfunction:new
uvm_object tmp;
$cast(cfg,tmp);
endfunction
endclass:Sequencer
èndif
Sequence
A sequence is defined by extending uvm_sequence class. This sequence of transactions
should be defined in budy() method of uvm_sequence class. UVM has macros and
methods to define the transaction types. We will use macros in this example.
You can define as many sequences as you want. We will define 2 sequences.
1) Define sequence by extending
classSeq_device0_and_device1 extendsuvm_sequence #(Packet);
endclass:Seq_device0_and_device1
2) Define constructor method.
functionnew(stringname="Seq_do");
super.new(name);
endfunction:new
3) Declare utilities macro.With this macro, this sequence is tied to Sequencer.
ùvm_sequence_utils(Seq_device0_and_device1,Sequencer)
4) The algorithm for the transaction should be defined in body() method of the
sequence. In this sequence we will define the algorithm such that alternate
transactions for device port 0 and 1 are generated.
The device addresses are available in configuration object which is in sequencer.
Every sequence has a handle to its sequence through p_sequencer. Using p_sequencer
handle, access the device address.
virtualtaskbody();
foreverbegin
ùvm_do_with(item,{da ==p_sequencer.cfg.device_add[0];});
end
endtask:body
Sequence Source Code

classSeq_device0_and_device1 extendsuvm_sequence #(Packet);
functionnew(stringname="Seq_device0_and_device1");
super.new(name);
endfunction:new
Packet item;
ùvm_sequence_utils(Seq_device0_and_device1,Sequencer)
virtualtaskbody();
foreverbegin
end
endtask:body
One more Sequence
classSeq_constant_length extendsuvm_sequence #(Packet);
functionnew(stringname="Seq_constant_length");
super.new(name);
endfunction:new
Packet item;
ùvm_sequence_utils(Seq_constant_length,Sequencer)
virtualtaskbody();
foreverbegin
ùvm_do_with(item,{length ==10;da ==p_sequencer.cfg.device_add[0];});
end
endtask:body
endclass:Seq_constant_length
uvm_switch_5.tar
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TUTORIALS
PHASE 6 DRIVER
SystemVerilog
Driver
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
In this phase we will develop the driver. Driver is defined by extending uvm_driver.
Driver takes the transaction from the sequencer using seq_item_port. This transaction
will be driven to DUT as per the interface specification. After driving the transaction
to DUT, it sends the transaction to scoreboard using uvm_analysis_port.
In driver class, we will also define task for resetting DUT and configuring the DUT.
After completing the driver class implementation, we will instantiate it in
environment class and connect the sequencer to it. We will also update the test case
and run the simulation to check the implementation which we did till now.
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) Define the driver class by extending uvm_driver;

OpenVera
Constructs
Switch TB
RVM Switch TB
ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
classDriver extendsuvm_driver #(Packet);
RVM Ethernet sample endclass:Driver
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
2) Create a handle to configuration object. Using this object we can get DUT
interfaces and DUT port addresses.
Configuration cfg;
3) Declare input and memory interfaces
4) Declare uvm_analysis_port which is used to send packets to scoreboard.
uvm_analysis_port #(Packet)Drvr2Sb_port;
http://testbench.in/UL_09_PHASE_6_DRIVER.html[9/26/2012 2:31:07 PM]
5) Declare component utilities macro.

6) Define the constructor method. Pass the parent object to super class.
functionnew(stringname="",uvm_component parent =null);
super.new(name,parent );
endfunction:new
7) In the build method and construct Drvr2Sb_port object.
super.build();
Drvr2Sb_port =new("Drvr2Sb_port",this);
endfunction:build
8) In the end_of_elaboration() method, get the
get_config_object and update the virtual interfaces.
configuration
object using
uvm_object tmp;
super.end_of_elaboration();
$cast(cfg,tmp);
this.input_intf =cfg.input_intf;
this.mem_intf =cfg.mem_intf;
9) Define the reset_dut() method which will be used for resetting the DUT.
uvm_report_info(get_full_name(),"Start of reset_dut() method ",UVM_LOW);
mem_intf.mem_data<=0;
mem_intf.mem_add <=0;
mem_intf.mem_en<=0;
mem_intf.mem_rd_wr <=0;
input_intf.data_in <=0;
input_intf.data_status <=0;
uvm_report_info(get_full_name(),"End of reset_dut() method ",UVM_LOW);
endtask:reset_dut
10) Define the cfg_dut() method which does the configuration due port address.
uvm_report_info(get_full_name(),"Start of cfg_dut() method ",UVM_LOW);
@(mem_intf.cb);
foreach(cfg.device_add[i])begin
@(mem_intf.cb);
mem_intf.cb.mem_add<=i;
mem_intf.cb.mem_data <=cfg.device_add[i];
uvm_report_info(get_full_name(),$psprintf("
",i,cfg.device_add[i]),UVM_LOW);
end
@(mem_intf.cb);
Port
%0d
Address
%h
uvm_report_info(get_full_name(),"End of cfg_dut() method ",UVM_LOW);

endtask:cfg_dut
11) Define drive() method which will be used to drive the packet to DUT. In this
method pack the packet fields using the pack_bytes() method of the transaction and
drive the packed data to DUT interface.
virtualtaskdrive(Packet pkt);
byteunsignedbytes[];
intpkt_len;
pkt_len =pkt.pack_bytes(bytes);
uvm_report_info(get_full_name(),"Driving packet ...",UVM_LOW);
foreach(bytes[i])
begin
@(input_intf.cb);
input_intf.data_in <=bytes[i];
end
@(input_intf.cb);
repeat(2)@(input_intf.cb);
endtask:drive
12) Now we will use the above 3 defined methods and update the run() method of
uvm_driver.
First call the reset_dut() method and then cfg_dut(). After completing the
configuration, in a forever loop get the transaction from seq_item_port and send it
DUT using drive() method and also to scoreboard using Drvr2SB_port .
virtualtaskrun();
Packet pkt;
@(input_intf.cb);
reset_dut();
cfg_dut();
foreverbegin
seq_item_port.get_next_item(pkt);
Drvr2Sb_port.write(pkt);
@(input_intf.cb);
drive(pkt);
@(input_intf.cb);
end
endtask:run
Driver class source code
ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
classDriver extendsuvm_driver #(Packet);
Configuration cfg;
uvm_analysis_port #(Packet)Drvr2Sb_port;
functionnew(stringname="",uvm_component parent =null);

endfunction:new
super.build();
Drvr2Sb_port =new("Drvr2Sb",this);
endfunction:build
uvm_object tmp;
$cast(cfg,tmp);
virtualtaskrun();
Packet pkt;
@(input_intf.cb);
reset_dut();
cfg_dut();
foreverbegin
@(input_intf.cb);
drive(pkt);
@(input_intf.cb);
end
endtask:run
uvm_report_info(get_full_name(),"Start of reset_dut() method ",UVM_LOW);
mem_intf.mem_en<=0;
uvm_report_info(get_full_name(),"End of reset_dut() method ",UVM_LOW);

endtask:reset_dut
uvm_report_info(get_full_name(),"Start of cfg_dut() method ",UVM_LOW);
@(mem_intf.cb);
foreach(cfg.device_add[i])begin
@(mem_intf.cb);
mem_intf.cb.mem_add<=i;
mem_intf.cb.mem_data <=cfg.device_add[i];
uvm_report_info(get_full_name(),$psprintf("
Port
%0d
Address
",i,cfg.device_add[i]),UVM_LOW);
end
@(mem_intf.cb);
uvm_report_info(get_full_name(),"End of cfg_dut() method ",UVM_LOW);

endtask:cfg_dut
virtualtaskdrive(Packet pkt);
intpkt_len;
uvm_report_info(get_full_name(),"Driving packet ...",UVM_LOW);
%h
foreach(bytes[i])
begin
@(input_intf.cb);
end
@(input_intf.cb);
repeat(2)@(input_intf.cb);
endtask:drive
endclass:Driver
èndif
Environment Updates
We will take the instance of Sequencer and Driver and connect them in Environment
class.
1) Declare handles to Driver and Sequencer.

Sequencer Seqncr;
Driver Drvr;
2) In build method, construct Seqncr and Drvr object using create() method.
Drvr =Driver::type_id::create("Drvr",this);
Seqncr =Sequencer::type_id::create("Seqncr",this);
2) In connect()
seq_item_export.
method
connect
the
sequencer
seq_item_port
Drvr.seq_item_port.connect(Seqncr.seq_item_export);
Environment class code
ìfndef GUARD_ENV
`define GUARD_ENV
class Environment extends uvm_env;
Sequencer Seqncr;
Driver Drvr;
function new(string name , uvm_component parent = null);
super.new(name, parent);
endfunction: new
to drivers
virtual function void build();

super.build();
endfunction
virtual function void connect();

super.connect();
endfunction
endclass : Environment
èndif
Testcase Updates
We will update the testcase and run the simulation.
1)In the build() method, update the configuration address in the configuration object
which in top module.
super.build();
cfg.device_add[0]=0;
2) In the build() method itself, using set_config_object , configure the configuration
object with the one which is in top module.
with this, the configuration object in Sequencer and Driver will be pointing to the
one which in top module.
set_config_object("t_env.*","Configuration",cfg);
3) In the build method, using set_config_string, configure the default_sequence of the
sequencer to use the sequence which we defined.
set_config_string("*.Seqncr","default_sequence","Seq_device0_and_device1");
4) Set the sequencer count value to 2 .
set_config_int("*.Seqncr","count",2);
5) Update the run() method to print the Sequencer details.
t_env.Seqncr.print();
Testcase code
class test1 extends uvm_test;
Environment t_env ;
function new (string name="test1", uvm_component parent=null);
super.new (name, parent);
t_env = new("t_env",this);
endfunction : new
super.build();
endfunction
virtual task run ();
#3000ns;
endtask : run
endclass : test1
uvm_switch_6.tar
UVM_INFO @ 0 [RNTST] Running test test1...
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] START of build
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] END of build
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] START of connect
UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] END of connect
---------------------------------------------------------------------Seqncr Sequencer - Seqncr@14
--rsp_export uvm_analysis_export - rsp_export@16
--seq_item_exportuvm_seq_item_pull_+ -seq_item_export@40
--default_sequence string19uvm_random_sequence
--countintegral32 -1
--max_random_count integral32 'd10
--sequencesarray 5 ----[0]string19uvm_random_sequence
----[1]string23 uvm_exhaustive_sequ+
----[2]string19uvm_simple_sequence
----[3]string23 Seq_device0_and_dev+
----[4]string19Seq_constant_length
--max_random_depth integral32'd4
--num_last_reqsintegral32'd1
--num_last_rspsintegral32'd1
---------------------------------------------------------------------UVM_INFO @ 30: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
UVM_INFO @ 70: uvm_test_top.t_env.Drvr [uvm_test_top.t_env.Drvr]
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
UVM_INFO @ 190: uvm_test_top.t_env.Drvr
Driving packet ...
Driving packet ...
Driving packet ...
[uvm_test_top.t_env.Drvr]

UVM_INFO : 16
UVM_WARNING :0
UVM_ERROR :0
UVM_FATAL :0
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Index
Introduction
Specification
Phase 1 Top
Receiver
Testcase
Receiver collects the data bytes from the interface signal. And then unpacks the bytes Phase 4 Packet
in to packet using unpack_bytes method and pushes it into Rcvr2Sb_port for score Phase 5 Sequencer N
Sequence
boarding.
Phase 6 Driver
Phase 7 Receiver
Receiver class is written in Reveicer.sv file.
Phase 8 Scoreboard
Receiver class is defined by extending uvm_component class. It will drive the received
transaction to scoreboard using uvm_analysis_port.
PHASE 7 RECEIVER

input is what keeps
with time!
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
1) Define Receiver class by extending uvm_component.
Switch TB
RVM Switch TB
classReceiver extendsuvm_component;
RVM Ethernet sample
Specman E
Interview Questions
endclass:Receiver
èndif
2) Declare configuration class object.
Configuration cfg;
3) Declare an integer to hold the receiver number.
integerid;
4) Declare a virtual interface of dut out put side.
http://testbench.in/UL_10_PHASE_7_RECEIVER.html[9/26/2012 2:31:16 PM]
5) Declare analysis port which is used by receiver to send the received transaction to
scoreboard.
uvm_analysis_port #(Packet)Rcvr2Sb_port;
6) Declare the utility macro. This utility macro provides the implementation of creat()
and get_type_name() methods.
ùvm_component_utils(Receiver)
endfunction:new
8) Define the build method and construct the Rcvr2Sb_port.
super.build();
Rcvr2Sb_port =new("Rcvr2Sb",this);
endfunction:build
configuration
object using
uvm_object tmp;
$cast(cfg,tmp);
output_intf =cfg.output_intf[id];
10) Define the run() method. This method collects the packets from the DUT output
interface and unpacks it into high level transaction using transactions unpack_bytes()
method.
virtualtaskrun();
Packet pkt;
fork
forever
begin
// declare the queue and dynamic array here
// so they are automatically allocated for every packet
bit[7:0]bq[$],bytes[];
begin
bq.push_back(output_intf.cb.data_out);
end
bytes =new[bq.size()](bq);// Copy queue into dyn array
uvm_report_info(get_full_name(),"Received packet ...",UVM_LOW);
pkt =new();
void'(pkt.unpack_bytes(bytes));
Rcvr2Sb_port.write(pkt);
end
join
endtask:run
Receiver class source code

classReceiver extendsuvm_component;
Configuration cfg;
integerid;
uvm_analysis_port #(Packet)Rcvr2Sb_port;
ùvm_component_utils(Receiver)
endfunction:new
super.build();
endfunction:build
uvm_object tmp;
$cast(cfg,tmp);
virtualtaskrun();
Packet pkt;
fork
forever
begin
// declare the queue and dynamic array here
// so they are automatically allocated for every packet
bit[7:0]bq[$],bytes[];
begin
bq.push_back(output_intf.cb.data_out);
end
bytes =new[bq.size()](bq);// Copy queue into dyn array
uvm_report_info(get_full_name(),"Received packet ...",UVM_LOW);
pkt =new();
void'(pkt.unpack_bytes(bytes));
end
join
endtask:run
endclass:Receiver
Environment Class Updates
We will update the Environment class and take instance of receiver and run the
testcase.
1) Declare 4 receivers.
Receiver Rcvr[4];
2) In the build() method construct the Receivers using create() methods. Also update
the id variable of the receiver object.
foreach(Rcvr[i])begin
Rcvr[i] =Receiver::type_id::create($psprintf("Rcvr%0d",i),this);
Rcvr[i].id =i;
end
Environment class source code
ìfndef GUARD_ENV
`define GUARD_ENV
Sequencer Seqncr;
Driver Drvr;
Receiver Rcvr[4];
endfunction: new
super.build();
Drvr = Driver::type_id::create("Drvr",this);
Seqncr = Sequencer::type_id::create("Seqncr",this);
Rcvr[i].id =i;
end
endfunction

super.connect();
endfunction
èndif
uvm_switch_7.tar
--rsp_export uvm_analysis_export - rsp_export@16
--seq_item_exportuvm_seq_item_pull_+ -seq_item_export@40
--default_sequence string19uvm_random_sequence
--sequencesarray 5 ----[0]string19uvm_random_sequence
----[1]string23 uvm_exhaustive_sequ+
----[2]string19uvm_simple_sequence
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
Driving packet ...
Driving packet ...
UVM_INFO @ 610: uvm_test_top.t_env.Rcvr0 [uvm_test_top.t_env.Rcvr0]
Received packet ...
Driving packet ...
Received packet ...
UVM_INFO : 18
UVM_WARNING :0
UVM_ERROR :0
UVM_FATAL :0
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TUTORIALS
PHASE 8 SCOREBOARD
SystemVerilog
Verification
Constructs
Scoreboard
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Scoreboard is implemented by extending uvm_scorboard. For our requirement, we can

use uvm_in_order_comparator, but we will see develop our own scoreboard by
extending uvm_scorboard. Scoreboard has 2 analysis imports. One is used to for
getting the packets from the driver and other from the receiver.Then the packets
are compared and if they don't match, then error is asserted. For comparison,
compare () method of the Packet class is used.
Implement the scoreboard in file Scoreboard.sv.
Steps to create a scoreboard:
1)
Useing
macro
ùvm_analysis_imp_decl(<_portname>),
to
declare
uvm_analysis_imp_<_portname>class.
2) The above macro, creates write_<_portname>(). This method has to be define as
per our requirements.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
1) We need 2 import, one for expected packet which is sent by driver and received
packet which is coming from receiver.
Declare 2 imports using ùvm_analysis_imp_decl macros should not be defined
inside the class.
ùvm_analysis_imp_decl(_rcvd_pkt)
ùvm_analysis_imp_decl(_sent_pkt)
RVM Ethernet sample 2) Declare a scoreboard by extending uvm_scoreboard class.
classScoreboard extendsuvm_scoreboard;
Specman E
Interview Questions
endclass:Scoreboard
ùvm_component_utils(Scoreboard)
4) Declare a queue which stores the expected packets.
Packet exp_que[$];
5) Declare imports for getting expected packets and received packets.
http://testbench.in/UL_11_PHASE_8_SCOREBOARD.html[9/26/2012 2:31:24 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
uvm_analysis_imp_rcvd_pkt #(Packet,Scoreboard)Rcvr2Sb_port;
uvm_analysis_imp_sent_pkt #(Packet,Scoreboard)Drvr2Sb_port;
6) In the constructor, create objects for the above two declared imports.
endfunction:new
7)
Define
write_sent_pkt()
method
which
was
created
ùvm_analysis_imp_decl(_sent_pkt).
In this method, store the received packet in the expected queue.
by
macro
8)
Define
write_rcvd_pkt()
method
which
was
created
by
In this method, get the transaction from the expected queue and compare.
macro
virtualfunctionvoidwrite_sent_pkt(inputPacket pkt);
exp_que.push_back(pkt);
endfunction:write_sent_pkt
virtualfunctionvoidwrite_rcvd_pkt(inputPacket pkt);
Packet exp_pkt;
pkt.print();
if(exp_que.size())
begin
exp_pkt =exp_que.pop_front();
exp_pkt.print();
if(pkt.compare(exp_pkt))
uvm_report_info(get_type_name(),
$psprintf("Sent packet and received packet matched"),UVM_LOW);
else
uvm_report_error(get_type_name(),
$psprintf("Sent packet and received packet mismatched"),UVM_LOW);
end
else
$psprintf("No more packets in the expected queue to compare"),UVM_LOW);
endfunction:write_rcvd_pkt
9) Define the report() method to print the Scoreboard information.
virtualfunctionvoidreport();
$psprintf("Scoreboard Report %s",this.sprint()),UVM_LOW);
endfunction:report
Complete Scoreboard Code
ùvm_analysis_imp_decl(_sent_pkt)
classScoreboard extendsuvm_scoreboard;
ùvm_component_utils(Scoreboard)
Packet exp_que[$];
uvm_analysis_imp_rcvd_pkt #(Packet,Scoreboard)Rcvr2Sb_port;
uvm_analysis_imp_sent_pkt #(Packet,Scoreboard)Drvr2Sb_port;
endfunction:new
Packet exp_pkt;
pkt.print();
if(exp_que.size())
begin
exp_pkt.print();
$psprintf("Sent packet and received packet matched"),UVM_LOW);
else
$psprintf("Sent packet and received packet mismatched"),UVM_LOW);
end
else
$psprintf("No more packets
to in the expected
queue
compare"),UVM_LOW);
$psprintf("Scoreboard Report %s",this.sprint()),UVM_LOW);
endfunction:report
endclass:Scoreboard
èndif
to

We will take the instance of scoreboard in the environment and connect its ports to
driver and receiver ports.
1) Declare scoreboard object.

Scoreboard Sbd;
2) Construct the scoreboard object using create() method in build() method.
Sbd =Scoreboard::type_id::create("Sbd",this);
3) In connect() method, connect the driver and receiver ports to scoreboard.
Drvr.Drvr2Sb_port.connect(Sbd.Drvr2Sb_port);
foreach(Rcvr[i])
Rcvr[i].Rcvr2Sb_port.connect(Sbd.Rcvr2Sb_port);
Environemnt class code
ìfndef GUARD_ENV
`define GUARD_ENV
Sequencer Seqncr;
Driver Drvr;
Receiver Rcvr[4];
Scoreboard Sbd;
endfunction: new
super.build();
foreach(Rcvr[i]) begin
Rcvr[i] = Receiver::type_id::create($psprintf("Rcvr%0d",i),this);
Rcvr[i].id = i;
end
endfunction

super.connect();
foreach(Rcvr[i])
Rcvr[i].Rcvr2Sb_port.connect(Sbd.Rcvr2Sb_port);
endfunction
èndif
uvm_switch_8.tar
rsp_export uvm_analysis_export - rsp_export@16
seq_item_exportuvm_seq_item_pull_+ -seq_item_export@40
default_sequence string19uvm_random_sequence
countintegral32 -1
sequencesarray 5 [0]string19uvm_random_sequence
[1]string23 uvm_exhaustive_sequ+
[2]string19uvm_simple_sequence
[3]string23 Seq_device0_and_dev+
[4]string19Seq_constant_length
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
Driving packet ...
Driving packet ...
Received packet ...
UVM_INFO @ 610: uvm_test_top.t_env.Sbd [Scoreboard]
Sent packet and received packet matched
Driving packet ...
Received packet ...
Sent packet and received packet matched
Scoreboard Report
---------------------------------------------------------------------SbdScoreboard-Sbd@52
Drvr2Sbuvm_analysis_imp_s+ -Drvr2Sb@56
Rcvr2Sbuvm_analysis_imp_r+ -Rcvr2Sb@54
------------------------------------------------------------------------ UVM Report Summary --** Report counts by severity
UVM_INFO : 21
UVM_WARNING :0
UVM_ERROR :0
UVM_FATAL :0
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DPI
Index
Introduction
Specification
In this tutorial, we will verify the Switch RTL core using OVM in SystemVerilog. Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
3) Building the Verification Environment. We will build the Environment in Multiple Sequence
Phase 6 Driver
In this verification environment, I will not use agents and monitors to make this Phase 7 Receiver
Phase 8 Scoreboard
tutorial simple and easy.
UVM Tutorial
Phase 1) We will develop the interfaces, and connect it to DUT in top module.
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
INTRODUCTION

input is what keeps
Phase 2) We will develop the Configuration class.
Phase 3) We will develop the Environment class and Simple testcase and simulate with time!
them.
Phase 4) We will develop packet class based on the stimulus plan. We will also write
a small code to test the packet class implementation.
Phase 5) We will develop sequencer and a sample sequences.
VMM Ethernet sample Phase 6) We will develop driver and connect it to the Sequencer in to environment.
Verilog
Verification
Verilog Switch TB
Phase 7) We will develop receiver and instantiate in environment.

Phase 8) We will develop scoreboard which does the comparison of the expected
packet with the actual packet received from the DUT and connect it to driver and
receiver in Environment class.
Basic Constructs
OpenVera
Constructs
I would like to thank to Vishnu Prashant(Vitesse) for teaching me OVM.
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CM_01_INTRODUCTION.html[9/26/2012 2:31:33 PM]
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TUTORIALS
SystemVerilog
Verification
Constructs
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DPI
Index
Introduction
Specification
Verification Plan
packet which comes from the input port to output ports based on the address Phase 2 Configuration
Testcase
The switch has a one input port from which the packet enters. It has four output ports Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
SPECIFICATION

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Packet Format:
bytes.
Packet header:
Length: Length of the data is of 8 bits and from 0 to 255. Length is measured in
terms of bytes.
http://testbench.in/CM_02_SPECIFICATION.html[9/26/2012 2:31:40 PM]

and data.
Configuration:
signal.
MEMORY INTERFACE:
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
signal.

INPUT PORT
signal.
input[7:0]data;
inputdata_status;
1.
2.
3.
4.

OUTPUT PORT
Signal list is
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
RTLcode:
files.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Index
Introduction
Specification
Overview
Verification Plan
based on System Verilog Hardware Verification Language. The methodology used for Phase 2 Configuration
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Feature Extraction
Sequence
Phase 6 Driver
Phase 7 Receiver
1)
Phase 8 Scoreboard
ID:Configuration
VERIFICATION PLAN

2)
input is what keeps
ID: Packet DA
Description: DA field of packet should be any of the port address. All the 4 port Testbench.in improving
with time!
3)
ID : Packet payload
4)
ID: Length
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
5)
ID: FCS
Description:
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/CM_03_VERIFICATION_PLAN.html[9/26/2012 2:31:48 PM]
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Index
Introduction
Specification
In phase 1,
Verification Plan
1) We will write SystemVerilog Interfaces for input port, output port and memory Phase 1 Top
port.
Testcase
3) DUT and interfaces are connected in top module.
Phase 4 Packet
4) We will implement Clock generator in top module.
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Interface
Phase 8 Scoreboard
input is what keeps
PHASE 1 TOP
This approach will avoid race conditions between the design and the verification with time!
environment.
Easy Labs : VMM

AVM Switch TB
Interface Source Code
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
//////////////////////////////////////////
//////////////////////////////////////////
OpenVera
Constructs
Switch TB
wire[7:0]mem_data;
wire[1:0]mem_add;
RVM Ethernet sample wire mem_en;
wire mem_rd_wr;
Specman E
output mem_data;
Interview Questions
outputmem_add;
outputmem_en;
outputmem_rd_wr;
endclocking:cb
RVM Switch TB
////////////////////////////////////////////
http://testbench.in/CM_04_PHASE_1_TOP.html[9/26/2012 2:31:56 PM]

////////////////////////////////////////////
wire data_status;
wire [7:0]data_in;
reg reset;
outputdata_status;
outputdata_in;
endclocking:cb
/////////////////////////////////////////////////
/////////////////////////////////////////////////
wire[7:0]data_out;
wireready;
wireread;
input data_out;
input ready;
outputread;
endclocking:cb
//////////////////////////////////////////////////
èndif
Top Module
1) The first step is to import the ovm packages
ìnclude"ovm.svh"
importovm_pkg::*;
bitClock;
initial
begin
#20;
end
5) Connect all the interfaces and DUT.The design which we have taken is in
Top module Scource Code
ìfndefGUARD_TOP
`defineGUARD_TOP
/////////////////////////////////////////////////////
// Importing OVM Packages//
/////////////////////////////////////////////////////
ìnclude"ovm.svh"
importovm_pkg::*;
typedefclassConfiguration;
moduletop();
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
bitClock;
initial
begin
#20;
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
endmodule:top
èndif
Download the files:
ovm_switch_1.tar
Browse the code in ovm_switch_1.tar
Command to compile
vcs -sverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv+incdir+. rtl.sv
interface.sv top.sv
qverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv+incdir+. rtl.sv
interface.sv top.sv
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TUTORIALS
PHASE 2 CONFIGURATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
In this phase we will implement the configuration class. All the requirements of the
testbench configurations will be declared inside this class. Virtual interfaces required
by verification components driver and receiver for connecting to DUT are declared in
this class. We will also declare 4 variables which will hold the port address of the
DUT.
ovm_object does not have the simulation phases and can be used in get_config_object
and set_config_object method. So we will implement the configuration class by
extending ovm_object.
Configuration
VMM Tutorial
1) Define configuration class by extending ovm_object
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
classConfiguration extendsovm_object;
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
èndif
VMM Ethernet sample 2) Declare All the interfaces which are required in this verification environment.
Verification
Verilog Switch TB
3) Declare 4 variables which holds the device port address.
Verilog
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
bit[7:0]device0_add
bit[7:0]device1_add
bit[7:0]device2_add
bit[7:0]device3_add
;
;
;
;
4) ovm_object required to define the ovm_object::creat() method.

ovm_object::create method allocates a new object of the same type as this object
and returns it via a base ovm_object handle.
In create method, we have to construct a new object of configuration class and
update all the important fields and return it.
virtualfunctionovm_object create(stringname="");
t.device0_add =this.device0_add;
returnt;
http://testbench.in/CM_05_PHASE_2_CONFIGURATION.html[9/26/2012 2:32:03 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
endfunction:create
Configuration class source code
classConfiguration extendsovm_object;
bit[7:0]device0_add
bit[7:0]device1_add
bit[7:0]device2_add
bit[7:0]device3_add
;
;
;
;
virtualfunctionovm_object create(stringname="");
returnt;
endfunction:create
èndif
Updates To Top Module
In top module we will create an object of the above defined configuration class and
update the interfaces so that all the verification components can access to physical
interfaces in top module using configuration class object.
1) Declare a Configuration class object
Configuration cfg;
2) Construct the configuration object and update the interfaces.
initialbegin
cfg =new();
3) In top module , we have to call the run_test() method.
run_test();
Top module updates
typedef class Configuration;
module top();
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
bit Clock;
initial
begin
#20;
forever #10 Clock = ~Clock;
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Creat Configuration and Strart the run_test//
/////////////////////////////////////////////////////
Configuration cfg;
initialbegin
cfg =new();
run_test();
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
endmodule : top
èndif
ovm_switch_2.tar
Command to compile
interface.sv top.sv
interface.sv top.sv
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TUTORIALS
PHASE 3 ENVIRONMENT N TESTCASE
SystemVerilog
Verification
Constructs
Interface
In the phase we will implement the skeleton for environment class.

We will declare virtual interfaces and Extend Required Environment class virtual
methods.
We will also implement a simple testcase and run the simulation.
OOPS
Randomization
Functional Coverage
Assertion
DPI
Environment class is used to implement verification environments in OVM. It is

extension on ovm_env class.The testbench simulation needs some systematic flow
like building the components, connection the components, starting the components
etc. ovm_env base class has methods formalize the simulation steps. All methods are
declared as virtual methods.

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
We will not implement all the ovm_env virtual methods in this phase but will we print
messages from these methods which are required for this example to understand the
simulation execution.
Testcase contains the instance of the environment class. This testcase Creates a
Environment object and defines the required test specific functionality.

RVM Ethernet sample module. These virtual interfaces are made to point to physical interface in the
testcase.
RVM Switch TB
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Environment
1) Extend ovm_env class to define Environment class.
ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsovm_env;
èndif
http://testbench.in/CM_06_PHASE_3_ENVIRONMENT_N_TESTCASE.html[9/26/2012 2:32:13 PM]
2)Declare the utility macro. This utility macro provides the implementation of
create() and get_type_name() methods.
òvm_component_utils(Environment)
3) Define the constructor. In the constructor, call the super methods and pass the
endfunction:new
4) Define build method. In build method, just print messages and super.build() must
be called. This method is automatically called.
Build is the first phase in simulation. This phase is used to construct the child
components of the current class.
super.build();
ovm_report_info(get_full_name(),"START of build ",OVM_LOW);
ovm_report_info(get_full_name(),"END of build ",OVM_LOW);
endfunction
5) Define connect method. In connect method, just print messages and
super.connect() must be called.
This method is called automatically after the build() method is called. This method is
used for connecting port and exports.
super.connect();
ovm_report_info(get_full_name(),"START of connect ",OVM_LOW);
ovm_report_info(get_full_name(),"END of connect ",OVM_LOW);

endfunction
Environment class Source Code
ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsovm_env;
endfunction:new
super.build();
endfunction
super.connect();

endfunction
èndif
Testcase
Now we will implement testcase. In OVM, testcases are implemented by extending
ovm_test. Using ovm_test , provides the ability to select which test to execute using
the OVM_TESTNAME command line option or argument to the ovm_root::run_test task.
We will use OVM_TESTNAME command line argument.
1) Define a testcase by extending ovm_test class.
endclass
3) Take the instance of Environemtn.
Environment t_env ;
In this method, construct the environment class object and dont forget to pass the
parent argument.
endfunction:new
5) Define run() method.
run() method is the only task which is time consuming. After completing the
start_of_simulation() phase , this method is called.
To terminate this task, we will use global_stop_request().
As we dont have anything now to write in this testcase, just call the
global_stop_request() after some delay.
taskrun ();
#1000;
endtask:run
With this, for the first time, we can do the simulation.
Testcase Source code
Environment t_env ;
endfunction:new
taskrun ();
#1000;
endtask:run
endclass:test1
ovm_switch_3.tar

interface.sv top.sv -R +OVM_TESTNAME=test1
OVM_INFO
OVM_INFO
OVM_INFO
OVM_INFO
OVM_INFO
@
@
@
@
@

0: ovm_test_top.t_env [ovm_test_top.t_env]
START of build
END of build
START of connect
END of connect
--- OVM Report Summary --** Report counts by severity

OVM_INFO :5
OVM_WARNING :0
OVM_ERROR :0
OVM_FATAL :0
** Report counts by id
[RNTST ] 1
[ovm_test_top.t_env] 4
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TUTORIALS
PHASE 4 PACKET
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
In this Phase, we will develop Transaction as per the verification plan. We will define
required methods and constraints. We will also develop a small logic to test our
implementation of this class.
Packet
One way to model Packet is by extending ovm_sequence_item. ovm_sequence_item
provides basic functionality for sequence items and sequences to operate in a
sequence mechanism. Packet class should be able to generate all possible packet
types randomly. To define copy, compare, record, print and sprint methods, we will
use OVM field macros. For packing and Unpacking, we will define the logic and not use
the fieldmacros.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
1) Define enumerated type data for fcs.

Verilog
Verification
Verilog Switch TB
Basic Constructs
2) Define transaction by extending ovm_sequence_item.
classPacket extendsovm_sequence_item;
endclass:Packet
OpenVera
Constructs
3) Define all the fields as rand variables.
RVM Switch TB
randbit[7:0]length;
RVM Ethernet sample randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
Specman E
Switch TB
Interview Questions
4) Define constraints to constraint payload size of data.


http://testbench.in/CM_07_PHASE_4_PACKET.html[9/26/2012 2:32:21 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
super.new(name);
endfunction:new
6) In post_randomize() , define the fcs value based on fcs_kind.
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();
7) Define cal_fcs() method which computes the fcs value.
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
8) Using ovm_field_* macros, define transaction required method.
We will define packing and unpacking methods manually, so use OVM_NOPACK for
excluding atomic creation of packing and un packing method.
9) Define do_pack() method which does the packing operation.
foreach(data[i])
endfunction:do_pack
10) Define do_unpack() method which does the unpacking operation.
intsz;
data.delete();
data=new[length];
foreach(data[i])
Packet class source code
ìfndefGUARD_PACKET
`defineGUARD_PACKET
ìnclude"ovm.svh"
importovm_pkg::*;
classPacket extendsovm_sequence_item;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
super.new(name);
endfunction:new
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();

integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
foreach(data[i])
endfunction:do_pack
intsz;
data.delete();
data=new[length];
foreach(data[i])
endclass:Packet
Test The Transaction Implementation
Now we will write a small logic to test our packet implantation. This module is not
used in normal verification.
Define a module and take the instance of packet class. Randomize the packet and call
the print method to analyze the generation. Then pack the packet in to bytes and
then unpack bytes and then call compare method to check all the method
implementation.
1) Declare Packet objects and dynamic arrays.

2) In a initial block, randomize the packet, pack the packet in to pkdbytes and then
unpack it and compare the packets.
if(pkt1.randomize)
begin
pkt1.print();
pkt2.print();
else
\n \n");
Logic to test the transaction implementation
moduletest;
initial
repeat(10)
if(pkt1.randomize)
begin
$display(" Randomization Successesfull.");
pkt1.print();
pkt2.print();
else
\n \n");
end
else
endmodule
ovm_switch_4.tar
vcs -sverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv-R Packet.sv
qverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv-R Packet.sv
---------------------------------------------------------------------pkt1 Packet-pkt1@3
--da integral8'ha5
--sa integral8'ha1
--fcsintegral8'h75
---------------------------------------------------------------------Size of pkd bits10
---------------------------------------------------------------------pkt2 Packet-pkt2@5
--da integral8'ha5
--sa integral8'ha1
--fcsintegral8'h75
---------------------------------------------------------------------Packing,Unpacking and compare worked
....
....
....
....
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TUTORIALS
PHASE 5 SEQUENCER N SEQUENCE
SystemVerilog
In this phase we will develop Sequence and Sequencer.
Verification
Constructs
Interface
OOPS
Randomization
A sequence is series of transaction and sequencer is used to for controlling the flow of
transaction generation.
A sequence of transaction (which we already developed in previous phase) is defined
by extending ovm_sequence class. ovm_sequencer does the generation of this
sequence of transaction, ovm_driver takes the transaction from Sequencer and
processes the packet/ drives to other component or to DUT.
Functional Coverage
Assertion
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample Sequencer
Verilog
A Sequencer is defined by extending ovm_sequencer. ovm_sequencer has a port

seq_item_export which is used to connect to ovm_driver for transaction transfer.
Verification
Verilog Switch TB
1) Define a sequencer by extending ovm_sequence.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
classSequencer extendsovm_sequencer #(Packet);

endclass:Sequencer
èndif
RVM Ethernet sample 2) We need Device port address, which are in configuration class. So declare a
configuration class object.
Specman E
Configuration cfg;
Interview Questions
3) Declare Sequencer utility macros.

òvm_sequencer_utils(Sequencer)
òvm_update_sequence_lib_and_item(Packet)
endfunction:new
http://testbench.in/CM_08_PHASE_5_SEQUENCER_N_SEQUENCE.html[9/26/2012 2:32:29 PM]
5) In end_of_elaboration() method, using get_config_object(), get the configuration

object which will be passed from testcase.
get_config_object() returns object of type ovm_object, so using a temporary
ovm_object and cast it to configuration object.
ovm_object tmp;
$cast(cfg,tmp);
endfunction
Sequencer source code
classSequencer extendsovm_sequencer #(Packet);
Configuration cfg;
òvm_sequencer_utils(Sequencer)
òvm_update_sequence_lib_and_item(Packet)
endfunction:new
ovm_object tmp;
$cast(cfg,tmp);
endfunction
endclass:Sequencer
èndif
Sequence
A sequence is defined by extending ovm_sequence class. This sequence of transactions
should be defined in budy() method of ovm_sequence class. OVM has macros and
methods to define the transaction types. We will use macros in this example.
You can define as many sequences as you want. We will define 2 sequences.
1) Define sequence by extending
classSeq_device0_and_device1 extendsovm_sequence #(Packet);
2) Define constructor method.
functionnew(stringname="Seq_do");
super.new(name);
endfunction:new
3) Declare utilities macro.With this macro, this sequence is tied to Sequencer.
òvm_sequence_utils(Seq_device0_and_device1,Sequencer)
4) The algorithm for the transaction should be defined in body() method of the
sequence. In this sequence we will define the algorithm such that alternate
transactions for device port 0 and 1 are generated.
The device addresses are available in configuration object which is in sequencer.
Every sequence has a handle to its sequence through p_sequencer. Using p_sequencer
handle, access the device address.
virtualtaskbody();
foreverbegin
òvm_do_with(item,{da ==p_sequencer.cfg.device0_add;});
end
endtask:body
Sequence Source Code

classSeq_device0_and_device1 extendsovm_sequence #(Packet);
functionnew(stringname="Seq_device0_and_device1");
super.new(name);
endfunction:new
Packet item;
òvm_sequence_utils(Seq_device0_and_device1,Sequencer)
virtualtaskbody();
foreverbegin
end
endtask:body
One more Sequence
classSeq_constant_length extendsovm_sequence #(Packet);
functionnew(stringname="Seq_constant_length");
super.new(name);
endfunction:new
Packet item;
òvm_sequence_utils(Seq_constant_length,Sequencer)
virtualtaskbody();
foreverbegin
òvm_do_with(item,{length ==10;da ==p_sequencer.cfg.device0_add;});
end
endtask:body
endclass:Seq_constant_length
ovm_switch_5.tar
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TUTORIALS
PHASE 6 DRIVER
SystemVerilog
Driver
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
In this phase we will develop the driver. Driver is defined by extending ovm_driver.
Driver takes the transaction from the sequencer using seq_item_port. This transaction
will be driven to DUT as per the interface specification. After driving the transaction
to DUT, it sends the transaction to scoreboard using ovm_analysis_port.
In driver class, we will also define task for resetting DUT and configuring the DUT.
After completing the driver class implementation, we will instantiate it in
environment class and connect the sequencer to it. We will also update the test case
and run the simulation to check the implementation which we did till now.
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) Define the driver class by extending ovm_driver;

OpenVera
Constructs
Switch TB
RVM Switch TB
ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
classDriver extendsovm_driver #(Packet);
RVM Ethernet sample endclass:Driver
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
2) Create a handle to configuration object. Using this object we can get DUT
interfaces and DUT port addresses.
Configuration cfg;
3) Declare input and memory interfaces
4) Declare ovm_analysis_port which is used to send packets to scoreboard.
ovm_analysis_port #(Packet)Drvr2Sb_port;
http://testbench.in/CM_09_PHASE_6_DRIVER.html[9/26/2012 2:32:38 PM]
5) Declare component utilities macro.

òvm_component_utils(Driver)
6) Define the constructor method. Pass the parent object to super class.
functionnew(stringname="",ovm_component parent =null);
endfunction:new
7) In the build method and construct Drvr2Sb_port object.
super.build();
Drvr2Sb_port =new("Drvr2Sb_port",this);
endfunction:build
configuration
object using
ovm_object tmp;
$cast(cfg,tmp);
9) Define the reset_dut() method which will be used for resetting the DUT.
ovm_report_info(get_full_name(),"Start of reset_dut() method ",OVM_LOW);
mem_intf.mem_en<=0;
ovm_report_info(get_full_name(),"End of reset_dut() method ",OVM_LOW);
endtask:reset_dut
10) Define the cfg_dut() method which does the configuration due port address.
ovm_report_info(get_full_name(),"Start of cfg_dut() method ",OVM_LOW);
mem_intf.mem_en <=1;
mem_intf.mem_add<=8'h0;
mem_intf.mem_data <=cfg.device0_add;
$psprintf(" Port 0 Address %h ",cfg.device0_add),OVM_LOW);
mem_intf.mem_en<=0;
ovm_report_info(get_full_name(),"End of cfg_dut() method ",OVM_LOW);
endtask:cfg_dut
11) Define drive() method which will be used to drive the packet to DUT. In this
method pack the packet fields using the pack_bytes() method of the transaction and
drive the packed data to DUT interface.
taskdrive(Packet pkt);
intpkt_len;
ovm_report_info(get_full_name(),"Driving packet ...",OVM_LOW);
foreach(bytes[i])
begin
end
endtask:drive
12) Now we will use the above 3 defined methods and update the run() method of
ovm_driver.
First call the reset_dut() method and then cfg_dut(). After completing the
configuration, in a forever loop get the transaction from seq_item_port and send it
DUT using drive() method and also to scoreboard using Drvr2SB_port .
taskrun();
Packet pkt;
reset_dut();
cfg_dut();
foreverbegin
drive(pkt);
end
endtask:run
Driver class source code
ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
classDriver extendsovm_driver #(Packet);
Configuration cfg;
ovm_analysis_port #(Packet)Drvr2Sb_port;
òvm_component_utils(Driver)
functionnew(stringname="",ovm_component parent =null);

endfunction:new
super.build();
endfunction:build
ovm_object tmp;
$cast(cfg,tmp);
taskrun();
Packet pkt;
reset_dut();
cfg_dut();
foreverbegin
drive(pkt);
end
endtask:run
ovm_report_info(get_full_name(),"Start of reset_dut() method ",OVM_LOW);
mem_intf.mem_en<=0;
ovm_report_info(get_full_name(),"End of reset_dut() method ",OVM_LOW);

endtask:reset_dut
ovm_report_info(get_full_name(),"Start of cfg_dut() method ",OVM_LOW);
mem_intf.mem_en <=1;
mem_intf.mem_en<=0;
ovm_report_info(get_full_name(),"End of cfg_dut() method ",OVM_LOW);

endtask:cfg_dut
intpkt_len;
ovm_report_info(get_full_name(),"Driving packet ...",OVM_LOW);
foreach(bytes[i])
begin
end
endtask:drive
endclass:Driver
èndif
Environment Updates
We will take the instance of Sequencer and Driver and connect them in Environment
class.
1) Declare handles to Driver and Sequencer.
Sequencer Seqncr;
Driver Drvr;
2) In build method, construct Seqncr and Drvr object using create() method.
2) In connect()
seq_item_export.
method
connect
the
sequencer
seq_item_port
to drivers
Environment class code
ìfndef GUARD_ENV
`define GUARD_ENV
class Environment extends ovm_env;
Sequencer Seqncr;
Driver Drvr;
function new(string name , ovm_component parent = null);
endfunction: new
super.build();
endfunction
function void connect();

super.connect();
endfunction
èndif
Testcase Updates
We will update the testcase and run the simulation.
1)In the build() method, update the configuration address in the configuration object
which in top module.
super.build();
cfg.device0_add
cfg.device1_add
cfg.device2_add
cfg.device3_add
=0;
=1;
=2;
=3;
2) In the build() method itself, using set_config_object , configure the configuration

object with the one which is in top module.
with this, the configuration object in Sequencer and Driver will be pointing to the
one which in top module.
3) In the build method, using set_config_string, configure the default_sequence of the

sequencer to use the sequence which we defined.
4) Set the sequencer count value to 2 .
5) Update the run() method to print the Sequencer details.
Testcase code
class test1 extends ovm_test;
Environment t_env ;
function new (string name="test1", ovm_component parent=null);
super.new (name, parent);
t_env = new("t_env",this);
endfunction : new
super.build();
cfg.device0_add =0;
cfg.device1_add =1;
cfg.device2_add =2;
cfg.device3_add =3;
endfunction
task run ();
#1000;
endtask : run
endclass : test1
ovm_switch_6.tar
vcs -sverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv +incdir+. rtl.sv
qverilog +incdir+$OVM_HOME/src $OVM_HOME/src/ovm_pkg.sv +incdir+. rtl.sv
OVM_INFO @ 0 [RNTST] Running test test1...
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] START of build
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] END of build
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] START of connect
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] END of connect

--rsp_export ovm_analysis_export - rsp_export@16
--seq_item_exportovm_seq_item_pull_+ -seq_item_export@40
--default_sequence string19ovm_random_sequence
--sequencesarray 5 ----[0]string19ovm_random_sequence
----[1]string23 ovm_exhaustive_sequ+
----[2]string19ovm_simple_sequence
---------------------------------------------------------------------OVM_INFO @ 30: ovm_test_top.t_env.Drvr [ovm_test_top.t_env.Drvr]
OVM_INFO @ 70: ovm_test_top.t_env.Drvr [ovm_test_top.t_env.Drvr]
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
Driving packet ...
Driving packet ...
Driving packet ...
OVM_INFO : 16
OVM_WARNING :0
OVM_ERROR :0
OVM_FATAL :0
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TUTORIALS
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Interface
OOPS
Randomization
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Assertion
DPI
UVM Tutorial
Index
Introduction
Specification
Phase 1 Top
Receiver
Testcase
Receiver collects the data bytes from the interface signal. And then unpacks the bytes Phase 4 Packet
in to packet using unpack_bytes method and pushes it into Rcvr2Sb_port for score Phase 5 Sequencer N
Sequence
boarding.
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Receiver class is defined by extending ovm_component class. It will drive the received
transaction to scoreboard using ovm_analysis_port.
PHASE 7 RECEIVER

input is what keeps
with time!
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
1) Define Receiver class by extending ovm_component.
Switch TB
RVM Switch TB
classReceiver extendsovm_component;
RVM Ethernet sample
Specman E
Interview Questions
endclass:Receiver
èndif
2) Declare configuration class object.
Configuration cfg;
3) Declare an integer to hold the receiver number.
integerid;
4) Declare a virtual interface of dut out put side.
http://testbench.in/CM_10_PHASE_7_RECEIVER.html[9/26/2012 2:32:47 PM]
5) Declare analysis port which is used by receiver to send the received transaction to
scoreboard.
ovm_analysis_port #(Packet)Rcvr2Sb_port;
6) Declare the utility macro. This utility macro provides the implementation of creat()
and get_type_name() methods.
òvm_component_utils(Receiver)
endfunction:new
8) Define the build method and construct the Rcvr2Sb_port.
super.build();
endfunction:build
configuration
object using
ovm_object tmp;
$cast(cfg,tmp);
10) Define the run() method. This method collects the packets from the DUT output
interface and unpacks it into high level transaction using transactions unpack_bytes()
method.
virtualtaskrun();
bit[7:0]bytes[];
Packet pkt;
fork
forever
begin
wait(output_intf.ready)
output_intf.read <=1;
while(output_intf.ready)
begin
bytes[bytes.size-1]=output_intf.data_out;
end
ovm_report_info(get_full_name(),"Received packet ...",OVM_LOW);
pkt =new();
pkt.unpack_bytes(bytes);
bytes.delete();
end
join
endtask:run
Receiver class source code

classReceiver extendsovm_component;
Configuration cfg;
integerid;
ovm_analysis_port #(Packet)Rcvr2Sb_port;
òvm_component_utils(Receiver)
endfunction:new
super.build();
endfunction:build
ovm_object tmp;
$cast(cfg,tmp);
virtualtaskrun();
bit[7:0]bytes[];
Packet pkt;
fork
forever
begin
wait(output_intf.ready)
while(output_intf.ready)
begin
bytes[bytes.size-1]=output_intf.data_out;
end
ovm_report_info(get_full_name(),"Received packet ...",OVM_LOW);
pkt =new();
pkt.unpack_bytes(bytes);
bytes.delete();
end
join
endtask:run
endclass:Receiver
We will update the Environment class and take instance of receiver and run the
testcase.
1) Declare 4 receivers.
Receiver Rcvr[4];
2) In the build() method construct the Receivers using create() methods. Also update
the id variable of the receiver object.
Rcvr[i].id =i;
end
Environment class source code
ìfndef GUARD_ENV
`define GUARD_ENV
Sequencer Seqncr;
Driver Drvr;
Receiver Rcvr[4];
endfunction: new
super.build();
Rcvr[i].id =i;
end
endfunction

super.connect();
endfunction
èndif
ovm_switch_7.tar

OVM_INFO @ 0 [RNTST] Running test test1...
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] START of build
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] END of build
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] START of connect
OVM_INFO @ 0: ovm_test_top.t_env [ovm_test_top.t_env] END of connect
--rsp_export ovm_analysis_export - rsp_export@16
--seq_item_exportovm_seq_item_pull_+ -seq_item_export@40
--default_sequence string19ovm_random_sequence
--sequencesarray 5 ----[0]string19ovm_random_sequence
----[1]string23 ovm_exhaustive_sequ+
----[2]string19ovm_simple_sequence
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
Driving packet ...
Driving packet ...
OVM_INFO @ 610: ovm_test_top.t_env.Rcvr0 [ovm_test_top.t_env.Rcvr0]
Received packet ...
Driving packet ...
Received packet ...
OVM_INFO : 18
OVM_WARNING :0
OVM_ERROR :0
OVM_FATAL :0
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TUTORIALS
PHASE 8 SCOREBOARD
SystemVerilog
Verification
Constructs
Scoreboard
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Scoreboard is implemented by extending ovm_scorboard. For our requirement, we can

use ovm_in_order_comparator, but we will see develop our own scoreboard by
extending ovm_scorboard. Scoreboard has 2 analysis imports. One is used to for
getting the packets from the driver and other from the receiver.Then the packets
are compared and if they don't match, then error is asserted. For comparison,
compare () method of the Packet class is used.
Implement the scoreboard in file Scoreboard.sv.
Steps to create a scoreboard:
1)
Useing
macro
òvm_analysis_imp_decl(<_portname>),
to
declare
ovm_analysis_imp_<_portname>class.
2) The above macro, creates write_<_portname>(). This method has to be define as
per our requirements.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) Declare a scoreboard by extending ovm_scoreboard class.

OpenVera
Constructs
Switch TB
classScoreboard extendsovm_scoreboard;
endclass:Scoreboard
2) We need 2 import, one for expected packet which is sent by driver and received
packet which is coming from receiver.
RVM Ethernet sample Declare 2 imports using òvm_analysis_imp_decl macros.
RVM Switch TB
Specman E
Interview Questions
òvm_analysis_imp_decl(_rcvd_pkt)
òvm_analysis_imp_decl(_sent_pkt)
òvm_component_utils(Scoreboard)
4) Declare a queue which stores the expected packets.
Packet exp_que[$];
5) Declare imports for getting expected packets and received packets.
ovm_analysis_imp_rcvd_pkt #(Packet,Scoreboard)Rcvr2Sb_port;
http://testbench.in/CM_11_PHASE_8_SCOREBOARD.html[9/26/2012 2:32:56 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Testcase
Phase 4 Packet
Phase 5 Sequencer N
Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
input is what keeps
with time!
ovm_analysis_imp_sent_pkt #(Packet,Scoreboard)Drvr2Sb_port;
6) In the constructor, create objects for the above two declared imports.
endfunction:new
7)
Define
write_sent_pkt()
method
which
was
created
òvm_analysis_imp_decl(_sent_pkt).
In this method, store the received packet in the expected queue.
by
macro
8)
Define
write_rcvd_pkt()
method
which
was
created
by
In this method, get the transaction from the expected queue and compare.
macro
Packet exp_pkt;
pkt.print();
if(exp_que.size())
begin
exp_pkt.print();
ovm_report_info(get_type_name(),
$psprintf("Sent packet and reeived packet mathed"),OVM_LOW);
else
ovm_report_error(get_type_name(),
$psprintf("Sent packet and reeived packet mismatched"),OVM_LOW);
end
else
$psprintf("No more packets in the expected queue to compare"),OVM_LOW);
9) Define the report() method to print the Scoreboard information.
$psprintf("Scoreboard Report %s",this.sprint()),OVM_LOW);
endfunction:report
Complete Scoreboard Code
òvm_analysis_imp_decl(_sent_pkt)
classScoreboard extendsovm_scoreboard;
òvm_component_utils(Scoreboard)
Packet exp_que[$];
ovm_analysis_imp_rcvd_pkt #(Packet,Scoreboard)Rcvr2Sb_port;
ovm_analysis_imp_sent_pkt #(Packet,Scoreboard)Drvr2Sb_port;
endfunction:new
Packet exp_pkt;
pkt.print();
if(exp_que.size())
begin
exp_pkt.print();
$psprintf("Sent packet and reeived packet mathed"),OVM_LOW);
else
$psprintf("Sent packet and reeived packet mismatched"),OVM_LOW);
end
else
$psprintf("No more packets
to in the expected
queue
compare"),OVM_LOW);
$psprintf("Scoreboard Report %s",this.sprint()),OVM_LOW);
endfunction:report
endclass:Scoreboard
èndif
to

We will take the instance of scoreboard in the environment and connect its ports to
driver and receiver ports.
1) Declare scoreboard object.

Scoreboard Sbd;
2) Construct the scoreboard object using create() method in build() method.
3) In connect() method, connect the driver and receiver ports to scoreboard.
Rcvr[0].Rcvr2Sb_port.connect(Sbd.Rcvr2Sb_port);
Environemnt class code
ìfndef GUARD_ENV
`define GUARD_ENV
Sequencer Seqncr;
Driver Drvr;
Receiver Rcvr[4];
Scoreboard Sbd;
endfunction: new
super.build();
foreach(Rcvr[i]) begin
Rcvr[i] = Receiver::type_id::create($psprintf("Rcvr%0d",i),this);
Rcvr[i].id = i;
end
endfunction

super.connect();
endfunction
èndif
ovm_switch_8.tar
OVM_INFO
OVM_INFO
OVM_INFO
OVM_INFO
OVM_INFO
@
@
@
@
@

START of build
END of build
START of connect
END of connect
rsp_export ovm_analysis_export - rsp_export@16
seq_item_exportovm_seq_item_pull_+ -seq_item_export@40
default_sequence string19ovm_random_sequence
countintegral32 -1
sequencesarray 5 [0]string19ovm_random_sequence
[1]string23 ovm_exhaustive_sequ+
[2]string19ovm_simple_sequence
[3]string23 Seq_device0_and_dev+
[4]string19Seq_constant_length
Port 0 Address 00
Port 1 Address 01
Port 2 Address 02
Port 3 Address 03
Driving packet ...
Driving packet ...
Received packet ...
OVM_INFO @ 610: ovm_test_top.t_env.Sbd [Scoreboard]
Sent packet and reeived packet mathed
Driving packet ...
Received packet ...
Sent packet and reeived packet mathed
Scoreboard Report
---------------------------------------------------------------------SbdScoreboard-Sbd@52
Drvr2Sbovm_analysis_imp_s+ -Drvr2Sb@56
Rcvr2Sbovm_analysis_imp_r+ -Rcvr2Sb@54
------------------------------------------------------------------------ OVM Report Summary --** Report counts by severity
OVM_INFO : 21
OVM_WARNING :0
OVM_ERROR :0
OVM_FATAL :0
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Index
Introduction
Specification
Verification Plan
Phase 1 Top
In this tutorial, we will verify the Switch RTL core using VMM in SystemVerilog. Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
3) Building the Verification Environment. We will build the Environment in Multiple Phase 9 Coverage
INTRODUCTION

Phase 1) We will develop the testcase and interfaces, and integrate them in these on This section - Your
input is what keeps
with the DUT in top module.
with time!
Phase 2) We will Develop the Environment class.
Phase 3) We will develop reset and configuration methods in Environment class.

Then using these methods, we will reset the DUT and configure the port address.
Phase 4) We will develop a packet class based on the stimulus plan. We will also
write a small code to test the packet class implementation.
Phase 5) We will create atomic generator in the environment class.
Phase 6) We will develop a driver class. Packets are taken from the generator and
sent to DUT using driver.
Phase 7) We will develop receiver class. Receiver collects the packets coming from
the output port of the DUT.
Phase 8) We will develop scoreboard class which does the comparison of the
expected packet with the actual packet received from the DUT.
Phase 9) We will develop coverage class based on the coverage plan. Coverage is
sampled using the driver callbacks.
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/VL_01_INTRODUCTION.html[9/26/2012 2:33:04 PM]
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http://testbench.in/VL_01_INTRODUCTION.html[9/26/2012 2:33:04 PM]
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Index
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Specification
Verification Plan
packet which comes from the input port to output ports based on the address Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
The switch has a one input port from which the packet enters. It has four output ports Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
SPECIFICATION
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Packet Format:
bytes.
Packet header:
Length: Length of the data is of 8 bits andfrom 0 to 255. Length is measured in terms
of bytes.
http://testbench.in/VL_02_SPECIFICATION.html[9/26/2012 2:33:13 PM]

and data.
Configuration:
signal.
MEMORY INTERFACE:
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
signal.

INPUT PORT
signal.
input[7:0]data;
inputdata_status;
1.
2.
3.
4.

OUTPUT PORT
Signal list is
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
RTLcode:
files.
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Index
Introduction
Specification
Overview
Verification Plan
based on System Verilog Hardware Verification Language. The methodology used for Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Feature Extraction
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
1)
ID:Configuration
VERIFICATION PLAN
input is what keeps

2)
ID: Packet DA
Description: DA field of packet should be any of the port address. All the 4 port with time!
3)
ID : Packet payload
4)
ID: Length
Send Packet with correct length field and incorrect length fields.
Verilog
5)
Verification
ID: FCS
Verilog Switch TB
Description:
Basic Constructs
AVM Switch TB
OpenVera
Constructs
1)
2)
RVM Switch TB
3)
RVM Ethernet sample 4)
Switch TB
Specman E
Interview Questions
Packet DA: Generate packet DA with the configured address.

Payload length: generate payload length ranging from 2 to 255.
Correct or Incorrect Length field.
Generate good and bad FCS.
Coverage Plan
1)Cover all the port address configurations.
2)Cover all the packet lengths.
3)Cover all correct and incorrect length fields.
4)Cover good and bad FCS.
5)Cover all the above combinations.
http://testbench.in/VL_03_VERIFICATION_PLAN.html[9/26/2012 2:33:22 PM]
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Index
Introduction
Specification
Verification Plan
In phase 1,
Phase 1 Top
1) We will write SystemVerilog Interfaces for input port, output port and memory Phase 2 Environment
Phase 3 Reset
port.
Phase 4 Packet
Phase 5 Generator
3) DUT and TestBench interfaces are connected in top module.
Phase 6 Driver
4) Clock is generator in top module.
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
NOTE:In every file you will see the syntax
ìfndefGUARD_*
èndifGUARD_*
PHASE 1 TOP
Interfaces
Easy Labs : SV
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Easy Labs : VMM
AVM Switch TB

VMM Ethernet sample This approach will avoid race conditions between the design and the verification
Verilog
environment.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
//////////////////////////////////////////
//////////////////////////////////////////
RVM Ethernet sample parametersetup_time =5ns;
Specman E
Interview Questions
wire[7:0]mem_data;
wire[1:0]mem_add;
wire mem_en;
wire mem_rd_wr;
output mem_data;
outputmem_add;
outputmem_en;
outputmem_rd_wr;
endclocking:cb
http://testbench.in/VL_04_PHASE_1_TOP.html[9/26/2012 2:33:32 PM]

input is what keeps
with time!
////////////////////////////////////////////
////////////////////////////////////////////
wire data_status;
wire [7:0]data_in;
wire reset;
outputdata_status;
outputdata_in;
endclocking:cb
/////////////////////////////////////////////////
/////////////////////////////////////////////////
wire[7:0]data_out;
wireready;
wireread;
input data_out;
input ready;
outputread;
endclocking:cb
//////////////////////////////////////////////////
èndif
Testcase
Testcase is a program block which provides an entry point for the test and creates a
scope that encapsulates program-wide data. Currently this is an empty testcase which
just ends the simulation.Program block contains all the above declared interfaces as
arguments. This testcase has initial and final blocks.
Inside the program block, include the vmm.sv file.
]);
ìnclude"vmm.sv"
initial
begin
#1000;
end
final
endprogram
èndif
Top Module
bitClock;
initial
begin
#20;
end
5)Do the instance of testcase and pass all the above declared interfaces.
6)Do the instance of DUT.
switch DUT(.
7)Connect all the interfaces and DUT.The design which we have taken is in
Top Module Source Code:

ìfndefGUARD_TOP
`defineGUARD_TOP
moduletop();
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
bitClock;
initial
begin
#20;
end
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
//Program block Testcase instance//
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
endmodule
èndif
vmm_switch_1.tar
Browse the code in vmm_switch_1.tar
Run the simulation:
vcs -sverilog -f filelist -R -ntb_opts rvm
Log file after simulation:
******************** End of testcase *****************
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Assertion
Index
Introduction
Specification
Verification Plan
In this phase, we will write
Phase 1 Top
Phase 2 Environment
Environment class.
Phase 3 Reset
Virtual interface declaration.
Phase 4 Packet
Defining Environment class constructor.
Phase 5 Generator
Defining required methods for execution . Currently these methods will not be Phase 6 Driver
implemented in this phase.
Phase 7 Receiver
Phase 8 Scoreboard
All the above are done in Environment .sv file.
Phase 9 Coverage
DPI
We will write a testcase using the above define environment class in testcase.sv file.
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
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Randomization
Functional Coverage
PHASE 2 ENVIRONMENT
UVM Tutorial
VMM Tutorial
Environment Class:
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
The class is a base class used to implement verification environments.

Environment class is extension on vmm_env class.The testbench simulation needs
some systematic flow like reset, initialize etc. vmm_env base class has methods
formalize the simulation steps. All methods are declared as virtual methods.
We will not implement all the vmm_env virtual methods in this phase but will we print
messages from these methods to understand the simulation execution.
Testcase contains the instance of the environment class and has access to all the
public declaration of environment class. This testcase Creates a Environment object
and calls the run() method which are defined in the environment class. Run() method
runs all the simulation methods which are defined in environment class.
module.
Constructor method should be declared with virtual interface as arguments, so that
when the object is created, in the testcase can pass the interfaces in to environment
class.
Switch TB
RVM Switch TB
Connecting the virtual interfaces of Environment class to the physical interfaces of
RVM Ethernet sample top module.
Specman E
Interview Questions
http://testbench.in/VL_05_PHASE_2_ENVIRONMENT.html[9/26/2012 2:33:42 PM]

input is what keeps
with time!
Extend vmm_env class to define Environment class.

ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsvmm_env;
endclass
èndif
Declare virtual interfaces in Environmentclass.

The construction of Environment class is declared with virtual interface as arguments.
super.new("Environment ");
In constructor methods, the interfaces which are arguments are connected to the
virtual interfaces of environment class.
`vmm_note(this.log,"Created env object");
Extend all the vmm_env virtual methods. Call the super.<method_name> in all the
vmm_env virtual method extensions.
Include `vmm_note() messages for identifying the simulation steps in the log file.
super.gen_cfg();

endfunction
super.build();
endfunction
....
....
....
Do the above for reset_dut(), cfg_dut(), start(), wait_for_end(), stop() cleanup() and
report() methods.
Run :
The run method is called from the testcase to start the simulation. run method calls
all the methods which are defined in the Environment class.

ìfndefGUARD_ENV
`defineGUARD_ENV
classEnvironment extendsvmm_env;
`vmm_note(this.log,"Created env object");

endfunction:new
super.gen_cfg();
endfunction
super.build();
endfunction
super.reset_dut();
endtask
super.cfg_dut();
endtask
virtualtaskstart();
super.start();
endtask
virtualtaskwait_for_end();
endtask
virtualtaskstop();
super.stop();
endtask
virtualtaskcleanup();
super.cleanup();
endtask
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
We will create a file Global.sv for global requirement. In this file,define all the port
address as macros in this file.
ìfndefGUARD_GLOBALS
`defineGUARD_GLOBALS
`defineP08'h00
`defineP18'h11
`defineP28'h22
`defineP38'h33
èndif
Now We will update the testcase. Take an instance of the Environment class and call
the run method of the Environment class.
ìfndef GUARD_TESTCASE
`define GUARD_TESTCASE
program
testcase(mem_interface.MEM
input_intf,output_interface.OP output_intf[4]);
mem_intf,input_interface.IP
ìnclude "vmm.sv"
Environment env;
initial
begin
env.run();
end
final
endprogram
èndif
vmm_switch_2.tar
Run the simulation:
Log report after the simulation:
Normal[NOTE] on Environment() at0:
Created env object

--------------------------------------------------------------------Simulation PASSED on /./ (/./) at0 (0 warnings, 0 demoted errors & 0

demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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Index
Introduction
Specification
Verification Plan
In this phase we will reset and configure the DUT.
Phase 1 Top
The Environment class has reset_dut() method which contains the logic to reset the Phase 2 Environment
DUT and cfg_dut() method which contains the logic to configure the DUT port address. Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
PHASE 3 RESET
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
NOTE:Clocking block signals can be driven only using a non-blocking assignment.

In reset_dut() method.
1) Set all the DUT input signals to a known state. And reset the DUT.
virtual task reset_dut();
super.reset_dut();
RVM Ethernet sample mem_intf.cb.mem_en<=0;
Specman E
Interview Questions
// Reset the DUT

RVM Switch TB

endtask
http://testbench.in/VL_06_PHASE_3_RESET.html[9/26/2012 2:33:52 PM]
2) Updated the cfg_dut method.

virtual task cfg_dut();
super.cfg_dut();
`vmm_note(this.log ,$psprintf("
Port 0 Address %h ",`P0));

endtask
(3) In wait_for_end method, wait for some clock cycles.
repeat(10000)@(input_intf.clock);
Download the Phase 3 source code:
vmm_switch_3.tar
Run the simulation:
Log File report
Created env object

Normal[NOTE] on Environment() at 60:
Port 0 Address 00
Port 1 Address 11
Port 2 Address 22
Port 3 Address 33
--------------------------------------------------------------------Simulation PASSED on /./ (/./) at 100170 (0 warnings, 0 demoted errors & 0

demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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TUTORIALS
PHASE 4 PACKET
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
In this Phase , We will define a packet and then test it whether it is generating as
expected.
Packet is modeled using class. Packet class should be able to generate all possible
packet types randomly. Packet class should also implement allocate(), psdisplay(),
copy(), compare(), byte_pack() and byte_unpack()of vmm_data methods.
Using vmm macros, we will create atomic generator and channel for Packet.
3) Correct or Incorrect Length field.
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
1) Declare FCS types as enumerated data types. Name members as GOOD_FCS and
BAD_FCS.
2) Declare the length type as enumerated data type. Name members as
GOOD_LENGTH and BAD_LENGTH.
Verification
Verilog Switch TB
3) Extend vmm_data class to define Paclet class.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
4) Declare a vmm_log object and construct it.
5) Declare the length type and fcs type variables as rand.
RVM Ethernet sample randfcs_kind_t fcs_kind;
Specman E
Interview Questions
6) Declare the packet field as rand. All fields are bit data types. All fields are 8 bit
packet array. Declare the payload as dynamic array.
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbytefcs;
7) Constraint the DA field to be any one of the configured address.
http://testbench.in/VL_07_PHASE_4_PACKET.html[9/26/2012 2:34:03 PM]
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
input is what keeps
with time!
8) Constrain the payload dynamic array size to between 1 to 255.

9) Constrain the payload length to the length field based on the length type.
Use solve before to direct the randomization to generate first the payload dynamic
array size and then randomize length field.
10) Define a port_randomize method. In this method calculate the fcs based on the
fcs_kind.
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();
11) Define the FCS method.
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
12) Define acllocate() method.
Packet pkt;
pkt =new();
returnpkt;
13) Define psdisplay() method. psdisplay() method displays the current value of the
packet fields to a string.
inti;
$write(psdisplay,"
%s
packet
$write(psdisplay,"
%s%s
length:0x%h
if(data.size()>1)
if(data.size()>4)
if(data.size()>2)
if(data.size()>3)
endfunction
14) Define copy() method. copy() method copies the current values of the object
instance.
Packet cpy;

if(to ==null)
cpy =new;
else

if(!$cast(cpy,to))
begin
copy =null;
returncopy;
end
cpy.da =this.da;
cpy.sa =this.sa;
foreach(data[i])
begin
end
cpy.fcs =this.fcs;
copy =cpy;
endfunction:copy
15) Define Compare() method. Compares the current value of the object instance with
the specified object instance.
If the value is different, FALSE is returned.
=-1);
Packet cmp;

if(!$cast(cmp,to))
begin
compare=0;
returncompare;
end

begin
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
foreach(data[i])
begin
data[%0d]
values:
0x%h
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
endfunction:compare
!=
16)Define byte_pack() method().
Packing is commonly used to convert the high level data to low level data that can be
applied to DUT.In packet class various fields are generated. Required fields are
concatenated to form a stream of bytes which can be driven conveniently to DUT
interface by the driver.
inputint kind =-1);
byte_pack =0;
bytes[0]=this.da;
bytes[1]=this.sa;
foreach(data[i])
bytes[3+i]=data[i];
17) Define byte_unpack() method:
The unpack() method does exactly the opposite of pack method. Unpacking is
commonly used to convert a data stream coming from DUT to high level data packet
object.
inputintlen=-1,
inputintkind =-1);
this.da =bytes[0];
this.sa =bytes[1];
foreach(data[i])
returnbytes.size();
18) Define Packet_channel for Packet using macro.

19) Define Packet_atomic_gen for generating Packet instances using macro.
`vmm_atomic_gen(Packet,"Packet Gen")
Packet Class Source Code
ìfndefGUARD_PACKET
`defineGUARD_PACKET
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbytefcs;
constraintpayload_size_c {data.sizeinside{[1:255};}
functionnew();
endfunction:new
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();
integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
Packet pkt;
pkt =new();
returnpkt;
inti;
$write(psdisplay,"
%s
packet
$write(psdisplay,"
%s%s
length:0x%h
if(data.size()>1)
if(data.size()>4)
if(data.size()>2)
if(data.size()>3)
endfunction

Packet cpy;

if(to ==null)
cpy =new;
else

if(!$cast(cpy,to))
begin
copy =null;
returncopy;
end
cpy.da =this.da;
cpy.sa =this.sa;
foreach(data[i])
begin
end
cpy.fcs =this.fcs;
copy =cpy;
endfunction:copy

=-1);
Packet cmp;

if(!$cast(cmp,to))
begin
compare=0;
returncompare;
end

begin
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
foreach(data[i])
begin
data[%0d]
values:
0x%h
!=
compare=0;
returncompare;
end
begin
compare=0;
returncompare;
end
endfunction:compare
inputint kind =-1);
byte_pack =0;
bytes[0]=this.da;
bytes[1]=this.sa;
foreach(data[i])
bytes[3+i]=data[i];
inputintlen=-1,
inputintkind =-1);
this.da =bytes[0];
this.sa =bytes[1];
foreach(data[i])
returnbytes.size();
endclass
/////////////////////////////////////////////////////////
//// Create vmm_channel and vmm_atomic_gen for packet////
/////////////////////////////////////////////////////////
`vmm_atomic_gen(Packet,"Packet Gen")
Now we will write a small program to test our packet implantation. This program
block is not used to verify the DUT.
Write a simple program block and do the instance of packet class. Randomize the
packet and call the display method to analyze the generation. Then pack the packet
in to bytes and then unpack bytes and then call compare method to check all the
methods.
Program Block Source Code
programtest;
packet pkt1 =new();
packet pkt2 =new();
logic[7:0]bytes[];
initial
repeat(10)
if(pkt1.randomize)
begin
$display(" Randomization Successes full.");
pkt1.display();
void'(pkt1.byte_pack(bytes));
pkt2 =new();
pkt2.byte_unpack(bytes);
$display(" Packing, Unpacking and compare worked");
else
$display(" *** Something went wrong in Packing or Unpacking or compare ***");
end
else
endprogram
Download the packet class with program block.
vmm_switch_4.tar
Run the simulation
Log file report:
Pkt1 packet #0.0.0
Pkt1 da:0x00
Pkt1 sa:0x40
Pkt1 length:0xbe (data.size=190)
Pkt1 data[0]:0xf7 data[1]:0xa6.... data[188]:0x49 data[189]:0x79
Pkt1 fcs:0x1a
Pkt2 packet #0.0.0
Pkt2 da:0x00
Pkt2 sa:0x40
Pkt2 length:0xbe (data.size=190)
Pkt2 data[0]:0xf7 data[1]:0xa6.... data[188]:0x49 data[189]:0x79
Pkt2 fcs:0x1a
Packing,Unpacking and compare worked
Pkt1 packet #0.0.0
Pkt1 da:0x33
Pkt1 sa:0xfd
Pkt1 length:0xc7 (data.size=199)
Pkt1 data[0]:0x1e data[1]:0x80.... data[197]:0x15 data[198]:0x30
Pkt1 fcs:0xa5
Pkt2 packet #0.0.0
Pkt2 da:0x33
Pkt2 sa:0xfd
Pkt2 length:0xc7 (data.size=199)
Pkt2 data[0]:0x1e data[1]:0x80.... data[197]:0x15 data[198]:0x30
Pkt2 fcs:0xa5
Packing,Unpacking and compare worked
Pkt1 packet #0.0.0
Pkt1 da:0x00
Pkt1 sa:0xa6
Pkt1 length:0x9b (data.size=155)
Pkt1 data[0]:0x72 data[1]:0x9f.... data[153]:0x53 data[154]:0x4b
Pkt1 fcs:0x24
Pkt2 packet #0.0.0
Pkt2 da:0x00
Pkt2 sa:0xa6
Pkt2 length:0x9b (data.size=155)
Pkt2 data[0]:0x72 data[1]:0x9f.... data[153]:0x53 data[154]:0x4b
Pkt2 fcs:0x24
..........
..........
..........
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PHASE 5 GENERATOR
SystemVerilog
Verification
Constructs
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OOPS
Randomization
Functional Coverage
In This phase, we will the usage of vmm atomic generator.In phase 4,

using`vmm_atomic_gen macro we defined Packet_atomic_gen.
In Environment class, we will create an instance ofPacket_atomic_gen, and connect
it to the instance of Packet_channel, i.e gen2drvr_chan. The Packet_channel instance
gen2drvr_chan will be used to connect the atomic generator to the driver
instance.We will also configure the atomic generator to generate 10 instances of
packet.
Assertion
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) In Environment class, declare a Packet_atomic_gen instance.

Packet_atomic_gen atomic_gen;
2) Declare a Packet_channel instance.
OpenVera
Constructs
Switch TB
RVM Switch TB
Packet_channel gen2drvr_chan;
3) Construct the gen2drvr_chan in build() method.
gen2drvr_chan =new("gen2drvr","chan");
RVM Ethernet sample 4) Construct the atomic_gen in build() method.
atomic_gen =new("atomic_gen",0,gen2drvr_chan);
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
5) Configure the atomic_gen to generate 10 instances.

atomic_gen.stop_after_n_insts =10;
6) In start() method, start the atomic_gen.
atomic_gen.start_xactor();
7) In stop() method, call the stop_xactor() method of atomic_gen.
atomic_gen.stop_xactor();
http://testbench.in/VL_08_PHASE_5_GENERATOR.html[9/26/2012 2:34:13 PM]

ìfndef GUARD_ENV
`define GUARD_ENV
class Environment extends vmm_env;
virtual mem_interface.MEMmem_intf;
`vmm_note(this.log, "Created env object");

endfunction : new
virtual function void gen_cfg();
super.gen_cfg();
endfunction
super.build();
gen2drvr_chan =new("gen2drvr","chan");
atomic_gen =new("atomic_gen",0,gen2drvr_chan);
atomic_gen.stop_after_n_insts =10;
endfunction
super.reset_dut();
// Reset the DUT

endtask
super.cfg_dut();
`vmm_note(this.log ,$psprintf(" Port
0 Address %h ",`P0));

endtask
virtual task start();
super.start();
endtask
virtual task wait_for_end();
endtask
virtual task stop();
super.stop();
endtask
virtual task cleanup();
super.cleanup();
endtask
virtual task report();
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
Download the phase 5 source code.

vmm_switch_5.tar
Run the simulation
Log file report:
Created env object
Normal[NOTE] on Environemnt() at 60:
Port 0 Address 00
Normal[NOTE] on Environemnt() at110:
Port 1 Address 11
Port 2 Address 22
Port 3 Address 33

demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Specification
In phase 6 we will write a driver and then insatiate the driver in environment and Verification Plan
Phase 1 Top
send packet in to DUT. Driver class is defined in Driver.sv file.
Phase 2 Environment
In this Driver class, take the packets from the generator and then drives it to the DUT Phase 3 Reset
Phase 4 Packet
input interface and then send the packet to a channel for scoreboard purpose.
Phase 5 Generator
Phase 6 Driver
In this class, we also add 2 callback methods.
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
PHASE 6 DRIVER
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
1) Extend vmm_xactor_callbacks to define Driver_callbacks. In this class, declare 2

methods pre_trans() and post_trans(). pre_trans() method is called before driving the
packet transaction and post_trans() method will be called after driving the packet
transaction.
// Called before a transaction is executed
virtualtaskpre_trans(Packet tr);
endtask:pre_trans
Specman E
// Called after a transaction has been executed

virtualtaskpost_trans(Packet tr);
endtask:post_trans
Interview Questions
endclass:Driver_callbacks
1) Extend vmm_xactor to define Driver class.
2) Declare a virtual input_interface of the switch. We will connect this to the Physical
interface of the top module same as what we did in environment class.
http://testbench.in/VL_09_PHASE_6_DRIVER.html[9/26/2012 2:34:23 PM]
3) Define a channel "gen2drv_chan" which is used to get packets from generator.

Packet_channelgen2drv_chan;
4) Define a channel "drv2sb_chan" which is used to send the packets to the score
board.
Packet_channeldrv2sb_chan;
4) Define new constructor with arguments, virtual input interface and channels
"gen2drv_chan" and "drv2sb_chan".
In the constructor, call the parent constructor and pass the instance name and
stream_id.
Connect the channel and virtual interfaces which are passed as constructor arguments
to the class members.
functionnew(stringinst,
intstream_id =-1,
virtualinput_interface.IPinput_intf_new,
Packet_channel gen2drv_chan =null,
Packet_channel drv2sb_chan =null);
super.new("driver",inst,stream_id);
this.input_intf =input_intf_new;
if(gen2drv_chan ==null)
`vmm_fatal(log,"gen2drv_channel is null");
else
this.gen2drv_chan =gen2drv_chan;
if(drv2sb_chan ==null)
`vmm_fatal(log,"drvr2sb_channel is null");
else
this.drv2sb_chan =drv2sb_chan;
`vmm_note(log,"Driver created ");

endfunction
4)Define drive() method. This method drives the packet to the dut.
logic[7:0]pack[];
intpkt_len;
pkt_len =pkt.byte_pack(pack,0,0);
for(inti=0;i<pkt_len -1;i++)
begin
input_intf.cb.data_in <=pack[i];
end
@(input_intf.clock);
input_intf.cb.data_in <=pack[pkt_len -1];
this.drv2sb_chan.put(pkt);
endtask
4) Define the main() method. First call the super.main() method.
super.main();
`vmm_note(this.log," started main task ");
5)In main()method,starta foreverthread,which gets the packets from the
'gen2drv_chan' .The
emptyorstopped.
thread
iteration
has
to
be
block ifthe channel is
foreverbegin
Packet pkt;
wait_if_stopped_or_empty(this.gen2drv_chan);
this.gen2drv_chan.get(pkt);
`vmm_trace(this.log,"Starting transaction...");
`vmm_debug(this.log,pkt.psdisplay(" "));
6)Call the drive()method,which drives the packet to DUT.Call the pre_tans()call
backmethod using `vmm_callbackmacro beforecalling the drive method
andpost_trans()callback method after driving the packet.
`vmm_callback(Driver_callbacks,pre_trans(pkt));
drive(pkt);
`vmm_callback(Driver_callbacks,post_trans(pkt));
Driver Class Source Code:

ìfndefGUARD_DRIVER
`defineGUARD_DRIVER
// Called before a transaction is executed
virtualtaskpre_trans(Packet tr);
endtask:pre_trans
// Called after a transaction has been executed
virtualtaskpost_trans(Packet tr);
endtask:post_trans
endclass:Driver_callbacks
Packet_channelgen2drv_chan;
Packet_channeldrv2sb_chan;
functionnew(stringinst,
intstream_id =-1,
virtualinput_interface.IPinput_intf_new,
Packet_channel gen2drv_chan =null,
Packet_channel drv2sb_chan =null);
this.input_intf =input_intf_new;
`vmm_fatal(log,"gen2drv_channel is null");
else
`vmm_fatal(log,"drvr2sb_channel is null");
else
`vmm_note(log,"Driver created ");
endfunction
logic[7:0]pack[];
intpkt_len;
begin
input_intf.cb.data_in <=pack[i];
end
input_intf.cb.data_in <=pack[pkt_len -1];
this.drv2sb_chan.put(pkt);
endtask
taskmain();
super.main();
foreverbegin
Packet pkt;
wait_if_stopped_or_empty(this.gen2drv_chan);
this.gen2drv_chan.get(pkt);
`vmm_trace(this.log,"Starting transaction...");
`vmm_callback(Driver_callbacks,pre_trans(pkt));
drive(pkt);
`vmm_callback(Driver_callbacks,post_trans(pkt));
`vmm_trace(this.log,"Completed transaction...");
end
endtask
endclass
èndif
Now we will take the instance of the driver in the environment class.
1) Declare a channel "drvr2sb_chan" which will be used to connect the scoreboard and
driver.
Packet_channel drvr2sb_chan;
2) Declare a driver object "drvr".
Driver drvr;
3) In build method, construct the channel.
drvr2sb_chan =new("drvr2sb","chan");
4) In build method, construct the driver object. Pass the input_intf and drvr2sb_chan
channel and gen2drvr_chan channel.
drvr =new("Drvr",0,input_intf,gen2drvr_chan,drvr2sb_chan);
5) To start sending the packets to the DUT, call the start method of "drvr" in the start
method of Environment class.
drvr.start();
5)In the stop() method, call the stop_xactor() method of drvr.
drvr.stop_xactor();
ìfndef GUARD_ENV
`define GUARD_ENV
Driver drvr;

endfunction : new
super.gen_cfg();
endfunction
super.build();
gen2drvr_chan = new("gen2drvr","chan");
drvr2sb_chan =new("drvr2sb","chan");
drvr =new("Drvr",0,input_intf,gen2drvr_chan,drvr2sb_chan);
atomic_gen = new("atomic_gen",0,gen2drvr_chan);
atomic_gen.stop_after_n_insts = 10;
endfunction
super.reset_dut();
// Reset the DUT

endtask
super.cfg_dut();
`vmm_note(this.log,"Start of cfg_dut() method
`vmm_note(this.log ,$psprintf(" Port 0 Address
");
%h ",`P0));
%h ",`P1));
%h ",`P2));
`vmm_note(this.log ,$psprintf(" Port 3 Address %h ",`P3));
endtask
super.start();
drvr.start_xactor();
endtask
endtask
super.stop();
drvr.stop_xactor();
endtask
super.cleanup();
endtask
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
vmm_switch_6.tar
Run the command:
Log file report.
Created env object

Normal[NOTE] on driver(Drvr) at0:
Driver created
Port 0 Address 00
Port 1 Address 11
Port 2 Address 22
Port 3 Address 33
started main task

demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Introduction
Specification
Phase 1 Top
Phase 2 Environment
Receiver collects the data bytes from the interface signal. And then unpacks the bytes Phase 3 Reset
Phase 4 Packet
in to packet and pushes it into channel for score boarding.
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
PHASE 7 RECEIVER
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
1) Extend vmm_xactor and define Receiver class.

classReceiver extendsvmm_xactor;
OpenVera
Constructs
Switch TB
RVM Switch TB
1) Declare a virtual output_interface. We will connect this to the Physical interface of

the top module, same as what we did in environment class.
RVM Ethernet sample 2) Declare a channel "rcvr2sb_chan" which is used to send the packets to the score
board
Specman E
Interview Questions
Packet_channel rcvr2sb_chan;
3) Define new constructor with arguments, virtual input interface and a channel which
is used to send packets from the receiver to scoreboard. Implement the restof the
logic as it was done in the driver constructor.
functionnew(stringinst ="class",
intunsignedstream_id =-1,
virtualoutput_interface.OPoutput_intf_new,
Packet_channel rcvr2sb_chan);
super.new("Receiver",inst,stream_id);
http://testbench.in/VL_10_PHASE_7_RECEIVER.html[9/26/2012 2:34:33 PM]
if(rcvr2sb_chan ==null)
`vmm_fatal(log,"rcvr2sb_channel is null");
else
this.rcvr2sb_chan =rcvr2sb_chan;
`vmm_note(log,"Receiver created ");
endfunction:new
4) Define the main() method.
First call the super.main() method.
Then start a thread which collects the data from the outputinterface and then unpack
the data to a packet and put into channel.
forever
begin
begin
end
`vmm_note(this.log,"Received a packet ");
pkt =new();
pkt.display("rcvr");
rcvr2sb_chan.put(pkt);
bytes.delete();
end
Receiver Class Source Code:
classReceiver extendsvmm_xactor;
virtualoutput_interface.OPoutput_intf_new,
Packet_channel rcvr2sb_chan);
super.new("Receiver",inst,stream_id);
`vmm_fatal(log,"rcvr2sb_channel is null");
else
`vmm_note(log,"Receiver created ");

endfunction:new
taskmain();
logic[7:0]bytes[];
Packet pkt;
super.main();
forever
begin
begin
end
`vmm_note(this.log,"Received a packet ");
pkt =new();
pkt.display("rcvr");
rcvr2sb_chan.put(pkt);
bytes.delete();
end
endtask:main
endclass
èndif
Now we will take the instance of the receiver in the environment class.
1) Declare a channel "rcvr2sb_chan" which will be used to connect the scoreboard and
receiver.
2) Declare 4 receiver object "rcvr".
Receiver rcvr[4];
3) In build method, construct the rcvr2sb_chan.
rcvr2sb_chan =new("rcvr2sb","chan");
4) In build method, construct the receiver object. Pass the output_intf and
rcvr2sb_chan. There are 4 output interfaces and receiver objects. We will connect
one receiver for one output interface.
foreach(rcvr[i])
rcvr[i]=new($psprintf("Rcvr-%0d",i),i,output_intf[i],rcvr2sb_chan);
5) To startthe receiver activities, call the start_xactor() method of rcvr objects in
the start() method of Environment class.
rcvr[0].start_xactor();
6) Call the stop_xactor() method of the receiver object in the stop() method of the
Environment .
rcvr[0].stop_xactor();
ìfndef GUARD_ENV
`define GUARD_ENV
Driver drvr;
Receiver rcvr[4];

endfunction : new
super.gen_cfg();
endfunction
super.build();
drvr2sb_chan = new("drvr2sb","chan");
rcvr2sb_chan =new("rcvr2sb","chan");
drvr = new("Drvr",0,input_intf,gen2drvr_chan,drvr2sb_chan);
foreach(rcvr[i])
rcvr[i]=new($psprintf("Rcvr-%0d",i),i,output_intf[i],rcvr2sb_chan);
endfunction
super.reset_dut();
// Reset the DUT

endtask
super.cfg_dut();
");
%h ",`P0));
%h ",`P1));
%h ",`P2));
%h ",`P3));

endtask
super.start();
endtask
endtask
super.stop();
drvr.stop_xactor();
endtask
super.cleanup();
endtask
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
vmm_switch_7.tar
Run the command:
Log file report.
Created env object

Driver created
Normal[NOTE] on Receiver(Rcvr-0) at0:
Receiver created
Receiver created
Receiver created
Receiver created
Port 0 Address 00
Port 1 Address 11
Port 2 Address 22
Port 3 Address 33
started main task
started main task
started main task
started main task
started main task
Received a packet
rcvr packet #0.0.0
rcvr da:0x00
rcvr sa:0xac
rcvr length:0x05 (data.size=4)
rcvr data[0]:0xcb data[1]:0x7e data[2]:0x52 data[3]:0xa4
rcvr fcs:0x29
Received a packet
rcvr packet #0.0.0
rcvr da:0x11
rcvr sa:0xf3
rcvr data[0]:0xc4 data[1]:0xd5.... data[3]:0xf3 data[4]:0x88
rcvr fcs:0x5b
Received a packet
rcvr packet #0.0.0
rcvr da:0x33
rcvr sa:0x6b
rcvr data[0]:0x32 data[1]:0x27
rcvr fcs:0x1c


demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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TUTORIALS
PHASE 8 SCOREBOARD
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
In this phase we will see the scoreboard implementation. Vmm has scoreboard classes
with lot of features. For this example, we will write a simple scoreboard which is
implemented using the vmm_xactor.
Scoreboard has 2 channels. One is used to for getting the packets from the driver and
other from the receiver.Then the packets are compared and if they don't match,
then error is asserted. For comparison, compare () method of the Packet class is used.
Functional Coverage
Assertion
Scoreboard in implemented in file Scoreboard.sv.
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
1) Declare 2 channels drvr2sb_chan and rcvr2sb_chan.

2) Declare a constructor method with drvr2sb_chan , rcvr2sb_chan , a string for
instance name and stream_id as arguments.
RVM Ethernet sample Packet_channel drvr2sb_chan =null,
Packet_channel rcvr2sb_chan =null);
RVM Switch TB
Specman E
Interview Questions
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
3) Call the super.new() method and Connect the channels of the constructor to the
channels of the scoreboard.
super.new("sb",inst,stream_id);
if(drvr2sb_chan ==null)
`vmm_fatal(this.log,"drvr2sb_channel is not constructed");
else
this.drvr2sb_chan =drvr2sb_chan;
`vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
http://testbench.in/VL_11_PHASE_8_SCOREBOARD.html[9/26/2012 2:34:42 PM]
else
`vmm_note(log,"Scoreboard created ");
4) Definevmm_xactor main() method. First call the super.main() method and then do
the following steps forever.
Wait until there is a packet is in "rcvr2sb_chan". Then pop the packet from channel.
rcvr2sb_chan.get(pkt_rcv);
$display(" %0d : Scorebooard : Scoreboard received a packet from receiver
",$time);
Then pop the packet from drvr2sb_chan.
drvr2sb_chan.get(pkt_exp);
Compare both packets and assert an error if the comparison fails using `vmm_error.
if(pkt_rcv.compare(pkt_exp,msg))
$display(" %0d : Scoreboard :Packet Matched ",$time);
else
`vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg));
Scoreboard Class Source Code:
classScoreboard extendsvmm_xactor;
Packet_channel drvr2sb_chan =null,
Packet_channel rcvr2sb_chan =null);
super.new("sb",inst,stream_id);
if(drvr2sb_chan ==null)
`vmm_fatal(this.log,"drvr2sb_channel is not constructed");
else
this.drvr2sb_chan =drvr2sb_chan;
`vmm_fatal(this.log,"rcvr2sb_channel is not constructed");
else
`vmm_note(log,"Scoreboard created ");

endfunction:new
taskmain();
Packet pkt_rcv,pkt_exp;
stringmsg;
super.main();
forever
begin
rcvr2sb_chan.get(pkt_rcv);
$display(" %0d : Scoreboard : Scoreboard received a packet from receiver ",$time);
drvr2sb_chan.get(pkt_exp);
if(pkt_rcv.compare(pkt_exp,msg))
$display(" %0d : Scoreboard :Packet Matched ",$time);
else
`vmm_error(this.log,$psprintf(" Packet MissMatched \n %s ",msg));
end
endtask:main
endclass
èndif
Now we will see how to connect the scoreboard in the Environment class.
1) Declare a scoreboard handle.

Scoreboard sb;
2) Construct the scoreboard in the build() method. Pass the drvr2sb_chan and
rcvr2sb_chan channels to the score board constructor.
sb =new("Sb",0,drvr2sb_chan,rcvr2sb_chan);
3) Start the scoreboard activities in the start() method.
sb.start_xactor();
4) Stop the scoreoard activities in stop() method.
sb.stop_xactor();
Source Code Of The Environment Class:
ìfndef GUARD_ENV
`define GUARD_ENV
Driver drvr;
Receiver rcvr[4];
Scoreboard sb;

endfunction : new
super.gen_cfg();
endfunction
super.build();
rcvr2sb_chan = new("rcvr2sb","chan");
foreach(rcvr[i])
rcvr[i] = new($psprintf("Rcvr-%0d",i),i,output_intf[i],rcvr2sb_chan);
sb =new("Sb",0,drvr2sb_chan,rcvr2sb_chan);
endfunction
super.reset_dut();
// Reset the DUT

endtask
super.cfg_dut();

endtask
super.start();
sb.start_xactor();
endtask
endtask
super.stop();
drvr.stop_xactor();
sb.stop_xactor();
endtask
super.cleanup();
endtask
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
vmm_switch_8.tar
Run the simulation:
Log File Report:
Created env object
Driver created
Receiver created
Receiver created
Receiver created
Receiver created
Normal[NOTE] on sb(Sb) at0:
Scoreboard created
Port 0 Address 00
Port 1 Address 11
Port 2 Address 22
Port 3 Address 33
started main task
started main task
started main task
started main task
started main task
size 8 ****

Received a packet
rcvr packet #0.0.0
rcvr da:0x00
rcvr sa:0xac
rcvr data[0]:0xcb data[1]:0x7e data[2]:0x52 data[3]:0xa4
rcvr fcs:0x29
470 : Scorebooard : Scoreboard received a packet from receiver
size 9 ****
Received a packet
rcvr packet #0.0.0
rcvr da:0x11
rcvr sa:0xf3
rcvr data[0]:0xc4 data[1]:0xd5.... data[3]:0xf3 data[4]:0x88
rcvr fcs:0x5b
size 6 ****
Received a packet
rcvr packet #0.0.0
rcvr da:0x33
rcvr sa:0x6b
rcvr data[0]:0x32 data[1]:0x27
rcvr fcs:0x1c

demoted warnings)
---------------------------------------------------------------------

******************** End of testcase *****************
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Index
Introduction
Specification
In this phase we will write the functional coverage for switch protocol. Functional Verification Plan
coverage is written in DrvrCovCallback.sv file. After running simulation, you will Phase 1 Top
analyze the coverage results and find out if some test scenarios have not been Phase 2 Environment
Phase 3 Reset
exercised and write tests to exercise them.
Phase 4 Packet
Phase 5 Generator
The points which we need to cover are
Phase 6 Driver
1) Cover all the port address configurations.
Phase 7 Receiver
2) Cover all the packet lengths.
Phase 8 Scoreboard
3) Cover all correct and incorrect length fields.
Phase 9 Coverage
4) Cover good and bad FCS.
5) Cover all the above combinations.
PHASE 9 COVERAGE

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
We will do the coverage sampling in the driver porst_trans() callback method which
we developed in PHASE_6.
1) Define a cover group with following cover points. Define this cover group in a class
which extends Driver_callbacks.
classDrvrCovCallback extendsDriver_callbacks;
a) All packet lengths:
OpenVera
Constructs
b) All port address:
binsp0 ={`P0};
RVM Switch TB
binsp1 ={`P1};
RVM Ethernet sample binsp2 ={`P2};
binsp3 ={`P3};}
Switch TB
Specman E
Interview Questions
c) Correct and incorrect Length field types:

d) Good and Bad FCS:
5) Cross product of all the above cover points:
2) In constructor method, construct the cover group
http://testbench.in/VL_12_PHASE_9_COVERAGE.html[9/26/2012 2:34:52 PM]
functionnew();
endfunction:new
3) Write task which calls the sample method to cover the points.
this.pkt =pkt;
endtask:sample
Source Code Of Coverage Class:
ìfndefGUARD_DRVR_CALLBACK_1
`defineGUARD_DRVR_CALLBACK_1
classDrvrCovCallback extendsDriver_callbacks;
Packet pkt;
covergroupswitch_coverage;
binsp0 ={`P0};
binsp1 ={`P1};
binsp2 ={`P2};
binsp3 ={`P3};}
endgroup
functionnew();
endfunction:new
virtualtaskpost_trans(Packet pkt);
this.pkt =pkt;
endtask:post_trans
endclass:DrvrCovCallback
èndif
Now we will connect this callback instance to the Driver.
1) Take the instance of DrvrCovCallback in the Environemtn class.
DrvrCovCallback cov_cb;
2) Construct the cov_cb object in build method.
cov_cb =new();
3) In the Build method, call the append_callback() of the drvr and pass the cov_cb
object.
drvr.append_callback(cov_cb);
Source code of the Environment class:

ìfndef GUARD_ENV
`define GUARD_ENV
Driver drvr;
Receiver rcvr[4];
Scoreboard sb;
DrvrCovCallback cov_cb;

endfunction : new
super.gen_cfg();
endfunction
super.build();
rcvr2sb_chan = new("rcvr2sb","chan");
foreach(rcvr[i])
rcvr[i] = new($psprintf("Rcvr-%0d",i),i,output_intf[i],rcvr2sb_chan);
sb = new("Sb",0,drvr2sb_chan,rcvr2sb_chan);
cov_cb =new();
drvr.append_callback(cov_cb);
endfunction
super.reset_dut();
// Reset the DUT

endtask
super.cfg_dut();
");
%h ",`P0));
%h ",`P1));
%h ",`P2));
%h ",`P3));

endtask
super.start();
sb.start_xactor();
endtask
endtask
super.stop();
endtask
super.cleanup();
endtask
$display("---------------------------------------------------------------------");
super.report();
$display("---------------------------------------------------------------------");
$display("\n\n");
endtask
endclass
èndif
vmm_switch_9.tar
Run the simulation:
urg -dir simv.cm/
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TUTORIALS
AVM INTRODUCTION
SystemVerilog
Mentor Graphics Advanced Verification Methodology(AVM) is opensource and nonproperietary SystemVerilog and systemc methodology. This is based on OSCI(open
systemC initiative) TLM standared. AVM can be downloaded for free from mentors
website. AVM contains TLM(Transaction Level modaling) concepts, rules, suggesation
with lot of examples for better understanding. AVM focuses on constrained
randomization, Coverage , Assertions & scorboarding.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
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AVM Switch TB
AVM provides base classes to improve user productivity. AVM has TLM interfaces to
communicate between testbench components. AVM liberary has the following base
classes.
Reporting class: Has reporting methods, verbosity level controls etc.

Building Blocks: avm_transaction, avm_stimulus, avm_in_order_comparator, avm_env Report a Bug or Comment
etc.
input is what keeps
TML library: TLM inteaces, TLM channels.
Verification components can be class or modules. Modules are handy for HDL users. with time!
One of the main advantage of using module based avm testbench is it supports system
verilog assertions.In SystemVerilog ,Assertions canot be part of class.
Where as class are more flexible as they are OO. Randomization is easy with class.
Dynamic instancsation and classes can be used as varibles for communication.
AVM components intarect with DUT using SystemVerilog virtual interface.
VMM Ethernet sample Hear Im going to discussing the avm base classes which are used in the example. For
more details refer to avm cookbook.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
Tlm:
All the verification components use TLM interfacess whether they are class based or
module based. Main operations on the TLM or put,get and peek.
Initiator puts transaction to a target and can get trasaction from a target.
There are two types of TLMs.
BLOCKING MODEL: Waits until the put transaction is completed befor the next put
operation. Blocking operation is time consuming.
NON BLOCKING MODEL: Nonblocking operations are instansations. Every thing happens
in zero time.
RVM Ethernet sample TLM supports unidirectional and bidirectional data flow. tlm_fifos are bases for TLM.
Specman E
Interview Questions
Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard
tlm_fifo has put,peek(get a copy) and get interface for communication tranctions. It
also has put_ap,get_ap(analaysis ports for commucating with score board or covarage
model).
Lets see how to use ports and exports.
The TLM interface is called port. tlm_fifo sub blocks are called export.
EXAMPLE
Declare a tlm_fifo:
tlm_fifo#(packet)gen2drv;
Creat putport in initiator block(lets call it gen):

tlm_blocking_put_if#(packet)put_port;
http://testbench.in/AV_01_AVM_INTRODUCTION.html[9/26/2012 2:35:02 PM]
Creat getport in target block(lets call it drvr):

tlm_blocking_get_if#(packet)get_port;
Connect the exports to ports:
gen.put_port =gen2drv.blocking_put_export;
drvr.get_port =gen2drv.blocking_get_export;
Noe putcan be done in gen andgetcan be done in drvr.
Building Blocks
There are two types of bases class used for building AVM components.
1)avm_named_component
2)avm_verificatino_component.
avm_named_components has information about the hierarchy of the instantiatio and
are used for TLM port and export connections. This also has built in message
controlling system.
avm_verification_components
are
inherited
from
avm_named_component.
avm_verification_component are used to build testbench component like
driver,monitor,transactor etc. In addition to avm_named_component feauters, a run()
method is provided for uses to define, and this run() method is forked from avm_env
automatically.
Avm_transactors:
Avm transaction is base class for creating tranctions. In order to allow the avm and
tlm libraries to work, we need methods to print, compare and clone transactions.
For any given transaction, T, to do four things to use avm_transaction:

Inherit from avm_transaction
Implement the virtual function string convert2string. This is for messaging.
Implement a function bit comp( input T t ). Used by the comparators for checking in
scoreboard.
Implement a function T clone(). This used for tlm_fifos. clone() returns a copy() of
.this(its object handle).
Avm_env:
avm_env class is the top level of testbench. avm_env has do_test() method which
starts building and execution of the testbench components.
Environment execution stars when do_test() task is called.
There are 5 execution phases.
Construct: Constructs all the class based verification components.
Connect: Connect the class based verification components together.
Configure: Configuration of the testbench components in Zero time.
Execute: do_run() forks off all the components run() methods and then execute
method.
Report:End of simulation messages goes hear.
Avm_messaging:
avm_messaging
supports
four
types
of
severity
levels.
They
are
MESSAGE,WARNING,ERROR,FATAL
avm_messaging supports four types of actions. They are DISPLAY,LOG,COUNT,EXIT.
Each of the actions are define by severity and id.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Avm Introduction
Dut Specification
Rtl
This DUT is a simple switch, which can drive the incoming packet to destination ports Top
Interface
based on the address contained in the packet.
Environment
The dut contain one input interface from which the packet enters the dut. It has four Packet
Packet Generator
output interfaces where the packet is driven out.
Configuration
Driver
Reciever
Scoreboard
DUT SPECIFICATION
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
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Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Packet format:
OpenVera
Constructs
Switch TB
Packet : Header, data and frame check sequence. Packet width is 8 bits and the
length of the packet can be between 4 bytes to 259 bytes.
RVM Switch TB
Packet header:
RVM Ethernet sample Packet header contains three fields DA, SA and length.
Specman E
Interview Questions
DA: Destination address of the packet. It is 8 bits. The switch drives the packet to
respective ports based on this destination address of the packets.
SA: Source address of the packet from where it originate.
Length: This is the length of the data. It can be from 0 to 255.
Data: Data should be in terms of bytes. It can be between 0 to 255 bytes.
FCS: This field contains the security check of the packet. It is calculated over the
header and data.
http://testbench.in/AV_02_DUT_SPECIFICATION.html[9/26/2012 2:35:12 PM]
Configuration:
Dut has four output ports. These output ports have to be configure to a address. Dut
matches the DA field of the packet with this configured port address and sends the
packet on to that port. To configure the dut, a memory interface is provided. The
address of the ports should be unique. It is 8 bits wide. Memory address (0,1,2,3)
contains the address of port(0,1,2,4) respectively.
The dut has one input Interface, from where the packet enters the dut and 4 output
port address can be configured.
Memory Interface:
address of the port 0,1,2,3 respectively. If the DA feild in the packet matches with
the confugured address of any port ,then the packet comes out of thatport.
Input Interface:
The status signal has to be high when data is when packet is sent on to the dut it has
to become low after sending last byte of the packet. 2 clocks gap should be
maintained between packets.
Output Interface:
There are 4 ports, each having data, ready and read signals.
When the data is ready to be sent out from the port, dut makes the ready signal high
indicating that data is ready to be sent.
If the read signal is made high when ready is high, then the data comes out of the
data signal.
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TUTORIALS
RTL
SystemVerilog
CODE:rtl.v
modulefifo (clk,
Constructs
reset,
write_enb,
Interface
read,
OOPS
data_in,
data_out,
Randomization
empty,
Functional Coverage
full);
Assertion
input clk;
input reset;
DPI
inputwrite_enb;
UVM Tutorial
inputread;
input[7:0]data_in;
VMM Tutorial
output[7:0]data_out;
OVM Tutorial
outputempty;
outputfull;
Easy Labs : SV
wire clk;
Easy Labs : UVM
wirewrite_enb;
wireread;
Easy Labs : OVM
wire [7:0]data_in;
Easy Labs : VMM
reg[7:0]data_out;
wireempty;
AVM Switch TB
wirefull;
VMM Ethernet sample reg[7:0]ram[0:25];
regtmp_empty;
regtmp_full;
integerwrite_ptr;
Verilog
integerread_ptr;
Verification
always@(negedgereset)
Verilog Switch TB
begin
data_out=8'b0000_0000;
Basic Constructs
tmp_empty =1'b1;
tmp_full=1'b0;
write_ptr =0;
OpenVera
read_ptr=0;
Constructs
end
Verification
Switch TB
assignempty=tmp_empty;
assignfull=tmp_full;
RVM Ethernet sample always@(posedgeclk)begin
if((write_enb ==1'b1)&&(tmp_full ==1'b0))begin
ram[write_ptr]=data_in;
tmp_empty <=1'b0;
Specman E
write_ptr =(write_ptr +1)%16;
if(read_ptr ==write_ptr )begin
Interview Questions
tmp_full <=1'b1;
end
end
RVM Switch TB
if((read ==1'b1)&&(tmp_empty ==1'b0))begin

data_out <=ram[read_ptr];
tmp_full <=1'b0;
read_ptr =(read_ptr +1)%16;
tmp_empty <=1'b1;
http://testbench.in/AV_03_RTL.html[9/26/2012 2:35:22 PM]
Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard
input is what keeps
with time!
end
end
end
endmodule//fifo
moduleport_fsm (clk,
reset,
write_enb,
ffee,
hold,
data_status,
data_in,
data_out,
mem0,
mem1,
mem2,
mem3,
addr);
inputclk;
inputreset;
input [7:0] mem0;
input [7:0] mem1;
input [7:0] mem2;
input [7:0] mem3;
output[3:0]write_enb;
inputffee;
inputhold;
inputdata_status;
input[7:0]data_in;
output[7:0] addr;
reg[7:0]data_out;
reg[7:0]addr;
reg[3:0]write_enb_r;
regfsm_write_enb;
reg[3:0]state_r;
reg[3:0]state;
reg[7:0]parity;
reg[7:0]parity_delayed;
regsus_data_in,error;
parameterADDR_WAIT =4'b0000;
parameterDATA_LOAD =4'b0001;
parameterPARITY_LOAD=4'b0010;
parameterHOLD_STATE=4'b0011;
parameterBUSY_STATE=4'b0100;
begin
error=1'b0;
data_out =8'b0000_0000;
addr =8'b00000000;
write_enb_r=3'b000;
fsm_write_enb=1'b0;
state_r=4'b0000;
state=4'b0000;
parity =8'b0000_0000;
parity_delayed =8'b0000_0000;
sus_data_in=1'b0;
end
assignbusy =sus_data_in;
always@(data_status)begin:addr_mux
if(data_status ==1'b1)begin
case(data_in)
mem0 :begin
write_enb_r[0]=1'b1;
end
mem1 :begin
end
mem2 :begin
end
mem3 :begin
end
default:write_enb_r =3'b000;
endcase
//$display("
data_inii
%d
,mem0
mem3",data_in,mem0,mem1,mem2,mem3);
end//if
end//addr_mux;
always@(posedgeclk)begin:fsm_state
state_r <=state;
end//fsm_state;
%d
,mem1
%d
,mem2
%d
always@(state_r ordata_status orffee orhold ordata_in)

begin:fsm_core
state =state_r; //Default state assignment
case(state_r)
ADDR_WAIT: begin
if((data_status ==1'b1)&&
((mem0 ==data_in)||(mem1 ==data_in)||(mem3 ==data_in)||(mem2
==data_in)))begin
if(ffee ==1'b1)begin
state =DATA_LOAD;
end
elsebegin
state =BUSY_STATE;
end//if
end//if;
sus_data_in =!ffee;
==data_in))&&
(ffee ==1'b1))begin
addr =data_in;
data_out=data_in;
fsm_write_enb =1'b1;
end
elsebegin
end//if
end// of case ADDR_WAIT
PARITY_LOAD:begin
state =ADDR_WAIT;
data_out =data_in;
end// of case PARITY_LOAD
DATA_LOAD: begin
(hold ==1'b0))begin
state =DATA_LOAD;
end
elseif((data_status ==1'b0)&&
(hold ==1'b0))begin
state =PARITY_LOAD;
end
elsebegin
state =HOLD_STATE;
end//if
sus_data_in =1'b0;
(hold ==1'b0))begin
data_out =data_in;
end
(hold ==1'b0))begin
data_out =data_in;
end
elsebegin
end//if
end//end of case DATA_LOAD
HOLD_STATE:begin
if(hold ==1'b1)begin
state =HOLD_STATE;
end
elseif((hold ==1'b0)&&(data_status ==1'b0))begin
state =PARITY_LOAD;
end
elsebegin
state =DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out =data_in;
end//if
end//end of case HOLD_STATE
BUSY_STATE:begin
state =BUSY_STATE;
end
elsebegin
state =DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
addr =data_in;// hans
data_out=data_in;
end//if
end//end of case BUSY_STATE
endcase
end//fsm_core
assignwrite_enb[0]=write_enb_r[0]&fsm_write_enb;
endmodule//port_fsm
moduleswitch (clk,
reset,
data_status,
data,
port0,
port1,
port2,
port3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3,
mem_en,
mem_rd_wr,
mem_add,
mem_data);
inputclk;
inputreset;
inputdata_status;
input[7:0]data;
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
wire [7:0]data_out_0;
wirell0;
wirell1;
wirell2;
wirell3;
wireempty_0;
wireempty_1;
wireempty_2;
wireempty_3;
wireffee;
wireffee0;
wireffee1;
wireffee2;
wireffee3;
wireld0;
wireld1;
wireld2;
wireld3;
wirehold;
wire [3:0]write_enb;
wire [7:0]data_out_fsm;
wire [7:0]addr;
reg[7:0]mem[3:0];
wirereset;
fifo queue_0 (.clk (clk),
.reset (reset),
.write_enb (write_enb[0]),
.read(read_0),
.data_in (data_out_fsm),
.data_out(data_out_0),
.empty (empty_0),
.full(ll0));
.reset (reset),
.read(read_1),
.empty (empty_1),
.full(ll1));
.reset (reset),
.read(read_2),
.empty (empty_2),
.full(ll2));
.reset (reset),
.read(read_3),
.empty (empty_3),
.full(ll3));
port_fsm in_port (.clk (clk),

.reset (reset),
.write_enb (write_enb),
.ffee(ffee),
.hold(hold),
.data_status(data_status),
.data_in (data),
.data_out(data_out_fsm),
.mem0(mem[0]),
.mem1(mem[1]),
.mem2(mem[2]),
.mem3(mem[3]),
.addr(addr));
assignport0 =data_out_0; //make note assignment only for
//consistency with vlog env
assignport1 =data_out_1;
assignready_0 =~empty_0;
assignffee0 =(empty_0
|(addr
|(addr
|(addr
|(addr
!=mem[0]));
!=mem[1]));
!=mem[2]));
!=mem[3]));
assignffee=ffee0 &ffee1 &ffee2 &ffee3;

assignld0
assignld1
assignld2
assignld3
=(ll0
=(ll1
=(ll2
=(ll3
&(addr
&(addr
&(addr
&(addr
==mem[0]));
==mem[1]));
==mem[2]));
==mem[3]));
assignhold =ld0 |ld1 |ld2 |ld3;

always@(posedgeclk)
begin
if(mem_en)
if(mem_rd_wr)
begin
mem[mem_add]=mem_data;
///$display("%d%d %d %d %d",mem_add,mem[0],mem[1],mem[2],mem[3]);
end
end
endmodule//router
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Avm Introduction
Dut Specification
Verilog Top
Rtl
Top level module containts the design and testbench instance. Top module also Top
contains clock generator. There is no need to instantiate the top module. Testbench Interface
and dut instances are connected using interface instance. Make an instance of env Environment
Packet
class and creat it. Call the do_test() method which starts the testbench components.
Packet Generator
Configuration
Driver
Reciever
Scoreboard
TOP
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
CODE: top.v
ìnclude"mem_env.sv"
moduletop();
// Make an instance of SystemVerilog interface.
switch_if intf();
Constructs
Switch TB
//As the RTL is in verilog and the SV Interface ports are not used,Connect signals by
signal names
RVM Ethernet sample switch switch1(.clk(intf.clock),
.reset(intf.reset),
.data_status (intf.data_status),
.data (intf.data_in),
Specman E
.port0 (intf.data_out[0]),
Interview Questions
.ready_0 (intf.ready[0]),
.read_0 (intf.read[0]),
.read_1 (intf.read[1]),
.read_2(intf.read[2]),
.read_3(intf.read[3]),
RVM Switch TB
http://testbench.in/AV_04_TOP.html[9/26/2012 2:35:32 PM]
.mem_en (intf.mem_en),
.mem_rd_wr(intf.mem_rd_wr),
.mem_add(intf.mem_add),
.mem_data (intf.mem_data));
// Creat a clock generator.
initialbegin
intf.clock =0;
#10;
foreverbegin
#5intf.clock =!intf.clock;
end
end
// Make an instance of testbench env
sw_env env;
initial
begin
@(posedgeintf.clock);
// Pass the interface to testbench environment.
env =new(intf);
//Call do_test task. extecution of the testbench starts.
env.do_test;
$finish;
end
endmodule//top
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
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Index
Avm Introduction
Dut Specification
Creat an interface .Define modport to specifies direction. These are used to connect Rtl
Top
testbench environment and dut in top module.
Interface
Environment
CODE:interface
Packet
ìfndefINTF
Packet Generator
`defineINTF
Configuration
Driver
interfaceswitch_if();
Reciever
bit data_status;
Scoreboard
bit [7:0]data_in;
wire[3:0][7:0]data_out;
wire [3:0]ready;
bit [3:0]read;
input is what keeps
bit[7:0]mem_data;
bit[1:0]mem_add;
with time!
bitreset;
bitmem_en;
bitmem_rd_wr;
bitclock;
INTERFACE
Easy Labs : OVM
modportTB(
outputdata_status,
outputdata_in,
AVM Switch TB
input data_out,
VMM Ethernet sample input ready,
outputread,
output mem_data,
outputmem_add,
Verilog
outputreset,
Verification
outputmem_en,
Verilog Switch TB
outputmem_rd_wr
);
Basic Constructs
Easy Labs : VMM
OpenVera
endinterface:switch_if
èndif
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/AV_05_INTERFACE.html[9/26/2012 2:35:39 PM]
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Index
Avm Introduction
Dut Specification
Environment is extended class of avm_env. Environment holds all the instancess of Rtl
Top
avm_verification_component and fifos for connections.
Interface
Environment
Packet
CODE:env.sv
Packet Generator
importavm_pkg::*;
Configuration
Driver
Reciever
ìnclude"Configuration.sv"
Scoreboard
ìnclude"packet.sv"
ìnclude"mem_driver.sv"
ìnclude"reciever.sv"
ìnclude"score_board.sv"
ENVIRONMENT
classsw_env extendsavm_env;
// channels and interface

localvirtualswitch_if intf;
Easy Labs : UVM
tlm_fifo#(packet)gen2drv;
tlm_fifo#(packet)drv2sb;
Easy Labs : OVM
tlm_fifo#(packet)rcv2sb;
Easy Labs : VMM
// specific components
AVM Switch TB
localConfiguration cfg;
VMM Ethernet sample localdriver drvr;
localreciever rcvr_0;
Verilog
Verification
localscoreboard sb;
Verilog Switch TB
localgenerator gen;
localpacket pkt;
Basic Constructs
stringmsg;
OpenVera
functionnew(virtualswitch_if intf );
Constructs
this.intf =intf;
Switch TB
cfg =new("cfg",intf);
RVM Switch TB
pkt =new();
RVM Ethernet sample drvr =new("driver",cfg);
rcvr_0 =new("reciever_0",0);
Specman E
sb =new();
Interview Questions
gen =new();
gen2drv =new();
drv2sb =new();
rcv2sb =new();
endfunction
avm_report_message("gen_cfg"," Starting... Gen_cfg \n");

Easy Labs : SV
http://testbench.in/AV_06_ENVIRONMENT.html[9/26/2012 2:35:52 PM]
input is what keeps

with time!
if(!cfg.randomize())
avm_report_error("gen_cfg","Configuration Randomization Failed!\n");
cfg.display();
avm_report_message("gen_cfg"," Ending.... Gen_cfg \n");
pkt.do_cfg(cfg);
// connect all the virtual interfacess.
drvr.intf =intf;
rcvr_0.intf =intf;
rcvr_1.intf =intf;
rcvr_2.intf =intf;
rcvr_3.intf =intf;
// connect all the TLM interfacess

gen.put_port =gen2drv.blocking_put_export;
drvr.get_port =gen2drv.blocking_get_export;
drvr.put_sb =drv2sb.blocking_put_export;
rcvr_0.put_sb =rcv2sb.blocking_put_export;
sb.drv_port =drv2sb.blocking_get_export;
sb.rcv_port =rcv2sb.blocking_get_export;
endfunction
taskexecute;
wait(sb.no_rcv_pkt ==10);
terminate;
endtask
taskterminate;
$swrite(msg,"\n\n Total number of packets sent %d, Total no of packet recieved
%d\n\n",sb.no_drv_pkt,sb.no_rcv_pkt);
avm_report_message("env",msg);
endtask
endclass
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Index
Avm Introduction
Dut Specification
Packet is inherited from avm_tranction. 3 methods copy,comp and convert2string Rtl
definition. convert2string method returns a string which describes the transaction. Top
comp method is for determining equality of two objects. clone method returns a Interface
Environment
handle to a newly allocated copy of this(object).
Packet
Packet Generator
CODE:packet.sv
Configuration
Driver
Reciever
ìfndefPKT_CLASS
Scoreboard
`definePKT_CLASS
PACKET
DPI

input is what keeps
with time!
UVM Tutorial
VMM Tutorial
OVM Tutorial
//Define the enumerated types for packet payload size type

typedefenum{SMALL_P,MEDIUM_P,LARGE_P}payload_size_t ;
typedefenum{GOOD_P,BAD_P}packet_kind_t;
Easy Labs : SV
Easy Labs : UVM
classpacket extendsavm_transaction ;
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
stringmsg;
VMM Ethernet sample randpayload_size_t payload_size;//Control field for the payload size
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
byteuid;// Unique id field to identify the packet

randbit[7:0]len;
randbit[7:0]da;
randbit[7:0]sa;

randbyteparity;
staticbit[7:0]mem [3:0];
constraintaddr_8bit {(da
==mem[2]);}
==mem[3])||(da
==mem[0])||(da
==mem[1])||(da
// Constrain the len according the payload_size control field

constraintlen_size {
RVM Switch TB
(payload_size ==SMALL_P)->leninside{[5:6]};
RVM Ethernet sample (payload_size ==MEDIUM_P)->leninside{[7:8]};
(payload_size ==LARGE_P)->leninside{[9:10]};}
Switch TB
Specman E
Interview Questions
// Control field for GOOD/BAD

randpacket_kind_t packet_kind;
// May be assigned either a good or bad value,parity will be calculated in
portrandomize
constraintparity_type {
(packet_kind ==GOOD_P)->parity ==0;
(packet_kind ==BAD_P )->parity !=0;}
// define clone as per avm
functionpacket clone();
http://testbench.in/AV_07_PACKET.html[9/26/2012 2:35:59 PM]
packet t =new();
t.copy(this);
returnt;
endfunction
functionvoiddo_cfg(Configuration cfg);
this.mem[0]=cfg.da_port[0];
$swrite(msg," packet new ::%x %x %x %x",mem[0],mem[1],mem[2],mem[3]);
avm_report_message("packet",msg);
endfunction
// as per avm, define convert2string

functionstringconvert2string;
stringpsdisplay;
inti;
$write(psdisplay,"da:0x%hsa:0x%hlen:0x%h \n",this.da,this.sa,this.len,);
for(i
=0;i <this.len;i++)$write(psdisplay,"%s
data[%0d]
0x%h
\n",psdisplay,i,data[i]);
$write(psdisplay,"%s parity :0x%h \n",psdisplay,this.parity);
convert2string =psdisplay;
endfunction
functionvoidcopy(inputpacket to =null);

if(!$cast(this,to))
begin
avm_report_error("packet","Attempting to copy to a non packet instance");
return;
end
this.da =to.da;
this.sa =to.sa;
this.len=to.len;
this.data=new[to.len];
foreach(data[i])
begin
this.data[i]=to.data[i];
end
this.parity =to.parity;
return;
endfunction
//unpacking function for converting recived data to class properties

functionvoidunpack(bytebytes[$]);
$swrite(msg," bytes size %d",bytes.size());
void'(bytes.pop_front());
da =bytes.pop_front();
sa =bytes.pop_front();
len=bytes.pop_front();
$swrite(msg,"recieved
packet::da:0x%hsa:0x%hlen:0x%h
\n",this.da,this.sa,this.len);
avm_report_message("packet",msg);
data=new[len-4];
parity =bytes.pop_back();
foreach(data[i])data[i]=bytes.pop_front();
endfunction
functionbyteparity_cal();
integeri;
byteresult ;
result =result ^this.da;
result =result ^this.sa;
result =result ^this.len;
for(i =0;i<this.len;i++)
begin
result =result ^this.data[i];
end
returnresult;
endfunction
//post randomize fun to cal parity

data=new[len];
foreach(data[i])
data[i]=$random();
parity =parity ^parity_cal();
endfunction
functionvoidpre_randomize();
data.delete();
endfunction
// define comp a per avm
functionbitcomp(inputpacket cmp,inputpacket to);
stringdiff;
bitcompare;
if(!$cast(cmp,to))
begin
avm_report_error("packet","Attempting to compare to a non packet instance");
compare=0;
returncompare;
end

if(to.da !=cmp.da)
begin
$swrite(diff,"Different DA values: %b != %b",to.da,cmp.da);
compare=0;
avm_report_error("packet",diff);
returncompare;
end
if(to.sa !=cmp.sa)
begin
$swrite(diff,"Different SA values: %b != %b",to.sa,cmp.sa);
compare=0;
returncompare;
end
if(to.len!=cmp.len)
begin
$swrite(diff,"Different LEN values: %b != %b",to.len,cmp.len);
compare=0;
returncompare;
end
foreach(data[i])
if(to.data[i]!=cmp.data[i])
begin
$swrite(diff,"Different
data[%0d]
values:
0x%h
0x%h",i,to.data[i],cmp.data[i]);
compare=0;
returncompare;
end
if(to.parity !=cmp.parity)
begin
$swrite(diff,"Different PARITY values: %b != %b",to.parity,cmp.parity);
compare=0;
returncompare;
end
return1;
endfunction
functionintunsignedbyte_pack(reflogic[7:0]bytes[],
inputintunsignedoffset ,
inputint kind);
byte_pack =0;
bytes =new[this.len+4];
bytes[0]=this.da;
bytes[1]=this.sa;
bytes[2]=this.len;
foreach(data[i])
bytes[3+i]=data[i];
bytes[this.len+3]=parity;
byte_pack =this.len+4;
endfunction
endclass
èndif
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!=
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TUTORIALS
PACKET GENERATOR
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Use a class to build packet generator. Make an instance of this class. Packet generator
generator generates packets and sends to driver using gen2drv channel. gen2drv is
used to connect the packet generator and driver. Packet generator generates the
packet and randomizes the packet. Then the packet is put into gen2drv channel.
Always check whether the randomization is sucessful and display a message.
CODE: gen.sv
classgenerator extendsavm_verification_component;
// define tml interface for communication
tlm_blocking_put_if#(packet)put_port;
VMM Tutorial
taskrun;
OVM Tutorial
packet pkt;
Easy Labs : SV
Easy Labs : UVM
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begin
pkt =new();
Easy Labs : VMM
if(!pkt.randomize())
avm_report_error("genarator"," randomiation failed\n");
else
VMM Ethernet sample avm_report_message("generator"," randomization done\n");
put_port.put(pkt);
end
endtask
Verilog
AVM Switch TB
Verification
Verilog Switch TB
endclass
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/AV_08_PACKET_GENERATOR.html[9/26/2012 2:36:08 PM]
Index
Avm Introduction
Dut Specification
Rtl
Top
Interface
Environment
Packet
Packet Generator
Configuration
Driver
Reciever
Scoreboard
input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Index
Avm Introduction
Dut Specification
Confoguration class is inherited from avm_verification_component. This class Rtl
Top
genarates addresses to configure the dut 4 output ports.
Interface
Environment
CODE:CFG.SV
Packet
Packet Generator
ìfndefCFG_CLASS
Configuration
`defineCFG_CLASS
Driver
classConfiguration extendsavm_verification_component;
Reciever
randbit[7:0]da_port [4];
Scoreboard
stringmsg;

constraintda_ports
{(da_port[0]!=da_port[1])&&(da_port[1]!=da_port[2])&&(da_port[2]!=da_port[3 on This section - Your
input is what keeps
]);}
CONFIGURATION
virtualfunctionvoiddisplay(stringprefix ="Test Configuration");

$swrite(msg,"
addresss
%x
%x
\n",da_port[0],da_port[1],da_port[2],da_port[3]);
avm_report_message("cfg",msg);
endfunction
Easy Labs : VMM
with time!
%x
functionnew(stringnm,virtualswitch_if intf,avm_named_component p =null);

super.new(nm,p);
avm_report_message("cfg"," Configuration Created \n");
VMM Ethernet sample endfunction
AVM Switch TB
Verilog
Verification
Verilog Switch TB
taskrun;
endtask
endclass
èndif
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/AV_09_CONFIGURATION.html[9/26/2012 2:36:17 PM]
%x
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Avm Introduction
Dut Specification
Driver is a tranctor. It is extension of avm_verification_component. Get the packets Rtl
from gen2drv chennel and drive them on to dut interface. Put the packets in to Top
Interface
drv2sb channel.
Environment
Packet
CODE:driver.sv
Packet Generator
Configuration
classdriver extendsavm_verification_component;
Driver
Reciever
virtualswitch_if intf;
Scoreboard
stringmsg;
packet pkt;
Configuration cfg;
input is what keeps
tlm_blocking_get_if#(packet)get_port;
with time!
tlm_blocking_put_if#(packet)put_sb;
DRIVER
functionnew(stringnm,Configuration cfg);
this.cfg =cfg;
super.new(nm);
endfunction
functionvoidconnect;
VMM Ethernet sample
endfunction
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
taskrun;
reset_dut();
cfg_dut();
forever
begin
get_port.get(pkt);
$display("consumer: sendging %s packet\n",pkt.convert2string);
drive(pkt);
avm_report_message("Driver","Puting packet to score board");
put_sb.put(pkt);
@(negedgeintf.clock);
end
endtask
taskdrive(packet pkt);
logic[7:0]pack[];
intpkt_len;
$swrite(this.msg,"Packed packet length %d \n",pkt_len);
avm_report_message("Driver",this.msg);
begin
http://testbench.in/AV_10_DRIVER.html[9/26/2012 2:36:24 PM]
intf.data_status <=1;
intf.data_in <=pack[i];
end
intf.data_in <=pack[pkt_len -1];
endtask
taskreset_dut();
avm_report_message("reset_dut"," Starting... reset_dut \n");
avm_report_message("reset_dut"," Starting... reset_dut \n");
intf.data_status<=0;
intf.data_in<=0;
intf.read <=0;
intf.mem_data <=0;
intf.mem_add<=0;
intf.reset<=0;
intf.mem_en <=0;
intf.mem_rd_wr<=0;
#2intf.reset <=1;
#2intf.reset <=0;
avm_report_message("reset_dut"," Ending...reset_dut \n");
endtask
taskcfg_dut();
avm_report_message("cfg_dut"," Starting... cfg_dut \n");
begin
intf.mem_en<=1;
intf.mem_rd_wr <=1;
intf.mem_add <=i;
intf.mem_data<=cfg.da_port[i];
end
intf.mem_en<=0;
intf.mem_rd_wr <=0;
intf.mem_add <=0;
intf.mem_data<=0;
avm_report_message("cfg_dut"," Ending...cfg_dut \n");
endtask
endclass
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Index
Avm Introduction
Dut Specification
Reciever is a tranctor. Start the collection of packet from dut in the run() task and Rtl
Top
send them to score_board through rcv2sb channel.
Interface
Environment
CODE:reciever.sv
Packet
Packet Generator
classreciever extendsavm_verification_component;
Configuration
statictlm_blocking_put_if#(packet)put_sb;
Driver
virtualswitch_if intf;
Reciever
intport;
Scoreboard
stringname;
functionnew(stringnm,intport);
super.new(nm);
this.name=nm;
input is what keeps
this.port =port;
endfunction
with time!
RECIEVER
Easy Labs : UVM
taskrun;
bytereceived_bytes[$];
packet rcv_pkt,pkt;
Easy Labs : VMM
pkt =new();
AVM Switch TB
forever
VMM Ethernet sample begin
@(posedge(intf.ready[port]));
while(intf.ready[port])begin
intf.read <=4'b0001<<port;
Verilog
Verification
received_bytes.push_back(intf.data_out[port]);
Verilog Switch TB
end
intf.read <=4'h0;
Basic Constructs
Easy Labs : OVM
Switch TB
pkt.unpack(received_bytes);
received_bytes ={};
rcv_pkt =newpkt;
put_sb.put(rcv_pkt);
end
RVM Switch TB
endtask
OpenVera
Constructs
RVM Ethernet sample
endclass
Specman E
Interview Questions
http://testbench.in/AV_11_RECIEVER.html[9/26/2012 2:36:33 PM]
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Avm Introduction
Dut Specification
When the packet comes from reciever, the scoreboard gets the expected packet from Rtl
Top
drv2sb channel and compare them.
Interface
Environment
Packet
CODE:scoreboard.sv
Packet Generator
ìfndefSB_CLASS
Configuration
`defineSB_CLASS
Driver
Reciever
classscoreboard extendsavm_verification_component;
Scoreboard
packet exp_pkt,drv_pkt;
packet exp_que[$];
packet rcv_pkt;
input is what keeps
integerno_drv_pkt;
with time!
integerno_rcv_pkt;
stringmsg;
tlm_blocking_get_if#(packet)drv_port;
tlm_blocking_get_if#(packet)rcv_port;
SCOREBOARD
functionnew();
super.new("Scoreboard");
no_drv_pkt =0;
VMM Ethernet sample no_rcv_pkt =0;
Verilog
avm_report_message("sb","Scoreboard created");
endfunction
Verification
Verilog Switch TB
taskrun();
Basic Constructs
avm_report_message("sb"," STARTED main task ");

fork
forever
OpenVera
begin
Constructs
drv_port.get(drv_pkt);
this.no_drv_pkt++;
Switch TB
$swrite(msg,"Recieved
packet
no
from
RVM Switch TB
queue%d\n",no_rcv_pkt,exp_que.size());
RVM Ethernet sample avm_report_message("sb",msg);
exp_que.push_front(drv_pkt);
Specman E
end
join_none
Interview Questions
forever
begin
rcv_port.get(rcv_pkt);
this.no_rcv_pkt++;
exp_pkt =exp_que.pop_back();
$swrite(msg,"Recieved packet no %d\n",no_rcv_pkt);
avm_report_message("sb",msg);
if(rcv_pkt.comp(rcv_pkt,exp_pkt))
avm_report_message("sb"," Packet matched ");
http://testbench.in/AV_12_SCOREBOARD.html[9/26/2012 2:36:42 PM]
driver
%d
size
of
else
avm_report_error("sb"," Packet mismatch ");
end
endtask
endclass
èndif
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Index
Introduction
Linear Tb
SystemVerilog
File Io Tb
Test Bench Overview
Verification
Constructs
TestBench must verify that the design does everything it is supposed to do anddoes Task Based Tb
not do anything it is not supposed to do. There are different styles of writing Self Checking Testbench
Interface
testbenchs. These styles are called methodologies. Methodologies states how to verify Verification Flow
OOPS
Clock Generator
complex scenarios to what file name you should use also.
Simulation
Randomization
Functional Coverage
Store And Restore
Assertion
DPI
Stimulus Generation
UVM Tutorial
A Myth
VMM Tutorial
Race Condition
Checker
OVM Tutorial
Task And Function
Easy Labs : SV
Process Control
Easy Labs : UVM
Watchdog
Easy Labs : OVM
Easy Labs : VMM
Switchs
Debugging
AVM Switch TB
About Code Coverage
VMM Ethernet sample
Testing Stratigies
File Handling
Verilog Semaphore
Verilog
Verification
Terimination
Error Injuction
Verilog Switch TB
Basic Constructs
Regression
OpenVera
Tips
TUTORIALS
INTRODUCTION
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_01_INTRODUCTION.html[9/26/2012 2:36:52 PM]

input is what keeps
with time!
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TUTORIALS
SystemVerilog
LINEAR TB
Verification
Linear Testbench:
Constructs
VMM Tutorial
Linear TestBench approach to TestBench creation is especially bad for performance.

As this is simplest, fastest and easiest way of writing testbenchs, this became novice
verification engineer choice. Small models like simple state machine can be verified
with this approach. The following code snippet shows linear testbench. Development
time increases exponentially as the number of scenarios increases. It is not possible to
list all possible input combinations if the number input vectors increases.Just
imagine how many inputs are needed to test simple 32 bit adder. Usually Outputs are
checked using waveform viewer. As the number of outputs increases, analysis of all
the outputs is nightmare. There is no controllability in this method. To test another
scenario like read operation, full test bench need to be coded. The simulator must
evaluate and schedule a very large number of events. This reduces simulation
performance in proportion to the size of the stimulus process.
OVM Tutorial
Linear test bench for a memory model.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Easy Labs : SV
initial
begin
#10read_write
Easy Labs : OVM
#10read_write
Easy Labs : VMM
#10read_write
#10read_write
AVM Switch TB
#10read_write
Easy Labs : UVM
=1;address
=1;address
=1;address
=1;address
=1;address
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_02_LINEAR_TB.html[9/26/2012 2:36:59 PM]
=100;data=10;
=101;data=11;
=102;data=12;
=103;data=13;
=104;data=14;
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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Search
TUTORIALS
FILE IO TB
SystemVerilog
File I/O Based Testbench
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Another way of getting the Stimulus is get the vectors from an external file. The
external vector file is generally formatted so that each value in the file represents
either a specific input pattern .Verilog HDL contains the $readmemb or $readmemh
system tasks to do the file read if the file data is formatted in a specific way using
either binary or hexadecimal data. TestBench is like just an interface between
external vector source and DUT. Sometimes outputs are also to written to external
files. For example, to verify a a dsp algorithm implemented asDUT, get the input
vectors from matlab tool and send the outputs to a file and then compare the outputs
of the matlab for the same algorithm.
Fallowing example illustrates how to initialize a memory array from data stored as
hexadecimal values in a data file, Simulate this file directly to see the results.
Note: The data file must reside in the same directoryas the .v file for the module in
this example.
EXAMPLE: verilog file
modulereadmemh_demo;
Easy Labs : OVM
reg[31:0]Mem [0:11];
initial$readmemh("data.txt",Mem);
AVM Switch TB
VMM Ethernet sample integerk;

initialbegin
#10;
$display("Contents of Mem after reading data file:");
Verilog
for(k=0;k<6;k=k+1)$display("%d:%h",k,Mem[k]);
Verification
end
Easy Labs : VMM
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
endmodule
EXAMPLE: data.txt file
234ac
23ca5
b3c34
23a4a
234ca
b3234
RESULT:
0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234
Reading or writing to files during simulation is costly to performance, because the

simulator must halt and wait while the OS completes each transaction with the file
system. One way to improve performance is to replace ASCII vector files with a
constant table in HDL itself. Do this using Perl script.
http://testbench.in/TB_03_FILE_IO_TB.html[9/26/2012 2:37:08 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
reg[31:0]Mem [0:11];
ìnclude"data.v"
integerk;
initialbegin
#10;
end
endmodule
EXAMPLE: data.v file
initial
begin
Mem[0]=32'h234ac;
Mem[1]=32'h23ca5;
Mem[2]=32'hb3c34;
Mem[3]=32'h23a4a;
Mem[4]=32'h234ca;
Mem[5]=32'hb3234;
end
RESULT:
0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234
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TUTORIALS
STATE MACHINE BASED TB
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
By definition, a stat machine TestBench used state machine to generate input vector
and drive it to the I/O ports of the design. One testbench can have multiple state
machines each handling a different functionality. To achieve the quality of
verification required by today's complex designs, testbench must be robust. State
machine based verification cannot support todays verification needs. A state machine
based testbench is hardly seen nowadays.
always@(posedgeclk)
case(state)
Assertion
READ:if(i <No_of_reads)
begin
DPI
read_write =0;
UVM Tutorial
address =$random;
i=i+1;
VMM Tutorial
end
OVM Tutorial
else
$finish
Easy Labs : SV
WRITE:if(j <no_of_writes)
Easy Labs : UVM
begin
read_write =1;
Easy Labs : OVM
address =$random;
Easy Labs : VMM
data=$random;
j=j+1;
AVM Switch TB
end
VMM Ethernet sample else
state =READ;
endcase
Verilog
Functional Coverage
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Now lets see how to develop our scenarios:

Only 10 write operations,
initial
begin
No_of_reads =0;
No_of_writes =10;
end
RVM Switch TB
RVM Ethernet sample Only 10 read operations,
Specman E
Interview Questions
initial
begin
No_of_reads =10;
No_of_writes =0;
end
With the above style of testbench, the controllability is less and hard to change the
code to add new features like to convert the above code to alternate read and write
operation, its very difficult.
http://testbench.in/TB_04_STATE_MACHINE_BASED_TB.html[9/26/2012 2:37:17 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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Search
TUTORIALS
TASK BASED TB
SystemVerilog
Task And Function Based Tb:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Task based verification is more flexible over all the above approaches. All the
operations in are done using takes and functions. The task based BFM is extremely
efficient if the device under test performs many calculations. Each task or function
focuses on one single functionality. Verification of DUT using the task based testbench
is faster. Using tasks makes it possible to describe structural testbenchs. These tasks
can be ported without much effort.
EXAMPLE:
taskwrite(inputintegerdata,inputintegeraddress);
begin
@(posedgeclock);
read_write =1;
address =$random;
data=$random;
end
endtask
Easy Labs : UVM
taskread(inputintegeraddress,outputintegerdata);
begin
@(posedgeclock);
Easy Labs : VMM
read_write =0;
address =$random;
AVM Switch TB
// Do some operation to get data
endtask
Easy Labs : OVM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Now lets see how to develop the senarious.

1) 10 write operations.
initial
repeat(10)
write($random,$random);
2) 10 read operations
initial
repeat(10)
read($random,data);
3) Alternate read and write operations.
initial
repeat(10)
begin
write($random,$random);
read($random,data);
end
4) Do the write and read the same location.
initial
begin
write(10,20);
read (10,data);
http://testbench.in/TB_05_TASK_BASED_TB.html[9/26/2012 2:37:28 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
end
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Search
TUTORIALS
SELF CHECKING TESTBENCH
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Two important aspects of todays functional verification are quality and re usability.
Design engineers have made design reuse to reduce development time and effort in
designing an ASIC. Significant design blocks are reused from one project to the next.
The lack of flexible verification environments that allow verification components
reuse across ASIC design projects keep the verification cost very high. Considering the
fact that verification consumes more resources than design does , it would be of
great value to build verification components that are modular and reusable. When a
design is passing all the tests in the verification environment, it has not been possible
to know whether the design under verification is correct, and may be safely tapedout, or whether the verification environment is just incapable of finding any bugs that
may still remain in DUT.
ADVANTAGES:
Speeds up verification and results in early tape out of the chip.
Less man power is required, by which the over all cost of the project will be low.
Environment can be reusable.
Easy tracking of verification progress(functional coverage).
Developing self checking testbench is very interesting.
Todays functional verification flow mainly contains following steps:
Generate the stimulus vectors.

Send the Stimulus to the DUT.
VMM Ethernet sample Monitor the response generated by the DUT.
Verify the response generated.
Generate report about the DUT performance.
Some kind of feedback to show the quality of testbench.
Verilog
AVM Switch TB
Verification
Verilog Switch TB
Basic Constructs
OpenVera
A test-bench is built to functionally verify the design by providing meaningful

scenarios to check that given certain input, the design performs to specification. Test
bench provides the stimulus to exercise DUT code. A self checking testbench is a
intelligent testbench which does some form of output sampling of DUT and compares
the sampled output with the expected outputs. A simulation environment is typically
composed of several types of components:
Constructs
Switch TB
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Self Checking
Testbench
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Stimulus Generator:
In order to test the model of some design, a verification engineer must apply test
patterns to the input ports and observe the output ports over time to decide whether
http://testbench.in/TB_06_SELF_CHECKING_TESTBENCH.html[9/26/2012 2:37:37 PM]
the inputs were transformed to the expected outputs. The generator component
generates input vectors. For simple memory stimulus generator generates read, write
operations, address and data to be stored in the address if its write operation.
Modern generators generate random, biased, and valid stimuli. In verilog $random
does this job. The randomness is important to achieve a high distribution over the
huge space of the available input stimuli. To this end, users of these generators
intentionally under-specify the requirements for the generated tests. It is the role of
the generator to randomly fill this gap. This mechanism allows the generator to
create inputs that reveal bugs not being searched for directly by the user. Generators
also bias the stimuli toward design corner cases to further stress the logic. Biasing and
randomness serve different goals and there are tradeoffs between them, hence
different generators have a different mix of these characteristics. Since the input for
the design must be valid and many targets should be maintained, many generators use
the Constraint Satisfaction Problem technique to solve the complex testing
requirements. SystemVerilog, Vera, SystemC and Specman have " constraints " to
specify The legality of the design inputs. In verilog ,to constrain the memory address
to be between 0 to 63, {$random} % 64 is used. The model-based generators use this
model to produce the correct stimuli for the target design. The stimulus generator
should be intelligent and easily controllable.
Bus Functional Models
The Bus Functional Model (BFM) for a device interacts with the DUT by both driving
and sampling the DUT signals. A bus functional model is a model that provides a task
or procedural interface to specify certain bus operations for a defined bus protocol.
For a memory DUT, transactions usually take the form of read and write operations.
Bus functional models are easy to use and provide good performance. It has to follow
the timing protocol of the DUT interface. BFM describes the functionality and provides
a cycle accurate interface to DUT. It models external behavior of the device. For re
usability, the implementation of the BFM functionality should be kept as independent
of the communication to the BFM as it can be.
Driver
Driver is a types of BFM. The drivers translate the stimuli produced by the generator
into the actual inputs for the design under verification. Generators create inputs at a
high level of abstraction; namely, as transactions like read write operation. The
drivers convert this input into actual design inputs which is at a low level like bits ,as
defined in the specification of the designs interface. If the generator generates read
operation, then read task is called, in that, the DUT input pin "read_write" is asserted.
Reciver
Receiver is also a type of BFM. The output of the DUT is collected. The output of the
DUT is available in a low level format. Let<92>s take a packet protocol. The interface
has "start of the packet" and "end of packet" signal to indicate the packet arrival. The
receiver starts collecting the packet looking at the signal "start of packet" and does
this job until "end of the packet".
Protocol Monitor:
Protocol monitor do not drive any signals, monitor the DUT outputs, identifies all the
transactions and report any protocol violations. The monitor converts the state of the
design and its outputs to a transaction abstraction level so it can be stored in a 'scoreboards' database to be checked later on. Again let<92>s take a packet protocol. The
monitor gets the information from the packet like, length of the packet, address of
the packet etc.
Scoreboard:
Scoreboard is sometimes referred as storage structure. The stimulus generator
generated the random vectors. These are derived to the dut. These stimulus are
stored in scoreboard until the output comes out of the DUT. When a write operation is
done on a memory with address 101 and data 202,asfter some cycles, if a read is done
at address 101,what should be the data?.The score board recorded the address and
data when write operation is done. Get the data stored at address of 101 in
scoreboard and compare with the output of the DUT in checker. Scoreboard also has
expected logic if needed. Take an 2 input and gate. The expect logic does the " and "
operation on the two inputs and stores the output.
Checker:
Checker is part of score board. The checker validates that the contents of the 'scoreboards' are legal. There are cases where the generator creates expected results, in
addition to the inputs. In these cases, the checker must validate that the actual
results match the expected ones.
Coverage:
Coverages are of two types, Functional coverage and code coverage. Code coverage is
not part of Testbench. Functional Coverage is part of test bench. Functional coverage
cannot be done in Verilog.
Code Coverage:
Code coverage, in short, is all about how thoroughly your tests exercise your code
base. The intent of tests, of course, is to verify that your code does what it's
expected to, but also to document what the code is expected to do. Taken further,
code coverage can be considered as an indirect measure of quality -- indirect because
we're talking about the degree to what our tests cover our code, or simply, the
quality of tests. In other words, code coverage is not about verifying the end product's
quality.
Statement coverage: measures the number of statements executed .
Branch coverage: measures the expressions and case statements that affect the
control flow of the HDL execution
Condition coverage: breaks down the condition on the branch into elements that make
the result true or false
Toggle coverage: counts low-to-high and high-to-low transitions
Finite State Machine: state and state transition coverage
Functional Coverage:
Functional is the metric which shows how much we have verified. It shows how many
possible scenarios are possible and how many are covered. Take a memory. If the
memory address is 64 byte depth, and if the address is generated randomly, we are
not sure that every location is covered. Functional coverages gives report how many
address are possible and how may we have covered.
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Index
Introduction
Linear Tb
SystemVerilog
File Io Tb
Verification of a design usually follows the flow synopsis below.
Verification
Constructs
Task Based Tb
Planning:
Interface
After the preliminary design specification is completed, the first verification phase is Verification Flow
OOPS
Clock Generator
started Verification planning.
Simulation
Randomization
Verification
planning
consists,
following
main
tasks.
Functional Coverage
Store And Restore
Assertion
1) Feature extraction from design specification.
2)
Listing
out
Testcases.
DPI
Stimulus Generation
3) Verification Environment Architecture plan.
UVM Tutorial
A Myth
VMM Tutorial
Race Condition
Feature Extraction:
Checker
OVM Tutorial
Task And Function
Extract
all
the
features
of
the
DUT
from
the
design
specification.
Easy Labs : SV
Mainly the features are configuration, Interface protocol, data processing protocol Process Control
Easy Labs : UVM
and status communication.
Watchdog
Categorizing
all
this
features
according
to
where
these
features
are
verified.
Easy Labs : OVM
What are the features covered by random stimulus generation?
Easy Labs : VMM
Switchs
What are the features verifiable by writing separate test cases?
Debugging
What features assertions can catch?
AVM Switch TB
About Code Coverage
What features the coverage module contains?
VMM Ethernet sample
Testing Stratigies
File Handling
Verilog Semaphore
Verification Environment Architecture Plan:
Verilog
Verification
plan
contains
the
structure
of
the
Verification
environment.
Based
on
the
Verification
Terimination
project requirements, following points are considered while Architecture is built.
Error Injuction
Verilog Switch TB
Reusability, Is it a verification IP. What blocks the verification language can support.
Controllability of the stimulus generation etc.
Basic Constructs
Next phase is to build the Verification environment.
Regression
Final phase is to verify the DUT using the environment built.
OpenVera
Tips
TUTORIALS
VERIFICATION FLOW
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_07_VERIFICATION_FLOW.html[9/26/2012 2:37:44 PM]

input is what keeps
with time!
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Search
TUTORIALS
CLOCK GENERATOR
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Clocks are the main synchronizing events to which all other signals are referenced. If
the RTL is in verilog, the Clock generator is written in Verilog even if the TestBench is
written in other languages like Vera, Specman or SystemC. Clock can be generated
many ways. Some testbenchs need more than one clock generator. So testbench need
clock with different phases some other need clock generator with jitter. The very first
transition of clock at time zero may be perceived as a transition because clock has an
unknown value before time zero and gets assigned to a value at time zero. How this
time zero clock transition is perceived is simulator dependent, and thus care must be
taken.
Fallowing examples show simple clock generators with 50% duty cycles.
EXAMPLE:
initialclk =0;
always#10clk =~clk;
EXAMPLE:
always
begin
clk =0;
#10;
clk =1;
#10;
end
Verilog
Verification
Verilog Switch TB
Basic Constructs
always
begin
clk =0;
forever#10clk =~clk;
end
Different testbenchs need different clock periods. It is beneficial to use parameters to
represent the delays, instead of hard coding them. For example, to generate a clock
starting with zero that has a 50% duty cycle, the following code can be used:
OpenVera
EXAMPLE:
moduleTb();
regclock;
Switch TB
integerno_of_clocks;
RVM Switch TB
RVM Ethernet sample parameterCLOCK_PERIOD=5;

initialno_of_clocks =0;
initialclock =1'b0;
Specman E
always#(CLOCK_PERIOD/2)clock =~clock;
Interview Questions
always@(posedgeclock)
no_of_clocks =no_of_clocks +1;
initial
begin
#50000;
$display("End of simulation time is %d , total number of clocks seen is %d
expected is %d",$time,no_of_clocks,($time/5));
$finish;
end
Constructs
http://testbench.in/TB_08_CLOCK_GENERATOR.html[9/26/2012 2:37:54 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
endmodule
RESULTS:
End of simulation time is 50000 , total number of clocks seen is 12500 expected is
10000
Total number of clocks are 12500 and the expected are 1000.There are 25 % of more
clocks than expected. The reason is half clock period is 2 insted of 2.5.
Make sure that CLOCK_PERIOD is evenly divided by two. If CLOCK_PERIOD is odd, the
reminder is truncated the frequency of the clock generated in not what expected. If
integer division is replaced by real division, the result is rounded off according to the
specified resolution.
EXAMPLE:
moduleTb();
regclock;
parameterCLOCK_PERIOD=5;
initialclock =1'b0;
always#(CLOCK_PERIOD/2.0)clock =~clock;
initial
begin
#50000;
$display("End of simulation time is %d , total number of clocks seen is %d
$finish;
end
endmodule
RESULTS:
10000
Look at the result, total number of clock seen are 8333, where the rest of the clocks
have gone? There is some improvement than earlier example. But the results are not
proper. Well that is because of `timeprecision. By default time precision is 1ns/1ns.
Half of the clock period is 2.5 . It is rounded of to 3 . So total time period is 6 and
resulted 8333 clocks( 50000/6) instead of (50000/5). 2.5 can be rounded to 3 or 2 .
LRM is specific about this. So try out this example on your tool. You may see 12500.
Timescale And Precision Enlightment:
Delay unit is specified using 'timescale, which is declared as `timescale time_unit base
/ precision base
--time_unit is the amount of time a delay of 1 represents. The time unit must be 1 10
or 100
--base is the time base for each unit, ranging from seconds to femtoseconds, and
must be: s ms us ns ps or fs
--precision and base represent how many decimal points of precision to use relative
to the time units.
Time precision plays major role in clock generators. For example, to generate a clock
with 30% duty cycle and time period 5 ns ,the following code has some error.
EXAMPLE:
`timescale1ns/100ps
moduleTb();
regclock;
parameterCLOCK_PERIOD=5;
initialclock =1'b0;
always
begin
#(CLOCK_PERIOD/3.0)clock =1'b0;
#(CLOCK_PERIOD-CLOCK_PERIOD/3.0)clock =1'b1;
end
initial
begin
#50000;
$display(" End of simulation time is %d , total number of clocks seen is %d
$finish;
end
endmodule
RESULTS:
10000
Now CLOCK_PERIOD/3.0 is 5/3 which is 1.666. As the time unit is 1.0ns, the delay is
1.666ns. But the precision is 100ps. So 1.666ns is rounded to 1.700ns only.
and when (CLOCK_PERIOD - CLOCK_PERIOD/3.0) is done, the delay is 3.300ns instead
of 3.333.The over all time period is 5.If the clock generated is implemented without
taking proper care, this will be the biggest BUG in testbench.
All the above clock generators have hard coded duty cycle. The following example
shows the clock generation with parameterizable duty cycle. By changing the
duty_cycle parameter, different clocks can be generated. It is beneficial to use
parameters to represent the delays, instead of hard coding them. In a single
testbench, if more than one clock is needed with different duty cycle, passing duty
cycle values to the instances of clock generators is easy than hard coding them.
NOTE: Simulation with `timescale 1ns/1ns is faster than `timescale 1ns/10ps
A simulation using a `timescale 10ns/10ns and with `timescale 1ns/1nswill take
same time.
EXAMPLE:
parameterCLK_PERIOD=10;
parameterDUTY_CYCLE=60;//60% duty cycle
parameterTCLK_HI=(CLK_PERIOD*DUTY_CYCLE/100);
parameterTCLK_LO=(CLK_PERIOD-TCLK_HI);
regclk;
initial
clk =0;
always
begin
#TCLK_LO;
clk =1'b1;
#TCLK_HI;
clk =1'b0;
end
Make sure that parameter values are properly dividable. The following example
demonstrates how the parameter calculations results. A is 3 and when it is divided by
2,the result is 1.If integer division is replaced by real division, the result is rounded
off according to the specified resolution. In the following example is result of real
number division.
EXAMPLE:
moduleTb();
parameterA =3;
parameterB =A/2;
parameterC =A/2.0;
initial
begin
$display(" A is %e ,B is %e ,C is %e ",A,B,C);
end
endmodule
RESULTS:
A is 3.000000e+00 ,B is 1.000000e+00 ,C is 1.500000e+00
Often clockgenerators are required to generate clock with jitter.The following is

simple way to generate clock with jitter.
EXAMPLE:
initialclock =1'b0;
alwaysclock =#1~clock;
jitter =$random()%range;
assignjittered_clock =#(jitter)clock;
With the above approace,over all clock period is increased. A better approach for
clock divider is as follows
EXAMPLE:
parameterDELAY=TIMEPERIOD/2.0-range/2.0;
initialclock =1'b0;
always
begin
jitter =$dist_uniform(seed,0,jitter_range);
#(DELAY+jitter)clock =~clock;
end
Clock dividers and multipliers are needed when more than one clock is needed to be
generated from base clock and it should be deterministic. Clock multipliers are simple
to design. A simple counter does this job. Clock division is little bit tricky. TO design a
lock divider i.e a frequency multiplier, first the time period has to be captured and
then it is used to generate another clock. With the following approach, the jitter in
the base clock is carried to derived clock.
EXAMPLE:Clock multipler with N times multiplication
initiali =0;
always@(base_clock )begin
i =i %N;
if(i ==0)derived_clock =~derived_clock;
i =i +1;
end
EXAMPLE:Clock division with N times division
initialbegin
derived_clock =1'b0;
period =10;// for initial clock
foreverderived_clock =#(period/(2N))~derived_clock;
end
always@(posedgebase_clock)
begin
T2=$realtime;
period =T2-T1;
T1=T2;
end
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TUTORIALS
SIMULATION
SystemVerilog
Simulation Steps:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Simulation is defined as the process of creating a model (i.e., an abstract

representation) of a systemin order to identify and understand those factors which
control the system and/or to predict (forecast) the future behavior of the
system.The simulation model need not reflect any understanding of the underlying
technology, and the simulator need not know that the design is intended for any
specific technology.
The underlying purpose of simulation is to shed light on the underlying mechanisms
that control the behavior of a system. More practically, simulation can be used to
predict (forecast) the future behavior of a system, and determine what you can do to
influence that future behavior. That is, simulation can be used to predict the way in
which the system will evolve and respond to its surroundings, so that you can identify
any necessary changes that will help make the system perform the way that you want
it to.
Simulation Eliminates the time-consuming need for constant physical
prototyping.Simulation should be performed during ALL stages of ASIC design.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
Macro Preprocessing:
The macro preprocessing step performs textual substitutions of macros defined with
VMM Ethernet sample `define statements, textual inclusion with ìnclude statements, and conditional
compilation by ìfdef and ìfndef statements.
Verilog
Verification
Compilation (Analyzer)
Verilog Switch TB
Checks source code to checksyntax and semantic rules. If a syntax or semantic error
occurs, then the compiler gives error message. If there are no errors , compilation
produces an internal representation for each HDL design unit.
Basic Constructs
OpenVera
Constructs
Elaboration
The elaboration process constructs a design hierarchy based on the instantiation and
configuration information in the design, establishes signal connectivity . Memory
RVM Switch TB
storage is allocated for the required signals. The elaboration process creates a
RVM Ethernet sample hierarchy of module instances that ends with primitive gates and statements.
Switch TB
Specman E
Interview Questions
Optimization:
Some tools support optimization at this level. This is optional step.
Initialization :
Initial values preset in the declarations statement are assigned to signals / variables.
Execution
Every process is executed until it suspends. Signal values are updated only after the
http://testbench.in/TB_09_SIMULATION.html[9/26/2012 2:38:03 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
process suspends. Simulator accepts simulation commands like (run, assign, watch),
which control the simulation of the system and specify the desired simulator
output.Simulation endswhen all signals have been updated and new values have
been assigned to signals. This design hierarchy is stored in a simulation snapshot. The
snapshot is the representation of your design that the simulator uses to run the
simulation.
Simulation Process :
When Simulation time is incremented, On receiving Simulation commands, a signal is
updated. All processes sensitive to that signal are placed on a Process Execution
queue. Each resumed process is executed until it suspends. Effects of the logic
changes that have occurred as a result of process execution are evaluated. Simulation
time is set to the next event in queue, or halted if simulation time is exhausted.
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TUTORIALS
INCREMENTAL COMPILATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Incremental compilation means that the compiler inspects your code, determines
which parts of the application are affected by your changes, and only recompiles the
newer files. Incremental compilation can help reduce compile time on small
applications, but you achieve the biggest gains on larger applications. The default
value of the incremental compiler option is true for most tools.
While recompiling , Incremental compilation does less work than full recompile. The
simulation doesn't show any difference , only the compilation time is
reduced.Imagine you are working with hundreds of files and U just changed one file,
During full recompilation , all the files are recompiled, where in incremental
compilation , only the file which is changed and the files which are dependent on
changed files are compiled and linked to the already compiled database.
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_10_INCREMENTAL_COMPILATION.html[9/26/2012 2:38:12 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Incremental
Compilation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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http://testbench.in/TB_10_INCREMENTAL_COMPILATION.html[9/26/2012 2:38:12 PM]
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TUTORIALS
STORE AND RESTORE
SystemVerilog
Incremental compilation means that the compiler inspects your code, determines
which parts of the application are affected by your changes, and only recompiles the
newer files. Incremental compilation can help reduce compile time on small
applications, but you achieve the biggest gains on larger applications. The default
value of the incremental compiler option is true for most tools.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
While recompiling , Incremental compilation does less work than full recompile. The
simulation doesn't show any difference , only the compilation time is
reduced.Imagine you are working with hundreds of files and U just changed one file,
During full recompilation , all the files are recompiled, where in incremental
compilation , only the file which is changed and the files which are dependent on
changed files are compiled and linked to the already compiled database.
Save and Restore saves the complete state of the simulator to a file that can be used
to restart simulation at the point of the save.
Easy Labs : SV
If multiple simulation, have same property for several hours of simulation, then the
simulation state can be shared across all the simulation. For example, In System Level
verification, it takes more than a day for operating system to boot in RTL, then the
Easy Labs : OVM
testing scenarios starts. This boot operations in RTL can be saved to a state. Using
Easy Labs : VMM
this saved state, user can directly start simulation from the saved point. Typically,
once a bug is discovered, perhaps hours or days into a simulation, the simulation
AVM Switch TB
would need to be repeated for hours or days to verify the bug fix. In Verilog, the
VMM Ethernet sample simulation state can be saved at any time and restored, to skips hours or days into a
simulation and validate a bug fix. This feature not only allows quick verification of
bug fixes, but enables much longer simulations by not rerunning previously validated
code.
Verilog
Easy Labs : UVM
Verification
Verilog Switch TB
Basic Constructs
Three system tasks $save, $restart, and $incsave work in conjunction with one
another to save the complete state of simulation into a permanent file such that the
simulation state can be reloaded at a later time and processing can continue where it
left off.
OpenVera
Constructs
EXAMPLE:
Switch TB
$save("file_name");
RVM Switch TB
$restart("file_name");
RVM Ethernet sample $incsave("incremental_file_name");
Specman E
Interview Questions
All three system tasks take a file name as a parameter. The file name has to be
supplied as a string enclosed in quotation marks.
The $save system task saves the complete state into the host operating system file
specified as a parameter.
The $incsave system task saves only what has changed since the last invocation of
$save. It is not possible to do an incremental save on any file other than the one
produced by the last $save.
The $restart system task restores a previously saved state from a specified file.
Restarting from an incremental save is similar to restarting from a full save, except
http://testbench.in/TB_11_STORE_AND_RESTORE.html[9/26/2012 2:38:22 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
that the name of the incremental save file is specified in the restart command. The
full save file that the incremental save file was based upon shall still be present, as it
is required for a successful restart. If the full save file has been changed in any way
since the incremental save was performed, errors will result.
Take care while using Pli application . Since PLI application may have some other form
of simulation snapshot storage, the simulation tool doesn't have the control on them.
$save system task, creates a checkpoint file and PLI tr routines are there to save the
PLI snapshot.
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http://testbench.in/TB_11_STORE_AND_RESTORE.html[9/26/2012 2:38:22 PM]
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TUTORIALS
EVENT CYCLE SIMULATION
SystemVerilog
Event Based Simulation
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Event simulation typically traces every signal transition and continues this until stable
state is reached. Simulation based on events in logic, which means, whenever there is
change in a input event, the output is evaluated. Means both timing and functional
information is available. With this glitches in signal changes can be observed. Event
based simulators are slow when compared with cycle based simulators.
Cycle Based Simulation
Cycles based simulator takes the advantage of the fact that most digital circuits are
synchronous in nature.Cycle simulation typically re-evaluates the state of the circuit
as a whole, once upon each external trigger, usually without evaluating any
intermediate node states. Cycle based simulator is very fast compared to event based
simulator. Disadvantage of cycle based simulator are it cannot detect glitches and
setup and hold checks cannot be done. In cycle based simulators, delays cannot be
specified.
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_12_EVENT_CYCLE_SIMULATION.html[9/26/2012 2:38:29 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
<< PREVIOUS PAGE
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http://testbench.in/TB_12_EVENT_CYCLE_SIMULATION.html[9/26/2012 2:38:29 PM]
Search
TUTORIALS
TIME SCALE AND PRECISION
SystemVerilog
Time Scale And Time Precision:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
RECAP:
Delay unit is specified using 'timescale, which is declared as `timescale time_unit base
/ precision base
--time_unit is the amount of time a delay of #1 represents. The time unit must be 1
10 or 100
--base is the time base for each unit, ranging from seconds to femtoseconds, and
must be: s ms us ns ps or fs
--precision and base represent how many decimal points of precision to use relative
to the time units.
VMM Tutorial
For example : `timescale 1 ns / 100 ps means

time values to be read as ns and to be rounded to the nearest 100 ps.
OVM Tutorial
If timescale is omitted, there is a default time scale.
Easy Labs : SV
Easy Labs : UVM
The following examples demonstrate how the time scale and time precision effect
$stime, #delay and toggling in waveform.
Easy Labs : OVM
EXAMPLE:
`timescale10ns/10ns
AVM Switch TB
moduletim();
VMM Ethernet sample regi;
Easy Labs : VMM
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
initial
begin
i=0;
#7.7212;
i=1;
$display("STATEMENT 1 :: time is ",$stime);
#7.123;
$finish;
end
endmodule
moduletry;
timedelay_time =7.721;
initialbegin
$display("STATEMENT 2 :: delay for %0t",delay_time );
end
endmodule
RESULTS:
STATEMENT 1 :: time is 8
STATEMENT 2 :: delay for 8
regi toggled at 80in waveform debugger
EXAMPLE:
`timescale10ns/1ns
moduletim();
http://testbench.in/TB_13_TIME_SCALE_AND_PRECISION.html[9/26/2012 2:38:38 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Time Scale And
Precision
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
regi;
initial
begin
i=0;
#7.7212;
i=1;
#7.123;
$finish;
end
endmodule
moduletry;
initialbegin
end
endmodule
RESULTS:
regi toggled at 77waveform debugger
EXAMPLE:
`timescale10ns/1ps
moduletim();
regi;
initial
begin
i=0;
#7.7212;
i=1;
#7.123;
$finish;
end
endmodule
moduletry;
initialbegin
end
endmodule
RESULTS:
regi toggled at 77.212in waveform debugger
In the timescale statement, the first value is the time unit and the second is the
precision for the simulation. So with the time unit, when the simulator displays a
value, you just have to multiply the value by this time unit to get the real time. With
a 10ns time unit, when a delay of #7.7212, that means that it is 77.212ns delay.
Now the second one (time precision) specify with which precision time values are
rounded. Asking for a 77.212ns delay is possible only with a 1ps precision. That's what
you can see with reg i. It toggles at 77ns with a 1ns precision and 77.212 with a 1ps
precision.
For the STATEMENT 1, $stime returns an integer scaled to timesale unit, that's why
results are always 8 which is 7.7212 rounded up to 8.
Now for STATEMENT 2, the way %t is printed depends on $timeformat. It seems that in
this case, 7.7212 is first rounded to an integer => 8 and then printed according to your
time precision.
Im not sure of this topic. If some one finds mistake in my understanding, please mail
me at gopi@testbench.in
Each module can have separate time scale. The smallest time_precision argument of
all the timescale compiler directives in the design determines the precision of the
time unit of the simulation.
Lets take an example. There are two modules. Module_1 is instance od Module_2.
Module_1 has timescale of 1 ns/1ps. Module_2 has time scale of 1ns / 10ps. The
smallest resolution is 1ps. This is taken as simulator resolution but each module
evaluates according to its precision mentioned.
Lets take another example. There are two modules. Module_1 is instance of
Module_2. Module_1 does not have any time scale. Module_2 is having time scale of
1ns/100 ps. As there is no time scale for Module_1 ,the simulator takes precision and
time unit of 100 ps i.e `timescale 100 ps/100 ps.
$Time Vs $Realtime
$time round offs the time to nearby integer where as $realtime does not. So when
you are using real valued delays, then use $realtime instead of $time , else there may
be a misunderstanding during debugging.
System Task Printtimescale
The $printtimescale system task displays the time unit and precision for a particular
module. When no argument is specified, $printtimescale displays the time unit and
precision of the module that is the current scope. When an argument is specified,
$printtimescale displays the time unit and precision of the module passed to it.
EXAMPLE:
`timescale1ms /1us
modulea_dat;
initial
$printtimescale(b_dat.c1);
endmodule
`timescale10fs /1fs
moduleb_dat;
c_dat c1 ();
endmodule
`timescale1ns /1ns
modulec_dat;
endmodule
RESULTS:
Time scale of (b_dat.c1) is 1ns / 1ns
System Task Timeformat
The $timeformat system task performs the following two functions:
1)It specifies how the %t format specification reports time information for the $write,
$display,$strobe, $monitor, $fwrite, $fdisplay, $fstrobe, and $fmonitor group of
system tasks.
2)It specifies the time unit for delays entered interactively.

The units number argument shall be an integer in the range from 0 to -15. This
argument represents the time
unit as shown in table
Unit number Time unit Unit number Time unit

01 s-8 10 ns
-1100 ms -9 1 ns
-210 ms-10100 ps
-31 ms -1110 ps
-4100 us -121 ps
-510 us-13100 fs
-61 us -1410 fs
-7100 ns -151 fs
Syntax : $timeformat(time unit, precision number, suffix string, and minimum field
width);
EXAMPLE:
`timescale1ms /1ns
modulecntrl;
initial
$timeformat(-9,5," ns",10);
endmodule
`timescale1fs /1fs
modulea1_dat;
regin1;
integerfile;
buf#10000000(o1,in1);
initialbegin
file =$fopen("a1.dat");
#00000000$fmonitor(file,"%m: %t in1=%d o1=%h",$realtime,in1,o1);
#10000000in1 =0;
#10000000in1 =1;
end
endmodule
RESULTS:
a1_dat: 0.00000 ns in1= x o1=x
a1_dat: 10.00000 ns in1= 0 o1=x
a1_dat: 20.00000 ns in1= 1 o1=0
a1_dat: 30.00000 ns in1= 1 o1=1
EXAMPLE:
`timescale1ms /1ns
modulecntrl;
initial
$timeformat(-9,5," ns",10);
endmodule
`timescale1ps /1ps
modulea2_dat;
regin2;
integerfile2;
buf#10000(o2,in2);
initialbegin
file2=$fopen("a2.dat");
#00000$fmonitor(file2,"%m: %t in2=%d o2=%h",$realtime,in2,o2);
#10000in2 =0;
#10000in2 =1;
end
endmodule
RESULTS:
a2_dat: 0.00000 ns in2=x o2=x

a2_dat: 10.00000 ns in2=0 o2=x
a2_dat: 20.00000 ns in2=1 o2=0
a2_dat: 30.00000 ns in2=1 o2=1
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TUTORIALS
STIMULUS GENERATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Verilog test benches range from simple descriptions signal values to descriptions that
test vector files and high level controllable descriptions that use functions or tasks
.There are many ways to create input test vectors to test DUT. Hardcoded value is
simplest way of creating a test vectors. This I used to do when I was in schooling. As
the number of inputs are less, this is comfortable to use.
Randomization
EXAMPLE:
moduleTb_mem();
Assertion
regclock;
regread_write;
DPI
reg[31:0]data;
UVM Tutorial
reg[31:0]address;
VMM Tutorial
initial
OVM Tutorial
begin
clock =0;
Easy Labs : SV
forever
Easy Labs : UVM
#10clock =~clock;
end
Easy Labs : OVM
Easy Labs : VMM

initial
begin
AVM Switch TB
@(negedgeclock)read_write
VMM Ethernet sample @(negedgeclock)read_write
Verilog
$finish;
Verification
end
Verilog Switch TB
initial
Basic Constructs
$monitor($time,"read_write
OpenVera
endmodule
Functional Coverage
Constructs
=1;data=4;address
=1;data=5;address
=1;data=6;address
=1;data=7;address
=1;data=8;address
%d
Switch TB
RESULT:
RVM Switch TB
20read_write = 1 ; data = 4 ; address = 1;
data
=1;
=2;
=3;
=4;
=5;
%d
address
RVM Ethernet sample 40read_write = 1 ; data = 5 ; address = 2;

Specman E
Interview Questions
Another way of getting the Stimulus is get the vectors from an external file. The
external vector file is generally formatted so that each value in the file represents
either a specific input pattern .Verilog HDL contains the $readmemb or $readmemh
system tasks to do the file read if the file data is formatted in a specific way using
either binary or hexadecimal data.
Fallowing example illustrates how to initialize a memory array from data stored as
hexadecimal values in a data file, Simulate this file directly to see the results.
Note: The data file must reside in the same directoryas the .v file for the module in
this example.
http://testbench.in/TB_14_STIMULUS_GENERATION.html[9/26/2012 2:38:47 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
EXAMPLE: verilog file

reg[31:0]Mem [0:11];
initial$readmemh("data.txt",Mem);
integerk;
initialbegin
#10;
end
endmodule
EXAMPLE: data.txt file
234ac
23ca5
b3c34
23a4a
234ca
b3234
RESULT:
0:000234ac
1:00023ca5
2:000b3c34
3:00023a4a
4:000234ca
5:000b3234
With the above approach,its not possible to list all the combinations manually if the
number of vectors get increases.
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TUTORIALS
SYSTEM FUNCTION RANDOM A MYTH
SystemVerilog
Verification
Constructs
Interface
Verilog has system function $random ,which can be used to generate random input
vectors. With this approach, we can generate values which we wouldn't have got, if
listed manually. In this topic I would like to discuss what natural things happening
behind $random and how we use it in different manners.
OOPS
EXAMPLE:
moduleTb_mem();
regclock;
Assertion
regread_write;
reg[31:0]data;
DPI
reg[31:0]address;
UVM Tutorial
initial
VMM Tutorial
begin
OVM Tutorial
clock =0;
forever
Easy Labs : SV
#10clock =~clock;
Easy Labs : UVM
end
Easy Labs : OVM

initial
Easy Labs : VMM
begin
repeat(5)@(negedgeclock)
AVM Switch TB
beginread_write =$random;data=$random;address =$random;end
VMM Ethernet sample $finish;
end
initial
Verilog
$monitor($time,"read_write
=
%d
;
data
=
%d
;
address
Verification
Verilog Switch TB
endmodule
Basic Constructs
Randomization
Functional Coverage
RESULT:
OpenVera
Constructs
20read_write
40read_write
60read_write
80read_write
=
=
=
=
0
1
1
1
;
;
;
;
data
data
data
data
=
=
=
=
3230228097 ; address = 2223298057;

112818957 ; address = 1189058957;
2302104082 ; address = 15983361;
992211318 ; address = 512609597;
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
System Function
Random A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips

RVM Switch TB
input is what keeps
RVM Ethernet sample
$random()system function returns a new 32-bit random number each time it is with time!
Switch TB
Specman E
Interview Questions
called. The random number is a signed integer; it can be positive or negative. The
following example demonstrates random generation of signed numbers.
EXAMPLE:
moduleTb();
integeraddress;
initial
begin
repeat(5)
#1address =$random;
end
http://testbench.in/TB_15_SYSTEM_FUNCTION_RANDOM_A_MYTH.html[9/26/2012 2:38:57 PM]
initial
$monitor("address = %d;",address);
endmodule
RESULT:
address
address
address
address
address
=
=
=
=
=
303379748;
-1064739199;
-2071669239;
-1309649309;
112818957;
We have seen how to generate random numbers. But the numbers range from - (2**32
-1) to 2 **32. Most of the time, the requirement don't need this range. For example,
take a memory. The address starts from 0 to some 1k or 1m.Generating a random
address which DUT is not supporting is meaningless. In verilog there are no constructs
to constraint randomization. Fallowing example demonstrated how to generate
random number between 0 to 10.Using % operation, the remainder of any number is
always between 0 to 10.
EXAMPLE:
moduleTb();
integeradd_1;
initial
begin
repeat(5)
begin
#1;
add_1 =$random%10;
end
end
initial
$monitor("add_1 = %d",add_1);
endmodule
RESULT:
add_1
add_1
add_1
add_1
add_1
=
=
=
=
=
8;
4294967287;
4294967295;
9;
9;
OOPS!...... The results are not what is expected. The reason is $random generates
negative numbers also. The following example demonstrates proper way of generating
a random number between 0 to 10. Concatenation operator returns only bit vector.
Bit vectors are unsigned, so the results are correct as we expected. Verilog also has
$unsigned systemtask to convert signed numbers to signed number. This can also be
used to meet the requirements. The following example shows the usage of
concatenation operator and $unsigned.
EXAMPLE:
moduleTb();
integeradd_2;
reg[31:0]add_1;
integeradd_3;
initial
begin
repeat(5)
begin
#1;
add_1 =$random%10;
add_2 ={$random}%10;
add_3 =$unsigned($random)%10;
end
end
initial
$monitor("add_3 = %d;add_2 = %d;add_1 = %d",add_3,add_2,add_1);
endmodule
RESULT:
add_3
add_3
add_3
add_3
add_3
=
=
=
=
=
7;add_2
7;add_2
1;add_2
7;add_2
9;add_2
=
=
=
=
=
7;add_1
7;add_1
2;add_1
8;add_1
2;add_1
=
=
=
=
=
8
4294967287
4294967295
9
9
The above example shows the generation of numbers from 0 to N.Some specification
require the range to start from non Zero number. MIN + {$random} % (MAX - MIN ) will
generate random numbers between MIN and MAX.
EXAMPLE:
moduleTb();
integeradd;
initial
begin
repeat(5)
begin
#1;
add =40+{$random}%(50-40);
$display("add = %d",add);
end
end
endmodule
RESULT:
add =
add =
add =
add =
add =
48
47
47
47
47
Nowhow to generate a random number between two ranges? The number should be
between MIN1 and MAX1 or MIN2 and MAX2.The following example show how to
generate this specification.
EXAMPLE:
moduleTb();
integeradd;
initial
begin
repeat(5)
begin
#1;
if($random%2)
add =40+{$random}%(50-40);
else
add =90+{$random}%(100-90);
$display("add = %d",add);
end
end
endmodule
RESULT:
add =
add =
add =
add =
add =
97
47
47
42
49
All the random number generates above generate numbers of 32 vector. Not always
the requirements are 32 bit .For example, to generate a 5 bit and 45 bit vector
random number, the following method can be used.
EXAMPLE:
moduleTb();
reg[4:0]add_1;
reg[44:0]add_2;
initial
begin
repeat(5)
begin
add_1 =$random;
add_2 ={$random,$random};
$display("add_1 = %b,add_2 = %b ",add_1,add_2);
end
end
endmodule
RESULTS:
add_1
add_1
add_1
add_1
add_1
=
=
=
=
=
00100,add_2
00011,add_2
00101,add_2
01101,add_2
01101,add_2
=
=
=
=
=
111101000000110000100100001001101011000001001
110110000110101000110110111111001100110001101
100100001001000000000111100111110001100000001
100010111011000011110100011011100110100111101
101111000110001111100111111011110100111111001
Some protocols require a random number which is multiple some number. For
example, Ethernet packet is always in multiples of 8bits,and PCIExpress packets are
multiples of 4byts .Look at the following example. It generates a random number
which is multiple of 3 and 5.
EXAMPLE:
moduleTb();
integernum_1,num_2,tmp;
initial
begin
repeat(5)
begin
#1;
tmp ={$random}/3;
num_1 =(tmp)*3;
tmp ={$random}/3;
num_2 =(tmp)*5;
end
end
endmodule
RESULT:
num_1 = 303379746,num_2 = -1064739195
num_1 = -2071669239,num_2 = -1309649305
num_1 = 112818957,num_2 = 1189058955
num_1 = -1295874969,num_2 = -1992863210

num_1 = 15983361,num_2 = 114806025
All the above example show that the random numbers are integers only. In verilog
there is not special construct to generate a random real number. The following
method shows the generation of random real number.
EXAMPLE:
moduleTb();
integernum_1,num_2,num_3;
realr_num;
initial
begin
repeat(5)
begin
#1;
num_1 =$random;
num_2 =$random;
num_3 =$random;
r_num =num_1 +((10)**(-(num_2)))*(num_3);
end
end
endmodule
RESULT:
r_num
r_num
r_num
r_num
r_num
=
=
=
=
=
-2.071669e+03
2641.189059e+013
976361.598336e+01
57645.126096e+02
24589.097015e+0
To generate random real number , system function $bitstoreal can also be used.
EXAMPLE:
moduleTb();
realr_num;
initial
begin
repeat(5)
begin
#1;
r_num =$bitstoreal({$random,$random});
end
end
endmodule
RESULTS:
r_num
r_num
r_num
r_num
r_num
=
=
=
=
=
1.466745e-221
-6.841798e-287
2.874848e-276
-3.516622e-64
4.531144e-304
If you want more control over randomizing real numbers in terms of sign, exponential
and mantissa, use $bitstoreal() as shown in example below. For positive numbers, use
sgn = 0 etc.
EXAMPLE:
moduleTb();
regsgn;
reg[10:0]exp;
reg[51:0]man;
realr_num;
initial
begin
repeat(5)
begin
sgn =$random;
exp =$random;
man =$random;
r_num =$bitstoreal({sgn,exp,man});
end
end
endmodule
RESULTS:
r_num
r_num
r_num
r_num
r_num
=
=
=
=
=
3.649952e+193
-1.414950e-73
-3.910319e-149
-4.280878e-196
-4.327791e+273
Sometimes it is required to generate random numbers without repetition. The random

numbers should be unique. For example, to generate 10 random numbers b/w 0 to 9
without repetition, the following logic can be used.
EXAMPLE:
moduleTb();
integernum,i,j,index;
integerarr[9:0];
regind[9:0];
reggot;
initial
begin
index=0;
for(i=0;i<10;i=i+1)
begin
arr[i]=i;
ind[i]=1;
end
for(j =0;j<10;j=j+1)
begin
got =0;
while(got ==0)
begin
index={$random()}%10;
if(ind[index]==1)
begin
ind[index]=0;
got =1;
num=arr[index];
end
end
end
end
endmodule
RESULT:
|| num= 0 || num= 3 |
Random number system function has a argument called seed. The seed parameter
controls the numbers that $random returns such that different seeds generate
different random streams. The seed parameter shall be either a reg, an integer, or a
time variable. The seed value should be assigned to this variable prior to calling
$random. For each system function, the seed parameter is an in-out parameter; that
is, a value is passed to the function
and a different value is returned.
EXAMPLE:
moduleTb();
initial
begin
for(j =0;j<4;j=j+1)
begin
seed =j;
for(i =0;i <10;i=i+1)
begin
end
$display(" ");
end
end
endmodule
RESULT:
seed is 0
| num= 8 || num= 7 || num=
|| num= 1 || num= 9 |
seed is 1
| num= 8 || num= 8 || num=
|| num= 5 || num= 5 |
seed is 2
| num= 8 || num= 1 || num=
|| num= 1 || num= 6 |
seed is 3
| num= 8 || num= 2 || num=
|| num= 3 || num= 9 |
7 || num= 7 || num= 7 || num= 7 || num= 5 || num= 2

The $random function has its own implicit variable as seed when the used is not giving
explicitly giving seed. The following example shows that seed = 0 and implicit seed
are having same sequence. It means that the implicitly taken seed is also 0.
EXAMPLE:
moduleTb();
initial
begin
seed =0;
for(j =0;j<2;j=j+1)
begin
if(j ==0)
else
$display(" No seed is given ");
for(i =0;i <10;i=i+1)
begin
if(j ==0)
else
num={$random()}%10;
end
$display(" ");
end
end
endmodule
RESULT:
seed is 0
|| num= 1 || num= 9 |
No seed is given
|| num= 1 || num= 9 |
The system functions shall always return the same value given the same seed. This
facilitates debugging by making the operation of the system repeatable. The argument
for the seed parameter should be an integer variable that is initialized by the user and
only updated by the system function. This ensures the desired distribution is achieved.
EXAMPLE:
moduleTb();
initial
begin
for(j =0;j<4;j=j+1)
begin
seed =2;
for(i =0;i <10;i=i+1)
begin
end
$display(" ");
end
end
endmodule
RESULT:
seed is 2
| num= 8 || num= 1 || num=
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 || num=
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 || num=
|| num= 1 || num= 6 |
seed is 2
| num= 8 || num= 1 || num=
|| num= 1 || num= 6 |

Seed is inout port. Random number system functionreturns a random number and
also returns a random number to seed inout argument also. The results of the
following example demonstrates how the seed value is getting changed.
EXAMPLE:
moduleTb();
initial
begin
seed =0;
for(j =0;j<10;j=j+1)
begin
end
end
endmodule
RESULT:
|
|
|
|
|
|
|
|
|
|
num=
num=
num=
num=
num=
num=
num=
num=
num=
num=
8
7
7
7
7
7
5
2
1
9
|
|
|
|
|
|
|
|
|
|
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
is
is
is
is
-1844104698
1082744015
75814084
837833973
-2034665166
-958425333
851608272
154620049
-2131500770
-2032678137
From the above results we can make a table of seed values and return values of
$random. If a seed is taken from the table, then rest of the sequence has to follow
sequence in table.
Table is as falows for initial seed 0;
| num= 8 | seed is -1844104698
| num= 7 | seed is 1082744015
| num= 7 | seed is 75814084
| num= 7 | seed is 837833973
| num= 7 | seed is -2034665166
| num= 7 | seed is -958425333
| num= 5 | seed is 851608272
| num= 2 | seed is 154620049
| num= 1 | seed is -2131500770
| num= 9 | seed is -2032678137
.
.
.
.
.
table goes on........
In the following example, the seed is 837833973, which is the 4 th seed from the
above table.
EXAMPLE:
moduleTb();
initial
begin
seed =837833973;
for(j =0;j<10;j=j+1)
begin
end
end
endmodule
RESULTS:
|
|
|
|
|
|
|
|
|
num=
num=
num=
num=
num=
num=
num=
num=
num=
7
7
5
2
1
9
8
7
9
|
|
|
|
|
|
|
|
|
seed
seed
seed
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
is
is
is
-2034665166
-958425333
851608272
154620049
-2131500770
-2032678137
-1155272804
-1634874387
-153856566
| num= 2 | seed is -970066749
From the above example we can come to conclusion that $random is not giving a
random number. It is randomizing seed and returning corresponding number for that
seed.
Total possible seed values are 4294967295. Is it possible for $random to generate all
the seeds? . Lets say ,if the seed gets repeated after 10 iterations, then after the 10
iterations, same values are repeated. So $random is circulating inside a chain of 10
numbers.
The following example demonstrates how $random misses many seeds. I tried to
display the seeds between 0 to 20 in the chain formed by initial seed of 0. Results
show that total possible seeds are 4294967295 , and number of seeds possible in seed
chain are 4030768279 , so we are missing some seeds. Look at the seeds between 0 to
20. Seed == 1 is missing.
EXAMPLE:
moduleTb();
integernum,seed,j;
reg[0:31]i;
initial
begin
i =0;
seed =1;
while(seed !=0)
begin
if(i ==0)
seed =0;
i =i +1;
num=$random(seed);
end
end
endmodule
RESULTS:
seed is zero after this number of random numbers 4030768279total numbers
available are 4294967295
Now I tried to simulate with seed== 1 . Its interesting to know that some how the
sequence is able to enter this chain which is formed with seed==0 and there is no seed
value 1 in this chain and my simulation hanged. So aborted the simulation and parter
results show that the initial seed = 1 with enter the chain formed by seed 0.
EXAMPLE:
moduleTb();
integernum,seed,j;
reg[0:31]i;
initial
begin
i =0;
seed =0;
while(seed !=1)
begin
if(i ==0)
seed =1;
i =i +1;
num=$random(seed);
end
end
endmodule
RESULTS:
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
seed
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is
is

Verilog also has other system functions to generate random numbers. Each of these
functions returns a pseudo-random number whose characteristics are described by the
function name.
Following are the Verilog random number generator system functions:
$random
$dist_chi_square
$dist_erlang
$dist_exponential
$dist_normal
$dist_poisson
$dist_t
$dist_uniform
All parameters to the system functions are integer values. For the exponential ,
Poisson , chi-square , t , and erlangfunctions, the parameters mean, degree of
freedom, and k_stage must be greater than 0 .
$dist_uniform(seed, min, max) is similar to min + {$random(seed)}%(max-min+1),the
difference is that in $dist_uniform,the distribution is uniform. $dist_uniform returns a
number between min and max. In the $dist_uniform function, the start and end
parameters are integer inputs that bound the values returned. The start value should
be smaller than the end value.

The mean parameter, used by $dist_normal, $dist_exponential, $dist_poisson, and
$dist_erlang, is an integer input that causes the average value returned by the
function to approach the value specified. The standard deviation parameter used with
the $dist_normal function is an integer input that helps determine the shape of the
density function. Larger numbers for standard deviation spread the returned values
over a wider range.
The degree of freedom parameter used with the $dist_chi_square and $dist_t
functions is an integer input that helps determine the shape of the density function.
Larger numbers spread the returned values over a wider range.
EXAMPLE:
moduleTb();
integernum_1,num_2,seed;
initial
begin
seed =10;
repeat(5)
begin
#1;
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
23,num_2
22,num_2
25,num_2
23,num_2
=
=
=
=
=
50
55
54
51
55
As I discussed $random changes its seed , Lets see whether $dist_uniform is also doing
the same.
EXAMPLE:
moduleTb();
initial
begin
seedd =10;
seedr =10;
repeat(5)
begin
#1;
$display("num_1
=
%d,num_2
=
%d",num_1,num_2,seedd,seedr);
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
20,num_2
23,num_2
25,num_2
22,num_2
=
=
=
=
=
22,seedd
20,seedd
22,seedd
21,seedd
23,seedd
=
=
=
=
=
%d,seedd
%d
seedr
690691 seedr = 690691

460696424 seedr = 460696424
-1571386807 seedr = -1571386807
-291802762 seedr = -291802762
1756551551 seedr = 1756551551
Look at the results... Its interesting to note that $random and $dist_uniform have
same seed sequence flow also.

{$random(seed)}%(max-min+1). "similar" means they have some common functionality.
$dist_uniform is having uniform distribution, $random for that range, is also uniformly
distributed. Fallowing example ,demonstrates that $dist_uniform and $random are
uniformly distributed.
EXAMPLE:
moduleTb();
integernum,seed;
initial
begin
seed =10;
repeat(6000)
begin
num=$dist_uniform(seed,20,25);
if(num==20)
num_20 =num_20 +1;
if(num==21)
num_21 =num_21 +1;
if(num==22)
num_22 =num_22 +1;
if(num==23)
num_23 =num_23 +1;
if(num==24)
num_24 =num_24 +1;
if(num==25)
num_25 =num_25 +1;
end
end
endmodule
RESULTS:
1020
EXAMPLE:
moduleTb();
integernum;
initial
begin
seed =10;
repeat(6000)
begin
num=20+({$random()}%6);
if(num==20)
num_20 =num_20 +1;
if(num==21)
num_21 =num_21 +1;
if(num==22)
num_22 =num_22 +1;
if(num==23)
num_23 =num_23 +1;
if(num==24)
num_24 =num_24 +1;
if(num==25)
num_25 =num_25 +1;
end
end
endmodule
RESULTS:
1048
{$random(seed)}%(max-min+1). "similar" means they have some difference. The
difference is that they generate different sequence.
EXAMPLE:
moduleTb();
initial
begin
seedd =10;
seedr =10;
repeat(5)
begin
#1;
end
end
endmodule
RESULTS:
num_1
num_1
num_1
num_1
num_1
=
=
=
=
=
20,num_2
20,num_2
23,num_2
25,num_2
22,num_2
=
=
=
=
=
22
20
22
21
23
Till now what we have seen is $random has uniform distribution over integer values. It
means that distribution should be uniform across all the bits in 32 bit vector also. The
following example shows that bits positions 2,3,4,11,12,13 have equal probability of
getting 0. For demonstration I showed some indexes only. Try out rest of them and
see that results is same for all the bis.
EXAMPLE:
moduleTb();
integernum;
initial
begin
seed =10;
repeat(6000)
begin
num=$random();
if(num[2]==0)
num_2 =num_2 +1;
if(num[3]==0)
num_3 =num_3 +1;
if(num[4]==0)
num_4 =num_4 +1;
if(num[11]==0)
num_11 =num_11 +1;
if(num[12]==0)
num_12 =num_12 +1;
if(num[13]==1)
num_13 =num_13 +1;
end
end
endmodule
RESULTS:
3025
The distribution is uniform for system function $random. Suppose if the requirement
is to generate random numbers for more than one variable, and all the variables
should have uniform distribution, then use different seeds for each variable.
Otherwise distribution is distributed on all the variables as overall. But for lower bits,
the distribution is same as shown in example.
EXAMPLE:
moduleTb();
integerseed;
reg[1:0]var_1,var_2,var3,var4;
integernum_2,num_3,num_1,num_0;
integercou_2,cou_3,cou_1,cou_0;
initial
begin
seed =10;
num_2 =0;num_3=0;num_1=0;num_0=0;
cou_2=0;cou_3=0;cou_1=0;cou_0=0;
repeat(40000)
begin
var_1 =$random();
var3 =$random();
var4 =$random();
var_2 =$random();
if(var_1 ==0)
num_0 =num_0 +1;
if(var_1 ==1)
num_1 =num_1 +1;
if(var_1 ==2)
num_2 =num_2 +1;
if(var_1 ==3)
num_3 =num_3 +1;
if(var_2 ==0)
cou_0 =cou_0 +1;
if(var_2 ==1)
cou_1 =cou_1 +1;
if(var_2 ==2)
cou_2 =cou_2 +1;
if(var_2 ==3)
cou_3 =cou_3 +1;
end
$display("num_2
=
%0d;num_3=
%0d;",num_2,num_3,num_1,num_0);
$display("cou_2=
%0d;cou_3=
%0d;",cou_2,cou_3,cou_1,cou_0);
end
endmodule
%0d;num_1=
%0d;cou_1=
RESULTS:
num_2 = 9984;num_3= 10059;num_1= 10002;num_0= 9955;
%0d;num_0=
%0d;cou_0=
cou_2= 10060;cou_3= 9934;cou_1= 10072;cou_0= 9934;
Use system time as seed, so the same TB simulated at different times have different
random sequences and there is more probability of finding bugs. The following is c
code useful in PLI to get system time in to verilog.
#include <stdio.h>
#include <time.h>
char *get_time_string(int mode24);
int get_systime() {
time_t seconds;
seconds = time (NULL);
return seconds;
}
Verilog 1995, every simulator has its own random number generation algorithm.
Verilog 2001 , The standard made that every simulator has to follow same algorithm.
So the same random number sequence can seen on different simulators for same
seed.
Don't expect that the same sequence is generated on all the simulators. They are only
following same algorithm. The reason is, race condition. Look at the following
example, both the statements num_1 and num_2 are scheduled to execute at same
simulation time. The order of execution is not known. Some simulators take num_1 as
the first statement to execute and some other num_2 .If the TB is built without any
race condition to $random function calls, then the same random sequence can be
generated on different simulators.
EXAMPLE:
initial
#10num_1 =$random;
initial
#10num_2 =$random;
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TUTORIALS
RACE CONDITION
SystemVerilog
Verilog is easy to learn because its gives quick results.Although many users are
telling that their work is free from race condition.But the fact is race condition is
easy to create,to understand,to document but difficult to find.Here we will discuss
regarding events which creates the race condition &solution forthat.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
What Is Race Condition?

When two expressions are scheduled to execute at same time, and if the order of the
execution is not determined, then race condition occurs.
EXAMPLE
modulerace();
wirep;
regq;
assignp =q;
initialbegin
q =1;
#1q =0;
$display(p);
end
endmodule
The simulator is correct in displaying either a 1 or a 0. The assignment of 0 to q
VMM Ethernet sample enables an update event for p. The simulator may either continue or execute the
Verilog
Verification
$display system task or execute the update for p, followed by the $display task.
Then guess what can the value of p ?
Simulate the above code in your simulator. Then simulate the following code .
Statement "assign p = q;" is changed to end of the module.
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE
modulerace();
wirep;
regq;
assignp =q;
Switch TB
initialbegin
RVM Switch TB
q =1;
RVM Ethernet sample #1q =0;
$display(p);
end
endmodule
Specman E
Interview Questions
Analyze the effect if I change the order of the assign statement.

Why Race Condition?
To describe the behavior of electronics hardware at varying levels of abstraction,
Verilog HDL has to be a parallel programming language and Verilog simulator and
language itself are standard of IEEE, even though there are some nondeterministic
events which is not mentioned in IEEE LRM and left it to the simulator algorithm,
which causes the race condition. So it is impossible to avoid the race conditions from
http://testbench.in/TB_16_RACE_CONDITION.html[9/26/2012 2:39:08 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
the language but we can avoid from coding styles.

Look at following code. Is there any race condition?
EXAMPLE:
initial
begin
in =1;
out <=in;
end
Now if you swap these two lines:
EXAMPLE
initial
begin
out <=in;
in =1;
end
Think, is there any race condition created?
Here first statement will schedule a non-blocking update for "out" to whatever "in"
was set to previously, and then "in" will be set to 1 by the blocking assignment. Any
statement whether it is blocking or nonblocking statements in a sequential block (i.e.
begin-end block) are guaranteed to execute in the order they appear. So there is no
race condition in the above code also. Since it is easy to make the "ordering mistake",
one of Verilog coding guidelines is: "Do not mix blocking and nonblocking assignments
in the same always block". This creates unnecessary doubt of race condition.
When Race Is Visible?
Sometimes unexpected output gives clue to search for race. Even if race condition is
existing in code, and if the output is correct, then one may not realize that there
exists race condition in their code. This type of hidden race conditions may come out
during the following situation.
When different simulators are used to run the same code.
Some times when the new release of the simulator is used.
Adding more code to previous code might pop out the previously hidden race.
If the order of the files is changed.
When using some tool specific options.
If the order of the concurrent blocks or concurrent statements is changed.(One
example is already discussed in the previous topics)
Some simulators have special options which reports where exactly the race condition
is exists. Linting tools can also catch race condition.
How To Prevent Race Condition?
There are many details which is unspecified between simulators. The problem will be
realized when you are using different simulators. If you are limited to design
guidelines then there is less chance for race condition but if you are using Verilog
with all features for Testbench, then it is impossible to avoid. Moreover the language
which you are using is parallel but the processor is sequential. So you cant prevent
race condition.
Types Of Race Condition
Here we will see race condition closely.
Types of race condition

Write-Write Race:
it occurs when same register is written in both the blocks.
EXAMPLE:
always@(posedgeclk)
a =1;
always@(posedgeclk)
a =5;
Here you are seeing that one block is updating value of a while another also. Now
which always block should go first. This is nondeterministic in IEEE standard and left
that work to the simulator algorithm.
Read-Write Race:
it occurs when same register is read in one block and writes in another.
EXAMPLE:
always@(posedgeclk)
a =1;
always@(posedgeclk)
b =a;
Here you are seeing that in one always block value is assign to a while simultaneously
its value is assign to b means a is writing and read parallel. This type of race
condition can easily solved by using nonblocking assignment.
EXAMPLE
always@(posedgeclk)
a <=1;
always@(posedgeclk)
b <=a;
More Race Example:
1) Function calls
EXAMPLE:
functionincri();
begin
pkt_num =pkt_num +1;
end
endfunction
always@(...)
sent_pkt_num =incri();
always@(...)
sent_pkt_num_onemore =incri();
2) Fork join
EXAMPLE:
fork
a =0;
b =a;
join
3) $random
EXAMPLE:
always@(...)
$display("first Random number is %d",$random());
always@(...)
$display("second Random number is %d",$random());

4) Clock race
EXAMPLE
initial
clk =0;
always
clk =#5~clk;
If your clock generator is always showing "X" then there is a race condition. There is
one more point to be noted in above example. Initial and always starts executes at
time zero.
5) Declaration and initial
EXAMPLE:
rega =0;
initial
a =1;
6)Testbench DUT race condition.
In test bench , if driving is done at posedge and reading in DUT is done at the same
time , then there is race. To avoid this, write from the Testbench at negedge or
before the posedge of clock. This makes sure that the DUT samples the signal without
any race.
EXAMPLE:
moduleDUT();
inputd;
inputclock;
outputq;
q =d;
endmodule
moduletestbench();
DUTdut_i(d,clk,q);
initial
begin
@(posedgeclk)
d =1;
@(posedgeclock)
d =0;
end
endmodule
The above example has write read race condition.
Event Terminology:
Every change in value of a net or variable in the circuit being simulated, as
the named event, is considered an update event. Processes are sensitive to
events. When an update event is executed, all the processes that are sensitive
event are evaluated in an arbitrary order. The evaluation of a process is
event, known as an evaluation event.
well as
update
to that
also an
In addition to events, another key aspect of a simulator is time. The term simulation
time is used to refer to the time value maintained by the simulator to model the
actual time it would take for the circuit being simulated. The term time is used
interchangeably with simulation time in this section. Events can occur at different
times. In order to keep track of the events and to make sure they are processed in the
correct order, the events are kept on an event queue, ordered by simulation time.
Putting an event on the queue is called scheduling an event.
The Stratified Event Queue

The Verilog event queue is logically segmented into five different regions. Events are
added to any of the five regions but are only removed from the active region.
1) Events that
These are the
active events.
1.1 evaluation
1.2 evaluation
1.3 evaluation
1.4 evaluation
1.5 evaluation
occur at the current simulation time and can be processed in any order.
of
of
of
of
of
blocking assignment.
RHS of nonblocking assignment.
continuous assignment.
primitives I/Os
$display or $write
2) Events that occur at the current simulation time, but that shall be processed after
all the active events are processed. These are the inactive events.
#0 delay statement.
3) Events that have been evaluated during some previous simulation time, but that
shall be assigned at this simulation time after all the active and inactive events are
processed. These are the nonblocking assign update events.
4) Events that shall be processed after all the active, inactive, and non blocking
assign update events are processed. These are the monitor events.
$strobe and $monitor
5) Events that occur at some future simulation time. These are the future events.
Future events are divided into future inactive events, and future non blocking
assignment update events.
Example : PLI tasks
The processing of all the active events is called a simulation cycle.
Determinism
This standard guarantees a certain scheduling order.
1) Statements within a begin-end block shall be executed in the order in which they
appear in that begin-end block. Execution of statements in a particular begin-end
block can be suspended in favor of other processes in the model; however, in no case
shall the statements in a begin-end block be executed in any order other than that in
which they appear in the source.
2) Non blocking assignments shall be performed in the order the statements were
executed.
Consider the following example:
initialbegin
a <=0;
a <=1;
end
When this block is executed, there will be two events added to the non blocking
assign update queue. The previous rule requires that they be entered on the queue in
source order; this rule requires that they be taken from the queue and performed in
source order as well. Hence, at the end of time step 1, the variable a will be assigned
0 and then 1.
Nondeterminism
One source of nondeterminism is the fact that active events can be taken off the
queue and processed in any order. Another source of nondeterminism is that
statements without time-control constructs in behavioral blocks do not have to be
executed as one event. Time control statements are the # expression and @
expression constructs. At any time while evaluating a behavioral statement, the
simulator may suspend execution and place the partially completed event as a
pending active event on the event queue. The effect of this is to allow the
interleaving of process execution. Note that the order of interleaved execution is
nondeterministic and not under control of the user.
Guideline To Avoid Race Condition

(A). Do not mix blocking and nonblocking statements in same block.
(B). Do not read and write using blocking statement on same variable.( avoids read
write race)
(C). Do not initialize at time zero.
(D). Do not assign a variable in more than one block.( avoids write-write race)
(E). Use assign statement for inout types of ports & do not mix blocking and
nonblocking styles of declaration in same block. It is disallow variables assigned in a
blocking assignment of a clocked always block being used outside that block and
disallow cyclical references that don't go through a non-blocking assignment. It is
require all non-blocking assignments to be in a clocked always block.
(F). Use blocking statements for combinational design and nonblocking for sequential
design. If you want gated outputs from the flops, you put them in continuous
assignments or an always block with no clock.
Avoid Race Between Testbench And Dut
Race condition may occurs between DUT and testbench. Sometimes verification
engineers are not allowed to see the DUT, Sometimes they don't even have DUT to
verify. Consider the following example. Suppose a testbench is required to wait for a
specific response from its DUT. Once it receives the response, at the same simulation
time it needs to send a set of stimuli back to the DUT.
Most Synchronous DUT works on the posedge of clock. If the Testbench is also taking
the same reference, then we may unconditionally end in race condition. So it<92>s
better to choose some other event than exactly posedge of cock. Signals are stable
after the some delay of posedge of clock. Sampling race condition would be proper if
it is done after some delay of posedge of clock. Driving race condition can be avoided
if the signal is driven before the posedge of clock, so at posedge of clock ,the DUT
samples the stable signal.So engineers prefer to sample and drive on negedge of
clock, this is simple and easy to debug in waveform debugger also.
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TUTORIALS
CHECKER
SystemVerilog
Protocol Checker
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Protocol checking is the mechanism we use to verify IO buses functionality. Protocol

checkers are created to validate whether or not the DUT is compliant with the bus
protocol. It does this by checking the clock-by-clock state of the bus interface,
verifying that the DUT drives the bus in accordance to the rules and specifications of
the bus protocol. Protocol checker verifies that DUT adheres to the interface protocol
and also verifies that the assumptions about the temporal behavior of your inputs is
correct.
TheProtocol checker is responsible for extracting signal information from the DUT
and translating it into meaningful events and status information. This information is
available to other components. It also supplies information needed for functional
coverage. TheProtocol checker should never rely on information collected by other
components such as the BFM.
Typically, the buses that are checked are external buses and may be industry
standard buses such as PCI, DDR, I2C or proprietary buses . Protocol checking may
occur at a transaction or wire level.Protocol checker does not considered the data,
as data has nothing to do with interface. The data processing protocol checking is
done in data checker which is generally in scoreboard( or tracker) .
Easy Labs : VMM
Protocol checks can be divided mainly into 3 categories:

1) Duration checks
2) Condition checks
VMM Ethernet sample 3) Temporal or Sequence Checks.
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Duration checks are the simplest since they involve a single signal.For example,the
"req signal should be high for at least 3 clocks".
Data_checker
Data checker verifies the correctness of the device output. Data checking is based on
comparing the output with the input. The data processing protocol checking is done in
data checker which is generally in scoreboard( or tracker) . To do that you must:
--Collect the output data from the DUT and parse it.
--Match the output to its corresponding input.
--Forecast the DUT output by calculating the expected output.
--Compare the output to the input and to the expected results.
Modularization
One of the ways to reduce the amount of work is the ability to leverage components
from one environment to the next. The concept of modularization is to break up a
complex problem into manageable pieces, which has many benefits including
increasing the quality, maintainability, and reusability of the environment.
In order to reuse components of one environment to another, it is important to
separate functionality into specific entities. This separation allows the work to be
distributed to multiple people. Task separation is very similar to and goes hand in
hand with modularization. Another benefit of task separation is having different
people understanding the functionality.
http://testbench.in/TB_17_CHECKER.html[9/26/2012 2:39:17 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
<< PREVIOUS PAGE
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http://testbench.in/TB_17_CHECKER.html[9/26/2012 2:39:17 PM]
Search
Index
Introduction
Linear Tb
SystemVerilog
File Io Tb
Verification
Tasks and functions can bu used to in much the same manner but there are some State Machine Based Tb
Constructs
Task Based Tb
important differences that must be noted.
Interface
Verification Flow
OOPS
Clock Generator
Functions
Simulation
Randomization
A
function
is
unable
to
enable
a
task
however
functions
can
enable
other
functions.
Functional Coverage
Store And Restore
A function will carry out its required duty in zero simulation time.
Assertion
Within a function, no event, delay or timing control statements are permitted.
In
the
invocation
of
a
function
there
must
be
at
least
one
argument
to
be
passed.
DPI
Functions will only return a single value and cannot use either output or inout Stimulus Generation
UVM Tutorial
statements.
A Myth
Functions are synthesysable.
VMM Tutorial
Race Condition
Disable statements cannot be used.
Checker
OVM Tutorial
Function cannot have nonblocking statements.
Task And Function
Easy Labs : SV
Process Control
EXAMPLE:function
Easy Labs : UVM
Watchdog
modulefunction_calling(a,b,c);
Easy Labs : OVM
Easy Labs : VMM

Switchs
inputa,b ;
Debugging
outputc;
AVM Switch TB
About Code Coverage
wirec;
VMM Ethernet sample
Testing Stratigies
File Handling
functionmyfunction;
Verilog Semaphore
inputa,b;
begin
Verilog
myfunction
=(a+b);
Verification
Terimination
end
Error Injuction
Verilog Switch TB
endfunction
Basic Constructs
assignc =myfunction (a,b);
Regression
endmodule
OpenVera
Tips
TUTORIALS
TASK AND FUNCTION
Constructs

RVM Switch TB
input is what keeps
RVM Ethernet sample Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a with time!
Switch TB
Specman E
Interview Questions
Task
non zero simulation time.

Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or
inout.
A Task is unable to return a value but has the facility to pass multiple values via the
output and inout statements.
Tasks are not synthesisable.
Disable statements can be used.
EXAMPLE:task
moduletraffic_lights;
regclock,red,amber,green;
parameteron =1,off =0,red_tics =350,
amber_tics =30,green_tics =200;
http://testbench.in/TB_18_TASK_AND_FUNCTION.html[9/26/2012 2:39:27 PM]
initialred =off;
initialamber =off;
initialgreen =off;
alwaysbegin// sequence to control the lights.
red =on;// turn red light on
light(red,red_tics);// and wait.
green =on;// turn green light on
light(green,green_tics);// and wait.
amber =on;// turn amber light on
light(amber,amber_tics);// and wait.
end
// task to wait for tics positive edge clocks
// before turning color light off.
tasklight;
outputcolor;
input[31:0]tics;
begin
repeat(tics)@(posedgeclock);
color =off;// turn light off.
end
endtask
alwaysbegin// waveform for the clock.
#100clock =0;
#100clock =1;
end
endmodule// traffic_lights.
Task And Function Queries:
Why a function cannot call a task?
As functions does not consume time, it can do any operation which does not consume
time. Mostly tasks are written which consumes time. So a task call inside a function
blocks the further execution of function utile it finished. But it<92>s not true. A
function can call task if the task call consumes zero time, but the IEEE LRM doesn't
allow.
Why tasks are not synthesized?
Wrong question! Tasks can be synthesized if it doesn't consume time.
Why a function should return a value?
There is no strong reason for this in Verilog. This restriction is removed in
SystemVerilog.
Why a function should have at least one input?
There is no strong reason for this in verilog. I think this restriction is not removed fin
SystemVerilog. Some requirements where the inputs are taken from the global signal,
those functions don<92>t need any input. A work around is to use a dummy input. If
you have a better reason, just mail me at gopi@testbench.in
Why a task cannot return a value?
If tasks can return values, then Lets take a look at the following example.
A=f1(B)+f2(C);
and f1 and f2 had delays of say 5 and 10? When would B and C be sampled, or global
inside f1 and f2 be sampled? How long does then entire statement block? This is going
to put programmers in a bad situation. So languages gurus made that tasks can't
return .
Why a function cannot have delays?
The answer is same as above. But in Open Vera, delays are allowed in function. A
function returns a value and therefore can be used as a part of any expression. This
does not allow any delay in the function.
Why disable statements are not allowed in functions?
If disable statement is used in function, it invalids the function and its return value.
So disable statements are not allowed in function.
Constant Function:
Constant function calls are used to support the building of complex calculations of
values at elaboration time. A constant function call shall be a function invocation of a
constant function local to the calling module where the arguments to the function are
constant expressions.
EXAMPLE:constant function.
moduleram_model (address,write,chip_select,data);
parameterdata_width =8;
parameterram_depth =256;
localparamadder_width =clogb2(ram_depth);
input[adder_width -1:0]address;
inputwrite,chip_select;
inout[data_width -1:0]data;
//define the clogb2 function
functionintegerclogb2;
inputdepth;
integeri,result;
begin
for(i =0;2**i <depth;i =i +1)
result =i +1;
clogb2 =result;
end
endfunction
Reentrant Tasks And Functions:
Tasks and functions without the optional keyword automatic are static , with all
declared items being statically allocated. These items shall be shared across all uses
of the task and functions executing concurrently. Task and functions with the optional
keyword automatic are automatic tasks and functions. All items declared inside
automatic tasks and functionsare allocated dynamically for each invocation.
Automatic task items and function items cannot be accessed by hierarchical
references.
EXAMPLE:
moduleauto_task();
taskautomaticdisp;
inputintegera;
inputintegerd;
begin
#(d)$display("%t d is %d a is %d",$time,d,a);
end
endtask
initial
#10disp(10,14);
initial
#14disp(23,18);
initial
#4disp(11,14);
initial
#100$finish;
endmodule
RESULTS:
18 d is 14 a is 11
24 d is 14 a is 10
32 d is 18 a is 23
EXAMPLE:
moduletryfact;
// define the function
functionautomaticintegerfactorial;
input[31:0]operand;
integeri;
if(operand >=2)
factorial =factorial (operand -1)*operand;
else
factorial =1;
endfunction
// test the function
integerresult;
integern;
initialbegin
for(n =0;n <=7;n =n+1)begin
result =factorial(n);
$display("%0d factorial=%0d",n,result);
end
end
endmodule// tryfact
RESULTS:
0
1
2
3
4
5
6
7
factorial=1
factorial=1
factorial=2
factorial=6
factorial=24
factorial=120
factorial=720
factorial=5040
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Index
Introduction
Linear Tb
SystemVerilog
Nonblocking Task
File Io Tb
Verification
If there is a delay in a task and when it is called, it blocks the execution flow. Many State Machine Based Tb
Constructs
times in verification it requires to start a process and continue with the rest of the Task Based Tb
flow. The following example demonstrated how the task block the execution flow.
Interface
Verification Flow
OOPS
Clock Generator
EXAMPLE:
Simulation
Randomization
moduletb();
Functional Coverage
Store And Restore
initial
Assertion
begin
blocking_task();
DPI
Stimulus Generation
#5$display(" Statement after blocking_task at %t ",$time);
UVM Tutorial
end
A Myth
VMM Tutorial
Race Condition
taskblocking_task();
Checker
OVM Tutorial
begin
Task And Function
#10;
Easy Labs : SV
Process Control
$display(" statement inside blocking task at %t",$time);
Easy Labs : UVM
end
Watchdog
endtask
Easy Labs : OVM
endmodule
Easy Labs : VMM
Switchs
RESULTS:
Debugging
AVM Switch TB
About Code Coverage
statement inside blocking task at 10
VMM Ethernet sample Statement after blocking_task at 15
Testing Stratigies
File Handling
Verilog Semaphore
Verilog
To
make
the
task
call
does
not
block
the
flow,
use
events
as
follows.
The
event
Verification
Terimination
triggers the always block and the task is started. This does not block the flow.
Error Injuction
Verilog Switch TB
Basic Constructs
EXAMPLE:
moduletb();
Regression
evente;
OpenVera
Tips
initial
Constructs
begin
#1->e;
Switch TB
RVM Switch TB
input is what keeps
#20$finish;
with time!
always@(e)
begin
Specman E
blocking_task();
end
Interview Questions
taskblocking_task();
begin
#10;
$display(" statement inside blocking task at %t",$time);
end
endtask
endmodule
RESULTS
TUTORIALS
PROCESS CONTROL
http://testbench.in/TB_19_PROCESS_CONTROL.html[9/26/2012 2:39:37 PM]
Statement after blocking_task at 6

statement inside blocking task at11
Fork/Join Recap:
Fork/join is a parallel block. Statements shall execute concurrently. Delay values for
each statement shall be considered relative to the simulation time of entering the
block. Delay control can be used to provide time-ordering for assignments Control
shall pass out of the block when the last time-ordered statement executes. The timing
controls in a fork-join block do not have to be ordered sequentially in time.
EXAMPLE:
modulefork_join();
integerr ;
initial
fork
#50r =35;
#100r =24;
#150r =00;
#200r =7;
#250$finish;
join
initial
$monitor("%t , r is %d",$time,r);
endmodule
RESULTS:
50 , r is 35
100 , r is 24
150 , r is 0
200 , r is 7
As the statements are parallel running, there is race condition between some
statements. In the following example, first statement after delay of 50 + 100, r is 24
and in second statement at 150 r is 00. But only the statement which is executed last
overrides previous value.
EXAMPLE:
modulefork_join();
integerr ;
initial
fork
begin
#50r =35;
#100r =24;
end
#150r =00;
#200r =7;
#250$finish;
join
initial
$monitor("%t , r is %d",$time,r);
endmodule
RESULTS:
50 , r is 35
150 , r is 24
200 , r is 7
Fork/Join None
In the fork join, the parent process continues to execute after all the fork/join
processes are completed. To continue the parent process concurrently with all the
processes spawned by the fork use this trick. This is as simple as above nonblocking
task example. Just use fork/join the always block as shown below.
EXAMPLE:
moduletb();
evente;
initial
begin
#1->e;
#40$finish;
end
always@(e)
begin
fork
blocking_task_1();
blocking_task_2();
join
end
taskblocking_task_1();
begin
#10;
$display(" statement inside blocking task_1 at %t",$time);
end
endtask
begin
#20;
end
endtask
endmodule
RESULTS
statement inside blocking task_1 at11
Fork/Join Any
If you want to continue the parent process after finishing any of the child process,
then block the parent process until an event if triggered by the forked threads.
EXAMPLE:
moduletb();
evente,ee;
initial
begin
#1->e;
@(ee);
$display(" Statement after blocking_task at %t ",$time);

#40$finish;
end
always@(e)
begin
fork
beginblocking_task_1();->ee;end
beginblocking_task_2();->ee;end
join
end
begin
#10;
end
endtask
begin
#20;
end
endtask
endmodule
RESULTS
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Index
Introduction
Linear Tb
SystemVerilog
Disable
File Io Tb
Verification
The disable statement stops the execution of a labeled block and skips to the end of State Machine Based Tb
Constructs
the block. Blocks can be named by adding : block_name after the keyword begin or Task Based Tb
fork. Named block can only be disabled using disable statement.
Interface
Verification Flow
OOPS
Clock Generator
This example illustrates how a block disables itself.
Simulation
Randomization
EXAMPLE:
Functional Coverage
Store And Restore
begin:block_name
Assertion
rega =regb;
disableblock_name;
DPI
Stimulus Generation
regc =rega;// this assignment will never execute
UVM Tutorial
end
A Myth
VMM Tutorial
Race Condition
OVM Tutorial
This example shows the disable statement being used as an early return from a task. Checker
Task And Function
However, a task disabling itself using a disable statement is not a short-hand for the
Easy Labs : SV
Process Control
return statement found in programming languages.
Easy Labs : UVM
Watchdog
Easy Labs : OVM
EXAMPLE:
Easy Labs : VMM
Switchs
taskabc();
Debugging
begin:name
AVM Switch TB
About Code Coverage
:
VMM Ethernet sample :
Testing Stratigies
File Handling
:
Verilog Semaphore
if(something happened)
disablename;
Verilog
:
Verification
Terimination
:
Error Injuction
Verilog Switch TB
:
end
Basic Constructs
endtask
Regression
Goto
OpenVera
Tips
Constructs
Verilog does not have a goto, but the effect of a forward goto can be acheived as
shown:
Switch TB
TUTORIALS
DISABLEING THE BLOCK
RVM Switch TB
EXAMPLE:
RVM Ethernet sample begin:name
...
if(a)
disablename;
Specman E
...
end
Interview Questions
Execution will continue with the next statement after the end statement when the
disable is executed.
Break
The break statement as in C can be emulated with disable as shown in the following
example:
EXAMPLE:
http://testbench.in/TB_20_DISABLEING_THE_BLOCK.html[9/26/2012 2:39:47 PM]

input is what keeps
with time!
begin:break
for(i=0;i<16;i=i+1)begin
...
if(exit)
disablebreak;
...
end
end
Continue
The continue statement in C causes the current iteration of a loop to be terminated,
with execution continuing with the next iteration. To do the same thing in Verilog,
you can do this:
EXAMPLE:
for(i=0;i<16;i=i+1)begin:name
...
if(abort)
disablename;
...
end
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Search
TUTORIALS
WATCHDOG
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
A watchdog timer is a piece of code, that can take appropriate action when it judges
that a system is no longer executing the correct sequence of code. In this topic ,I will
discuss exactly the sort of scenarios a watch dog can detect, and the decision that
must be made by watchdog. Generally speaking, a watchdog timer is based on a
counter that counts down from some initial value to zero. If the counter reaches,
then the appropriate action is take. If the required functionality is archived, watchdog
can be disabled.
In software world, in watchdog articles you will see various terms like strobing,
stroking etc. In this topic I will use more visual metaphor of man kicking the dog
AVM Switch TB
periodically-with apologies to animal lovers. If the man stops kicking the dog, the dog
VMM Ethernet sample will take advantage of hesitation and bite the man. The man has to take a proper
decision for the dog bite. The process of restarting the watchdog timer's counter is
sometimes called "kicking the dog.".Bugs in DUT can cause the testbench to hang, if
they lead to an infinite loop and creating a deadlock condition. A properly designed
Verilog
watchdog should catch events that hang the testbench.
Easy Labs : VMM
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Once your watchdog has bitten ,you have to decide what action to be taken. The
testbench will usually assert the error message, other actions are also possible like
directly stop simulation or just give a warning in performance tests.
In the following example, I have taken a DUT model so its easy to understand than a
RTL to demonstrate watchdog.
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips

RVM Switch TB
input is what keeps
RVM Ethernet sample
There are two scenarios I generated in DUT. one is following the above protocol and with time!
Switch TB
Specman E
Interview Questions
DUT PROTOCOL:
DUT has 3 signals.Clock a,b;
output b should be 1 within 4 clock cycles after output a became 1.
the other violated the above rule. The testbench watchdog shows how it caught there
two scenarios.
EXAMPLE:
moduleDUT(clock,a,b);
outputa;
outputb;
inputclock;
rega,b;
initial
begin
repeat(10)@(posedgeclock)a =0;b =0;
http://testbench.in/TB_21_WATCHDOG.html[9/26/2012 2:39:57 PM]
@(posedgeclock)a =1;b =0;

repeat(10)@(posedgeclock)a =0;b =0;
end
endmodule
moduleTB();
wireaa,bb;
regclk;
DUTdut(clk,aa,bb);
always
#5clk =~clk;
initial
#400$finish;
initial
begin
clk =0;
$display(" TESTBENCH STARTED");
wait(aa ==1);
watchdog();
wait(aa ==1);
watchdog();
end
taskwatchdog();
begin
$display(" WATCHDOG : started at %0d ",$time);
fork:watch_dog
begin
wait(bb ==1);
$display(" bb is asserted time:%0d",$time);
$display(" KICKING THE WATCHDOG ");
disablewatch_dog;
end
begin
repeat(4)@(negedgeclk);
$display(" bb is not asserted time:%0d",$time);
$display(" WARNING::WATCHDOG BITED ");
disablewatch_dog;
end
join
end
endtask
endmodule
RESULTS:
TESTBENCH STARTED
WATCHDOG : started at 105
bb is asserted time:135
KICKING THE WATCHDOG
WATCHDOG : started at 245
bb is not asserted time:280
WARNING::WATCHDOG BITED
Statement " disable watch_dog " is the trick hear. If that statement is not there, the
statement " wait(b == 1) " is waiting and the simulation goes hang. This watchdog is
just giving a warning about bite. You can also assert a ERROR message and call $finish
to stop simulation.
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TUTORIALS
COMPILATION N SIMULATION SWITCHS
SystemVerilog
Compilation And Simulation Directives:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
Conditional Compilation directive switches vs Simulation directive switches

Verilog has following conditional compiler directives.
ìfdef
èlse
èlsif
èndif
ìfndef
UVM Tutorial
The ìfdef compiler directive checks for the definition of a text_macro_name. If the
text_macro_name is defined, then the lines following the ìfdef directive are
included. If the text_macro_name is not defined and an èlse directive exists, then
OVM Tutorial
this source is
compiled. The ìfndef compiler directive checks for the definition of a
Easy Labs : SV
text_macro_name. If the text_macro_name is not defined, then the lines following
Easy Labs : UVM
the ìfndef directive are included. If the text_macro_name is defined and an èlse
directive exists, then this source is compiled. If the èlsif directive exists (instead of
Easy Labs : OVM
the èlse) the compiler checks for the definition of the text_macro_name. If the name
Easy Labs : VMM
exists the lines following the èlsif directive are included. The èlsif directive is
equivalent to the compiler directive sequence èlse ìfdef ... èndif. This directive
AVM Switch TB
does not need a corresponding èndif directive. This directive must be preceded by an
VMM Ethernet sample ìfdef or ìfndef directive.
VMM Tutorial
Verilog
Verification
EXAMPLE:
moduleswitches();
Verilog Switch TB
initial
begin
ìfdefTYPE_1
$display(" TYPE_1 message ");
èlse
OpenVera
ìfdefTYPE_2
Constructs
èndif
Switch TB
èndif
RVM Switch TB
end
RVM Ethernet sample endmodule
Basic Constructs
Specman E
Interview Questions
Compile with+define+TYPE_1
Then simulate,result is
RESULT:
TYPE_1 message
Compile with+define+TYPE_2
RESULT:
http://testbench.in/TB_22_COMPILATION_N_SIMULATION_SWITCHS.html[9/26/2012 2:40:04 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Compilation N
Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
TYPE_2 message
TYPE_1 and TYPE_2 are called switches.
In the above example, When TYPE_1 switch is given, statement " $display(" TYPE_1
message "); " is only compile and statement " $display(" TYPE_2 message "); " is not
compiled.
Similarly for TYPE_2 switch. It wont take much time to compile this small example.
Compilation time is not small for real time verification environment. Compiler takes
time for each change of conditional compilation switches.
Simulation directives are simple. This is archived by `define macros. The following
example demonstrated the same functionality as the above example.
EXAMPLE:
moduleswitches();
initial
begin
if($test$plusargs("TYPE_1"))
else
if($test$plusargs("TYPE_2"))
end
endmodule
No need to give +define+TYPE_1or +define+TYPE_2 during compilation
Simulate with +TYPE_1
RESULT:
TYPE_1 message
Simulate with +TYPE_2

RESULT:
TYPE_2 message
With the above style of programing,we can save recompilation times.
This system function searches the list of plusargs (like the $test$plusargs system
function) for a user specified plusarg string. The string is specified in the first
argument to the system function as either a string or a register which is interpreted
as a string. If the string is found, the remainder of the string is converted to the type
specified in the user_string and the resulting value stored in the variable provided. If
a string is found, the function returns a non-zero integer. If no string is found
matching, the function returns the integer value zero and the variable provided is not
modified.
%d decimal conversion
%o octal conversion
%h hexadecimal conversion
%b binary conversion
%e real exponential conversion
%f real decimal conversion
%g real decimal or exponential conversion
%s string (no conversion)
The first string, from the list of plusargs provided to the simuator, which matches the
plusarg_string portion of the user_string specified shall be the plusarg string available
for conversion. The remainder string of the matching plusarg (the remainder is the
part of the plusarg string after the portion which matches the users plusarg_string)
shall be converted from a string into the format indicated by the format string and
stored in the variable provided. If there is no remaining string, the value stored into
the variable shall either be a zero (0) or an empty string value.
Example
modulevaluetest();
integeri;
realr;
reg[11:0]v;
reg[128:0]s;
initial
begin
if($value$plusargs("STRING=%s",s))
$display(" GOT STRING ");
if($value$plusargs("INTG=%d",i))
$display(" GOT INTEGER ");
if($value$plusargs("REAL=%f",r))
$display(" GOT REAL ");
if($value$plusargs("VECTOR=%b",v))
$display(" GOT VECTOR ");
$display(" String is %s ",s);

$display(" Integer is %d ",i);
$display(" Realnum is %f ",r);
$display(" Vectoris %b ",v);
end
endmodule
Compilation :
command filename.v
Simulation :
command+STRING=rrf +INTG=123+REAL=1.32+VECTOR=10101
RESULTS:
GOT STRING
GOT INTEGER
GOT REAL
GOT VECTOR
String is rrf
Integer is 123
Realnum is 1.320000e+00
Vectoris 000000010101
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TUTORIALS
DEBUGGING
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Debugging is a methodical process of finding and reducing the number of bugs. When
a the outputs are of the DUT are not what expected, then a bug may be in DUT or
sometimes it may be in testbench. Debuggers are software tools which enable the
verification and design engineers to monitor the execution of a program, stop it, restart it, run it in interactive mode.
The basic steps in debugging are:
-----------
Recognize that a bug exists

Isolate the source of the bug
Identify the cause of the bug
Determine a fix for the bug
Apply the fix and test it
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Pass Or Fail
Easy Labs : UVM
At the end of simulation of every test, TEST FAILED or TEST PASSED report should be
generated. This is called self checking. Log files and Waveform viewer can help for
further debugging if test failed.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
An error count should be maintained to keep track of number of errors occurred.

Simplest way to increment an error counter is using named event.
EXAMPLE:
moduletop();
integererror;
Verification
eventerr;
Verilog Switch TB
//ur testbench logic
initial
Basic Constructs
begin
#10;
if("There is error ")
OpenVera
->error;
Constructs
#10
if("There is error ")
Switch TB
->error;
RVM Switch TB
#10
RVM Ethernet sample if("There is error ")
->error;
// call final block to finish simulation
Specman E
end
Interview Questions
//Initilize error to 0
initial
error =0;
// count number of errors
always@(err)
error =error +1;
// final block--to end simulation

taskfinish();
begin
Verilog
http://testbench.in/TB_23_DEBUGGING.html[9/26/2012 2:40:13 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
#10;// so delay to make sure that counter increments for the last triggered
error.
if(error ==0)
$dsplay("************ TEST PASSED ***************");
else
$dsplay("************ TEST FAILED ***************");
end
endtask
endmodule
Waveform Viewer:
For post process debug, Waveform viewer needs VCD(value change dump) file. A value
change dump (VCD) file contains information about value changes on selected
variables in the design stored by value change dump system tasks. Two types of VCD
files exist:
a) Four state: to represent variable changes in 0, 1, x, and z with no strength
information.
b) Extended: to represent variable changes in all states and strength information.
This clause describes how to generate both types of VCD files and their format.
The steps involved in creating the four state VCD file are listed below .
a) Insert the VCD system tasks in the Verilog source file to define the dump file name
and to specify the variables to be dumped.
b) Run the simulation.
A VCD file is an ASCII file which contains header information, variable definitions, and
the value changes for all variables specified in the task calls. Several system tasks can
be inserted in the source description to create and control the VCD file.
The $dumpfile task shall be used to specify the name of the VCD file.
EXAMPLE:
initial
$dumpfile("my_dump_file");
$dumpvar//Dump all the variables
// Alternately instead of $dumpvar, one could use
$dumpvar(1,top)//Dump variables in the top module.
$dumpvar(2,top)//Dumps all the variables in module top and 1 level below.
Executing the $dumpvarstask causes the value change dumping to start at the end of
the current simulation time unit. To suspend the dump, the $dumpofftask may be
invoked. To resume the dump, the $dumpontask may be invoked.
Due to dumping the value changes to a file,there is simulation over head. Not all the
time the dumping is required. So controlling mechanism to dump VCD files needs to
be implemented.
EXAMPLE:
ìfdefDUMP_ON
$dumpon;
èndif
Log File:
Log file keeps track of the operation in text format. Using Display system tasks,
proper information can be sent to log files. The display group of system tasks are
divided into three categories: the display and write tasks, strobed monitoring tasks,
and continuous monitoring tasks.
These are the main system task routines for displaying information. The two sets of
tasks are identical except that $display automatically adds a newline character to the
end of its output, whereas the $write task does not.
The system task $strobe provides the ability to display simulation data at a selected
time. That time is the
end of the current simulation time, when all the simulation events that have occurred
for that simulation
time, just before simulation time is advanced.
$monitor displays when any of the arguments values change.
Message Control System:
Sending message to log file is useful for debugging. But what messages are useful to
send and not. Sometimes only few messages are required to send to log file, other
times very detailed messages. If the number of messages are more, the simulation
time is more. So messaging should be controllable.
EXAMPLE:
always@(error)
begin
ìfdefDEBUG
$display(" ERROR : at %d ",$time);
èndif
end
With the above approach only one level of controlling is achieved. Messages can be
conveyed with wide range of severity levels. Following is the message controlling
system I used in my projects. This has 3 levels of controllability and 3 severity levels.
Message Severity Levels:
Following are the 4 severity levels of messaging:
INFO:
The messages is used to convey simple information.
WARNING:
This message conveys that some thisis bad but doesn't stop the simulation.
ERROR:
This messages indicate that some error has occurred.Simulation can be terminated.
DEBUG:
These messages are fordebugging purpose.
NOTE:%m prints hierarchy path.
EXAMPLE:
$display("
$display("
$display("
$display("
INFO : %t : UR MESSAGE GOES HEAR",$time);

WARN : %t : UR MESSAGE GOES HEAR",$time);
EROR : %t : UR MESSAGE GOES HEAR",$time);
DBUG : %t : UR MESSAGE GOES HEAR",$time);
Message Controlling Levels

By default ,messages INFO, WARN and EROR are logged. When a special switch is
used, Debug messages are logged. This example also removes lot of manly coding.
EXAMPLE:
ìfndefDEBUG
`defineSHOW0
èlse
`defineSHOW1
èndif
`defineINFO$write("INFO : %5t :%m:",$time);$display
`defineWARN$write("WARN : %5t :%m:",$time);$display

`defineEROR$write("EROR : %5t :%m:",$time);$display
`defineDBUGif(`SHOW==1)$write("DBUG
:%m:",$time);if(`SHOW==1)$display
%t
modulemsg();
initial
begin
#10;
ÌNFO("UR MESSAGE GOES HEAR");
`WARN("UR MESSAGE GOES HEAR");
ÈROR("UR MESSAGE GOES HEAR");
`DBUG("UR MESSAGE GOES HEAR");
end
endmodule
When compilation is done without +define+DEBUG
RESULTS:
INFO :10 :msg:UR MESSAGE GOES HEAR
WARN :10 :msg:UR MESSAGE GOES HEAR
EROR :10 :msg:UR MESSAGE GOES HEAR
When compilation is done with+define+DEBUG
RESULTS:
INFO :10 :msg:UR MESSAGE GOES HEAR
WARN :10 :msg:UR MESSAGE GOES HEAR
EROR :10 :msg:UR MESSAGE GOES HEAR
DBUG :10 :msg:UR MESSAGE GOES HEAR
The above results show that DEBUG messages can be disable if not needed.
With the above approach, the controllability is at compilation level. If the

controllability is at simulation level, compilation time can be saved. The following
message controlling system has controllability at simulation level.
EXAMPLE:
`defineINFO$write("INFO : %0t :%m:",$time);$display
`defineWARN$write("WARN : %0t :%m:",$time);$display
`defineEROR$write("EROR : %0t :%m:",$time);$display
`defineDBUGif(top.debug ==1)$write("DBUG : %0t :%m:",$time);if(top.debug
==1)$display
moduletop();
regdebug =0;
initial
if($test$plusargs("DEBUG"))
#0debug =1;
initial
begin
#10;
ÌNFO("UR MESSAGE GOES HEAR");
`WARN("UR MESSAGE GOES HEAR");
ÈROR("UR MESSAGE GOES HEAR");
`DBUG("UR MESSAGE GOES HEAR");
end
endmodule
When simulation is done without +DEBUG
RESULTS:
INFO :10 :top:UR MESSAGE GOES HEAR
WARN :10 :top:UR MESSAGE GOES HEAR
EROR :10 :top:UR MESSAGE GOES HEAR
When simulation is done with+DEBUG

RESULTS:
INFO :10 :top:UR MESSAGE GOES HEAR
WARN :10 :top:UR MESSAGE GOES HEAR
EROR :10 :top:UR MESSAGE GOES HEAR
DBUG :10 :top:UR MESSAGE GOES HEAR
Passing Comments To Waveform Debugger
This is simple trick and very useful. By passing some comments to waveform,
debugging becomes easy. Just declare a string and keep updating the comments.
There is no slandered way to pass comments to waveform debugger but some tools
have their own methods to do this job.
EXAMPLE:
modulepass_comments();
reg[79:0]Comment;// holds 10 characters.
reg[7:0]status;
initial
begin
#10status=8'b10101010;
comment =Preambel;
#10status=8'b10101011;
comment =Startofpkt;
end
endmodule
The reg " Comment " holds string. This strings can be viewed in waveform debugger.
$Display N $Strobe
According to scheduling semantics of verilog, $display executes before the
nonblocking statements update LHS. Therefore if $display contains LHS variable of
nonblocking assignment, the results are not proper. The $strobe command shows
updated values at the end of the time step after all other commands, including
nonblocking assignments, have completed.
EXAMPLE:
moduledisp_stro;
rega;
initialbegin
a =0;
a <=1;
$display(" $display a=%b",a);
$strobe(" $strobe a=%b",a);
#1$display("#1 $display a=%b",a);
#1$finish;
end
endmodule
RESULTS:
$display a=0
$strobe a=1
#1 $display a=1
Who Should Do The Rtl Debugging?
One of the important question in debugging is who should do the RTL debugging?
Verification engineer or the RTL designer?
I personally like to debug the RTL as verification engineer. This is a great opportunity
to know RTL methodology. This also improves my understanding ability of RTL.
Sometimes test fails because of the Verification environment, before I go and ask RTL
designer, I am sure that there is no bug in my environment. By debugging RTL, the bug
report is more isolated and designer can fix it sooner. Designer is fast enough to catch
cause of the bug, as he knows more about the RTL then verification engineer.
Verification and Designer should sit together and debug the issue, if the bug is in RTL,
verification engineer can file the bug, if it is in Testbench, no need to file it.
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TUTORIALS
ABOUT CODE COVERAGE
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
To check whether the Testbench has satisfactory exercised the design or not?
Coverage is used. It will measure the efficiency of your verification implementation.
Code coverage answers the questions like
Have all the lines of the DUT has been exercised?
Have all the states in the FSM has been entered?
Have all the paths within a block have been exercised?
Have all the branches in Case have been entered?
Have all the conditions in an if statement is simulated?
With the above information, verification engineer can plan for more test cases and
excursive uncovered areas to find bugs.
By default, every tool disables the code coverage. If user enables then only code
coverage is done. By enabling the code coverage there is overhead on the simulation
and the simulation takes more time. So it is recommended not to enable the code
coverage always. Enabling the code coverage during the regression saves user time a
lot.
Easy Labs : UVM

Easy Labs : OVM
Types Of Coverage
Easy Labs : VMM
Implementation of Testbench can be separated by following types of coverage

hierarchy.
AVM Switch TB
VMM Ethernet sample
Code Coverage:
Verilog
Verification
It specifies that how much deep level the design is checked. There are sub parts of
the code coverage that will be discussed bellow.
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Statement Coverage /Line Coverage:

This is the easiest understandable type of coverage. This is required to be 100% for
every project.From N lines of code and according to the applied stimulus how many
statements (lines) are covered in the simulation is measured by statement coverage.
Lines like module, endmodule, comments, timescale etc are not covered.
Switch TB
always@(posedgeclk)
RVM Switch TB
begin
RVM Ethernet sample if(a >b)statement 1
begin
y =a andb;statement 2
z =a orb;statement 3
Specman E
end
if(a <b)
Interview Questions
begin
y =a xorb;
z =a xnorb;
end
if(a ==b)
begin
y =notb;
z =a %b;
end
end
http://testbench.in/TB_24_ABOUT_CODE_COVERAGE.html[9/26/2012 2:40:22 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
As seen in example those statements only will execute whose condition is satisfied.
Statement coverage will only consider those statements.
Block/Segment Coverage:
The nature of the statement and block coverage looks somewhat same. The
difference is that block which is covered by begin-end, if-else or always, those group
of statements which is called block counted by the block coverage.
Branch / Decision / Conditional Coverage:

Branch coverage will report the true or false of the branch like if-else, case and the
ternary operator (? :) statements. In bellow branch of casez, sequences of statements
are given. Their execution is depending upon the implementation of stimulus. The
default branch in case statement in RTL is not exercised mostly because the Design
guidelines insist to mention all the branches of the case statement.
case(state)
idle :casez(bus_req)
4'b0000:next=idle;
4'b1???:next=grant1;
4'b01??:next=grant2;
4'b001?:next=grant3;
4'b0001:next=grant4;
default:next=idle;
endcase
As per the case selectivity list it will check all the statements are reached or not?
Path Coverage:
Due to conditional statements like if-else, case in the design different path is created
which diverts the flow of stimulus to the specific path.
Path coverage is considered to be more complete than branch coverage because it

can detect the errors related to the sequence of operations. As mentioned in the
above figure path will be decided according to the if-else statement According to the
applied stimulus the condition which is satisfied only under those expressions will
execute, the path will be diverted according to that. Path coverage is possible in
always and function blocks only in RTL. Path created by more than one block is not
covered.Analysis of path coverage report is not so easy task.
Expression Coverage:
It is the ratio of no. of cases checked to the total no. of cases present. Suppose one
expression having Boolean expression like AND or OR, so entries which is given to that
expression to the total possibilities is called expression coverage.
y =(a xorb)+(c xord);
In above example it analyzes the right and side of the expression and counts how
many times it executed. The expression which involves the Boolean expression for
that expression coverage will make its truth table with number of times it executed.
If any expression is uncovered then table will come with plane line.
Toggle Coverage:
It makes assures that how many time reg, net and bus toggled? Toggle coverage could
be as simple as the ratio of nodes toggled to the total number of nodes.
X or Z --> 1 or H
X or Z --> 0 or L
1 or H --> X or Z
0 or L --> X or Z
Above example shows the signal changes from one level to another. Toggle coverage
will show which signal did not change the state. Toggle coverage will not consider
zero-delay glitches.All types of transitions mentioned above are not interested. Only
1->0 and 0->1 are much important. This is very useful in gate level simulation.
Variable Coverage:
After the one step of toggle coverage variable coverage comes. Both the coverage
looks same but there is a minor different between them is toggle coverage works on
gate level but it fail on large quantity. For entity like bus we use variable coverage.
Triggering / Event Coverage:

Events are typically associated with the change of a signal. Event coverage checks the
process whenever the individual signal inside the sensitivity list changes.
EXAMPLE:
always@(a orb orc)
if((a &b)|c)
x =1'b 1;
else
x =1'b 0;
As per the change in above sensitivity list whether the process is triggered or not.
Parameter Coverage:
It works on the specification which is defined in the design process. If you have
implemented 30bit design instead of 32bit, here code coverage check for the
functionality while if your design is parameterized then parameter coverage will give
error which shows size mismatch.
Functional Coverage:
It works on the functional part of the stimuli's implementation. Functional coverage
will check the overall functionality of the implementation. Verilog does not support
functional coverage. To do functional coverage, Hardware verification languages like

SystemVerilog, Specman E or Vera are needed.
Fsm Coverage :
It is the most complex type of coverage, because it works on the behavior of the
design. In this coverage we look for how many times states are visited, transited and
how many sequence are covered. Thats the duty of FSM coverage.
State Coverage:
It gives the coverage of no. of states visited over the total no. of states. Suppose you
have N number of states and state machines transecting is in between only N-2 states
then coverage will give alert that some states are uncovered. It is advised that all the
states must be covered.
Transition Coverage:
It will count the no. of transitionfrom one state to another and it will compare it
with other total no. of transition. Total no. of transition is nothing but all possible no.
of transition which is present in the finite state machine. Possible transition = no. of
states * no. of inputs.
Sequence Coverage:
suppose your finite state machine detects the particular sequences. So there is more
than 1 possibilities of sequences through which your desired output can be achieved.
So here sequence coverage will check which sequence is covered and which is missed?
This is a small and corner problem but stimulus should be such a way that all the
possibilities must be covered.
Tool Support:
Coverage tool should have following features:
Capability to merge reports generated by different test cases.
Capability to disable specified block,statement,module,signal.
A GUI report for easy analysis.
Capability to enable or disable any type of coverage.
User options for default branch in case statement coverage.
Limitation Of Code Coverage:
Coverage does not know anything about what design supposed to do. There is no way
to find what is missing in the code. It can only tell quality of the implementation.
Sometime we get the bug because of the incorrectly written RTL code. If we found
that all the lines of the code are used, it doesn't mean that we have tasted all the
lines. Sometimes we want the 2nd input of the mux but due to mistake in stimulus if
it has taken 1st during that cycle. So whether we got he correct data or not? This
cannot tell by coverage. Thats depend on us weather we are feeding correct stimulus
or not?
so remember "VERIFICATION IS NOT COMPLETED EVEN AFTER 100% CODE

COVERAGE"
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TUTORIALS
TESTING STRATIGIES
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Function verification approaches can be divided into two categories. Bottom-up and
flat approaches.
Bottom-Up
Bottom-up approach can be done at 4 levels.
1)Unit (Module-level) Level
2)Sub-ASIC (Functional Blocks) Level
3)ASIC Level
4)System Level
VMM Tutorial
Unit Level
OVM Tutorial
In unit level verification, a module is verified in its own test environment to prove
that the logic, control, and data paths are functionally correct. The goal of module
level verification is to ensure that the component/unitbeing tested conforms to its
specifications and is ready to be integrated with other subcomponents of the product.
In unit level verification good coverage percentage is expected.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Sub-Asic Level
VMM Ethernet sample In sub-asic level ,the goal is to ensure that the interfaces among the unitsare
Verilog
correct & the units work together to execute the functionality correctly. Sometimes
this level can be skipped.
Verification
Asic Level
Verilog Switch TB
Asic level verification is the process of verifying the ASIC to see that it meets its
specified requirements. ASIC level verification must concentrate on ensuring the use
and interaction of ASIC rather than on checking the details of its implementations .
Basic Constructs
OpenVera
System Level
Constructs
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips

RVM Switch TB
input is what keeps
RVM Ethernet sample In this ,verification approaches by combining interface models and transaction
with time!
streams to test the Complete ASIC.
Switch TB
Flat
Specman E
Interview Questions
http://testbench.in/TB_25_TESTING_STRATIGIES.html[9/26/2012 2:40:32 PM]
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http://testbench.in/TB_25_TESTING_STRATIGIES.html[9/26/2012 2:40:32 PM]
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TUTORIALS
FILE HANDLING
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
The system tasks and functions for file-based operations are divided into three
categories:
Functions and tasks that open and close files
Tasks that output values into files
Tasks that output values into variables
Tasks and functions that read values from files and load into variables or memories
Fopen And Fclose
$fopen and $fclose
The function $fopen opens the file specified as the filename argument and returns
either a 32 bit multi channel descriptor, or a 32 bit file descriptor, determined by the
Easy Labs : SV
absence or presence of the type argument. Filename is a character string, or a reg
containing a character string that names the file to be opened.
Easy Labs : UVM
The multi channel descriptor mcd is a 32 bit reg in which a single bit is set indicating
Easy Labs : OVM
which file is opened. The least significant bit (bit 0) of a mcd always refers to the
standard output. Output is directed to two or more files opened with multi channel
Easy Labs : VMM
descriptors by bitwise oring together their mcds and writing to the resultant value.
AVM Switch TB
The most significant bit (bit 32) of a multi channel descriptor is reserved, and shall
VMM Ethernet sample always be cleared, limiting an implementation to at most 31 files opened for output
via multi channel descriptors. The file descriptor fd is a 32 bit value. The most
significant bit (bit 32) of a fd is reserved, and shall always be set; this allows
implementations of the file input and output functions to determine how the file was
Verilog
opened. The remaining bits hold a small number indicating what file is opened.
OVM Tutorial
Verification
EXAMPLE
// file open close example
Basic Constructs
modulefopenclose();
integermcd,number;
initial
begin
OpenVera
mcd =$fopen("xyz.txt");// opening the file
Constructs
repeat(7)
Switch TB
begin
number =$random;
RVM Switch TB
$fdisplay(mcd," Number is ",number);
$fclose(mcd);// closing the file
end
endmodule
Specman E
Verilog Switch TB
Interview Questions
After simulating the above code, file name called "xyz.txt" will be opened in the same
directory. In above example you show that file is getting open and closing, so
according to that there will be change in value of mcd.
EXAMPLE
// Display mcd value before and after the opening the file.
modulefopenclose();
integermcd,number;
initial
begin
$display("value of mcd before opening the file %b ",mcd);
http://testbench.in/TB_26_FILE_HANDLING.html[9/26/2012 2:40:40 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
mcd =$fopen("xyz.txt");// opening the file

$display("value of mcd after opening the file %b ",mcd);
repeat(7)
begin
number =$random;
end
$fclose(mcd);// closing the file
end
endmodule
RESULT
value of mcd before opening the file xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
value of mcd after opening the file 00000000000000000000000000000010
Then how can we check that file is closed or not??
In above example its clear that mcd value is changed as file is opened, if we dont
close the file than it will be remain in stack. But how will we come to
know that file is closed?? That will come after following examples.
Fdisplay
$fdisplay, $fdisplayb, $fdisplayo, $fdisplayh
$display has its own counterparts. Those are $fdisplay, $fdisplayb, $fdisplayo,
$fdisplayh. Instead of writing on screen they are writing on the specific file with is
pointed by the mcd. $fdisplay write in decimal format, $fdisplay in binary, $fdisplay
in octal and $fdisplayh in hex format. so no need to put %d-b-o-h.
EXAMPLE
// file open close example with all $fdisplay
modulefopenclose();
integermcd,number;
initial
begin
mcd =$fopen("temp.txt");// mcd = multi_channel_descriptor
repeat(7)
begin
number =$random;
$fdisplay(mcd,"Number is ",number);
end
$fclose(mcd);
end
endmodule
RESULT
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
303379748
-1064739199
-2071669239
-1309649309
112818957
1189058957
-1295874971
EXAMPLE $displayb
modulefopenclose();
integermcd,number;
initial
begin

repeat(7)
begin
number =$random;
$fdisplayb(mcd,"Number is ",number);
end
$fclose(mcd);
end
endmodule
RESULT
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
00010010000101010011010100100100
11000000100010010101111010000001
10000100100001001101011000001001
10110001111100000101011001100011
00000110101110010111101100001101
01000110110111111001100110001101
10110010110000101000010001100101
EXAMPLE c. $displayo
modulefopenclose();
integermcd,number;
initial
begin
repeat(7)
begin
number =$random;
$fdisplayo(mcd,"Number is ",number);
end
$fclose(mcd);
end
endmodule
RESULT
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
02205232444
30042257201
20441153011
26174053143
00656275415
10667714615
26260502145
EXAMPLE. $displayh
modulefopenclose();
integermcd,number;
initial
begin
repeat(7)
begin
number =$random;
$fdisplayh(mcd,"Number is ",number);
end
$fclose(mcd);
end
endmodule
RESULT
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
12153524
c0895e81
8484d609
b1f05663
06b97b0d
46df998d
b2c28465
In below example we will see that how we will come to know that file is closed or
not?? so even after closing the file I will try to write in that file, for that it should
give error.
EXAMPLE
modulefopenclose();
integermcd,number;
initial
begin
$display("value of mcd before opening the file %b ",mcd);
mcd =$fopen("xyz.txt");
$display("value of mcd after opening the file %b ",mcd);
repeat(7)
begin
number =$random;
end
$fclose(mcd);
$fdisplay("value of mcd after closing the file %b ",
mcd);
end
endmodule
RESULT
Error during elaboration.
Fmonitor
$fmonitor,
$fstrobeh
$fmonitorb,
$fmonitoro,
$fmonitorh,
$fstrobe,
$fstrobeb,$fstrobeo,
Like $display; $monitor and $strobe also have counterparts. They also write in
decimal, binary, octal and hexadecimal.
EXAMPLE
// file open close example with $fmonitor
modulemonitortask();
integermcd,number;
initial
begin
#0;
mcd =$fopen("abc.txt");
$monitoron;
repeat(7)
begin
#1number =$random;
end
$monitoroff;
$fclose(mcd);
end
initial
$fmonitorh(mcd," Number is ",number);
endmodule
RESULT
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
12153524
c0895e81
8484d609
b1f05663
06b97b0d
46df998d
Due to initial-initial race condition we have to put the #0 delay in first initial block
and $monitoron-$monitoroff system task, otherwise it is not able to
cache the updated value of integer "number" because "number" is updated in
active(1st) event while monitor in system task(3rd) event in the event queue.
Fwrite
$fwrite, $fwriteb, $fwriteo, $fwriteh
Like $display; $write also have counterparts. They also write in decimal,binary, octal
and hexadecimal.
EXAMPLE
// file open close example with $fwrite
modulewritetask();
integermcd1,mcd2,number,pointer;
initial
begin
$display("value of mcd1 before opening the file %b ",mcd1);
$display("value of mcd2 before opening the file %b ",mcd2);
mcd1 =$fopen("xyz.txt");
mcd2 =$fopen("pqr.txt");
$display("value of mcd1 after opening the file %b ",mcd1);
$display("value of mcd2 after opening the file %b ",mcd2);
repeat(7)
begin
pointer =$random;
number =$random%10;
$fwriteo(mcd1," Number is ",number);
$fwriteh(mcd2," Pointer is ",pointer);
end
$fclose(mcd1);
$fclose(mcd2);
end
endmodule
One of the reasons behind writing this example is to show how the integers are
getting different value as per the number of files are opened.
RESULT
value of mcd1 before opening the file xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
value of mcd2 before opening the file xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
value of mcd1 after opening the file 00000000000000000000000000000010
value of mcd2 after opening the file 00000000000000000000000000000100
in file pqr.txt
Pointer is 12153524 Pointer is 8484d609 Pointer is 06b97b0d
Pointer is b2c28465 Pointer is 00f3e301 Pointer is 3b23f176
Pointer is 76d457ed
In file xyz.txt
Number is 37777777767 Number is 37777777767 Number is
00000000007 Number is 37777777774 Number is 00000000011 Number
is 00000000007 Number is 00000000002
Mcd
Simultaneously writing same data to two different file. This example shows how to
set up multi channel descriptors. In this example, two different channels are opened
using the $fopen function. The two multi channel descriptors that are returned by the
function are then combined in a bit-wise or operation and assigned to the integer
variable "broadcast". The "broadcast" variable can then be used as the first parameter
in a file output task to direct output to all two channels at once.
EXAMPLE
modulewritetask();
integermcd1,mcd2,broadcast,number;
initial
begin
mcd1 =$fopen("lsbbit1.txt");
broadcast =mcd1 |mcd2 ;
repeat(7)
begin
number =$random;
$fdisplayh(broadcast," Number is ",number);
end
$fclose(mcd1);
$fclose(mcd2);
end
endmodule
RESULT
In lsbbit1.txt
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
12153524
c0895e81
8484d609
b1f05663
06b97b0d
46df998d
b2c28465
In lsbbit2.txt
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
12153524
c0895e81
8484d609
b1f05663
06b97b0d
46df998d
b2c28465
To create a descriptor that directs output to the standard output that is monitor
screen as well as both the files, the "broadcast" variable is a bit-wise
logical or with the constant 1, which effectively writes to both files as well as monitor
screen.
EXAMPLE
modulewritetask();
integermcd1,mcd2,broadcast,number;
initial
begin
broadcast =1|mcd1 |mcd2 ;
repeat(7)
begin
number =$random;
$fdisplayh(broadcast," Number is ",number);
end
$fclose(mcd1);
$fclose(mcd2);
end
endmodule
endmodule
RESULT
Number
Number
Number
Number
Number
Number
Number
is
is
is
is
is
is
is
12153524
c0895e81
8484d609
b1f05663
06b97b0d
46df998d
b2c28465
Formating Data To String

The $swrite family of tasks are based on the $fwrite family of tasks, and accept the
same type of arguments as the tasks upon which they are based, with one exception:
The first parameter to $swrite shall be a reg variable to which the resulting string
shall be written, instead of a variable specifying the file to which to write the
resulting string.
The system task $sformat is similar to the system task $swrite, with a one major
difference. Unlike the display and write family of output system tasks, $sformat
always interprets its second argument, and only its second argument as a format
string. This format argument can be a static string, such as "data is %d" , or can be a
reg variable whose content is interpreted as the format string. No other arguments
are interpreted as format strings. $sformat supports all the format specifies supported
by $display.
EXAMPLE:
$sformat(string,"Formatted %d %x",a,b);
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TUTORIALS
VERILOG SEMAPHORE
SystemVerilog
Semaphore In Verilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A semaphore is a type of Interposes communication resource used for synchronization

and mutual exclusion between any two asynchronous processes. A semaphore object is
a synchronization object that maintains a count between zero and a specified
maximum value. The count is decremented each time a thread completes a wait for
the semaphore object and incremented each time a thread releases the semaphore.
When the count reaches zero, no more threads can successfully wait for the
semaphore object state to become signaled. The state of a semaphore is set to
signaled when its count is greater than zero, and non-signaled when its count is zero.
The semaphore object is useful in controlling a shared resource that can support a
limited number of users. It acts as a gate that limits the number of threads sharing
the resource to a specified maximum number.
Take an example, Many components in the testbench wants to access the dut
memory. But memory has only one interface. So only one can do write and read
operation at a time. Using semaphore, we can make sure that only one operation is
done at a time.
Imagine a home with six persons living. They have only one car. Everyone wants to
drive the car. But others plan to make a trip, when some other has gone out with car.
The eldest person in home made a rule. Key will be withhim. Whoever wants, come
to me and get the key. After finishing the job, return the key to him. This way, only
one can plan for the trip.
VMM Ethernet sample
Verilog
EXAMPLE:
modulesema();
integerkeys;
Verilog Switch TB
initial
keys =1;
Basic Constructs
taskget_key();
inputintegeri;
OpenVera
begin
Constructs
if(keys ==0)
begin
Switch TB
$display(" KEY IS NOT AVAILABLE : WAITING FOR KEYS : process %d",i);
RVM Switch TB
wait(keys ==1);
$display(" GOT THE KEY : GET SET GO :process %d",i);
keys =0;
end
Specman E
endtask
Interview Questions
taskput_keys();
inputintegeri;
begin
keys =1;
$display(" PROCESS %d gave the key back ",i);
end
endtask
initial
begin
Verification
http://testbench.in/TB_27_VERILOG_SEMAPHORE.html[9/26/2012 2:40:48 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
#10;
get_key(1);
repeat(4)
#10$display(" PROCESS 1 GOT KEYS : OTHERS CANT WRITE MESSAGE TO LOG ");
put_keys(1);
end
initial
begin
#10;
get_key(2);
repeat(4)
put_keys(2);
end
endmodule
RESULTS:
GOT THE KEY : GET SET GO :process 1
KEY IS NOT AVAILABLE : WAITING FOR KEYS : process 2
PROCESS 1 GOT KEYS : OTHERS CANT WRITE MESSAGE TO
PROCESS 1 gave the key back
LOG
LOG
LOG
LOG
LOG
LOG
LOG
LOG
In this home, some of them are not interested to wait until they got the key. So they
want tp progress to other works without waiting for keys.
The following example shows, if keys are not available, the process don't wait.
EXAMPLE:
modulesema();
integerkeys;
initial
keys =1;
taskget_key();
inputintegeri;
begin
if(keys ==0)
begin
wait(keys ==1);
end
keys =0;
end
endtask
functionget_key_dont_wait();
inputintegeri;
reggot;
begin
got =0;
if(keys ==0)
$display(" KEY IS NOT AVAILABLE : LEAVING WITHOUT WAITING FOR KEYS : process
%d",i);
else
begin
keys =0;
got =1;
end
get_key_dont_wait =got;
end
endfunction
taskput_keys();
inputintegeri;
begin
keys =1;
end
endtask
initial
begin
#10;
get_key(1);
repeat(4)
put_keys(1);
end
initial
begin
#10;
if(get_key_dont_wait(2))
begin
repeat(4)
put_keys(2);
end
else
$display(" IM not interested to wait ");
end
endmodule
RESULTS:
KEY IS NOT AVAILABLE : LEAVING WITHOUT WAITING FOR KEYS : process 2
IM not interested to wait
PROCESS 1 GOT KEYS : OTHERS CANT WRITE MESSAGE TO LOG
After some days, they got new car to home. Now they have two cars, at once 2
members can go on drive. Looking at the following code. The keys are initialized to 2.
Two processes are running at once.
EXAMPLE:
modulesema();
integerkeys;
initial
keys =2;
taskget_key();
inputintegeri;
begin
if(keys ==0)
begin
wait(keys >0);
end
keys =keys -1;
end
endtask
functionget_key_dont_wait();
inputintegeri;
reggot;
begin
got =0;
if(keys ==0)
$display(" KEY IS NOT AVAILABLE : LEAVING WITHOUT WAITING FOR KEYS : process
%d",i);
else
begin
keys =keys -1;
got =1;
end
get_key_dont_wait =got;
end
endfunction
taskput_keys();
inputintegeri;
begin
keys =keys +1;
end
endtask
initial
begin
#10;
get_key(1);
repeat(4)
#10$display(" PROCESS 1 GOT KEYS : IM ALOS RUNNING ");
put_keys(1);
end
initial
begin
#10;
if(get_key_dont_wait(2))
begin
repeat(4)
#10$display(" PROCESS 2 GOT KEYS : IM ALSO RUNNING ");
put_keys(2);
end
else
$display(" IM not interested to wait ");
end
endmodule
RESULTS:
PROCESS 1 GOT KEYS : IM ALOS RUNNING
PROCESS 2 GOT KEYS : IM ALSO RUNNING
PROCESS
PROCESS
PROCESS
PROCESS
1
1
2
2
GOT KEYS : IM ALOS RUNNING

gave the key back
GOT KEYS : IM ALSO RUNNING
gave the key back
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TUTORIALS
FINDING TESTSENARIOUS
SystemVerilog
Test scenarios can be divided in to following category whileimplementing @bull test

plan.
@bull Register Tests
@bull Interrupt Tests
@bull Interface Tests
@bull Protocol Tests
@bull Functional Tests
@bull Error Tests
@bull Golden Tests
@bull Performance Tests
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Register Tests
VMM Tutorial
This is complex to build efficiently. These tests requires more advanced planning and
architecting . A poorly planned infrastructure is buggy, insufficient, and hard to use.
OVM Tutorial
System Tests
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
These tests Verify whether ASIC interacts correctly with other ASICs / ICs correctly in
the system.
Interrupt Tests
These tests Verify how the interrupt logic is working.
VMM Ethernet sample Interface Tests
Verilog
These tests verify the Interface functionality.
Verification
Functional Tests
Verilog Switch TB
Contains scenarios related to specific features & combinations of these features.
Basic Constructs
OpenVera
Constructs
Error Tests
Error-oriented testing develops test data by focusing on the presence or absence of
errors in DUT.
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips

RVM Switch TB
Set of well defined test cases executed on a modified code to ensure that changes input is what keeps
RVM Ethernet sample made to the code haven't adversely affected previously existing functions. These
includes register tests, interrupt tests, interface tests, protocol tests, functional tests with time!
Switch TB
Golden Tests
& error tests.
Specman E
Interview Questions
Performance Tests
These tests measures how well the product meets its specified performance
objectives. Example: bandwidth monitoring.
http://testbench.in/TB_28_FINDING_TESTSENARIOUS.html[9/26/2012 2:40:58 PM]
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http://testbench.in/TB_28_FINDING_TESTSENARIOUS.html[9/26/2012 2:40:58 PM]
Search
TUTORIALS
HANDLING TESTCASE FILES
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
A test case is a file that describes an input, action, or event and an expected
response, to determine if a feature of an application is working correctly. A test case
should contain particulars such as test case identifier, test case name, objective, test
conditions/setup, input data requirements, steps, and expected results.
Note that the process of developing test cases can help find problems in the
requirements or design of an application, since it requires completely thinking through
the operation of the application. For this reason, it's useful to prepare test cases early
in the development cycle if possible.
The following example contains testbench environment and has 2 test cases.
EXAMPLE:top.v
moduletop();
// DUT instance, clock generator and TB components
// some tasks
Easy Labs : VMM
taskwrite()
begin
// some logic
endtask
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
taskread()
begin
// some logic
end
endtask
end
EXAMPLE: testcase_1.v
// Do 10 write operations
RVM Ethernet sample EXAMPLE: testcase_2.v
// Do 10 read operations
Specman E
Interview Questions
To test first test cases, We have to simulate the contents of top.v file and
testcase_1.v file.
1) Take an instance of module TEST in top.v file. Define the module definition in test
cases.
During compilation just use the following commands
for testcase_1.v file
comile_command top.v testcase_1.v
http://testbench.in/TB_29_HANDLING_TESTCASE_FILES.html[9/26/2012 2:41:06 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!

comile_command top.v testcase_2.v
EXAMPLE:top.v
moduletop();
// some tasks
taskwrite()
begin
// some logic
end
endtask
taskread()
begin
// some logic
end
endtask
//TEST case instance
TESTtst();
end
moduleTEST();
initial
repeat(10)
top.write();
endmodule
moduleTEST();
initial
repeat(10)
top.read();
endmodule
2) use ìnclude test.v file. This needs a small script to copy the testcase file to test
file. The compilation command is same. But copy command which copies the testcase
to test.v file is different.
During compilation just use the following commands
cp testcase_1 test.v
comile_command top.v test.v

cp testcase_2 test.v
comile_command top.v test.v
EXAMPLE:top.v
moduletop();
// some tasks
taskwrite()
begin
// some logic
end
endtask
taskread()
begin
// some logic
end
endtask
//incule test.v file
ìncludetest.v
end
initial
repeat(10)
top.write();
initial
repeat(10)
top.read();
2) With the above two approaches, for each test case, we have to do individual
compilation. Inthis method, compile once and use simulation command to test with
individual test case.
This needs a small script to convert all the test cases to single intermediate file.
compilation command is same. During simulation by giving the test case file name, we
can include particular testcase.
During compilation just give following command
cat testcase_1.v > test.v
cat testcase_2.v > test.v
compile_command top.v test.v
During simulation ,
for each test case, use
run_command +testcase_1
run_coomand +testcase_2
EXAMPLE:top.v
moduletop();
// some tasks
taskwrite()
begin
// some logic
end
endtask
taskread()
begin
// some logic
end
endtask
//incule test.v file
ìncludetest.v
end
repeat(10)
top.write();
repeat(10)
top.read();
Intermediate file generated contains all the testcase contents with some extra logic as
shown.
EXAMPLE: INTERMEDIATE FILE test.v
initial
begin
if($test$plusargs("testcase_1")
begin // testcase_1 contents
repeat(10)
top.write();
end
if($test$plusargs("testcase_2")
begin// testcase_2 contents
repeat(10)
top.read();
end
end
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TUTORIALS
TERIMINATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Simulation should terminate after all the required operations are done. Recommended
way to exit simulation is using a task. This termination task contains some messages
about the activities done and $finish. This task should be called after collecting all the
responses from DUT, then analyzing them only. If the simulation time is long and if
there is bug in DUT, you can stop simulation at that time itself. This saves lot of time.
Otherwise, even after the testbench found error, it will simulate till the end of the
process or it may get hanged and waste your time and costly licenses.
Sometimes, you are not just interested to terminate the simulation for known
unfixed bugs. Then there should be a controllable way not to stop the simulation even
after the error was found.
VMM Tutorial
EXAMPLE:
OVM Tutorial
taskteriminate();
begin
if(no_of_errors ==0)
$display(" *********TEST PASSED ***********");
else
$display(" *********TEST FAILED ***********");
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
#10$display(" SIMULATION TERMINATION at %d",$time);

$finish;
endtask
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
always@(error)
begin
no_of_errors =num_of_errors +1;
ìfndefCONTINUE_ON_ERROR
terminate();
èndif
end
Constructs
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
Switch TB
If you know already a well known bug is there and it is giving 2 error counts. Its on This section - Your
RVM Switch TB
better to stop the simulation after 2 errors. From command line just give input is what keeps
RVM Ethernet sample +define+NO_FO_ERR=2, simulation terminates after 3 errors.
with time!
Specman E
Interview Questions
EXAMPLE:
always@(error)
begin
no_of_errors =num_of_errors +1;
ìfndefCONTINUE_ON_ERROR
ìfndefNO_OF_ERR
`defineNO_OF_ERR0
èndif
if(`NO_OF_ERR<no_of_erros)
terminate();
èndif
end
http://testbench.in/TB_30_TERIMINATION.html[9/26/2012 2:41:13 PM]
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TUTORIALS
ERROR INJUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
To verify error detection, reporting, and recovery features of the DUT, an error
injection mechanism must be in place in testbench to generate error scenarios. The
objective is to ensure that the errors are handled correctly. This is accomplished by
introducing internal monitoring mechanisms. The simulation environment integrates a
structure to randomly set the errors and verify that each error condition is handled
properly.
Errors can be classified in to following categories:
Value Errors
The specification says that packet length should be greater than 64 and less than
1518. Testbench should be able to generate packets of length less than 64 and greater
than 1518 and verify how the DUT is handling these. Testbench should also monitor
that DUT is not generating any packets violating this rule.
Easy Labs : SV
Temporal Errors
Easy Labs : UVM
Errors like acknowledgement should come after 4 cycles of request.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
Interface Error
Sometimes interfaces have invalid pins or error pins to inform to DUT that the some
VMM Ethernet sample malfunction happened. Generate scenarios to test whether the DUT is properly
responding to these signals.
Verilog
Verification
Sequence Errors
Verilog Switch TB
To test protocols which define sequence of operations, generate sequence which

violates the rule and check the DUT.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_31_ERROR_INJUCTION.html[9/26/2012 2:41:22 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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http://testbench.in/TB_31_ERROR_INJUCTION.html[9/26/2012 2:41:22 PM]
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TUTORIALS
REGISTER VERIFICATION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Todays complex chips has thousands of register to configure the chip and to
communicate the status to software. These registersplay a complex role in the chip
operation So a test bench should verify these registers properly. Verification of these
registers is tedious. As there are thousands of registers in a chip, the testbench should
have a handy hooks to access these registers. Implementing testbench components
for these registers is not one time job. Most designs change their register
specification during the design development. So a very flexible testbench component
should be available to satisfy these needs. When I was working for Ample, we had a
script which generates testbench component for these registers. Register
specification is input to these script. So when ever register file is changed, Just run
the script, we don't need to change verilog module for these changes. These scripts
can be used across modules, across projects and across companies also. There are
some EDA tools just to do this job. I believe that a proper homemade script has better
control then getting it from some EDA guy and you know home made scripts are life
time free.
Easy Labs : SV
Easy Labs : UVM
Register Classification:
Easy Labs : OVM
Registers can be mainly classified in to these categories

1) Configuration Registers.
2) Status Registers.
AVM Switch TB
3) Mask Registers.
VMM Ethernet sample 4) Interrupt Registers(makeable and nonmaskable).
Easy Labs : VMM
Verilog
Verification
Features:
Verilog Switch TB
What are the features that this testbench component should support?
Basic Constructs
OpenVera
Constructs
1) It should have a data structure to store the values of config register .Testbench will
write in to these register while it is writing to dut registers. These are called shadow
registers. Shadow registers should have the same address and register name as DUT so
it is easy to debug.
2) Back door access: There are two type of access to register in DUT. Front door and
back door. Front door access uses physical bus . To write a value in to DUT registers,
RVM Switch TB
it takes some clock cycles in front door access. And writing for thousands of registers
RVM Ethernet sample is resource consuming. Remember, only one register can be assigned at a time. One
cannot make sure that only one method is called at one time. To make sure that only
one method is assessing the bus, semaphore is used. In back door access, registers are
access directly. In zero time. Accessing to these locations using back door will save
Specman E
simulation time. There should be a switch to control these feature. So after verifying
the actual access path of these registers, we can start using back door access. In
Interview Questions
verilog, using Hierarchy reference to DUT register, we can by pass this path.
Switch TB
3) The Shadow registers by default should contain default values from register
specification. A task should be provided to compare each register in shadow registers
and DUT. After reset, just call this task before doing any changes to DUT registers.
This will check the default values of the registers.
4) Methods should be provided for read or write operation to dut registers using name
and also address. Named methods are handy and readable mainly from test cases.
While address based methods are good while writing to bulk locations( using for loop
http://testbench.in/TB_32_REGISTER_VERIFICATION.html[9/26/2012 2:41:29 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
etc...).
5) Every register in Testbench may have these information.

// Comments which describes the register information.
Address of register.
Offset of register.
Width of register.
Reset value.
Access permissions.
Register value.
Register name as string.( Name should be self descriptive and same as in DUT. This
string is used in printing while debugging.)
Some are methods which are used for register in functional verification .
Read function.
Write task.
Update task.
Print task.
Check function.
write_random task.
All the above methods should be accessible by name and also by address.
Write random task:
Some registers values can be any constrained random value. Lets take an ether net.
The unicast destination address can be any value which is not broadcast or multi cast.
So the random values should be constraint. Some times, these random values depend
on some other registers also. If this task is not provided,while writing the test cases,
one may forget the limitation of the register value and the DUT misbehaves and may
spend hours in debugging. The best way to use random values is using this task.
Update task:
Interrupt and status registers in Testbench should be updated by update task. These
registers should contain the expected values. When check function is called, the
check reads the register values in DUT and compares with the expected value in
shadow registers.
Check task:
Check task compares the DUT and shadow registers. Care should be taken while using
back door access, as they are not cycle accurate. Config registers are compared for
what is configured and what is in the register. Interrupt and status registers are
compared with what is in DUT with the expected values.
Access permission:
Each register in test bench should maintain the permissions. This permissions are used
in write, read, check methods.
Fallowing are possible types of permissions:
read/write
read only
write only
read only,write can be by the design
clear on read
automatically set to 1 by design.
Automatically set to 0 by design.
Readable and settable by writing 1
Readable and clearable by writing 1
By default the type of permission is read/write. If you are using any scripts, if you
don't mention any permission, then it should be considered as read/write.
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Index
Introduction
Linear Tb
SystemVerilog
How do we get rid of the typing repeating functionality which should be present at File Io Tb
Verification
compilation level ?
Constructs
Task Based Tb
You can Use generate block. But Generate will not help always.
Interface
Verification Flow
OOPS
Clock Generator
Look at the example.
Randomization
There are four modules and_gate,or_gate,xor_gate,nand_gate. They are instantiated Simulation
in top modules.
Functional Coverage
Store And Restore
Assertion
Each module has 2 inputs a,b and one output c. Instance port are connected wires Event Cycle Simulation
which are prefixed with getname to signal name.
DPI
Stimulus Generation
Example
UVM Tutorial
A Myth
and_gatea_g (.a(and_a), .b(and_b), .c(and_c));
VMM Tutorial
Race Condition
Checker
OVM Tutorial
and is prefexed to signal "a","b" and "c".
Task And Function
Easy Labs : SV
Process Control
The following is what a novice engineer will do.
Easy Labs : UVM
Watchdog
CODE:
Easy Labs : OVM
Easy Labs : VMM
Switchs
moduletop();
Debugging
wireand_a,or_a,xor_a,nand_a ;
AVM Switch TB
About Code Coverage
wireand_b,or_b,xor_b,nand_b ;
VMM Ethernet sample wireand_c,or_c,xor_c,nand_c ;
Testing Stratigies
File Handling
Verilog Semaphore
and_gatea_g (.a(and_a),.b(and_b),.c(and_c));
or_gate o_g (.a(or_a),.b(or_b),.c(or_c) );
Verilog
xor_gatex_g
(.a(xor_a),.b(xor_b),.c(xor_c));
Verification
Terimination
nand_gate n_g (.a(nand_a),.b(nand_b),.c(nand_c));
Error Injuction
Verilog Switch TB
Basic Constructs
endmodule
Regression
OpenVera
Tips
moduleand_gate(a,b,c);
Constructs
inputa,b;
outputc;
Switch TB
endmodule
TUTORIALS
PARAMETERISED MACROS
RVM Switch TB
RVM Ethernet sample moduleor_gate(a,b,c);
Specman E
Interview Questions
inputa,b;
outputc;
endmodule
modulexor_gate(a,b,c);
inputa,b;
outputc;
endmodule
modulenand_gate(a,b,c);
inputa,b;
outputc;
endmodule
http://testbench.in/TB_33_PARAMETERISED_MACROS.html[9/26/2012 2:41:37 PM]
input is what keeps

with time!
This looks easy to do, as there are 3 inputs only. Real time projects doesnt have this
much less. One may probable spend half day to connect all the ports. Sometime later
if there is change in any of the ports, then all the instances needs to be changed.
Using parameterized macros, this job can be done easily. The directive <91>define
creates a macro for text substitution. This directive can be used both inside and
outside module definitions. After a text macro is defined, it can be used in the source
description by using the (<91>) character, followed by the macro name. The compiler
shall substitute the text of the macro for the string `macro_name. All compiler
directives shall be considered predefined macro names; it shall be illegal to redefine
a compiler directive as a macro name.
A text macro can be defined with arguments. This allows the macro to be customized
for each use individually. If a one-line comment (that is, a comment specified with
the characters //) is included in the text, then the comment shall not become part of
the substituted text.
EXAMPLE:
<91>define max(a,b)((a)>(b)?(a):(b))
n =<91>max(p+q,r+s);
To use this for the above discussed example,
First step is declare a parameterized macro.
Second step is just use macro instance.
CODE:
`defineGATE(M)M\
_gate M\
_g (.a(M\
_a),.b(M\
_b),.c(M\
_c));
`defineSIG and_\
S,or_\
S,xor_\
S,nand_\
S;\
moduletop();
wire`SIG(a)
wire`SIG(b)
wire`SIG(c)
`GATE(and)
`GATE(or)
`GATE(xor)
`GATE(nand)
endmodule
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TUTORIALS
WHITE GRAY BLACK BOX
SystemVerilog
Black Box Verification
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Black Box verification refers to the technique of

verification ifsystem with no knowledge of the internals of the DUT. Black Box
testbench do not have access to the source code of DUT, and are oblivious of the DUT
architecture. A Black Box testbench, typically, interacts with a system through a user
interface by providing inputs and examining outputs, without knowing where and how
the inputs were operated upon. In Black Box verification, the target DUT is exercised
over a range of inputs, and the outputs are observed for correctness. How those
outputs are generated or what is inside the box doesn't matter.
Easy Labs : SV
White Box Verification
Easy Labs : UVM
In White box verification, testbench has access to internal structure of DUT. This
makes the testbench environment reuse less. This is not much preferred in the
industry.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Gray Box Verification

Gray box verification, the name itself Conway that testbench has access to some part
of the DUT.
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_34_WHITE_GRAY_BLACK_BOX.html[9/26/2012 2:41:47 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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TUTORIALS
REGRESSION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Regression is re-running previously run tests and checking whether previously fixed
faults have re-emerged. New bugs may come out due to new changes in RTL or DUT to
unmasking of previously hidden bugs due to new changes. Each time time,when design
is changed, regression is done. One more important aspect of regression is testing by
generation new vectors. Usually the seed to generate stimulus is the system time.
Whenever a regression is done, it will take the current system time and generate new
vectors than earlier tested. This way testbench can reach corners of DUT.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/TB_35_REGRESSION.html[9/26/2012 2:41:54 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
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TUTORIALS
TIPS
SystemVerilog
How To Avoid &Quot;Module Xxx Already Defined&Quot; Error
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Sometimes compilation error "module xxx already defined" is tough to avoid when
hundreds of files are there. Its hard to find where ìnclude is including xxx file and
how many times the file is given in compilation command.
EXAMPLE: xxx.v file
modulexxx();
initial
$display(" MODULE ");
endmodule
EXAMPLE: yyy.v file
ìnclude"xxx.v"
moduleyyy()
endmodule
AVM Switch TB
VMM Ethernet sample Now compile with any of the comand.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
compile_ur_command xxx.v yyy.v

compile_ur_command xxx.v yyy.v yyy.v
To avoid this problem, Just use compilation switches. In the following example initial
macros XXX and YYY are not defined. When the compiler comes the xxx.v file first
times, macro XXX is defined. Nedtime when the comes across xxx.v, as already the
macro XXX is defined, it will neglect the module definition.
EXAMPLE: xxx.v file
ìfndefXXX
`defineXXX
modulexxx();
RVM Ethernet sample initial
$display(" MODULE ");
Specman E
Interview Questions
endmodule
èndif
EXAMPLE: yyy.v file
ìnclude"xxx.v"
ìfndefYYY
`defineYYY
moduleyyy()
endmodule
èndif
http://testbench.in/TB_36_TIPS.html[9/26/2012 2:42:03 PM]
Index
Introduction
Linear Tb
File Io Tb
Task Based Tb
Verification Flow
Clock Generator
Simulation
Store And Restore
Stimulus Generation
A Myth
Race Condition
Checker
Task And Function
Process Control
Watchdog
Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Terimination
Error Injuction
Regression
Tips
input is what keeps
with time!
Now compile with any of the command.

compile_ur_command xxx.v yyy.v
compile_ur_command xxx.v yyy.v yyy.v
You will not see any compilation error.
Colourful Messages:
Look at the picture. Do you want to make your Linux terminal colorful like this, while
you run yourverilog code?
Copy the following code and simulate in batch mode in Linux. What you can see is
colorful messages from verilog.
CODE:
modulecolour();
initial
begin
$write("%c[1;34m",27);
$display("*********** This is in blue ***********");
$write("%c[0m",27);
$display("%c[1;31m",27);
$display("*********** This is in red ***********");
$display("%c[0m",27);
$display("%c[4;33m",27);
$display("*********** This is in brown ***********");
$display("%c[5;34m",27);
$display("*********** This is in green ***********");
$display("%c[7;34m",27);
$display("*********** This is in Back ground color ***********");
end
endmodule
This works only in Linux or Unix terminals. To get required colors, ("%c[1;34m",27);
should be used to print once. Ordinary messages following this messages continue to
be the color specified.
Lets see how to get different colors and font format.
The message to be printed is("%c[TYPE;COLOURm",27);.
TYPE specifies how the message should be?
1
2
4
5
7
set bold
set half-bright (simulated with color on a color display)
set underscore (simulated with color on a color display)
set blink
set reverse video
COLOR specifies the message color.

30
31
32
33
34
35
36
37
set black foreground

set red foreground
set green foreground
set brown foreground
set blue foreground
set magenta foreground
set cyan foreground
set white foreground
If you really want to use in your environment, use macros.

`definedisplay_blue$write("%c[0m",27);$write("%c[1;34m",27);$display
`definedisplay_red $write("%c[0m",27);$write("%c[1;31m",27);$display
`definedisplay_green $write("%c[0m",27);$write("%c[1;32m",27);$display
Use the macros instead of $display().
EXAMPLE:
modulecolor();
initial
begin
`display_blue(" ******** this is blue ********** ");
`display_red(" ******** this is red ********** ");
`display_green(" ******** this is green ********** ");
end
endmodule
Debugging Macros
Most tools don't support Debugging Macros. The compilation error information is not
enough to find the exactly line where the bug is. In simulation/Compilation steps ,
the first step is Macro preprocessing. The macro preprocessing step performs textual
substitutions of macros defined with `define statements, textual inclusion with
ìnclude statements, and conditional compilation by ìfdef and ìfndef statements.
EXAMPLE:
`defineSUM(A,B)A +B ;
moduleexample();
integera,b,c;
initial
a =SUM(b,c);
endmodule
Run the above example and check where the error is.
The find the exact cause of error, simply use the C pre-processor.
Just use command
cpp file_name.v
NOTE: cpp cannot understand `define. Before using cpp, covert all `define to
#define.
Output of the above code using cpp preprocessor is
RESULTS
#
#
#
#
1
1
1
1
"fine_name.v"
"<built-in>"
"<command line>"
"fine_name.v"
module example();
integer a,b,c;
initial
a = b + c ;;
endmodule
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Index
Dut Specification
This DUT is a simple switch, which can drive the incoming packet to destination ports Rtl
Top
Packet
The dut contain one input interface from which the packet enters the dut. It has four Driver
Reciever
Scoreboard
Env
DUT SPECIFICATION
Randomization

input is what keeps
with time!
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
Packet format:
OpenVera
Constructs
Packet contains Header, data and frame check sequence. Packet width is 8 bits and
the length of the packet can be between 4 bytes to 259 bytes.
Switch TB
Packet header:
RVM Ethernet sample DA: Destination address of the packet. It is 8 bits. The switch drives the packet to
RVM Switch TB
Specman E
Interview Questions

header and data.
http://testbench.in/VS_01_DUT_SPECIFICATION.html[9/26/2012 2:42:12 PM]
Configuration:
Memory Interface:
Input Interface:
to become low after sending last byte of the packet.
When the dut is busy, and if it is not in a position to accept any more data, it will
assert busy signal. Data which is sent during this busy signal is lost if input is driving
when busy is high
Output Interface:
data signal.
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TUTORIALS
RTL
SystemVerilog
CODE: switch.v
modulefifo (clk,
reset,
Constructs
write_enb,
read,
Interface
data_in,
OOPS
data_out,
empty,
Randomization
full);
Functional Coverage
input clk;
Assertion
input reset;
inputwrite_enb;
DPI
inputread;
UVM Tutorial
input[7:0]data_in;
VMM Tutorial
outputempty;
OVM Tutorial
outputfull;
wire clk;
Easy Labs : SV
wirewrite_enb;
Easy Labs : UVM
wireread;
wire [7:0]data_in;
Easy Labs : OVM
reg[7:0]data_out;
Easy Labs : VMM
wireempty;
wirefull;
AVM Switch TB
reg[7:0]ram[0:25];
VMM Ethernet sample regtmp_empty;
regtmp_full;
integerwrite_ptr;
integerread_ptr;
Verilog
Verification
begin
Verilog Switch TB
data_out=8'b0000_0000;
tmp_empty =1'b1;
Basic Constructs
tmp_full=1'b0;
write_ptr =0;
read_ptr=0;
OpenVera
end
Verification
Constructs
assignempty=tmp_empty;
assignfull=tmp_full;
RVM Switch TB
always@(posedgeclk)begin
RVM Ethernet sample if((write_enb ==1'b1)&&(tmp_full ==1'b0))begin
tmp_empty <=1'b0;
Specman E
tmp_full <=1'b1;
Interview Questions
end
end
Switch TB

tmp_full <=1'b0;
tmp_empty <=1'b1;
end
http://testbench.in/VS_02_RTL.html[9/26/2012 2:42:22 PM]
Index
Dut Specification
Rtl
Top
Packet
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
end
end
endmodule//fifo
moduleport_fsm (clk,
reset,
write_enb,
ffee,
hold,
data_status,
data_in,
data_out,
mem0,
mem1,
mem2,
mem3,
addr);
inputclk;
inputreset;
input [7:0] mem0;
input [7:0] mem1;
input [7:0] mem2;
input [7:0] mem3;
inputffee;
inputhold;
inputdata_status;
input[7:0]data_in;
output[7:0] addr;
reg[7:0]data_out;
reg[7:0]addr;
regfsm_write_enb;
reg[3:0]state_r;
reg[3:0]state;
reg[7:0]parity;
parameterADDR_WAIT =4'b0000;
parameterDATA_LOAD =4'b0001;
parameterPARITY_LOAD=4'b0010;
parameterHOLD_STATE=4'b0011;
parameterBUSY_STATE=4'b0100;
begin
error=1'b0;
data_out =8'b0000_0000;
addr =8'b00000000;
write_enb_r=3'b000;
fsm_write_enb=1'b0;
state_r=4'b0000;
state=4'b0000;
parity =8'b0000_0000;
sus_data_in=1'b0;
end
assignbusy =sus_data_in;
always@(data_status)begin:addr_mux
case(data_in)
mem0 :begin
end
mem1 :begin
end
mem2 :begin
end
mem3 :begin
end
endcase
//$display("
data_inii
%d
,mem0
end//if
end//addr_mux;
always@(posedgeclk)begin:fsm_state
state_r <=state;
end//fsm_state;
%d
,mem1
%d
,mem2
%d
always@(state_r ordata_status orffee orhold ordata_in)

begin:fsm_core
state =state_r; //Default state assignment
case(state_r)
ADDR_WAIT: begin
==data_in)))begin
state =DATA_LOAD;
end
elsebegin
state =BUSY_STATE;
end//if
end//if;
sus_data_in =!ffee;
==data_in))&&
(ffee ==1'b1))begin
addr =data_in;
data_out=data_in;
end
elsebegin
end//if
PARITY_LOAD:begin
state =ADDR_WAIT;
data_out =data_in;
DATA_LOAD: begin
(hold ==1'b0))begin
state =DATA_LOAD;
end
(hold ==1'b0))begin
state =PARITY_LOAD;
end
elsebegin
state =HOLD_STATE;
end//if
sus_data_in =1'b0;
(hold ==1'b0))begin
data_out =data_in;
end
(hold ==1'b0))begin
data_out =data_in;
end
elsebegin
end//if
HOLD_STATE:begin
state =HOLD_STATE;
end
state =PARITY_LOAD;
end
elsebegin
state =DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out =data_in;
end//if
BUSY_STATE:begin
state =BUSY_STATE;
end
elsebegin
state =DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out=data_in;
end//if
endcase
end//fsm_core
endmodule//port_fsm
moduleswitch (clk,
reset,
data_status,
data,
port0,
port1,
port2,
port3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3,
mem_en,
mem_rd_wr,
mem_add,
mem_data);
inputclk;
inputreset;
inputdata_status;
input[7:0]data;
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
wirell0;
wirell1;
wirell2;
wirell3;
wireempty_0;
wireempty_1;
wireempty_2;
wireempty_3;
wireffee;
wireffee0;
wireffee1;
wireffee2;
wireffee3;
wireld0;
wireld1;
wireld2;
wireld3;
wirehold;
wire [7:0]addr;
reg[7:0]mem[3:0];
wirereset;
.reset (reset),
.read(read_0),
.empty (empty_0),
.full(ll0));
.reset (reset),
.read(read_1),
.empty (empty_1),
.full(ll1));
.reset (reset),
.read(read_2),
.empty (empty_2),
.full(ll2));
.reset (reset),
.read(read_3),
.empty (empty_3),
.full(ll3));

.reset (reset),
.ffee(ffee),
.hold(hold),
.data_in (data),
.mem0(mem[0]),
.mem1(mem[1]),
.mem2(mem[2]),
.mem3(mem[3]),
.addr(addr));
assignport0 =data_out_0; //make note assignment only for
|(addr
|(addr
|(addr
|(addr
!=mem[0]));
!=mem[1]));
!=mem[2]));
!=mem[3]));
assignffee=ffee0 &ffee1 &ffee2 &ffee3;

assignld0
assignld1
assignld2
assignld3
=(ll0
=(ll1
=(ll2
=(ll3
&(addr
&(addr
&(addr
&(addr
==mem[0]));
==mem[1]));
==mem[2]));
==mem[3]));
assignhold =ld0 |ld1 |ld2 |ld3;

always@(posedgeclk)
begin
if(mem_en)
if(mem_rd_wr)
begin
end
end
endmodule//router
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TUTORIALS
TOP
SystemVerilog
Verification Environment:
Verification
Constructs
Interface
This is simple verification environment.

It has top,tb,packet,Driver, Scoreboard and Receiver components.
OOPS
Randomization

input is what keeps
with time!
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Top Module:
Basic Constructs
Top module contains the instance of the Dut and verification environment.
It also has the clock generator. For more information about clock generation, go
through TB_CONCEPTS in this website. Do reset and Confgure the dut port address.
OpenVera
Index
Dut Specification
Rtl
Top
Packet
Driver
Reciever
Scoreboard
Env
CODE: top
moduletop();
Switch TB
regclock;
wirepacket_valid;
RVM Switch TB
wire[7:0]data;
RVM Ethernet sample wire[7:0]data_0;
wire[7:0]data_1;
wire[7:0]data_2;
wire[7:0]data_3;
Specman E
wireready_0;
Interview Questions
wireready_1;
wireready_2;
wireready_3;
wireread_0;
wireread_1;
wireread_2;
wireread_3;
regreset;
regmem_en;
regmem_rd_wr;
Constructs
http://testbench.in/VS_03_TOP.html[9/26/2012 2:42:32 PM]
reg[7:0]mem_data;
reg[1:0]mem_add;
reg[7:0]mem[3:0];
// take istance of testbench
sw_tbtb(clock,
packet_valid,
data,
data_0,
data_1,
data_2,
data_3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3);
// take instance dut
switch dut (clock,
reset,
packet_valid,
data,
data_0,
data_1,
data_2,
data_3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3,
mem_en,
mem_rd_wr,
mem_add,
mem_data);
//Clock generator
initial
clock =0;
always
begin
#5clock =!clock;
end
// Do reset and configure the dut port address
initialbegin
$dumpon;
mem[0]=$random;
mem[1]=$random;
mem[2]=$random;
mem[3]=$random;
mem_en =0;
@(posedgeclock);
#2reset =1;
@(posedgeclock);
#2reset =0;
mem_en =1;
@(negedgeclock);
mem_rd_wr =1;
mem_add =0;
mem_data =mem[0];
@(negedgeclock);
mem_rd_wr =1;
mem_add =1;
mem_data =mem[1];
@(negedgeclock);
mem_rd_wr =1;
mem_add =2;
mem_data =mem[2];
@(negedgeclock);
mem_rd_wr =1;
mem_add =3;
mem_data =mem[3];
@(negedgeclock);
mem_en=0;
mem_rd_wr =0;
mem_add =0;
mem_data =0;
end
endmodule//top
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TUTORIALS
PACKET
SystemVerilog
Packet is a class with all the fields in the packet randomly.

Types of possible packets :
Packet with DA with one of the configured port address..
Packets with DA which has unconfigured address.
Packets with valid and invalid length.
Packets with good and bad FCS.
Payload size types: SMALL, MEDIUM and LARGE
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Define a task which can generate the above feilds randomly. Defind a task which does Report a Bug or Comment
packing.
input is what keeps
Creat a parity function and call it in packing.
CODE: packet.v
`defineSMALL0
`defineMEDIUM1
`defineLARGE2
`defineGOOD0
`defineBAD1
Easy Labs : OVM
modulepktgen();
integerpayload_size;//Control field for the payload size
integerparity_type;// Control feild for the parity type.
AVM Switch TB
reg[0:7]uid;// Unique id field to identify the packet
VMM Ethernet sample
reg[7:0]len;
reg[7:0]Da;
reg[7:0]Sa;
Verilog
reg[0:7]pkt [0:64];//Size = MAX pkt size
Verification
reg[0:7]parity;
Easy Labs : VMM
Verilog Switch TB
Basic Constructs
Index
Dut Specification
Rtl
Top
Packet
Driver
Reciever
Scoreboard
Env
initial
uid =0;
taskrandomize();
begin
Constructs
uid =uid +1;
parity_type={$random}%2;// 0 and 1 are selected randomly
Switch TB
payload_size={$random}%3;// 0,1,2 are selected randomly
RVM Switch TB
Da =top.mem[({$random}%3)];//{$random}%3;// 0,1,2,3 are selected randomly
RVM Ethernet sample Sa =$random;
if(payload_size==`SMALL)
len={$random}%10;
elseif(payload_size==`MEDIUM)
Specman E
len=10+{$random}%10;
elseif(payload_size==`LARGE)
Interview Questions
len=20+{$random()}%10;
elselen={$random()}%10;
if(parity_type==0)
parity=8'b0;
else
parity=8'b1;
end
endtask
OpenVera
http://testbench.in/VS_04_PACKET.html[9/26/2012 2:42:42 PM]
with time!
taskpacking();
integeri;
begin
pkt[0]=Da;
pkt[1]=Sa;
pkt[2]=len;
$display("[PACKING]
pkt[0]
is
",pkt[0],Da,Sa,Sa,len,len);
for(i =0;i<len+3;i=i+1)
pkt[i+3]=$random();
pkt[3]=uid;
pkt[i+3]=parity ^parity_cal(0);
end
endtask
Da
%b
%d
Sa
%b
%d
len
// parity_calc()
//
// Return the byte resulting from xor-ing among all data bytes
// and the byte resulting from concatenating addr and len
//////////////////////////////////////////////////////////////
function[0:7]parity_cal(inputdummy);
integeri;
reg[0:7]result ;
begin
result =8'hff;
for(i =0;i<len+4;i=i+1)
begin
result =result ^pkt[i];
end
parity_cal=result;
end
endfunction
endmodule
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http://testbench.in/VS_04_PACKET.html[9/26/2012 2:42:42 PM]
%b %d
Search
TUTORIALS
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Interface
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UVM Tutorial
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Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Index
Dut Specification
Rtl
Take an instance of packet
Top
Define task to generate the packet and call the drive task.
This task first, calls randomize task in the packet then calls the pack to packing the Packet
Driver
packet.
Calls the drive packet wich drives the packet to dut. Then add the sent packet to Reciever
Scoreboard
score board.
Env
CODE:driver.v
DRIVER
moduledriver(clock,packet_valid,data,busy);
outputpacket_valid;
output[7:0]data;
input busy;
inputclock;
regpacket_valid;
reg[7:0]data;
integerdelay;
// Take an instance of packet
pktgen gen();
//Define task to generate the packet and call the drive task
taskgen_and_drive(inputintegerno_of_pkts);
integeri;
begin
VMM Ethernet sample for(i=0;i<no_of_pkts;i=i+1)
Switch TB
begin
delay={$random()}%4;
$display("DRIVER gen and drive pkt_no = %d delay %d",i,delay);
repeat(delay)@(negedgeclock);
// randomize the packet
gen.randomize();
//pack the packet
gen.packing();
// call the drive packet task.
@(negedgeclock);
drive_packet();
// add the sent packet to score board
top.tb.sb.add_pkt(i);
RVM Switch TB
end
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
endtask
Specman E
Interview Questions
taskdrive_packet();
integeri;
begin
$display("DRIVER Starting to drive packet to port %0d len %0d ",gen.Da,gen.len);
repeat(4)@(negedgeclock);
for(i=0;i<gen.len+4;i=i+1)
begin
@(negedgeclock);
packet_valid =1;
data[7:0]=gen.pkt[i];
http://testbench.in/VS_05_DRIVER.html[9/26/2012 2:42:51 PM]

input is what keeps
with time!
$display("[DRIVER] data %b at i %d",gen.pkt[i],i);

end
@(negedgeclock);
packet_valid =0;
@(negedgeclock);
end
endtask
endmodule
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Easy Labs : SV
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Easy Labs : OVM
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Index
Dut Specification
Rtl
Top
Build a receiver which can collect a packet on single port.
Packet
Define a task to unpack the recived packet.
Define a task to check whether the received packet and sent packet are same are not. Driver
Reciever
In the initial block Start collecting packet.
Scoreboard
Do unpacking,Call the checker task
Checker Checks whether the packet is coming on the proper port or not, then checker Env
gets the packet from scoreboard and comares the recived packet with the sent
packet. If any error is there then error is asserted.
RECIEVER
CODE:receiver.v
modulereceiver(clk,data,ready,read,port);
inputready;
inputclk;
input[7:0]data;
inputport;
outputread;
regread;
reg[0:7]mem [0:65];
wire[31:0]port;
integerj,delay;
reg[7:0]rec_address;
// Start collecting packet
initial
begin
while(1)
begin
begin
@(posedgeready)
delay={$random()}%5+1;
repeat(delay)@(negedgeclk);
Constructs
j=0;
@(negedgeclk);
read=1'b1;
RVM Switch TB
while(ready==1'b1)
@(negedgeclk);
mem[j]=data;
j=j+1;
Specman E
$display(" RECV BYTE at PORT[%d] %b",port,data);
Switch TB
Interview Questions
end//while
read=1'b0;
end
// Do unpacking
unpacking();
// Call the checker task
checker((j-1));
end
end
// Do unpack of the packet recived.
http://testbench.in/VS_06_RECIEVER.html[9/26/2012 2:42:59 PM]
input is what keeps

with time!
taskunpacking;
reg[7:0]rec_parity;
reg[7:0]rec_paclen;
reg[7:0]separate;
reg[7:0]rec_data[0:63];
begin
rec_paclen=mem[2];
rec_parity=mem[rec_paclen+3];
rec_address=mem[0];
$display("rec_parity=%b
rec_paclen=%0d
%b,
rec_address=%b
%b",rec_parity,rec_paclen,rec_paclen,rec_address,mem[0]);
end
endtask
header
taskchecker(inputintegersize);
integeri;
begin
$display("[CHECKER] Checker started for pkt_no %d ",top.tb.sb.pkt_no );
if(rec_address!=top.mem[port])
begin
->top.tb.error;
// Check whether the packet is coming on the proper port or not
$display("[CHECKER] ERROR PKT RECIVED ON PORT %d,PKT ADDRESS is
%d",top.mem[port],rec_address);
end
for(i=0;i<size;i=i+1)
// get the packet from score board and comare the recived packet with the sent
packet.
if(top.tb.sb.sent_pkt[i][top.tb.sb.pkt_no]!==mem[i])
begin
$display("[CHECKER] ERROR at %d pkt no %d ",i,top.tb.sb.pkt_no);
$display("[CHECKER]
at
%d
sentbyte
%b
rcevbyte
%b",i,top.tb.sb.sent_pkt[i][top.tb.sb.pkt_no],mem[i]);
->top.tb.error;
end
else
begin
$display("[CHECKER]
at
%d
sentbyte
%b
rcevbyte
%b",i,top.tb.sb.sent_pkt[i][top.tb.sb.pkt_no],mem[i]);
end
top.tb.sb.pkt_no=top.tb.sb.pkt_no+1;
end
endtask
endmodule
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TUTORIALS
SCOREBOARD
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
The expected packets are stored in scored board by driver.

Declare a memory to store sent packets
task to add packets to scoreboard
CODE: scoreboard.v
modulescoreboard();
// Declare a memory to store sent packets
reg[0:7]sent_pkt [0:64][0:10];
integerpkt_no;
initial
pkt_no=0;
// task to add packets to scoreboard
taskadd_pkt(inputintegerpkt_no);
integeri;
begin
for(i=0;i<65;i=i+1)
sent_pkt[i][pkt_no]=top.tb.dv.gen.pkt[i];
end
endtask
endmodule
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/VS_07_SCOREBOARD.html[9/26/2012 2:43:08 PM]
Index
Dut Specification
Rtl
Top
Packet
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Index
Dut Specification
Env is a module which contains all the components of verification. A logic to Rtl
Top
increment the error counter.
Take a Driver instance and creat four reciever instancess. connect it to specific port. Packet
Driver
Creat instance of scoreboard
Reciever
Call then packet gen and drive task in driver
Scoreboard
Creat a finish task which display the tesults of the test.
Env
CODE:env.v
ENV
Functional Coverage
modulesw_tb(clock,
Assertion
packet_valid,
data ,
DPI
data_0 ,
UVM Tutorial
data_1 ,
data_2 ,
VMM Tutorial
data_3 ,
OVM Tutorial
ready_0 ,
ready_1 ,
Easy Labs : SV
ready_2 ,
Easy Labs : UVM
ready_3 ,
read_0 ,
Easy Labs : OVM
read_1 ,
Easy Labs : VMM
read_2,
read_3
AVM Switch TB
);
VMM Ethernet sample inputclock;
outputpacket_valid;
output[7:0]data;
input [7:0]data_0;
Verilog
input [7:0]data_1;
Verification
input [7:0]data_2;
Verilog Switch TB
input [7:0]data_3;
input ready_0;
Basic Constructs
input ready_1;
input ready_2;
input ready_3;
OpenVera
output read_0;
Constructs
output read_1;
output read_2;
Switch TB
output read_3;
RVM Switch TB
regpkt_status;
RVM Ethernet sample integererror_count=0;
eventerror;
Specman E
Interview Questions
//Incriment the error counter on error.

always@(error)
begin
#0error_count=error_count+1;
$display(" ERROR RECIVED");
end
// Driver instance
driver dv(clock,packet_valid,data,busy);
// Make four reciever instancess. connect it to specific port.
receiver rec0(.clk(clock),.data(data_0),.ready(ready_0),
.read(read_0),
http://testbench.in/VS_08_ENV.html[9/26/2012 2:43:16 PM]

input is what keeps
with time!
.port(0)
);
.read(read_1),
.port(1)
);
.read(read_2),
.port(2)
);
.read(read_3),
.port(3)
);
// Creat instance of scoreboard
scoreboard sb();
// Call then packet gen and drive task in driver
initial
begin
#100;
dv.gen_and_drive(9);
#1000;
finish;
end
// finish task which display the tesults of the test.
taskfinish();
begin
if(error_count!=0)
$display("############# TEST FAILED ###############");
else
$display("############# TEST PASSED ###############");
$finish;
end
endtask
endmodule
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TUTORIALS
INTRODUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
This tutorial is aimed at the beginner. For Advanced Verilog for Verification topics ,
refer to Advanced Verilog for Verification
Introduction
The Verilog Hardware Description Language (Verilog HDL) became an IEEE standard
in 1995 as IEEE Std 1364-1995. Verilog HDL is a formal notation intended for use in all
phases of the creation of electronic systems. Because it is both machine readable and
human readable, it supports the development, verification, synthesis, and testing of
hardware designs; the communication of hardware design data; and the maintenance, Report a Bug or Comment
modification, and procurement of hardware.
input is what keeps
Verilog contains a rich set of built-in primitives, including logic gates, user-definable with time!
primitives, switches,
and wired logic. It also has device pin-to-pin delays and timing checks.
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Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
The Verilog language is extensible via the Programming Language Interface (PLI) and
the Verilog Procedural
Interface (VPI) routines.
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Comments : Verilog comments are the same as in C++. Use // for a single line
comment or /**/ for a multiline comment.
Punctuation : white spaces are ignored in Verilog. A semicolon is used to indicate the
end of a command line and commas are typically used to separate elements in a list.
Like C++, Verilog is case sensitive.
Identifiers : An identifier is usually a variable. You can use any letter, digit, the
underscore, or $. Identifiers may not begin with a digit and may not be the same as a
Verilog key word. As in C++ variable names should be chosen to assist in Report a Bug or Comment
documentation.
input is what keeps
Signal values : signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic Testbench.in improving
with time!
1), ?, X, or x ( don<92>t care or unknown), and Z or z for high impedance tri-state.
Parameters : a parameter in Verilog can be any Verilog constant. Parameters are used
to generalize a design. For example a 4-bit adder becomes more useful as a design if
it is put together as an n-bit adder where n is a parameter specified by the user
before compilation. Parameter declarations are done immediately after the module
declaration. Here are some typical parameter examples:
EXAMPLE:
parametern =12;
VMM Ethernet sample parameter[3:0]p1 =4'b1011;
parametern =12,m =32;
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Verification
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Basic Constructs
Memory : Verilog allows for two dimensional arrays which typically get used for
memory spaces. For example reg[7:0] m[63:0]; declares m to be a two-dimensional
array consisting of 64 eight-bit words. You can access any word as m[2] for example
but you do not get access to the bits in the word unless you copy the word to another
8-bit reg variable.
Strings : Strings are delimited by " ... ", and cannot be on multiple lines.
OpenVera
Constructs
"hello world"; // legal string
Number:Numbers in verilog are in the following format.

The size is always specified as a decimal number. If no is specified then the default
RVM Switch TB
size is at least 32bits and may be larger depending on the machine. Valid base formats
RVM Ethernet sample are 'b , 'B , 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal, decimal, and octal. Numbers
consist of strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean unknown, and the
Z's mean high impedance If no base format is specified the number is assumed to be a
decimal number. Some examples of valid numbers are:
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Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
EXAMPLE: Unsized constant numbers

659// is a decimal number
'h 837FF// is a hexadecimal number
'o7460// is an octal number
4af // is illegal (hexadecimal format requires <92>h)
EXAMPLE: Sized constant numbers
4'b1001// is a 4-bit binary number
5'D 3// is a 5-bit decimal number
http://testbench.in/VT_02_SYNTAX.html[9/26/2012 2:43:34 PM]
3'b01x// is a 3-bit number with the least

// significant bit unknown
12'hx// is a 12-bit unknown number
16'hz// is a 16-bit high-impedance number
EXAMPLE: Using sign with constant numbers

8'd -6// this is illegal syntax
-8'd 6// this defines the two<92>s complement of 6,
// held in 8 bits<97>equivalent to -(8<92>d 6)
4'hf// this denotes the 4-bit number <91>1111<92>, to
// be interpreted as a 2<92>s complement number,
// or <91>-1<92>. This is equivalent to -4<92>h 1
-4'sd15 // this is equivalent to -(-4<92>d 1), or <91>0001<92>.
EXAMPLE: Automatic left padding
reg[11:0]a,b,c,d;
initialbegin
a ='h x;// yields xxx
b ='h 3x;// yields 03x
c ='h z3;// yields zz3
d ='h 0z3;// yields 0z3
end
reg[84:0]e,f,g;
e ='h5;// yields {82{1'b0},3'b101}
f ='hx;// yields {85{1'hx}}
g ='hz;// yields {85{1'hz}}
EXAMPLE: Using underscore character in numbers
27_195_000
16'b0011_0101_0001_1111
32'h 12ab_f001
EXAMPLE: Real constants
1.2
0.1
2394.26331
1.2E12 (the exponent symbol can be e orE)
1.30e-2
0.1e-0
23E10
29E-2
236.123_763_e-12(underscores are ignored)
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The Verilog HDL value set consists of four basic values:

0 - represents a logic zero, or a false condition
1 - represents a logic one, or a true condition
x - represents an unknown logic value
z - represents a high-impedance state
The values 0 and 1 are logical complements of one another.

input is what keeps
The net data types shall represent physical connections between structural entities, Testbench.in improving
such as gates. A net shall not store a value (except for the trireg net). Instead, its with time!
Net
value shall be determined by the values of its drivers,such as a continuous

assignment or a gate. If no driver is connected to a net, its value shall be highimpedance (z) unless the net is a trireg, in which case it shall hold the previously
driven value. It is illegal to redeclare a name already declared by a net, parameter,
or variable declaration.
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Constructs
A variable is an abstraction of a data storage element. A variable shall store a value

from one assignment to the next. An assignment statement in a procedure acts as a
trigger that changes the value in the data storage element. The initialization value for
reg, time, and integer data types shall be the unknown value, x. The default
initialization value for real and realtime variable datatypes shall be 0.0. If a variable
declaration assignment is used , the variable shall take this value as if the assignment
occurred in a blocking assignment in an initial construct. It is illegal to redeclare a
name already declared by a net, parameter, or variable declaration.
Vectors
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A net or reg declaration without a range specification shall be considered 1 bit wide
and is known as a scalar. Multiple bit net and reg data types shall be declared by
RVM Ethernet sample specifying a range, which is known as a vector.
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Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
EXAMPLES:
wandw;// a scalar net of type wand
tri[15:0]busa;// a three-state 16-bit bus
trireg(small)storeit;// a charge storage node of strength small
rega;// a scalar reg
reg[3:0]v;// a 4-bit vector reg made up of (from most to
// least significant) v[3], v[2], v[1], and v[0]
regsigned[3:0]signed_reg;// a 4-bit vector in range -8 to 7
reg[-1:4]b;// a 6-bit vector reg
wirew1,w2;// declares two wires
reg[4:0]x,y,z;// declares three 5-bit regs
Memories
http://testbench.in/VT_03_DATA_TYPES.html[9/26/2012 2:43:42 PM]
A one dimensional array with elements of type reg is also called a memory. These
memories can be used to model read-only memories (ROMs), random access memories
(RAMs), and reg files. Each reg in the array is known as an element or word and is
addressed by a single array index. An n-bit reg can be assigned a value in a single
assignment, but a complete memory cannot. To assign a value to a memory word, an
index shall be specified. The index can be an expression. This option provides a
mechanism to reference different memory words, depending on the value of other
variables and nets in the circuit. For example, a program counter reg could be used
to index into a RAM.
EXAMPLE:
reg[7:0]mema[0:255];// declares a memory mema of 256 8-bit
// registers. The indices are 0 to 255
regarrayb[7:0][0:255];// declare a two dimensional array of
// one bit registers
wirew_array[7:0][5:0];// declare array of wires
integerinta[1:64];// an array of 64 integer values
timechng_hist[1:1000]// an array of 1000 time values
mema =0;// Illegal syntax- Attempt to write to entire array
arrayb[1]=0;// Illegal Syntax - Attempt to write to elements
// [1][0]..[1][255]
arrayb[1][12:31]=0;// Illegal Syntax - Attempt to write to
// elements [1][12]..[1][31]
mema[1]=0;//Assigns 0 to the second element of mema
arrayb[1][0]=0;// Assigns 0 to the bit referenced by indices
// [1][0]
inta[4]=33559;// Assign decimal number to integer in array
chng_hist[t_index]=$time;// Assign current simulation time to
// element addressed by integer index
reg[1:n]rega;// An n-bit register is not the same
regmema [1:n];// as a memory of n 1-bit registers
Net Types
There are several distinct types of nets , they are
wire,tri,tri0,supply0,wand,triand,tri1,supply1,wor,trior,trireg.
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Index
Introduction
Syntax
Binary Arithmetic Operators
Data Types
Binary arithmetic operators operate on two operands. Register and net (wire) Operators
operands are treated as unsigned. However, real and integer operands may be signed. Assignments
Control Constructs
If any bit is unknown ('x') then result is unknown.
Procedural Timing
Controls
Structure
Operator Name
Block Statements
+ Addition
- Subtraction
OPERATORS
* Multiplication
/ Division
% Modulus
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Unary Arithmetic Operators
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OperatorName
- Unary Minus
Relational Operators
VMM Ethernet sample Relational operators compare two operands and return a logical value, i. e., TRUE(1)
or FALSE(0). If any bit is unknown, the relation is ambiguous and the result is
unknown.
Verilog
Verification
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Basic Constructs
OpenVera
OperatorName
>Greater than
>= Greater than or equal
<Less than
<= Less than or equal
== Logical equality
!= Logical inequality
Constructs
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Logical Operators
Logical operators operate on logical operands and return a logical value, i. e.,
TRUE(1) or FALSE(0). Used typically in if and while statements. Do not confuse logical
operators with the bitwise Boolean operators. For example , ! is a logical NOT and ~ is
a bitwise NOT. The first negates, e. g., !(5 == 6) is TRUE. The second complements
the bits, e. g., ~{1,0,1,1} is 0100.
OperatorName
! Logical negation
&&Logical AND
||Logical OR
Bitwise Operators
http://testbench.in/VT_04_OPERATORS.html[9/26/2012 2:43:52 PM]

input is what keeps
with time!
Bitwise operators operate on the bits of the operand or operands. For example, the
result of A & B is the AND of each corresponding bit of A with B. Operating on an
unknown (x) bit results in the expected value. For example, the AND of an x with a
FALSE is an x. The OR of an x with a TRUE is a TRUE.
OperatorName
~ Bitwise negation
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
~&Bitwise NAND
~|Bitwise NOR
~^ or ^~Equivalence Bitwise NOT XOR
Unary Reduction Operators

Unary reduction operators produce a single bit result from applying the operator to all
of the bits of the operand. For example, &A will AND all the bits of A.
OperatorName
& AND reduction
| OR reduction
^ XOR reduction
~&NAND reduction
~|NOR reduction
~^XNOR reduction
Other Operators
The conditional operator operates much like in the language C.
Operator Name
=== Case equality
!== Case inequality
{ , } Concatenation
<<Shift left
>>Shift right
?:Conditional
Case equality : The bitwise comparison includes comparison of x and z values.All

bits must match for equality.Returns TRUE or FALSE.
Case inequality : The bitwise comparison includes comparison of x and z values.Any
bit difference produces inequality.Returns TRUE or FALSE.
Concatenation : Joins bits together with 2 or more comma-separated
expressions,e, g. {A[0], B[1:7]} concatenates the zeroth bit of A tobits 1 to 7 of B.
Shift left: Vacated bit positions are filled with zeros, e. g., A = A << 2; shifts A
two bits to left with zero fill.
Shift right : Vacated bit positions are filled with zeros.
Conditional : Assigns one of two values depending on the conditional expression.E.
g., A = C>D ? B+3 : B-2means if C greater than D, the value of A is B+3 otherwise B2.
Operator Precedence
The precedence of operators is shown below. The top of the table is the highest
precedence and the bottom is the lowest. Operators on the same line have the same
precedence and associate left to right in an expression. Parentheses can be used to
change the precedence or clarify the situation. We strongly urge you to use
parentheses to improve readability.
!&~&|~|^~^+- (highest precedence)

*/%
+<<>>
<<=>>+
==!====~==
&~&^~^
|~|
&&
||
?:
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Index
Introduction
The assignment is the basic mechanism for placing values into nets and variables. Syntax
Data Types
There are two basic forms of assignments:
Operators
-- The continuous assignment, which assigns values to nets
Assignments
-- The procedural assignment, which assigns values to variables
Control Constructs
Procedural Timing
Controls
Structure
Legal left-hand side forms in assignment statements
Block Statements
----------------------------------------------------------------Statement typeLeft-hand side (LHS)
ASSIGNMENTS
----------------------------------------------------------------Continuous assignment Net (vector or scalar)

Constant bit select of a vector net
Constant part select of a vector net
Constant indexed part select of a vector net
Concatenation of any of the above four LHS
----------------------------------------------------------------Procedural assignment Variables (vector or scalar)
Bit-select of a vector reg, integer, or time
variable
Constant part select of a vector reg,
integer, or time variable
Memory word
Indexed part select of a vector reg,
integer, or time variable
Concatenation of regs; bit or part selects of
regs
-----------------------------------------------------------------
The following is an example of the use of a continuous assignment to model a 4-bit

adder.
EXAMPLE:
moduleadder (sum_out,carry_out,carry_in,ina,inb);
output[3:0]sum_out;
outputcarry_out;
input[3:0]ina,inb;
inputcarry_in;
wirecarry_out,carry_in;
wire[3:0]sum_out,ina,inb;
assign{carry_out,sum_out}=ina +inb +carry_in;
endmodule
RVM Ethernet sample The following is an example of the useof a Procedural assignment to model a
Specman E
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4-bitadder.
EXAMPLE:
moduleadder (sum_out,carry_out,carry_in,ina,inb);
output[3:0]sum_out;
outputcarry_out;
input[3:0]ina,inb;
inputcarry_in;
regcarry_out;
wirecarry_in;
reg[3:0]sum_out;
wire[3:0]ina,inb;
always@(ina orinb orcarry_in)
{carry_out,sum_out}=ina +inb +carry_in;
http://testbench.in/VT_05_ASSIGNMENTS.html[9/26/2012 2:43:59 PM]

input is what keeps
with time!
endmodule
Blocking Procedural Assignments
A blocking procedural assignment statement shall be executed before the execution of
the statements that follow it in a sequential block. A blocking procedural assignment
statement shall not prevent the execution of statements that follow it in a parallel
block .
EXAMPLE:
rega =0;
rega[3]=1;// a bit-select
rega[3:5]=7;// a part-select
mema[address]=8'hff;// assignment to a mem element
{carry,acc}=rega +regb;// a concatenation
The Nonblocking Procedural Assignment
The nonblocking procedural assignment allows assignment scheduling without blocking
the procedural flow. The nonblocking procedural assignment statement can be used
whenever several variable assignments within the same time step can be made
without regard to order or dependence upon each other.
EXAMPLE:
moduleevaluates2 (out);
outputout;
rega,b,c;
initialbegin
a =0;
b =1;
c =0;
end
alwaysc =#5~c;
always@(posedgec)begin
a <=b;// evaluates, schedules,
b <=a;// and executes in two steps
end
endmodule
Procedural Continuous Assignments
The procedural continuous assignments (using keywords assign and force) are
procedural statements that allow expressions to be driven continuously onto variables
or nets.
The left-hand side of the assignment in the assign statement shall be a variable
reference or a concatenation of variables. It shall not be a memory word (array
reference) or a bit-select or a part-select of a variable. In contrast, the left-hand
side of the assignment in the force statement can be a variable reference or a net
reference. It can be a concatenation of any of the above. Bit-selects and part-selects
of vector variables are not allowed.
Assign And Deassign Procedural Statements
The assign procedural continuous assignment statement shall override all procedural
assignments to a variable. The deassign procedural statement shall end a procedural
continuous assignment to a variable. The value of the variable shall remain the same
until the reg is assigned a new value through a procedural assignment or a procedural
continuous assignment.
EXAMPLE:
moduledff (q, d, clear, preset, clock);
outputq;
inputd,clear,preset,clock;
regq;
always@(clearorpreset)
if(!clear)
assignq =0;
elseif(!preset)
assignq =1;
else
deassignq;
q =d;
endmodule
Force And Release Procedural Statements
Another form of procedural continuous assignment is provided by the force and release
procedural statements. These statements have a similar effect to the assign-deassign
pair, but a force can be applied to nets as well as to variables. The left-hand side of
the assignment can be a variable, a net, a constant bit-select of a vector net, a partselect of a vector net, or a concatenation. It cannot be a memory word (array
reference) or a bit-select or a part-select of a vector variable.
A force statement to a variable shall override a procedural assignment or procedural
continuous assignment that takes place on the variable until a release procedural
statement is executed on the variable. After the release procedural statement is
executed, the variable shall not immediately change value (as would a net that is
assigned with a procedural continuous assignment). The value specified in the force
statement shall be maintained in the variable until the next procedural assignment
takes place, except in the case where a procedural continuous assignment is active on
the variable.
A force procedural statement on a net overrides all drivers of the net gate outputs,
module outputs, and continuous assignments until a release procedural statement is
executed on the net. Releasing a variable that currently has an active procedural
continuous assignment shall re-establish that assignment.
EXAMPLE:
moduletest;
rega,b,c,d;
wiree;
andand1 (e,a,b,c);
initialbegin
$monitor("%d d=%b,e=%b",$stime,d,e);
assignd =a &b &c;
a =1;
b =0;
c =1;
#10;
forced =(a |b |c);
forcee =(a |b |c);
#10$stop;
released;
releasee;
#10$finish;
end
endmodule
Results:
0d=0,e=0
10d=1,e=1
20d=0,e=0
Delays
Delays are not synthesysable. In a delayed assignment Dt time units pass before the
statement is executed and the left-hand assignment is made. With intra-assignment
delay, the right side is evaluated immediately but there is a delay of Dt before the
result is place in the left hand assignment. If another procedure changes a right-hand
side signal during Dt, it does not effect the output. Delays are not supported by
synthesis tools.
Inter Assignmnet Delay .
This is the most common delay used - sometimes also referred to as inter-assignment
delay control.
EXAMPLE:
#10q =x +y;
It simply waits for the appropriate number of timesteps before executing the
command.
Intra-Assignment Delay Control
With this kind of delay, the value of x + y is stored at the time that the assignment is
executed, but this value is not assigned to q until after the delay period, regardless of
whether or not x or y have changed during that time.
EXAMPLE:
q =#10x +y;
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CONTROL CONSTRUCTS
SystemVerilog
Verilog HDL has a rich collection of control statements which can used in the
procedural sections of code, i. e., within an initial or always block. Most of them will
be familiar to the programmer of traditional programming languages like C. The main
difference is instead of C's { } brackets, Verilog HDL uses begin and end. In Verilog,
the { } brackets are used for concatenation of bit strings. Since most users are
familiar with C, the following subsections typically show only an example of each
construct.
Verification
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If And If Else Statements
The conditional statement (or if-else statement) is used to make a decision as to

whether a statement is executed or not.
EXAMPLE:
if(A ==4)
begin
B =2;
end
else
begin
B =4;
end
Case
VMM Ethernet sample The case statement is a multiway decision statement that tests whether an
expression matches one of a number of other expressions and branches accordingly.
Verilog
Verification
Verilog Switch TB
Basic Constructs
case(<expression>)
<value1>:<statement>
<value2>:<statement>
default:<statement>
endcase
The following example checks a 1-bit signal for its value.
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EXAMPLE:
case(sig)
1'bz:$display("Signal is floating");
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1'bx:$display("Signal is unknown");
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default:$display("Signal is %b",sig);
RVM Ethernet sample endcase
Constructs
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Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
Forever
Forever Continuously executes a statement or block till the end of simulation.
EXAMPLE:
initial
clock =0;
forever
#10clock =~clock;
end
Repeat
http://testbench.in/VT_06_CONTROL_CONSTRUCTS.html[9/26/2012 2:44:08 PM]

input is what keeps
with time!
Executes a statement a fixed number of times. If the expression evaluates to unknown

or high impedance, it shall be treated as zero, and no statement shall be executed.
EXAMPLE:
parametersize=8,longsize =16;
reg[size:1]opa,opb;
reg[longsize:1]result;
begin:mult
reg[longsize:1]shift_opa,shift_opb;
shift_opa =opa;
shift_opb =opb;
result =0;
repeat(size)begin
if(shift_opb[1])
result =result +shift_opa;
shift_opa =shift_opa <<1;
shift_opb =shift_opb >>1;
end
end
While
Executes a statement until an expression becomes false. If the expression starts out
false, the statement shall not be executed at all.
EXAMPLE:
begin:count1s
reg[7:0]tempreg;
count =0;
tempreg =rega;
while(tempreg)begin
if(tempreg[0])
count =count +1;
tempreg =tempreg >>1;
end
end
For
Controls execution of its associated statement(s) by a three-step process, as follows:
a) Executes an assignment normally used to initialize a variable that controls the
number of loops executed.
b) Evaluates an expression if the result is zero, the for-loop shall exit, and if it is not
zero, the for-loop shall execute its associated statement(s) and then perform step c.
If the expression evaluates to an unknown or high-impedance value, it shall be
treated as zero.
c) Executes an assignment normally used to modify the value of the loop-control
variable, then repeats step b.
EXAMPLE:
begin
initial_assignment;
while(condition)begin
statement
step_assignment;
end
end
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A procedural statement following the delay control shall be delayed in its execution
with respect to the procedural statement preceding the delay control by the specified
delay. If the delay expression evaluates to an unknown or high-impedance value, it
shall be interpreted as zero delay. If the delay expression evaluates to a negative
value, it shall be interpreted as a 2 s complement unsigned integer of the same size
as a time variable.
Specify parameters are permitted in the delay expression. They may be overridden by
SDF annotation, in which case the expression is reevaluated.
EXAMPLE
#10rega =regb;
#d rega =regb;// d is defined as a parameter
#((d+e)/2)rega =regb;// delay is average of d and e
#regr regr =regr +1;// delay is the value in regr
Event Control
The execution of a procedural statement can be synchronized with a value change on

a net or variable or the occurrence of a declared event. The value changes on nets
Easy Labs : VMM
and variable can be used as events to trigger the execution of a statement. This is
known as detecting an implicit event. The event can also be based on the direction of
AVM Switch TB
the change that is, towards the value 1 ( posedge) or towards the value 0 (negedge).
VMM Ethernet sample -- A negedge shall be detected on the transition from 1 to x, z, or 0, and from x or z
to 0
-- A posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z
to 1
Verilog
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Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE:
@r rega =regb;// controlled by any value change in the reg r
@(posedgeclock)rega =regb;// controlled by posedge on clock
forever@(negedgeclock)rega =regb;// controlled by negative edge
Named Events
A new data type, in addition to nets and variables, called event can be declared. An
identifier declared as an event data type is called a named event. A named event can
RVM Switch TB
be triggered explicitly. It can be used in an event expression to control the execution
RVM Ethernet sample of procedural statements in the same manner as event control . Named events can be
made to occur from a procedure. This allows control over the enabling of multiple
actions in other procedures. An event name shall be declared explicitly before it is
used.
Switch TB
Specman E
Interview Questions
http://testbench.in/VT_07_PROCEDURAL_TIMING_CONTROLS.html[9/26/2012 2:44:18 PM]
Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
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Assertion
DPI
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Index
Introduction
Syntax
Module
Data Types
A module in Verilog is used to define a circuit or a sub circuit. The module is the Operators
fundamental circuit building block in Verilog. Modules have the following structure: Assignments
(keywords in bold). Note that the module declaration ends with a semicolon but the Control Constructs
Procedural Timing
keyword endmodule does not.
Controls
Structure
Block Statements
CODE:
modulemodule_name (port_name list);
[declarations]
[assignstatements]
[initialblock]
input is what keeps
[alwaysblock]
[gate instantiations]
with time!
[other moduleinstantiations]
endmodule
STRUCTURE
Ports
Ports in Verilog can be of type input, output or inout. The module ports are given in
the port name list and are declared in the beginning of the module. Here is a sample
module with input and output ports.
AVM Switch TB
Verilog
Verification
moduleMyModule(aIn,bOut);
inputaIn;
outputbOut;
endmodule
Verilog Switch TB
Basic Constructs
The port names input and output default to type wire. Either can be a vector and the
output variables can be of redeclared to type reg. The output and input variables in a
module are typically names for the output and input pins on the implementation chip.
OpenVera
Constructs
Signals
Switch TB
a signal is represented by either a net type or a variable type in Verilog. The net type
represents a circuit node and these can be of several types. The two net types most
RVM Ethernet sample often used are wire and tri. Type nets do not have to be declared in Verilog since
Verilog assumes that all signals are nets unless they are declared otherwise. Variables
are either of type reg or integer. Integers are always 32-bits where the reg type of
variables may be of any length. Typically we use integers as loop counters and reg
Specman E
variables for all other variables. The generic form for representing a signal in Verilog
is:
Interview Questions
RVM Switch TB
CODE:
type[range]signal_name
The range is omitted for scalar variables but used for vectors.
The net types are typically used for input signals and for intermediate signals within
combinational logic. Variables are used for sequential circuits or for outputs which
are assigned a value within a sequential always block.
http://testbench.in/VT_08_STRUCTURE.html[9/26/2012 2:44:27 PM]
EXAMPLEs:
wirew;//w is a single net of type wire
wire[2:0]wVect;//Declares wVect[2], wVect[1], wVect[0]
tri[7:0]bus //An 8-bit tri state bus
integeri;//i is a 32-bit integer used for loop control
regr;//r is a 1-bit register
reg[7:0]buf;//buf is an 8-bit register
reg[3:0]r1,r2 //r1 and r2 are both 4-bit registers
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TUTORIALS
BLOCK STATEMENTS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
The block statements are a means of grouping two or more statements together so
that they act syntactically like a single statement. There are two types of blocks in
the Verilog HDL:
Sequential block, also called begin-end block
Parallel block, also called fork-join block
The sequential block shall be delimited by the keywords begin and end. The
procedural statements in sequential block shall be executed sequentially in the given
order.
The parallel block shall be delimited by the keywords fork and join. The procedural
statements in parallel block shall be executed concurrently.
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Sequential Blocks
A sequential block shall have the following characteristics:
-- Statements shall be executed in sequence, one after another
-- Delay values for each statement shall be treated relative to the simulation time of
the execution of the previous statement
-- Control shall pass out of the block after the last statement executes
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EXAMPLE:
begin
areg =breg;
VMM Ethernet sample creg =areg;// creg stores the value of breg
end
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Parallel Blocks
A parallel block shall have the following characteristics:
-- Statements shall execute concurrently
-- Delay values for each statement shall be considered relative to the simulation time
of entering the block
-- Delay control can be used to provide time-ordering for assignments
-- Control shall pass out of the block when the last time-ordered statement executes
Constructs
EXAMPLE:
fork
RVM Switch TB
@enable_a
#ta wa =0;
#ta wa =1;
#ta wa =0;
Specman E
end
@enable_b
Interview Questions
begin
#tb wb =1;
#tb wb =0;
#tb wb =1;
end
join
Switch TB
http://testbench.in/VT_09_BLOCK_STATEMENTS.html[9/26/2012 2:44:35 PM]
Index
Introduction
Syntax
Data Types
Operators
Assignments
Control Constructs
Procedural Timing
Controls
Structure
Block Statements
input is what keeps
with time!
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VMM Tutorial
Index
Introduction
Syntax
All procedures in the Verilog HDL are specified within one of the following four Data Types
Operators
statements:
Assignments
-- initial construct
Control Constructs
-- always construct
Procedural Timing
-- Task
Controls
-- Function
Structure
The initial and always constructs are enabled at the beginning of a simulation. The Block Statements
initial construct shall execute only once and its activity shall cease when the Structured Procedures
statement has finished. In contrast, the always construct shall execute repeatedly. Its
activity shall cease only when the simulation is terminated. There shall be no implied Report a Bug or Comment
order of execution between initial and always constructs. The initial constructs need on This section - Your
not be scheduled and executed before the always constructs. There shall be no limit input is what keeps
to the number of initial and always constructs that can be defined in a module
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Initial
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STRUCTURED PROCEDURES
with time!
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AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
An initial block consists of a statement or a group of statements enclosed in begin...

end or a signle statement , which will be executed only once at simulation time 0. If
there is more than one block they execute concurrently and independently. The initial
block is normally used for initialisation, monitoring, generating wave forms (eg, clock
pulses) and processes which are executed once in a simulation. An example of
initialisation and wave generation is given below
EXAMPLE:
initial
clock =1'b0;// variable initialization
initial
begin// multiple statements have to be grouped
alpha =0;
#10alpha =1;// waveform generation
#20alpha =0;
#5alpha =1;
#7alpha =0;
#10alpha =1;
#20alpha =0;
end;
RVM Ethernet sample Always
Specman E
Interview Questions
An always block is similar to the initial block, but the statements inside an always
block will repeated continuously, in a looping fashion, until stopped by $finish or
$stop.
NOTE: the $finish command actually terminates the simulation where as $stop.
merely pauses it and awaits further instructions. Thus $finish is the preferred
command unless you are using an interactive version of the simulator.
One way to simulate a clock pulse is shown in the example below. Note, this is not the
best way to simulate a clock. See the section on the forever loop for a better method.
EXAMPLE:
modulepulse;
http://testbench.in/VT_10_STRUCTURED_PROCEDURES.html[9/26/2012 2:44:45 PM]
regclock;
initialclock =1'b0;// start the clock at 0
always#10clock =~clock;// toggle every 10 time units
initial#5000$finish// end the simulation after 5000 time units
endmodule
Tasks and functions can bu used to in much the same manner but there are some
important differences that must be noted.
Functions
A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time.
Within a function, no event, delay or timing control statements are permitted.
In the invocation of a function their must be at least one argument to be passed.
Functions will only return a single value and can not use either output or inout
statements.
Functions are synthesysable.
Disable statements canot be used.
Function canot have numblocking statements.
EXAMPLE:function
modulefunction_calling(a,b,c);
inputa,b ;
outputc;
wirec;
functionmyfunction;
inputa,b;
begin
myfunction =(a+b);
end
endfunction
assignc =myfunction (a,b);
endmodule
Task
Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a
non zero simulation time.
Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or
inout.
A Task is unable to return a value but has the facility to pass multiple values via the
output and inout statements.
Tasks are not synthesisable.
Disable statements can be used.
EXAMPLE:task
moduletraffic_lights;
regclock,red,amber,green;
parameteron =1,off =0,red_tics =350,
amber_tics =30,green_tics =200;
// initialize colors.
initialred =off;
initialamber =
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TUTORIALS
SystemVerilog
Verification
INTRODUCTION
Introduction
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
OpenVera is an intuitive easy to learn language that combines the familiarity and
strengths of HDLs, C++ and Java, with additional constructs targeted at functional
verification making it ideal for developing testbenches, assertions and properties.
OpenVera accelerates the creation of a verification environment by providing highlevel constructs specifically designed for verification of complex SoCs. Designers
create testbenches and assertions using OpenVera and EDA vendors create tools that
are automatically interoperable.
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Comments In Openvera:
In OpenVera supports two tytes of comments.
# One line comment : Starts with
// and ends at the end of the line.
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# Block comments : Starts with
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/* and ends with */
AVM Switch TB
VMM Ethernet sample Numbers In Openvera:
Verilog
Verification
Verilog Switch TB
Basic Constructs
In OpenVera,numbers can be represented in two formats.

# Simple integer number.Ex: 1, 50, + 20 ,- 33,- 3_3.
# base ' size notaion . Ex: 1'b0,2'00,'haf,3`d555.
Underscore _ are ignored.
X and x are unknown and Z and z are high impedence values.
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OV_01_INTRODUCTION.html[9/26/2012 2:44:54 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
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Index
Introduction
Data Types
SystemVerilog
Linked List
OpenVeras basic data types are:
Verification
Operators Part 1
Constructs
Operators Part 2
Integer
Operators Part 3
Interface
Register
Operator Precedence
String
OOPS
Control Statements
Event
Randomization
Enumerated Types
Interprocess
Functional Coverage
Fork Join
Virtual Ports
Shadow Variables
Assertion
Arrays
Fork Join Control
Smart Queues
DPI
Wait Var
Class
Event Sync
UVM Tutorial
Standalone Coverage Group
Event Trigger
VMM Tutorial
Semaphore
Regions
OVM Tutorial
Integer :
Mailbox
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Timeouts
Integers are signed variables.For 32 bit mechine,range is between -231 and 231 -1.An Oop
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integer may become X (unknown) when it is not initialized or when an undefined value Casting
Easy Labs : OVM
is stored.
Randomization
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Register :
Constraint Block
AVM Switch TB
VMM Ethernet sample Registers are unsigned variables with the value 0, 1, z, or x.Registers can be declared Variable Ordaring
with multiple bit widths.
Aop
Predefined Methods
value condition
String Methods
Verilog
0logic 0
Queue Methods
Verification
1logic 1
Dut Communication
zhigh impedance
Functional Coverage
Verilog Switch TB
xunknown
TUTORIALS
Basic Constructs
DATA TYPES
Basic Data Types:

input is what keeps
A string is a sequence of characters enclosed by double quotes.OpenVera has
with time!
String:
OpenVera
Constructs
Switch TB
stringmethods for mamuplulating the charecters.
stringa;
stringb ="Hi";
RVM Ethernet sample stringc =b;
RVM Switch TB
Event :
Specman E
Interview Questions
A event can be triggered explicitly. It can be used in an event expression to control

the execution of procedural statements.
Enumerated Types :
Enumerated types are a user-defined list of named integer constants. They can either
be defined in the global name space, or in a class.Elements within enumerated type
definitions are numbered consecutively, starting from 0.Each element may have an
optional explicit value assigned to it.
Default numbering
Ex :enumcolors {red,green,blue,yellow,white,black};
http://testbench.in/OV_02_DATA_TYPES.html[9/26/2012 2:45:02 PM]
Explicit numbering
Ex :enuminstructions {add=10,sub,div,mul=4,jmp};
Class Scope enumration
Ex :classBus {enumTRAFFIC=PCI,AHB,USB;}
Virtual Ports :
A virtual port is a user-defined data type that contains a set of port signal members
grouped together under a given user-defined port name.
portrcv_port
{
frame_n;
valid_n;
busy;
packet;
}
Arrays :
OpenVera has one dimentional and multidimentional arrays.
There are four different types of arrays.
Fixed-Size Arrays:
Arrays whose size is fixed at compilation time are called fixed tsize arrays.The access
time is constant regardless of the number of elements in an array.Multi-dimensional
arrays are fixed-size arrays with multiple dimensions.
integerarray_ex[5]; // 1D array of size 5
integermatrix [2][5];// 2d array of size 2 x 5
integerx[2][2]={{0,1},{2,3}};// Array initilization
Dynamic Arrays :
The size of dynamic arrays can be allocated and resized at runtime.
integerarray_ex[*];
new[] : The new[] operator is used to set or change the size of dynamic
arrays during runtime.
integerpacketA[*],packetB[*];// Declare 2 arrays.
packetA =new[100];// Create packetA.
packetB =new[100](packetA);// create packetB and initia
Associative Arrays :
When the size of the collection is unknown or the data space is sparse, associative
array are used.Associative arrays do not have any storage allocated until it is used,
and the index expression is not restricted to integral expressions, but can be of any
type.
integerregular[];// bit indexed associative arrays
integerregular[bit];
integermap[string];
Smart Queues :
Smart Queue is a sequence / deque / vector of homogeneous elements. Smart queues

can be used to model a last in, first out buffer or first in, first out buffer. This
supports insertion and deletion of elements from random locations using an index.
integerqueue_of_int[$];//declare Smart Queue of integers
queue_of_int.push_front(1234);//inseqting 1234 into queue
Class :
The user-defined data type, class, is composed of data members of valid OpenVera
data types (known as properties) and tasks or functions (known as methods) for
manipulating the data members.The properties and methods, taken together, define
the contents and capabilities of a class instance or object.
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LINKED LIST
Linked List:
OpenVera supports Linked list.It also supports object based Linked list also.First
declare the Linked list type and then take instances of it.OpenVera has many
methodes to operate on this instancess.
List Definitions:
List :- A list is a doubly linked list, where every element has a predecessor and
successor. It is a sequence that supports both forward and backward traversal, as well
as amortized constant time insertion and removal of elements at the beginning, end,
or middle.
Container :- A container is a collection of objects of the same type .Containers are
objects that contain and manage other objects and provide iterators that allow the
contained objects (elements) to be addressed. A container has methods for accessing
its elements. Every container has an associated iterator type that can be used to
iterate through the containers elements.
Cterator :- Iterators provide the interface to containers. They also provide a means to
traverse the container elements. Iterators are pointers to nodes within a list. If an
iterator points to an object in a range of objects and the iterator is incremented, the
iterator then points to the next object in the range.
The following procedure shouws how to creat List and use it:
1)Creat List:
VMM Ethernet sample
MakeVeraList(data_type);
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
2)Declare Lists
VeraList_data_type list1;
3)Declare List Iterators
VeraListIterator_data_type iterator1;
List Methods:
OpenVera
size(): The size() method returns the number of elements in the list container.
empty() :The empty() method returns 1 if the number of elements in the list
Switch TB
container is 0:
clear() :The clear() method removes all the elements of the specified list.
RVM Switch TB
erase() :The erase() method removes the indicated element.
RVM Ethernet sample push_front():The push_front() method inserts data at the front of the list.
push_back() :The push_back() method inserts data at the end of the list.
pop_front() :The pop_front() method removes the first element of the list.
pop_back():The pop_back() method removes the last element of the list.
Specman E
insert():The insert() method inserts data before the indicated position:
Interview Questions
insert_range() :The insert_range() method inserts elements in a given range before
the indicated position.
start() :The start() method returns an iterator pointing to the first element in the
list.
finish():The finish() method returns an iterator pointing to the very end of the list.
next():The next() method moves the iterator so that it points to the next item in
the list.
prev():The prev() method moves the iterator so that it points to the previous item
in the list.
eq():The eq() method compares two iterators.
neq() :The neq() method compares two iterators.
Constructs
http://testbench.in/OV_03_LINKED_LIST.html[9/26/2012 2:45:12 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
front() :The front() method returns the first element in the list.
back():The back() method returns the last element in the list.
data():The data() method returns the data stored at a particular location:
EXAMPLE:Linked list
#include <VeraListProgram.vrh>
#include <ListMacros.vrh>
MakeVeraList(integer);
programmain{
VeraList_integer List1;
VeraListIterator_integeritor;
List1 =new();
printf(" size of list is %d \n",List1.size());
List1.push_front(22);
printf(" poping from list : %d \n",List1.front());
printf(" poping from list : %d \n",List1.front());
List1.pop_front();
List1.pop_front();
List1.push_back(5);
itor =List1.start();
printf(" startn of list %d \n",itor.data());
itor.next();
printf(" second element of list is %d \n",itor.data());
itor.next();
printf(" third element of list is %d \n",itor.data());
itor.next();
printf(" fourth element of list is %d \n",itor.data());
itor =List1.erase(itor);
printf(" after erasing element,the itor element of list is %d \n",itor.data());
itor.prev();
printf(" prevoious element is %d \n",itor.data());
printf(" END OF PROGRAM\n");

}
RESULTS:
size of list is 0
size of list is 2
size of list is 0
size of list is 4
startn of list 5
second element of list is 55
third element of list is 555

fourth element of list is 5555
after erasing element,the itor element of list is x
prevoious element is 555
END OF PROGRAM
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OPERATORS PART 1
Operators :
Concatenation
Arithmetic Operators
Relational Operators
Equality Operators
Logical Operators
Bit-wise Operators
Reduction Operators
Shift Operators
Increment and Decrement Operators
Conditional Operator
Concatenation :
{} concatenation right of assignment.
{} concatenation left of assignment.
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EXAMPLE :Concatenation
programmain {
bit[4:0]a;
AVM Switch TB
bitb,c,d;
VMM Ethernet sample b =0;
c =1;
d =1;
a ={b,c,0,0,d};
Verilog
`{b,c,d}=3'b111;
Verification
printf(" a %b b %b c %b d %b ",a,b,c,d);
}
Verilog Switch TB
Easy Labs : VMM
Basic Constructs
RESULTS
a 00001 b 1 c 1 d 1
OpenVera
Constructs
Switch TB
RVM Switch TB
Arithmetic:
# -unary arithmetic (negative)
RVM Ethernet sample # +, -, *, / binary arithmetic
# %modulus
Specman E
Interview Questions
EXAMPLE :Arithmetic
programmain {
integera,b;
b =10;
a =22;
printf(" -(nagetion) is %0d\n",-(a));

printf(" a + bis %0d\n",a+b);
printf(" a - bis %0d\n",a-b);
printf(" a * bis %0d\n",a*b);
printf(" a / bis %0d\n",a/b);
http://testbench.in/OV_04_OPERATORS_PART_1.html[9/26/2012 2:45:22 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
printf(" a modulus bis %0d\n",a%b);
}
RESULTS
-(nagetion) is -22
a + bis 32
a - bis 12
a * bis 220
a / bis 2
a modules b is 2
Relational:
# > >= < <=relational
EXAMPLE :Relational
programmain {
integera,b;
b =10;
a =22;
printf(" a < bis %0d\n",a <b);

printf(" a > bis %0d\n",a >b);
printf(" a <= bis %0d\n",a <=b);
printf(" a >= bis %0d\n",a >=b);
}
RESULTS
a
a
a
a
< bis 0
> bis 1
<= bis 0
>= bis 1
Equality:
== logical equality
!= logical inequality
===case equality
!==case inequality
=?=wildcard equality
!?=wildcard inequality
EXAMPLE :logical Equality
reg[3:0]a;
reg[7:0]x,y,z;
a =4'b0101;
x =8'b1000_0101;
y =8'b0000_0101;
z =8'b0xx0_0101;
if(x ==a)
printf("x equals a is TRUE.\n");
if(y ==a)
printf("y equals a is TRUE.\n");
if(z ==a)
printf("z equals a is TRUE.\n");
RESULTS
y equals a is TRUE.
EXAMPLE : Case equality
programmain {
rega_1,a_0,a_x,a_z;
regb_1,b_0,b_x,b_z;
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
printf("--------------------------\n");
printf(" ==01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 ==b_0,a_0 ==b_1,a_0 ==b_x,a_0 ==b_z);
printf(" 1 %b %b %b %b \n",a_1 ==b_0,a_1 ==b_1,a_1 ==b_x,a_1 ==b_z);
printf(" x %b %b %b %b \n",a_x ==b_0,a_x ==b_1,a_x ==b_x,a_x ==b_z);
printf(" z %b %b %b %b \n",a_z ==b_0,a_z ==b_1,a_z ==b_x,a_z ==b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" === 01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 ===b_0,a_0 ===b_1,a_0 ===b_x,a_0 ===b_z);
printf(" 1 %b %b %b %b \n",a_1 ===b_0,a_1 ===b_1,a_1 ===b_x,a_1 ===b_z);
printf(" x %b %b %b %b \n",a_x ===b_0,a_x ===b_1,a_x ===b_x,a_x ===b_z);
printf(" z %b %b %b %b \n",a_z ===b_0,a_z ===b_1,a_z ===b_x,a_z ===b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" =?= 01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 =?=b_0,a_0 =?=b_1,a_0 =?=b_x,a_0 =?=b_z);
printf(" 1 %b %b %b %b \n",a_1 =?=b_0,a_1 =?=b_1,a_1 =?=b_x,a_1 =?=b_z);
printf(" x %b %b %b %b \n",a_x =?=b_0,a_x =?=b_1,a_x =?=b_x,a_x =?=b_z);
printf(" z %b %b %b %b \n",a_z =?=b_0,a_z =?=b_1,a_z =?=b_x,a_z =?=b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" !=01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 !=b_0,a_0!=b_1,a_0!=b_x,a_0!=b_z);
printf(" 1 %b %b %b %b \n",a_1 !=b_0,a_1!=b_1,a_1!=b_x,a_1!=b_z);
printf(" x %b %b %b %b \n",a_x !=b_0,a_x!=b_1,a_x!=b_x,a_x!=b_z);
printf(" z %b %b %b %b \n",a_z !=b_0,a_z!=b_1,a_z!=b_x,a_z!=b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" !== 01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 !==b_0,a_0 !==b_1,a_0 !==b_x,a_0 !==b_z);
printf(" 1 %b %b %b %b \n",a_1 !==b_0,a_1 !==b_1,a_1 !==b_x,a_1 !==b_z);
printf(" x %b %b %b %b \n",a_x !==b_0,a_x !==b_1,a_x !==b_x,a_x !==b_z);
printf(" z %b %b %b %b \n",a_z !==b_0,a_z !==b_1,a_z !==b_x,a_z !==b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" !?= 01xz\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 !?=b_0,a_0 !?=b_1,a_0 !?=b_x,a_0 !?=b_z);
printf(" 1 %b %b %b %b \n",a_1 !?=b_0,a_1 !?=b_1,a_1 !?=b_x,a_1 !?=b_z);
printf(" x %b %b %b %b \n",a_x !?=b_0,a_x !?=b_1,a_x !?=b_x,a_x !?=b_z);
printf(" z %b %b %b %b \n",a_z !?=b_0,a_z !?=b_1,a_z !?=b_x,a_z !?=b_z);
printf("--------------------------\n");
}
RESULTS
-------------------------==01xz
-------------------------0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
--------------------------------------------------=== 01xz
-------------------------0 1 0 0 0
1 0 1 0 0
x 0 0 1 0
z 0 0 0 1
--------------------------------------------------=?= 01xz
-------------------------0 1 0 1 1
1 0 1 1 1
x 1 1 1 1
z 1 1 1 1
--------------------------------------------------!=01xz
-------------------------0 0 1 x x
1 1 0 x x
x x x x x
z x x x x
--------------------------------------------------!== 01xz
-------------------------0 0 1 1 1
1 1 0 1 1
x 1 1 0 1
z 1 1 1 0
--------------------------------------------------!?= 01xz
-------------------------0 0 1 0 0
1 1 0 0 0
x 0 0 0 0
z 0 0 0 0
--------------------------
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OPERATORS PART 2
Logical :
# !logical negation
# && logical and
# || logical or
OOPS
EXAMPLE : Logical
programmain {
rega_1,a_0,a_x,a_z;
Functional Coverage
regb_1,b_0,b_x,b_z;
Assertion
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
DPI
printf("--------------------------\n");
UVM Tutorial
printf(" && 0 1 x z\n");
printf("--------------------------\n");
VMM Tutorial
printf(" 0 %b %b %b %b \n",a_0 &&b_0,a_0 &&b_1,a_0 &&b_x,a_0 &&b_z);
OVM Tutorial
printf(" 1 %b %b %b %b \n",a_1 &&b_0,a_1 &&b_1,a_1 &&b_x,a_1 &&b_z);
printf(" x %b %b %b %b \n",a_x &&b_0,a_x &&b_1,a_x &&b_x,a_x &&b_z);
Easy Labs : SV
printf(" z %b %b %b %b \n",a_z &&b_0,a_z &&b_1,a_z &&b_x,a_z &&b_z);
Easy Labs : UVM
printf("--------------------------\n");
printf("--------------------------\n");
Easy Labs : OVM
printf(" || 0 1 x z\n");
Easy Labs : VMM
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 ||b_0,a_0 ||b_1,a_0 ||b_x,a_0 ||b_z);
AVM Switch TB
printf(" 1 %b %b %b %b \n",a_1 ||b_0,a_1 ||b_1,a_1 ||b_x,a_1 ||b_z);
VMM Ethernet sample printf(" x %b %b %b %b \n",a_x ||b_0,a_x ||b_1,a_x ||b_x,a_x ||b_z);
printf(" z %b %b %b %b \n",a_z ||b_0,a_z ||b_1,a_z ||b_x,a_z ||b_z);
printf("--------------------------\n");
printf("--------------------------\n");
Verilog
printf(" ! 0 1 x z\n");
Verification
printf("--------------------------\n");
Verilog Switch TB
printf(" %b %b %b %b \n",!b_0,!b_1,!b_x,!b_z);
printf("--------------------------\n");
Basic Constructs
}
RESULTS
Randomization
OpenVera
-------------------------&& 0 1 x z
-------------------------Switch TB
0 0 0 0 0
RVM Switch TB
1 0 1 0 1
RVM Ethernet sample x 0 0 0 0
z 0 1 0 1
--------------------------------------------------Specman E
|| 0 1 x z
-------------------------Interview Questions
0 0 1 0 1
1 1 1 1 1
x 0 1 0 1
z 1 1 1 1
--------------------------------------------------! 0 1 x z
------------------------- 1 0 x x
-------------------------Constructs
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
Bitwise :
#
#
#
#
#
#
#
~bitwise negation (unary)

&bitwise and (binary)
&~ bitwise nand (binary)
|bitwise or (binary)
|~ bitwise nor (binary)
^bitwise exclusive or (binary)
^~ bitwise exclusive nor (binary)
EXAMPLE : Bitwise
programmain {
rega_1,a_0,a_x,a_z;
regb_1,b_0,b_x,b_z;
a_1 ='b1;a_0 ='b0;a_x ='bx;a_z ='bz;
b_1 ='b1;b_0 ='b0;b_x ='bx;b_z ='bz;
printf("--------------------------\n");
printf(" ~ 0 1 x z\n");
printf("--------------------------\n");
printf(" %b %b %b %b \n",~b_0,~b_1,~b_x,~b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" & 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 &b_0,a_0 &b_1,a_0 &b_x,a_0 &b_z);
printf(" 1 %b %b %b %b \n",a_1 &b_0,a_1 &b_1,a_1 &b_x,a_1 &b_z);
printf(" x %b %b %b %b \n",a_x &b_0,a_x &b_1,a_x &b_x,a_x &b_z);
printf(" z %b %b %b %b \n",a_z &b_0,a_z &b_1,a_z &b_x,a_z &b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" &~ 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 &~b_0,a_0 &~b_1,a_0 &~b_x,a_0 &~b_z);
printf(" 1 %b %b %b %b \n",a_1 &~b_0,a_1 &~b_1,a_1 &~b_x,a_1 &~b_z);
printf(" x %b %b %b %b \n",a_x &~b_0,a_x &~b_1,a_x &~b_x,a_x &~b_z);
printf(" z %b %b %b %b \n",a_z &~b_0,a_z &~b_1,a_z &~b_x,a_z &~b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" | 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 |b_0,a_0 |b_1,a_0 |b_x,a_0 |b_z);
printf(" 1 %b %b %b %b \n",a_1 |b_0,a_1 |b_1,a_1 |b_x,a_1 |b_z);
printf(" x %b %b %b %b \n",a_x |b_0,a_x |b_1,a_x |b_x,a_x |b_z);
printf(" z %b %b %b %b \n",a_z |b_0,a_z |b_1,a_z |b_x,a_z |b_z);
printf("--------------------------\n");
printf(" |~ 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 |~b_0,a_0 |~b_1,a_0 |~b_x,a_0 |~b_z);
printf(" 1 %b %b %b %b \n",a_1 |~b_0,a_1 |~b_1,a_1 |~b_x,a_1 |~b_z);
printf(" x %b %b %b %b \n",a_x |~b_0,a_x |~b_1,a_x |~b_x,a_x |~b_z);
printf(" z %b %b %b %b \n",a_z |~b_0,a_z |~b_1,a_z |~b_x,a_z |~b_z);
printf("--------------------------\n");
printf("--------------------------\n");
printf(" ^ 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 ^b_0,a_0 ^b_1,a_0 ^b_x,a_0 ^b_z);

printf(" 1 %b %b %b %b \n",a_1 ^b_0,a_1 ^b_1,a_1 ^b_x,a_1 ^b_z);
printf(" x %b %b %b %b \n",a_x ^b_0,a_x ^b_1,a_x ^b_x,a_x ^b_z);
printf(" z %b %b %b %b \n",a_z ^b_0,a_z ^b_1,a_z ^b_x,a_z ^b_z);
printf("--------------------------\n");
printf(" ^~ 0 1 x z\n");
printf("--------------------------\n");
printf(" 0 %b %b %b %b \n",a_0 ^~b_0,a_0 ^~b_1,a_0 ^~b_x,a_0 ^~b_z);
printf(" 1 %b %b %b %b \n",a_1 ^~b_0,a_1 ^~b_1,a_1 ^~b_x,a_1 ^~b_z);
printf(" x %b %b %b %b \n",a_x ^~b_0,a_x ^~b_1,a_x ^~b_x,a_x ^~b_z);
printf(" z %b %b %b %b \n",a_z ^~b_0,a_z ^~b_1,a_z ^~b_x,a_z ^~b_z);
printf("--------------------------\n");
}
RESULTS
-------------------------~ 0 1 x z
------------------------- 1 0 x x
--------------------------------------------------& 0 1 x z
-------------------------0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
--------------------------------------------------&~ 0 1 x z
-------------------------0 1 1 1 1
1 1 0 x x
x 1 x x x
z 1 x x x
--------------------------------------------------| 0 1 x z
-------------------------0 0 1 x x
1 1 1 1 1
x x 1 x x
z x 1 x x
-------------------------|~ 0 1 x z
-------------------------0 1 0 x x
1 0 0 0 0
x x 0 x x
z x 0 x x
--------------------------------------------------^ 0 1 x z
-------------------------0 0 1 x x
1 1 0 x x
x x x x x
z x x x x
-------------------------^~ 0 1 x z
-------------------------0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
-------------------------Reduction :
#
#
#
#
&unary and
~& unary nand
|unary or
~| unary nor
# ûnary exclusive or
# ~^ unary exclusive nor
EXAMPLE : Reduction
programmain {
reg[3:0]a_1,a_0,a_01xz,a_1xz,a_0xz,a_0dd1,a_even1;
a_1 =4'b1111;
a_0 =4'b0000;
a_01xz=4'b01xz;
a_1xz =4'b11xz;
a_0xz =4'b00xz;
a_0dd1=4'b1110;
a_even1 =4'b1100;
printf("-------------------------------------------\n");
printf(" a_1 a_0 a_01xz a_1xz a_0xz\n");
printf("-------------------------------------------\n");
printf("& %b %b %b %b %b\n",&a_1,&a_0,&a_01xz,&a_1xz,&a_0xz);
printf("| %b %b %b %b %b\n",|a_1,|a_0,|a_01xz,|a_1xz,|a_0xz);
printf("~&%b %b %b %b
%b\n",~&a_1,~&a_0,~&a_01xz,~&a_1xz,~&a_0xz);
printf("~|%b %b %b %b
%b\n",~|a_1,~|a_0,~|a_01xz,~|a_1xz,~|a_0xz);
printf("-------------------------------------------\n");
printf("a_ood1 a_even1a_1xz\n");
printf("-------------------------------------------\n");
printf(" ^ %b %b%b\n",â_0dd1,â_even1,â_1xz);
printf(" ~^%b %b%b\n",~â_0dd1,~â_even1,~â_1xz);
printf("-------------------------------------------\n");
}
RESULTS
------------------------------------------ a_1 a_0 a_01xz a_1xz a_0xz
------------------------------------------& 1 0 0 x 0
| 1 0 1 1 x
~&0 1 1 x 1
~|0 1 0 0 x
------------------------------------------a_ood1 a_even1a_1xz
------------------------------------------^ 1 0x
~^0 1x
-------------------------------------------
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
OPERATORS PART 3
Shift :
# << left shift

# >> right shift
EXAMPLE :Shift
programmain {
reg[3:0]a_1,a_0;
a_1 =4'b1100;
a_0 =4'b0011;
printf(" <<
printf(" >>
printf(" >>
printf(" <<
}
RESULTS
by
by
by
by
1a_1is
2a_1is
2a_1is
1a_1is
%b
%b
%b
%b
a_0
a_0
a_0
a_0
is
is
is
is
%b
%b
%b
%b
\n
\n
\n
\n
",a_1
",a_1
",a_1
",a_1
<< by 1a_1is 1000 a_0 is 0110

>> by 2a_1is 0011 a_0 is 0000
>> by 2a_1is 0011 a_0 is 0000
<< by 1a_1is 1000 a_0 is 0110
Bit-Reverse :
>< bit reverse
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
EXAMPLE : Bit-reverse
programmain {
reg[3:0]a_1,a_0;
a_1 =4'b1100;
printf(" >< a_1is %b\n ",><a_1 );

}
RESULTS
>< a_1is 0011
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Increment And Decrement :

++ increment
-- decrement
EXAMPLE : Increment and Decrement
programmain {
integera_1,a_0;
a_1=20;
a_0=20;
a_1 ++;
a_0 --;
printf(" a_1 is %d a_0 is %d ",a_1,a_0);
}
RESULTS
a_1 is 21 a_0 is 19
<<1,a_0
>>2,a_0
>>2,a_0
<<1,a_0
<<1);
>>2);
>>2);
<<1);
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
Conditional :
?: conditional
EXAMPLE : Conditional
programmain {
integeri,j,sub;
for(i=0;i<3;i++)
for(j=3;j>0;j--){
sub =(i>j)?i-j :j-i;
printf("i = %0d\t j = %0d\tsub = %0d\n",i,j,sub);
}
}
RESULTS
i=
i=
i=
i=
i=
i=
i=
i=
i=
0j
0j
0j
1j
1j
1j
2j
2j
2j
=
=
=
=
=
=
=
=
=
3sub
2sub
1sub
3sub
2sub
1sub
3sub
2sub
1sub
=
=
=
=
=
=
=
=
=
3
2
1
2
1
0
1
0
1
Set
in !in dist
EXAMPLE : Set
programmain {
integeri;
i =20;
if(i in{10,20,30})
printf(" I is in 10 20 30 ");
}
RESULTS
I is in 10 20 30
Replication :
{ number {}}
EXAMPLE : Replication
programmain {
reg[5:0]i;
i ={3{2'b10}};
printf(" I is %b ",i);
}
RESULTS
I is 101010
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
OPERATOR PRECEDENCE
Operator Precedence :
()Highest precedence
++ -& ~& | ~| ^ ~^ ~ >< (unary)
* / %
+ << >>
< <= > >= in !in dist
=?= !?= == != === !==
& &~
^ ^~
| |~
&&
||
?:
= += -= *= /= %=
<<= >>= &= |= ^= ~&= ~|= ~^=Lowest precedence
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OV_07_OPERATOR_PRECEDENCE.html[9/26/2012 2:45:49 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
<< PREVIOUS PAGE
TOP
NEXT PAGE >>
http://testbench.in/OV_07_OPERATOR_PRECEDENCE.html[9/26/2012 2:45:49 PM]
Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
CONTROL STATEMENTS
Sequential Statements:
Statements inside sequential control constructs are executed sequentially.

if-else Statement:The if-else statement is the general form of selection
statement.
case Statement :The case statement provides for multi-way branching.
repeat loop:Repeat statements can be used to repeat the execution of a
statement or statement block a fixed number of times.
for loop :The for construct can be used to create loops.
while loop :The loop iterates while the condition is true.
do-while :condition is checked after loop iteration.
foreach:ech construct specifies iteration over the elements of an single
dimensional fixed-size arrays, dynamic arrays and SmartQs.
Loop Control :The break and continue statements are used for flow control
within loops.
EXAMPLE : if
programmain {
integeri;
i =20;
if(i ==20)
printf(" I is equal to %d ",i);
else
printf(" I is not equal to %d ",i);
}
RESULTS
I is equal to 20
Switch TB
RVM Switch TB
RVM Ethernet sample EXAMPLE : case and repeat
Specman E
Interview Questions
programmain {
integeri;
repeat(10){
i =random();
case(1){
(i<0) :printf(" i is less than zero i==%d\n",i);
(i>0) :printf(" i is grater than zero i=%d\n",i);
(i ==0):printf(" i is equal to zero i=%d\n",i);
}
}
}
RESULTS
i is grater than zero i=69120
http://testbench.in/OV_08_CONTROL_STATEMENTS.html[9/26/2012 2:45:58 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
i is
i is
i is
i is
i is
i is
i is
i is
i is
grater
grater
grater
grater
grater
grater
grater
grater
grater
than
than
than
than
than
than
than
than
than
zero
zero
zero
zero
zero
zero
zero
zero
zero
i=475628600
i=1129920902
i=773000284
i=1730349006
i=1674352583
i=1662201030
i=2044158707
i=1641506755
i=797919327
EXAMPLE : forloop
programfor_loop
{
integercount,i;
for(count =0,i=0;i*count<50;i++,count++)
printf("Value i = %0d\n",i);
}
RESULTS
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
Value i =
0
1
2
3
4
5
6
7
EXAMPLE : whileloop
programwhile_loop{
integeroperator=0;
while(operator<5){
operator +=1;
printf("Operator is %0d\n",operator);
}
}
RESULTS
Operator
Operator
Operator
Operator
Operator
is
is
is
is
is
1
2
3
4
5
EXAMPLE : dowhile
programtest
{
integeri =0;
do
{
printf("i = %0d \n",i);
i++;
}while(i <10);
}
RESULTS
i=
i=
i=
i=
i=
i=
i=
i=
i=
i=
0
1
2
3
4
5
6
7
8
9
EXAMPLE : foeach
programexample{
stringnames[$]={"Hello","Vera"};
foreach(names,i){
printf("Value at index %0d is %0s\n",i,names[i]);
}
}
RESULTS
Value at index 0 is Hello
Value at index 1 is Vera
EXAMPLE : randcase
programrand_case{
integeri;
repeat(10){
randcase
{
10:i=1;
20:i=2;
50:i=3;
}
printf(" i is %d \n",i);}
}
RESULTS
i is
i is
i is
i is
i is
i is
i is
i is
i is
i is
3
2
3
3
3
3
1
1
1
2
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
PROCEDURES AND METHODS

Procedures And Methods :
OpenVera supports two means of encapsulating program fragments:

functions and tasks. All functions and tasks are re-entrant and
therefore can be called recursively.
Function :
Functions are provided for implementing operations containing arguments passed to
the function and one return value.Functions can return values of any valid data type
as well as data structures.
Task :
Tasks are identical to functions except they do not return a value.
Subroutine Arguments :
OpenVera provides two means of accessing arguments in functions and tasks: pass by
value and pass by reference.
Pass By Value :
Pass by value is the default method through which arguments are passed into
functions and tasks. Each subroutine retains a local copy of the argument. If the
arguments are changed within the subroutine declaration, the changes do not affect
the caller.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
EXAMPLE : pass by value

programmain{
integeri;
i=0;
fork
pass(i);
display();
join
printf("End of Program at %d\n",get_time(LO));
}
Constructs
taskpass(inti){
delay(10);
i =1;
RVM Switch TB
printf(" i is changed to %d at %d\n",i,get_time(LO));
RVM Ethernet sample delay(10);
i =2;
}
Switch TB
Specman E
Interview Questions
taskdisplay(){
delay(15);
printf(" i is %d at %d\n",i,get_time(LO));
delay(10);
}
RESULTS
i is changed to 1 at 10
i is 0 at 15
http://testbench.in/OV_09_PROCEDURES_AND_METHODS.html[9/26/2012 2:46:07 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Procedures And
Methods
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
i is 0 at 25
End of Program at 25
Pass By Reference :
In pass by reference functions and tasks directly access the specified variables passed
as arguments.Its like passing pointer of the variable.
EXAMPLE : pass by reference
programmain{
integeri;
i=0;
fork
pass(i);
display();
join
printf("End of Program at %d\n",get_time(LO));
}
taskpass(varinti){
delay(10);
i =1;
delay(10);
i =2;
}
taskdisplay(){
delay(15);
delay(10);
}
RESULTS
i is 1 at 15
i is 2 at 25
End of Program at 25
Default Arguments:
To handle common cases or allow for unused arguments, OpenVera allows you to
define default values for each scalar argument.When the subroutine is called, you can
omit an argument that has a default defined for it. Use an asterisk (*) as a
placeholder in the subroutine call.
EXAMPLE : Default Arguments:
taskdisplay(integeri =0,integerk,reg[5:0]data =6'b0)
{
printf(" i si %d k is %d , datat is %b \n",i,k,data);
}
programmain{
integeri;
i=0;
display(1,4,6);
display(*,4,*);
display(*,8,4);
}
RESULTS
i si 1 k is 4 , datat is 000110
Optional Arguments:
To allow subroutines to evolve over time without having to change all of the existing
calls, OpenVera supports optional arguments.Optional arguments must have default
values.Any number of additional optional arguments can be created.Parentheses are
used to determine the depth level of an optional argument.
EXAMPLE : optional arguments
taskmy_task(integera,((integerb=1)),(integerc=1)){
printf(" a is %d, b is %d c is %d\n",a,b,c);
}
programmain{
integeri;
i=0;
my_task(1,2,3);
my_task(1);
my_task(1,2);
}
RESULTS
a is 1, b is 2 c is 3
Subroutine Termination :
Normally, functions and tasks return control to the caller after the last statement of
the block is executed. OpenVera provides the return statement to manually pass
control back to the caller.
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Index
Introduction
Data Types
SystemVerilog
OpenVera supports set of synchronization and communication mechanisms, all of Linked List
Verification
Operators Part 1
which can be created and reclaimed dynamically.
Constructs
Operators Part 2
Operators Part 3
Interface
fork and join Statement
Operator Precedence
wait_var()
OOPS
Control Statements
Event Methods
Randomization
Semaphores
Interprocess
Functional Coverage
Regions
Fork Join
Shadow Variables
Mailboxes
Assertion
Fork Join Control
Timeout
Limit
DPI
Wait Var
Event Sync
UVM Tutorial
Event Trigger
VMM Tutorial
Semaphore
Regions
OVM Tutorial
Mailbox
Easy Labs : SV
Timeouts
Oop
Easy Labs : UVM
Casting
Easy Labs : OVM
Randomization
Easy Labs : VMM
Constraint Block
AVM Switch TB
VMM Ethernet sample
Variable Ordaring
Aop
Predefined Methods
String Methods
Verilog
Queue Methods
Verification
Dut Communication
Functional Coverage
Verilog Switch TB
TUTORIALS
INTERPROCESS
Interprocess Synchronization And Communication :
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OV_10_INTERPROCESS.html[9/26/2012 2:46:14 PM]

input is what keeps
with time!
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Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
FORK JOIN
Fork Join:
Fork/join blocks provide the primary mechanism for creating concurrent

processes.The all | any | none options specify when the code after the fork/join block
executes.The default is all.
all :: The default is all. Code after the block executes after all of the concurrent
processes are completed.
any :: When any is used, code after the block executes after any single concurrent
process is completed.
none :: When none is used, code after the block executes immediately, without
waiting for any of the processes to complete.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs

input is what keeps
with time!
OpenVera
Constructs
Switch TB
RVM Switch TB
EXAMPLE : fork/join none

programmain {
Specman E
Interview Questions
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
printf(" BEFORE forktime = %d \n",get_time(LO));

fork{
delay(20);
printf("time = %d delay 20 \n ",get_time(LO));
}
{
delay(10);
}
{
delay(5);
}
http://testbench.in/OV_11_FORK_JOIN.html[9/26/2012 2:46:23 PM]
joinnone
printf(" time = %d Outside the main fork \n",get_time(LO));
delay(40);
}
RESULTS
time = 15 delay 5
time = 20 delay 10
time = 30 delay 20
EXAMPLE : fork/join any
programmain {
delay(10);
fork{
delay(20);
}
{
delay(10);
}
{
delay(5);
}
joinany
delay(40);
}
RESULTS
time = 15 delay 5
time = 20 delay 10
time = 30 delay 20
EXAMPLE : fork/join all
programmain {
delay(10);

fork{
delay(20);
}
{
delay(10);
}
{
delay(5);
}
joinall
delay(40);
}
RESULTS
time = 15 delay 5
time = 20 delay 10
time = 30 delay 20
When defining a fork/join block, encapsulating the entire fork inside braces ({})
results in the entire block being treated as a single thread, and the code executes
consecutively.
EXAMPLE : sequential statement in fork/join
programmain {
delay(10);
printf(" First forktime = %d \n",get_time(LO));
fork{
delay(20);
printf("time = %d delay 20 \n ",get_time(LO),i);
}
{
delay(10);
printf("time = %d delay 10 \n ",get_time(LO),j);
}
{
delay(5);
printf("time = %d delay 5 \n ",get_time(LO),m);
delay(2);
printf("time = %d delay 2 \n ",get_time(LO),m);
}
joinany
delay(40);
}
RESULTS
First forktime = 10
time = 15 delay 5
time = 17 delay 2
time = 20 delay 10
time = 30 delay 20
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Index
Introduction
Data Types
SystemVerilog
By default, all child processes have access to the parents variables.However, if Linked List
Verification
multiple processes independently use the same variable,races can occur. To avoid Operators Part 1
Constructs
Operators Part 2
races within fork/join blocks, shadow variables should be used.
Operators Part 3
Interface
Operator Precedence
EXAMPLE : without shadow variable
OOPS
Control Statements
Randomization
programmain {
Interprocess
call();
Functional Coverage
Fork Join
delay(40);
Shadow Variables
Assertion
printf(" END OF SIMUALTION \n");
Fork Join Control
}
DPI
Wait Var
Event Sync
UVM Tutorial
taskcall(){
Event Trigger
integeri;
VMM Tutorial
Semaphore
delay(10);
Regions
OVM Tutorial
for(i =0;i <3;i++){
Mailbox
fork
Easy Labs : SV
Timeouts
{
Oop
Easy Labs : UVM
delay(10);
Casting
printf("
time
=
%0d:
i
is
%0d
\n",get_time(LO),i);
Easy Labs : OVM
Randomization
}
Easy Labs : VMM
joinnone
Constraint Block
}
AVM Switch TB
}
VMM Ethernet sample
Variable Ordaring
Aop
Predefined Methods
RESULTS
String Methods
Verilog
Queue Methods
time
=
20:
i
is
3
Verification
Dut Communication
time = 20: i is 3
Functional Coverage
Verilog Switch TB
time = 20: i is 3
END OF SIMUALTION
Basic Constructs
TUTORIALS
OpenVera
Constructs
SHADOW VARIABLES
Shadow Variables
Look at the solution, i is 3 in all the threads.

EXAMPLE :with shadow variable
Switch TB
programmain {
call();
}
RVM Switch TB
Specman E
Interview Questions
taskcall(){
shadowintegeri;// using shadow variable
delay(10);
for(i =0;i <3;i++){
fork
{
delay(10);
printf(" time = %0d: i is %0d \n",get_time(LO),i);
}
joinnone
}
}
http://testbench.in/OV_12_SHADOW_VARIABLES.html[9/26/2012 2:46:32 PM]

input is what keeps
with time!
RESULTS
time = 20: i is 0
time = 20: i is 1
time = 20: i is 2
END OF SIMUALTION
The solution shows that ,Using the shadow keyword forces the Vera compiler to create
a copy of the variable i local to each child process, which eliminates race conditions.
Any descendants of the child processes will also have a copy of the variable local to
that descendant.
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Index
Introduction
Data Types
SystemVerilog
Linked List
Wait_chiled():
Verification
Operators Part 1
Constructs
The wait_child() system task is used to ensure that all child processes are executed Operators Part 2
Operators Part 3
before the Vera program terminates.
Interface
Operator Precedence
OOPS
Control Statements
EXAMPLE : without wait_var
Randomization
Interprocess
taskme
(){
Functional Coverage
Fork Join
integern ;
Shadow Variables
Assertion
Fork Join Control
for(n=0;n<10;n++){
DPI
Wait Var
fork
Event Sync
UVM Tutorial
{delay(10)
Event Trigger
printf(" inside for.join none ,time = %0d \n",get_time(LO));
VMM Tutorial
Semaphore
}
Regions
OVM Tutorial
joinnone
Mailbox
}
Easy Labs : SV
Timeouts
// wait_child() ;
Oop
Easy Labs : UVM
printf(" END of task \n");
Casting
}
Easy Labs : OVM
Randomization
Easy Labs : VMM
programmain {
Constraint Block
me();
AVM Switch TB
printf(" END of program \n");
VMM Ethernet sample }
Variable Ordaring
Aop
Predefined Methods
RESULTS
String Methods
Verilog
Queue Methods
END
of
task
Verification
Dut Communication
END of program
Functional Coverage
Verilog Switch TB
TUTORIALS
Basic Constructs
OpenVera
Constructs
FORK JOIN CONTROL

Fork And Join Control:
The soluton shows that inside forkjoin state ments are not printed.
EXAMPLE : with wait_var
Switch TB
taskme (){
integern ;
RVM Switch TB
for(n=0;n<10;n++){
RVM Ethernet sample fork
Specman E
Interview Questions
{delay(10)
printf(" inside for.join none ,time = %0d \n",get_time(LO));
}
joinnone
}
wait_child();
printf(" END of task \n");
}
programmain {
me();
printf(" END of program \n");
}
RESULTS
http://testbench.in/OV_13_FORK_JOIN_CONTROL.html[9/26/2012 2:46:39 PM]

input is what keeps
with time!
inside for.join none ,time = 10

END of task
END of program
Terminate:
The terminate statement terminates all active descendants of the current thread in
which it was called.If any of the child processes have other descendants, the
terminate command terminates them as well.
This example forks off several child processes within a task. After any of the child
processes is complete, the code continues to execute. Before the task is completed,
all remaining child processes are terminated.
EXAMPLE : without terminate
tasktask1(){
delay(10);
printf(" before forktime = %d \n",get_time(LO));
fork{
delay(20);
printf("time = %ddelay 20\n ",get_time(LO));
}
{
delay(10);
}
{
delay(5);
}
joinany
fork{
delay(35);
printf("time = %d delay 35\n ",get_time(LO));
}
{delay(25)
}
{delay(15)
}
joinnone
// terminate;
delay(100);
}
programmain {
task1();
printf(" Time = %d Task completed \n",get_time(LO));
}
RESULTS
before forktime = 10
time = 15delay 5
time = 20delay 10
time = 30delay 20
time = 30 delay 15
time = 40 delay 25
time = 50 delay 35
Time = 115 Task completed
EXAMPLE : with terminate

tasktask1(){
delay(10);
printf(" before forktime = %d \n",get_time(LO));
fork{
delay(20);
}
{
delay(10);
}
{
delay(5);
}
joinany
fork{
delay(35);
}
{delay(25)
}
{delay(15)
}
joinnone
terminate;
delay(100);
}
programmain {
task1();
printf(" Time = %d Task completed \n",get_time(LO));
}
RESULTS
before forktime = 10
time = 15delay 5
Time = 115 Task completed
Both the solutions ahow that the task is completed at time 115 .When teriminate is
not used, all the chaild process execute,when teriminate is use,all the chaild
processes are teriminated.
Suspend_thread:
The suspend_thread() system task is used to temporarily suspend the current thread.It
suspends the current thread and allows other ready concurrent threads to run. When
all ready threads have had one chance to block, the suspended thread resumes
execution.
EXAMPLE : without suspend_thread
programmain {
call();
delay(40);
}
taskcall(){
delay(10);
for(i =0;i <3;i++){
fork
{
delay(10);
printf(" Suspending the thread \n");
// suspend_thread();
printf(" After Suspending the thread\n");
}
joinnone
}
}
RESULTS
time = 20: i is 0
Suspending the thread
After Suspending the thread
time = 20: i is 0
time = 20: i is 1
time = 20: i is 1
time = 20: i is 2
time = 20: i is 2
END OF SIMUALTION
EXAMPLE : with suspend_thread

programmain {
call();
delay(40);
}
taskcall(){
delay(10);
for(i =0;i <3;i++){
fork
{
delay(10);
printf(" Suspending the thread \n");
suspend_thread();
printf(" After Suspending the thread\n");
}
joinnone
}
}
RESULTS
time = 20: i is 0
time = 20: i is 1
time = 20: i is 2
time = 20: i is 0
time = 20: i is 1
time = 20: i is 2
END OF SIMUALTION
The solution shows that all the child threads are suspended until all the calls are
made and then reumed.
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Index
Introduction
Data Types
SystemVerilog
The wait_var() system task blocks the calling process until one of the variables in its Linked List
Verification
arguments list changes values.Only true value changes unblock the process. Operators Part 1
Constructs
Reassigning the same value does not unblock. If more than one variable is specified, a Operators Part 2
Operators Part 3
change to any of the variables unblocks the process.
Interface
Operator Precedence
OOPS
Control Statements
EXAMPLE : wait_var()
programmain {
Randomization
Interprocess
call();
Functional Coverage
Fork Join
delay(40);
Shadow Variables
Assertion
Fork Join Control
}
DPI
Wait Var
Event Sync
UVM Tutorial
taskcall(){
Event Trigger
reg[7:0]data ;
VMM Tutorial
Semaphore
integeri;
Regions
OVM Tutorial
fork
Mailbox
{
Easy Labs : SV
Timeouts
while(1)
Oop
Easy Labs : UVM
{wait_var(data);
Casting
printf("time
=
%0d
has
changed
to:
%d\n",get_time(LO),data);
Easy Labs : OVM
Randomization
}
Easy Labs : VMM
}
Constraint Block
{
AVM Switch TB
for(i=0;i<10;i++){
VMM Ethernet sample data=random();
Variable Ordaring
Aop
delay(10);}
Predefined Methods
}
String Methods
joinall
Verilog
Queue Methods
}
Verification
Dut Communication
Functional Coverage
Verilog Switch TB
RESULTS
Basic Constructs
TUTORIALS
WAIT VAR
Wait_var:
time
time
OpenVera
time
Constructs
time
time
Switch TB
time
RVM Switch TB
time
RVM Ethernet sample time
time
time
=
=
=
=
=
=
=
=
=
=
0 has changed to: 0

10 has changed to: 156
Specman E
Interview Questions
http://testbench.in/OV_14_WAIT_VAR.html[9/26/2012 2:46:48 PM]

input is what keeps
with time!
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TUTORIALS
EVENT SYNC
SystemVerilog
Event Methods:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Events are variables that synchronize concurrent processes. When a sync is called, a
process blocks until another process sends a trigger to unblock it. Events act as the
go-between for triggers and syncs.
sync()::This method synchronizes statement execution to one or more triggers.
ALL :::The ALL sync type suspends the process until all of the specified events are
triggered.
For example:
sync(ALL,event_a,event_b,event_c);
ANY :::The ANY sync type suspends the process until any of the specified events is
triggered.
For example:
sync(ANY,event_a,event_b,event_c);
ORDER :::The ORDER sync type suspends the process until any of the specified events
is triggered.
For example:
sync(ORDER,event_a,event_b,event_c);
CHECK :::The CHECK sync type is called as a function. It does not suspend the thread.
It returns a 1 if the trigger is ON and a 0 if it is not.This sync type can only be used
with ON and OFF trigger types.This sync type can only be used with a single event per
call.
For example:
sync(CHECK,event_a);
EXAMPLE : sync ANY
Constructs
#include "vera_defines.vrh"
programmain {
eventevent1,event2;
RVM Switch TB
call();
RVM Ethernet sample sync(ANY,event1,event2);
printf(" time : %0d After sync \n",get_time(LO));
delay(40);
Specman E
}
Switch TB
Interview Questions
taskcall(){
fork
{
delay(10);
printf("time : %0d , triggering event1 \n",get_time(LO));
trigger(event1);
delay(10);
trigger(event2);
}
http://testbench.in/OV_15_EVENT_SYNC.html[9/26/2012 2:46:57 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
joinnone
}
RESULTS
time : 10 , triggering event1
time : 10 After sync
END OF SIMUALTION
EXAMPLE : sync ALL
programmain {
eventevent1,event2;
call();
sync(ALL,event1,event2);
delay(40);
}
taskcall(){
fork{
delay(10);
trigger(event1);
delay(10);
trigger(event2);
}
joinnone
}
RESULTS
END OF SIMUALTION
EXAMPLE : sync ORDER
programmain {
eventevent1,event2;
call();
sync(ORDER,event2,event1);
delay(40);
}
taskcall(){
fork{
delay(10);
trigger(event2);
delay(10);
trigger(event1);
delay(10);
trigger(event2);
}
joinnone
}
RESULTS
END OF SIMUALTION
EXAMPLE : sync CHECK
programmain {
eventevent1,event2;
bitcheck_bit;
call();
check_bit =sync(CHECK,event1);
printf(" time : %0d After sync check_bit is %d \n",get_time(LO),check_bit);
delay(40);
}
taskcall(){
fork{
trigger(ON,event1);
delay(10);
trigger(event1);
delay(10);
trigger(event2);
}
join
RESULTS
time : 0 After sync check_bit is 1
END OF SIMUALTION
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TUTORIALS
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Constructs
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OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
EVENT TRIGGER
Event Trigger:
This task is used to change the state of an event. Triggering an event unblocks waiting
syncs, or blocks subsequent syncs. By default, all events are OFF.
ONE_SHOT ::: The ONE_SHOT trigger is the default trigger type. If you use a
ONE_SHOT trigger, any process waiting for a trigger receives it.If there are no
processes waiting for the trigger, the trigger is discarded.
ONE_BLAST ::: ONE_BLAST triggers work just as ONE_SHOT triggers do with the
exception that they trigger any sync called within the simulation time, regardless of
whether or not it was called before the trigger was executed. If a ONE_BLAST trigger
is used for the situation diagrammed previously, all the processes are unblocked
regardless of execution order.
HAND_SHAKE ::: HAND_SHAKE triggers unblock only one sync, even if multiple syncs
are waiting for triggers. It triggers the most recent pending sync, or queues requests.
If the order of triggering the unblocking of a sync is important, use a semaphore_get()
and semaphore_put() around the sync to maintain order. If a sync has already been
called and is waiting for a trigger, the HAND_SHAKE trigger unblocks the sync. If no
sync has been called when the trigger occurs, the HAND_SHAKE trigger is stored. When
a sync is called, the sync is immediately unblocked and the trigger is removed.
Easy Labs : VMM
EXAMPLE : ONE_SHOT
programvshell
VMM Ethernet sample {
eventevent1;
fork
sync_then_trigger();
Verilog
trigger_then_sync();
Verification
joinall
Verilog Switch TB
}
Basic Constructs
tasksync_then_trigger()
{
printf("Sync_then_trigger syncing at time %d\n",get_time(LO));
OpenVera
sync(ALL,event1);
Constructs
printf("Sync_then_trigger syncedat time %d\n",get_time(LO));
#50;
Switch TB
printf("Sync_then_trigger triggering at time %d\n",get_time(LO));
RVM Switch TB
trigger(ONE_SHOT,event1);
RVM Ethernet sample }
tasktrigger_then_sync()
{
#20;
Specman E
printf("trigger_then_sync triggering at time %d\n",get_time(LO));
trigger(ONE_SHOT,event1);
Interview Questions
#10;
printf("trigger_then_sync syncing at time %d\n",get_time(LO));
sync(ALL,event1);
printf("trigger_then_sync synced at time %d\n",get_time(LO));
}
AVM Switch TB
RESULTS
Sync_then_trigger syncing at time 0
trigger_then_sync triggering at time 20
http://testbench.in/OV_16_EVENT_TRIGGER.html[9/26/2012 2:47:04 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
Sync_then_trigger syncedat time 20

trigger_then_sync syncing at time 30
Sync_then_trigger triggering at time 70
trigger_then_sync synced at time 70
EXAMPLE :ONE_BLAST
programvshell
{
eventevent1,event2,event3;
fork
call_task1();
call_task2();
joinnone
#150;
printf(" END of program");
}
taskcall_task1 ()
{
printf("In task call_task1 Sync all events at time %d\n",get_time(LO));
#30;
sync(ALL,event2,event3);
printf("In task call_task1 Synced at time %d\n",get_time(LO));
}
taskcall_task2()
{
printf("In task call_task2 triggering events at time %d\n",get_time(LO));
#40;
trigger(ONE_BLAST,event2);
#20;
printf("In task call_task2 event2 was triggered and task call_task2 is finished at
time %d \n",get_time(LO));
}
RESULTS
In task call_task1 Sync all events at time 0
In task call_task2 triggering events at time 0
In task call_task2 event2 was triggered and task call_task2 is finished at time 60
EXAMPLE :HAND_SHAKE
programvshell {
eventmy_event =ON;
fork
sync_event1();
sync_event2();
trigger_event1();
joinall
}
tasksync_event1(){
printf("before sync_event1at time %0d \n");
sync(ALL,my_event);
printf("after sync_event1at time %0d \n");

printf("before trigger sync_event1at time %0d\n");
trigger(ONE_BLAST,my_event);
}
tasksync_event2(){
printf("before sync_event2at time %0d \n");
sync(ALL,my_event);
printf("after sync_event2at time %0d \n");
printf("before trigger sync_event2at time %0d\n");
trigger(ONE_BLAST,my_event);
}
tasktrigger_event1(){
printf("before trigger_event1at time %0d \n");
trigger(HAND_SHAKE,my_event);
printf("after trigger_event1at time %0d \n");
sync(ALL,my_event);
printf("after sync trigger_event1 3 at time %0d \n");
}
RESULTS
before sync_event1at time
before sync_event2at time
before trigger_event1at time
after trigger_event1at time
after sync_event1at time
before trigger sync_event1at time
after sync_event2at time
before trigger sync_event2at time
after sync trigger_event1 3 at time
Event Variables :
These variables serve as the link between triggers and syncs. They are a unique data
type with several important properties.
EXAMPLE : Event Variables
taskT1(eventtrigger_a){
printf("\nT1 syncing at cycle=%0d",get_time(LO));
sync(ALL,trigger_a);// Blocked: proceed after receiving trigger
printf("\nT1 event trigger_a received at cycle=%0d",get_time(LO));
delay(70);
printf("\nT1 triggering trigger_a at cycle=%0d",get_time(LO));
trigger(trigger_a);
}
programtrigger_play
{
eventtrigger1;
fork
T1(trigger1);// start T1 and go on
joinnone
delay(80);// T1 is blocked waiting for
fork
{
printf("\nPROGRAM triggering trigger1 @cycle=%0d",get_time(LO));
printf("\nPROGRAM This unblocks T1");
trigger(trigger1);// unblock the waiting T1
}
{ delay(50);
printf("\nPROGRAM syncing @cycle=%0d\n\n",get_time(LO));
sync(ALL,trigger1);// wait for T1 to unblock me
}
join
wait_child();
printf("Trigger play done!");
}
RESULTS
T1 syncing at cycle=0
PROGRAM triggering trigger1 @cycle=80
PROGRAM This unblocks T1
T1 event trigger_a received at cycle=80
PROGRAM syncing @cycle=130
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TUTORIALS
SEMAPHORE
SystemVerilog
Semaphore:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A semaphore is an operation used for mutual exclusion and synchronization.

Conceptually, semaphores can be viewed as a bucket. When you allocate a
semaphore, you create a virtual bucket. Inside the bucket are a number of keys. No
process can be executed without first having a key. So, if a specific process requires a
key, only a finite number of occurrences of that process can be in progress
simultaneously. All others must wait until a key is returned to the virtual bucket.
Semaphore Allocation ::
To allocate a semaphore, you must use the alloc() system function.
Syntax : function integer alloc(SEMAPHORE, integer semaphore_id,integer
semaphore_count, integer key_count);
The alloc() function returns the base semaphore ID if the semaphores are successfully
created. Otherwise, it returns 0.
semaphore_id :::
is the ID number of the particular semaphore being created. It must be an integer
value. You should generally use 0. When you
use 0, a semaphore ID is automatically generated by the simulator. Using any other
number explicitly assigns an ID to the
semaphore being created.
semaphore_count:::
VMM Ethernet sample specifies how many semaphore buckets you want to create. It must be an
integer value.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
key_count :::
specifies the number of keys initially allocated to each semaphore bucket you
are creating.
Using Semaphore Keys ::
To check that there are enough keys left in the semaphore, you must use the
semaphore_get() system function.
Syntax : function integer semaphore_get(NO_WAIT | WAIT,integer semaphore_id,
integer key_count);
To put keys back into a semaphore, you must use the semaphore_put() system task.
RVM Switch TB
RVM Ethernet sample EXAMPLE : simaphore
programvshell {
integersema,get;
Specman E
Interview Questions
sema =alloc(SEMAPHORE,1,3,2);
if(!sema)
error("Semaphore Allocation failed\n");
repeat(3){
fork{
printf("Before getting key 1\n");
get =semaphore_get(NO_WAIT,sema,2);
if(!get)
error(" No sempahore key for inject2 \n");
else
printf(" Got Key from 1 \n");
http://testbench.in/OV_17_SEMAPHORE.html[9/26/2012 2:47:14 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
semaphore_put(sema,2);
printf(" Putting back key \n");
delay(10);
}
{
get =semaphore_get(NO_WAIT,sema +1,2);
if(!get)
else
semaphore_put(sema +1,2);
delay(10);
}
joinall
}
delay(1000);
}
RESULTS
Before getting key
Got Key from 1
Putting back key
Before getting key
Got Key from 2
Before getting key
Got Key from 1
Putting back key
Before getting key
Got Key from 2
Before getting key
Got Key from 1
Putting back key
Before getting key
Got Key from 2
1
2
1
2
1
2
The number of keys in the bucket can increase if more keys are put into the bucket
than are removed. Therefore, key_count is not necessarily the maximum number of
keys in the bucket.
EXAMPLE:
programvshell {
integersema,get;
sema =alloc(SEMAPHORE,0,1,1);
if(!sema)
error("Semaphore Allocation failed\n");

get =semaphore_get(WAIT,sema,1);
if(!get)
else
if(!get)
else
if(!get)
else
delay(1000);
}
RESULTS:
Before getting key 1
Got Key from 1
Putting back key
Putting back key
Got Key from 1
Got Key from 1
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
REGIONS
Regions:
A region is a mutual exclusion mechanism that guarantees that the requested values
are unique in the simulation. This feature is provided mostly for random type
simulations that may depend on the uniqueness of specific values such as addresses or
data-IDs.
Conceptually, regions can be viewed as a set of letters. First you allocate which
letters are included in the set. These letters are the only letters from which words can
be made. If one person uses the letters to spell CAT, no one else can spell TIN
because the T is already in use. Once the T is returned, TIN can be created.
Effectively, this ensures that data sets are unique, and it eliminates concurrent
crossover.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
To allocate a region, you must use the alloc() system function.

Syntax : function integer alloc(REGION, integer region_id, integer region_count);
region_id is the ID number of the particular region being created. It must be an
integer value. You should generally use 0. When you use 0,Vera automatically
generates a region ID.
region_count specifies how many regions you want to create. It must be an integer
value.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
The region_enter() system function checks to see if a particular region is in use.

The region_exit() system task removes the specified values from the in-use state.
VMM Ethernet sample EXAMPLE:REGIONS
Switch TB
taskCPU(integerid,integergrant,integerregID){
integerdata,address;
reg[31:0]randVar;
repeat(10)
{
randVar=random();
address=randVar[13:6];
data=randVar[29:22];
region_enter(WAIT,regID,address);
disp(address,data,grant);
region_exit(regID,address);
}
}
RVM Switch TB
taskdisp(integeradd,integerdata,integerid){
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
RVM Ethernet sample delay(random());
printf(" add %d data %d id %d\n",add,data,id);

}
Specman E
Interview Questions
programmain {
integerregID;
regID=alloc(REGION,0,1);
fork
CPU(0,2'b01,regID);
CPU(1,2'b10,regID);
join
}
RESULTS
add 56 data 0 id 1
http://testbench.in/OV_18_REGIONS.html[9/26/2012 2:47:22 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
add 230 data 13 id 2

add 252 data 1 id 1
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TUTORIALS
MAILBOX
SystemVerilog
Mailbox:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A mailbox is a mechanism to exchange messages between processes. Data can be sent

to a mailbox by one process and retrieved by another. Conceptually, mailboxes behave
like real mailboxes. When a letter is delivered and put into the mailbox, you can
retrieve the letter (and any data stored within). However, if the letter has not been
delivered when you check the mailbox, you must choose whether to wait for the
letter or retrieve the letter on subsequent trips to the mailbox.Similarly, OpenVera
s mailboxes allow you to transfer and retrieve data in a very controlled manner.
To allocate a mailbox, you must use the alloc() system function.
Syntax : function integer alloc(MAILBOX, integer mailbox_id, integer mailbox_count);
mailbox_id is the ID number of the particular mailbox being created. It must be an
integer value. You should generally use 0. When you use 0, Vera automatically
generates a mailbox ID.
mailbox_count specifies how many mailboxes you want to create. It must be an
integer value.
The mailbox_put() system task sends data to the mailbox.
The mailbox_get() system function returns data stored in a mailbox.
EXAMPLE : Mailbox
VMM Ethernet sample programvshell
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
{
integermy_mailbox;
my_mailbox =alloc(MAILBOX,0,1);
if(my_mailbox)
{
fork
put_packets();
get_packets();
joinnone
}
delay(1000);
printf("END of Program\n");
}
taskput_packets()
{
integeri;
for(i=0;i<10;i++)
{
delay(10);
mailbox_put(my_mailbox,i);
printf("Done putting packet %d @time %d\n",i,get_time(LO));
}
}
taskget_packets()
{
http://testbench.in/OV_19_MAILBOX.html[9/26/2012 2:47:31 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
integerret;
bit[63:0]packet;
while(1)
{
ret =mailbox_get(WAIT,my_mailbox,packet,CHECK);
if(ret >0)
printf("Got packet %d @time %d\n",packet,get_time(LO));
}
}
RESULTS
Done putting
Got packet 0
Done putting
Got packet 1
Done putting
Got packet 2
Done putting
Got packet 3
Done putting
Got packet 4
Done putting
Got packet 5
Done putting
Got packet 6
Done putting
Got packet 7
Done putting
Got packet 8
Done putting
Got packet 9
packet 0 @time
@time 10
packet 1 @time
@time 20
packet 2 @time
@time 30
packet 3 @time
@time 40
packet 4 @time
@time 50
packet 5 @time
@time 60
packet 6 @time
@time 70
packet 7 @time
@time 80
packet 8 @time
@time 90
packet 9 @time
@time 100
10
20
30
40
50
60
70
80
90
100
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Index
Introduction
Data Types
SystemVerilog
A process will wait forever in semaphore, region and mailbox if the waiting resources Linked List
Verification
are not available. However, the system task timeout() can be used to set a time limit. Operators Part 1
Constructs
Operators Part 2
Operators Part 3
These are examples of timeout statements:
Interface
Operator Precedence
OOPS
Control Statements
timeout(SEMAPHORE,100);
Randomization
timeout(REGION,50,2);
Interprocess
timeout(EVENT,20);
Functional Coverage
Fork Join
timeout(myevent,300);
Shadow Variables
Assertion
Fork Join Control
DPI
Wait Var
Event Sync
UVM Tutorial
Event Trigger
VMM Tutorial
Semaphore
Regions
OVM Tutorial
Mailbox
Easy Labs : SV
Timeouts
Oop
Easy Labs : UVM
Casting
Easy Labs : OVM
Randomization
Easy Labs : VMM
Constraint Block
AVM Switch TB
VMM Ethernet sample
Variable Ordaring
Aop
Predefined Methods
String Methods
Verilog
Queue Methods
Verification
Dut Communication
Functional Coverage
Verilog Switch TB
TUTORIALS
TIMEOUTS
Timeouts:
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OV_20_TIMEOUTS.html[9/26/2012 2:47:39 PM]

input is what keeps
with time!
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Search
TUTORIALS
OOP
SystemVerilog
Object Oriented Programming :
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Object oriented programming (OOP) involves the development of applications with

modular, reusable components.The object-oriented paradigm is built on three
important principles:
Encapsulation
Inheritance
Polymorphism
Encapsulation : Encapsulation is the principle of grouping together common
functionality and features into a code object.I
nheritance : Inheritance is the principle of transferring the functionality and
features of a parent to a child. Since the child is an autonomous unit, the properties
and methods inherited by the child can be modified or added to without affecting the
parent.
Polymorphism: Polymorphism allows the redefining of methods for derived classes
while enforcing a common interface.
Creating an object:
To create an object (i.e., an instance) of a declared class, there are two steps. First,
declare a handle to the class (a handle is a reference to the class instance, or object)
class_name handle_name;
VMM Ethernet sample Then, call the new() class method:
Verilog
handle_name =new();
Verification
or simple
Verilog Switch TB
class_name handle_name =new();
Basic Constructs
OpenVera
Constructs
new() is a default implementation which simply allocates memory for the object and Report a Bug or Comment
returns a handle to the object.
Assignment :
Packet p1;
p1 =new();
RVM Switch TB
Packet p2;
RVM Ethernet sample p2 =p1;
Switch TB
Specman E
Interview Questions
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
In this case, there is still only one object. This single object can be referred to with
either variable, p1 or p2.
The following code:
p2 =newp1;
makes a shallow copy of the object referenced by p1, and sets p2 to point to it. A
shallow copy creates a new object and copies the values of all properties from the
source object. It is a shallow copy because it does not make a copy of any nested
objects.
p2 =object_copy(p1);// creates a duplicate object of p, with the handle q .
http://testbench.in/OV_21_OOP.html[9/26/2012 2:47:48 PM]
input is what keeps

with time!
EXAMPLE : copy
classA{
integerj;
tasknew(){j=5;}
}
classB{
integeri;
A a;
tasknew(){i =1;}
}
tasktest(){
B b1 =new();// Create an object of class B
B b2; //Create a null variable of class B
b1.a =new; //Create an object of class A
b2 =newb1;// Create an object that is a copy of b1,
//but only copies the handle a, not the object
//referenced by a.
b2.i =10;// i is changed in b2, but not b1
printf("i in b2 = %0d\n",b2.i);// i equals 10
printf("i in b1 = %0d\n",b1.i);// i equals 1
//where as:
b2.a.j =50; // Change j in the object referenced
// by a. j is shared by both b1 and b2
printf("j is %0d in b1 and %d in b2\n",b1.a.j,b2.a.j);
}
programshallow_copy{
test();
}
RESULTS
i in b2 = 10
i in b1 = 1
j is 50 in b1 and 50 in b2
Properties:
The properties in a class may be of the following atomic types or may
be arrays of these types.
reg
reg [msb:0]
integer
string
event
class type
enum type
A property declaration may be preceded by one of these keywords:
local
public
protected
public is the default protection level for class members. Using public when declaring a
property allows global access to that member via class_name.member. In contrast, a
member designated as local isone that is only visible from within the class itself. A
protected property is not visible outside of the class scope, but it is visible to peer
objects and can be inherited by subclasses.
This:
The this keyword is used to unambiguously refer to properties or methods of the
current instance. For example, the following declaration is a common, way to write
an initialization task:
EXAMPLE : this
classDemo
{
integerx;
tasknew(integerx)
{
this.x =x;
}
}
programmain {
Demo D;
D =new(10);
printf(" D.x is %d \n",D.x);
}
RESULTS
D.x is 10
The x is now both a property of the class and an argument to the task new(). In the
task new(), an unqualified reference to x will be resolved by looking at the innermost
scope, in this case the subroutine argument declaration. To access the instance
property,we qualify it with this to refer to the current instance.
Class Extensions :
Subclasses and Inheritance :
OpenVera's OOP implementation provides the capability of inheriting from a base class
and extending its capabilities within a
subclass. This concept is called inheritance. When one inherits from a class into
another, the original class definition is not changed, however the new subclass
contains all the properties and methods of the base class and then can optionally add
additional properties and methods.
EXAMPLE : Inheritance
classA {
taskdisp_a (){
printf(" This is class A ");
}
}
classEAextendsA {
taskdisp_ea (){
printf(" This is Extended class A ");
}
}
programmain {
EAmy_ea;
my_ea =new();
my_ea.disp_a();
my_ea.disp_ea();
}
RESULTS
This is class A
Polymorphism :
Polymorphism allows the redefining of methods for derived classes while enforcing a
common interface.To achieve polymorphism the 'virtual' identifier must be used when
defining the base class and method(s) within that class. A virtual class is a class which
serves as a template for the construction of derived classes. One cannot create an
instance of a virtual class.
EXAMPLE :Polymorphism
classA {
virtualtaskdisp (){
printf(" This is class A ");
}
}
classEAextendsA {
taskdisp (){
printf(" This is Extended class A ");
}
}
programmain {
EAmy_ea;
A my_a;
my_ea =new();
my_a =my_ea;
my_ea.disp();
my_a.disp();
}
RESULTS
Super:
The super keyword is used from within a derived class to refer to properties of the
parent class. It is necessary to use super when the property of the derived class has
been overridden, and cannot be accessed directly.
EXAMPLE :
classA {
virtualtaskdisp (){
printf(" This is class A \n");
}
}
classEAextendsA {
taskdisp (){
super.disp();
printf(" This is Extended class A \n");
}
}
programmain {
EAmy_ea;
my_ea =new();
my_ea.disp();
}
RESULTS
This is class A
Abstract Class:
A set of classes can be created that can be viewed as all being derived from a
common base class.If base class is not supposed to be used to creat an object,then it
has to be declared as abstract class using keyword virtual.
EXAMPLE:
virtualclassBasePacket{
functionintegersend(bit[31:0]data){
}
}
classEtherPacket extendsBasePacket{
functionintegersend(bit[31:0]data){
// body of the function
...
}
}
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TUTORIALS
CASTING
SystemVerilog
The cast_assign() system function assigns values to variables that might not ordinarily
be valid because of type checking rules.
Syntax : function integer cast_assign(scalar dest_var, scalar source_exp [,CHECK]);
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
When the cast_assign() system function is called without CHECK, the function assigns
the source expression to the destination variable. If the assignment is illegal, a fatal
runtime error occurs. When the cast_assign() system function is called with CHECK
specified, the function makes the assignment and returns a 1 if the casting is
successful. If the casting is unsuccessful, the function does not make the assignment
and returns a 0.
EXAMPLE:
classbase {
virtualtaskpri(){
printf(" BASE CLASS STATEMENT\n");
}
}
classEX_1extendsbase {
taskpri(){
printf(" EX1 CLASS STATEMENT\n");
}
}
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
programmain{
base b;
EX_1e1;
b =new();
if(cast_assign(e2,b))
printf("casting done \n");
else
printf(" casting failed \n");
e2.pri();
printf(" END OF SIMULATION \n");
}
RVM Switch TB
RVM Ethernet sample RESULTS:
Specman E
casting done
BASE CLASS STATEMENT
END OF SIMULATION
Interview Questions
http://testbench.in/OV_22_CASTING.html[9/26/2012 2:47:58 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
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http://testbench.in/OV_22_CASTING.html[9/26/2012 2:47:58 PM]
Search
Index
Introduction
Data Types
SystemVerilog
Openvera allowses object-oriented programiming for random stimulus generation Linked List
Verification
Operators Part 1
subjected to specified constraints.
Constructs
During randomization, variables declared as rand and randc inside class are only Operators Part 2
considered for randomization.Built-in randomized() method is called to generate new Operators Part 3
Interface
Operator Precedence
random values for there variable.
OOPS
Control Statements
EXAMPLE:
Randomization
Interprocess
classSimple{
Functional Coverage
Fork Join
randintegerVar;
Shadow Variables
Assertion
}
Fork Join Control
programmain
{
DPI
Wait Var
Simple
Event Sync
UVM Tutorial
obj;
Event Trigger
obj =new();
VMM Tutorial
Semaphore
repeat(10)
Regions
OVM Tutorial
if(obj.randomize())
Mailbox
printf("
Randomization
sucsessfull
:
Var
=
%0d
\n",obj.Var);
Easy Labs : SV
Timeouts
else
Oop
Easy Labs : UVM
printf("Randomization failed\n");
Casting
Easy Labs : OVM
Randomization
}
Easy Labs : VMM
RESULTS:
Constraint Block
AVM Switch TB
VMM Ethernet sample Randomization sucsessfull : Var = -1671855048
Variable Ordaring
Aop
Predefined Methods
String Methods
Verilog
Queue Methods
Randomization
sucsessfull
:
Var
=
1674352583
Verification
Dut Communication
Functional Coverage
Verilog Switch TB
Basic Constructs
TUTORIALS
RANDOMIZATION
Constrained Random Verification
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Random Varible Declaration:

Varibles declared as rand and randc are only randomized.All other varible are
considered as state varibles.
EXAMPLE
classex{
rand[3:0]var1;
randc[3:0]var2;
randintegervar3;
}
Fixed Arrays,dynamic arrays,associative arrays and queues can be declared as rand
and randc ,all their elements are treated as rand and randc.Individual array elements
can also be constrained,in this ,index expression must be constant.For dynamic
arryas,the size of the array length can be constrained.Non integral data types like real
are not allowed for random varible declaration.
Rand Modifier :
http://testbench.in/OV_23_RANDOMIZATION.html[9/26/2012 2:48:07 PM]

input is what keeps
with time!
Variables declared with the rand keyword are standard random variables.
When ther are no other control on distrubution,these variables are uniformly
distributed.
Uniformly distribution is only on the valid values.
EXAMPLE
classrand_cl{
randbit[0:2]Var;
constraintlimit_c {Var <4;}
}
programrand_p{
rand_cl obj;
integercount_0,count_1,count_2,count_3;
obj =new();
repeat(10000)
{
void=obj.randomize();
}
printf(" count_0 = %0d , count_1 = %0d, count_2 = %0d, count_3 = %0d
",count_0,count_1,count_2,count_3);
}
RESULTS:
count_0 = 2501 , count_1 = 2553, count_2 = 2558, count_3 = 2388
Simulation results shou that the randvariable is distrubuted uniformly.
Randc Modifier :
Varibles declared as randc, randomly iterates over all the values in the range and no
value is repeated with in an iteration.
Iteration sequences are not same.Bit and enumarated types can be randc variables.To
reduce memory requirements, implementations can impose a limit on the maximum
size of a randc variable,but it should be no less than 8 bits.
EXAMPLE
classrand_c{
randcbit[1:0]Vari;
}
programrand_cp{
rand_c obj;
integeri;
obj =new();
for(i=0;i<20;i++)
{
printf("%0d_",obj.Vari);
if(i%4==3)
printf("\n");
}
}
RESULTS
1_2_0_3_
3_2_0_1_
3_1_2_0_
2_0_3_1_
1_3_2_0_
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
RANDOMIZATION METHODS
Randomization Built-In Methods
openvera has randomize(),pre_randomize() and post_randomize() built-in function for

randomization.
Calling randomize() causes new values to be selected for all of the random variables
in an object.
To perform operations immediately before or after randomization,pre_randomize()
and post_randomize() are used.
Randomize()
Every class has a virtualpredefined function randomize() ,which is provided for
generating a new value.Randomization function returns 1 if the solver finds a valid
solution.We cannot override this predefined function.
It is strongly recomemded to check the return value of randomize function.Constraint
solver never fails after one sucessful randomization,if solution space is not
changed.For every randomization call,Check the return value ,solver may fail due to
dynamically changing the constraints.
In the following example,there is no solution for Var < 100 and Var > 200,so the
randomization failes.
The best way to check for randomization return value is by using assertion.
assert(obj.randomize());
EXAMPLE
VMM Ethernet sample classSimple{
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
randintegerVar;
constraintc {Var <100;Var >200;}
}
programmain{
Simple obj;
obj =new();
if(obj.randomize())
printf(" Randomization sucsessfull : Var = %0d ",obj.Var);
else
printf("Randomization failed");
}
Switch TB
RESULTS:
RVM Switch TB
Constraint failure
RVM Ethernet sample
Pre_randomize And Post_randomize

Specman E
Interview Questions
Every class contains pre_randomize() and post_randomize() methods, which are

automatically called
by randomize() before and after computing new random values.When randomize() is
called,it first invokes the pre_randomize,then randomize() then if the randomization
is sucesusful,then only post_randomize is invoked.
EXAMPLE:
classsimple{
taskpre_randomize{
printf(" PRE_RANDOMIZATION ");
}
taskpost_randomize{
http://testbench.in/OV_24_RANDOMIZATION_METHODS.html[9/26/2012 2:48:14 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
printf(" PRE_RANDOMIZATION ");

}
}
programmain{
simple obj =new();

}
RESULTS:
PRE_RANDOMIZATIONPRE_RANDOMIZATION
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Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
CONSTRAINT BLOCK
Constraint Block
Constraint block contains declarative state ments which restrict the range of varable
or defines the relation between variables.Constraint programming is a pwerful mehod
that lets users build generic ,resuble objects that canbe extended or more
constrained later.Constraint solver can only support 2 stet variables.Constraint solver
fails only if there is no solution which satisfies all the constraints.constraint block can
also have nonrandom variables,but atleast one random variable is needed for
randomization.
Constraints
are
tied
to
objects.This
allows
inheritance,hirarchical
constraints,controlling the constraints of specific object.
EXAMPLE:
classBase{
randintegerVar;
}
classExtended extendsBase{
constraintrange {Var <100;Var >50;}// Overrighting the Base class constraints.
}
Easy Labs : OVM
programinhe{
Extended obj;
integeri;
AVM Switch TB
obj =new();
VMM Ethernet sample for(i=0;i <100;i++)
if(obj.randomize())
printf(" Randomization sucsessfull : Var = %0d ",obj.Var);
else
Verilog
printf("Randomization failed");
Verification
}
Easy Labs : VMM
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RESULTS:
RVM Switch TB
RVM Ethernet sample Inline Constraints
Specman E
Interview Questions
Inline constraints allows to add extra constraints to allready existing conrtints which
are declared inside class.If you have constraints already defined for variavle var,
solver solves those constraints wlong with the inline constraints.
EXAMPLE
classinline{
randintegerVar;
constraintdefault_c {Var >0;Var <100;}
}
programinline_p{
inline obj;
obj =new();
http://testbench.in/OV_25_CONSTRAINT_BLOCK.html[9/26/2012 2:48:23 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
void=obj.randomize()with{Var ==50;};
printf(" Randodmize sucessful Var %d ",obj.Var);
}
RESULTS:
Disabling Constraint Block
openvera supports to change the status of constraint block dynamically.To change the
staus of a Constraint block,built in constraint_mode() method is used.By default all
the constraint blocks are active.
When it is called as task,the arguments to the task determines the operation to be
performed.
0OFFSets the specified constraint block to inactive

so that it is not enforced by subsequent calls
to the randomize() method.
1ON Sets the specified constraint block to active so
that it is considered on subsequent calls to the
randomize() method.
When it is called as function,it returns the active status of the specified constrant
block.
EXAMPLE:
classrand_mo{
randintegerVar1;
randintegerVar2;
}
programrand_mo_p{
rand_mo obj =new();
printf(" Var1 : %d Var2 : %d \n",obj.Var1,obj.Var2);
void=obj.constraint_mode(0,"Var_1");
void=obj.constraint_mode(0,"Var_2");
}
RESULTS:
Var1 : 20 Var2 : 10
Var1 : 1923838927 Var2 : 10
Var1 : 1447386075 Var2 : -875228050
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Index
Introduction
Data Types
SystemVerilog
Linked List
A constraint_expression is any Openvera expression or one of the constraint specific
Verification
Operators Part 1
operators, -> (Implication) and dist.
Constructs
Operators Part 2
Operators Part 3
Set Membership
Interface
Operator Precedence
OOPS
A set membership is a list of expressions or a range.This operator searches for the Control Statements
Randomization
existences of the value in the specified expression or range and returns 1 if it is Procedures And Methods
Interprocess
existing.
Functional Coverage
Fork Join
Shadow Variables
Assertion
EXAMPLE:
Fork Join Control
classset_mem{
DPI
Wait Var
randintegerVar;
Event Sync
UVM Tutorial
constraintrange {Var in{0,1,{50,60},{90,100}};}
Event Trigger
taskpost_randomize(){
VMM Tutorial
Semaphore
printf("%0d__",Var);
Regions
OVM Tutorial
}
Mailbox
}
Easy Labs : SV
Timeouts
Oop
Easy Labs : UVM
programset_mem_p{
Casting
set_mem
obj=new();
Easy Labs : OVM
Randomization
repeat(10)
Easy Labs : VMM
Constraint Block
}
AVM Switch TB
Variable Ordaring
Aop
Predefined Methods
1__51__93__1__0__56__0__94__1__0__
String Methods
Verilog
Queue Methods
Verification
Dut Communication
If you want to define a range which is outside the set,use nagation.
Functional Coverage
Verilog Switch TB
EXAMPLE:
classset_mem{
Basic Constructs
randbit[0:2]Var;
constraintrange {!(Var in{0,1,5,6};)}
input is what keeps
OpenVera
printf("%0d__",Var);
with time!
Constructs
}
}
Switch TB
RVM Switch TB
programset_mem_p{
RVM Ethernet sample set_mem obj=new();
repeat(10)
}
TUTORIALS
CONSTRAINT EXPRESSION
Constraint Expressions
Specman E
Interview Questions
RESULTS:
2__7__2__4__7__3__3__4__2__7__
Weighted Distribution
There are two types of distribution operators.
The := operator assigns the specified weight to the item or, if the item is a range, to
every value in the range.
The :/ operator assigns the specified weight to the item or, if the item is a range, to
http://testbench.in/OV_26_CONSTRAINT_EXPRESSION.html[9/26/2012 2:48:33 PM]
the range as a whole. If

there are n values in the range, the weight of each value is range_weight / n.
Var dist{10:=1;20:=2;30:=2}
The probabulity of having 10,20,30 is in the ration of 1,2,2 respectively.
Var dist{10:=1;20:=2;[30:32]:=2}
The probabulity of having 10,20,30,31,32 is in the ration of 1,2,2,2,2 respectively.
If you use the := operator each element of the range has the assigned weight.
If you want to weight for the whole group,use :/ and the weight is distributed equally
for each element in that group.
Var dist{10:=1;20:=2;[30:32]:/2}
The probabulity of having 10,20,30,31,32 is in the ration of 1,2,2/3,2/3,2/3
respectively.
To demonstrate the distribution property,hear is an example.
EXAMPLE:
classDist{
randintegerVar;
constraintrange {Var dist{{0,1}:=50,{2,7}:=50};}
}
programDist_p{
Dist obj;
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
if(obj.randomize())
{
if(obj.Var inside {0,1})count_0_1 ++;
elseif(obj.Var inside {[2:7]})count_2_7 ++;
}
printf(" count_0 = %0d , count_1 = %0d, count_2 = %0d, count_3 = %0d, count_4 =
%0d,
count_5
=
%0d,
count_6
=
%0d,
count_7=
%0d
printf(" count_0_1 = %0d ;count_2_7 = %0d ",count_0_1,count_2_7);
}
RESULTS:
count_0 = 2450 , count_1 = 2420, count_2 = 1114, count_3 = 1071, count_4 = 871,
count_0_1 = 4870 ;count_2_7 = 5130
Now change the constraint to
constraintrange {Var dist{{0,1}:/50,{2,7}:/50};}
EXAMPLE:
classDist{
randintegerVar;
constraintrange {Var dist{{0,1}:/50,{2,7}:/50};}
}
programDist_p{
Dist obj;
obj=new();
count_0_1 =0;count_2_7 =0;
for(inti=0;i<10000;i++)
if(obj.randomize())
{
if(obj.Var in{0,1})count_0_1 ++;
elseif(obj.Var in{2,7}})count_2_7 ++;
}
printf(" count_0 = %0d , count_1 = %0d, count_2 = %0d, count_3 = %0d, count_4 =
%0d,
count_5
=
%0d,
count_6
=
%0d,
count_7=
%0d
printf(" count_0_1 = %0d ;count_2_7 = %0d ",count_0_1,count_2_7);
}
RESULTS:
count_0 = 1245 , count_1 = 1242, count_2 = 1211, count_3 = 1271, count_4 = 1287,
count_0_1 = 2487 ;count_2_7 = 7513
Both the reults show,how may times each value occured.

NOTE:If no wait is specified for items,the default weight is 1.
Weight 0 is also allowed.
NOTE:Variable declared as randc are not allowed int dist.
Implication
Implication operator can be used to predirect a relation.The syntax is expression ->
constraint set.
If the expression is true,then the constraint solver should satisfy the constraint set.
The booliean equvalant of a -> b is (!a || b).
randbita;
randbit[3:0]b;
The probabulity of a = 0 is 1/2**5,as bidirectional constraints are solved at once,the
solver pics the random value from the possible set of {a,b} which has 2**5 solutions.
EXAMPLE:
classimpli{
randbitVar;
randbit[3:0]b;
constraintc {(Var ==0)=>(b ==1);}
}
programimpli_p{
impli obj;
integercount_0 ,count_1,i ;
obj=new();
for(i=0;i<10000;i++)
{
obj =new();
if(obj.randomize())
{
}}
printf(" count_0 = %0d;count_1 = %0d;",count_0 ,count_1);
}
RESULTS:
count_0 = 2047;count_1 = 7953
If..Else
Just like implication,if...elsestyle constraints are bidirectional.Above example
applies hear too.
EXAMPLE:
classif_else{
randbita;
randbit[3:0]b;
}
programif_else_p{
if_else obj;
obj=new();
for(inti=0;i<10000;i++)
{
obj =new();
if(obj.randomize())
{
}}
}
RESULTS
count_0 = 2047;count_1 = 7953
Iterative
Iterative constraints allow Constraining individual fixed-size, dynamic, associative, or
queue elements.
foreach construct specifies iteration over the elements of array.
EXAMPLE:
classEth_pkt{
randbyte Payload[*];
constraintsize_c {Payload.size()inside {[46:1500]};}
constraintelement_c {foreach(Payload[i ])Payload[i ]inside {[50:100]};}
}
programiterative{
Eth_pkt obj;
obj =new();
for(inti=0;i<10000;i++)
{
if(obj.randomize())
printf(" RANDOMIZATION DONE ");
}}
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
VARIABLE ORDARING
Variable Ordaring
openvera allows to control the order of randomization variables.The solution space

remains the same,but the probabulity of picking up the values changes.the syntax for
variable ordering is "solve x before y".The exact meaning of this statement is "choos x
befor y"as the this state ment if to guide the distribution,but not the solution space.
Only rand variables are allowed.
EXAMPLE:
classVar_order{
randbita;
randbit[3:0]b;
constraintbidirectional {a ->b ==0;}}
The probabulity of a=1 is 1/2**5,as bidirectional constraints are solved at once,the
solver pics the random value from the possible set of {a,b} which has 2**5 solutions.To
make the probability of a= 0 to 50% and a = 1 to 50% ,use
Easy Labs : SV
constraintorder {solve Var1 beforeVar2 ;}
Easy Labs : UVM
This guides the solver to give highest priority to Var1 than Var2.This is explicit
variable ordaring.The solver follows the implicit variable ordaring also,like randc are
solved before rand variables,in dynamix arrays size and elements are solved with two
constraints,and size is solved before element.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
classvar_order{
VMM Ethernet sample randbitVar;
Verilog
randbit[3:0]b;
constraintc {if(Var ==0)(b ==1);}
constraintorder {solve Var beforeb ;}
Verification
programvar_order_{
Basic Constructs
var_order obj;
integercount_0 ,count_1,i ;
obj=new();
OpenVera
Constructs
for(i=0;i<10000;i++)
{
Switch TB
obj =new();
RVM Switch TB
if(obj.randomize())
RVM Ethernet sample {
}}
Specman E
}
Interview Questions
RESULTS:
Verilog Switch TB
count_0 = 5120;count_1 = 4880
Too many explicit variable ordering may lead to circular dependency.The LRM says
that "Circular dependencies created by the implicit variable ordering shall result in an
error." and "circular dependency is not allowed".
But it does not put restriction on what to do if a explicit circular dependency
http://testbench.in/OV_27_VARIABLE_ORDARING.html[9/26/2012 2:48:42 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
exists.Check with your tool,if explicit Circular dependency is existing,it may report
warning,it may fail solver or proceed by just ignoring the order.
EXAMPLE:
programCir_Dip_p{
classCir_Dep;
randintegera,b,c;
constrainta_c {solve a beforeb ;}
constraintb_c {solve b beforec ;}
constraintc_c {solve c beforea ;}
}
Cir_Dip obj=new();
}
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Search
Index
Introduction
Data Types
SystemVerilog
AOP is used in conjunction with object-oriented programming. By compartmentalizing Linked List
Verification
aspect code, cross-cutting concerns become easy to deal with. Aspects of a system Operators Part 1
Constructs
Operators Part 2
can be changed, inserted or removed at compile time, and become reusable.
Operators Part 3
Interface
Operator Precedence
placement :
OOPS
Control Statements
The placement element specifies where code is woven into a method.
before inserts the code inside a method just
Randomization
Interprocess
before:: it begins any execution (that included execution of initializers)
Functional Coverage
after :: inserts code at each return statement and at the end of the methods Fork Join
Shadow Variables
Assertion
block, if it falls through without a return
Fork Join Control
statement.
DPI
Wait Var
around:: executes the code in place of the methods original code.
Event Sync
UVM Tutorial
Event Trigger
VMM Tutorial
Semaphore
EXAMPLE : aop around
Regions
OVM Tutorial
classaop {
Mailbox
taskdisp(){
Easy Labs : SV
Timeouts
printf(" aop class ");
Oop
Easy Labs : UVM
ihop($ori_lin);
Casting
}
Easy Labs : OVM
Randomization
}
Easy Labs : VMM
Constraint Block
extendseaop (aop){
AVM Switch TB
aroundtaskdisp(){
VMM Ethernet sample printf("eaop class ");
Variable Ordaring
Aop
}
Predefined Methods
String Methods
programmain{
Verilog
Queue Methods
aop
obj;
Verification
Dut Communication
obj =new();
Functional Coverage
Verilog Switch TB
obj.disp();
}
Basic Constructs
TUTORIALS
AOP
Aspect Oriented Extensions :
RESULTS
OpenVera
Constructs
eaop class
Switch TB
EXAMPLE : aop before

classaop {
RVM Ethernet sample taskdisp(){
}
}
RVM Switch TB
Specman E
Interview Questions
extendseaop (aop){
beforetaskdisp(){
printf("eaop class ");
}
programmain{
aop obj;
obj =new();
obj.disp();
}
http://testbench.in/OV_28_AOP.html[9/26/2012 2:48:52 PM]

input is what keeps
with time!
RESULTS
eaop class
aop class
EXAMPLE : aop after
classaop {
taskdisp(){
}
}
extendseaop (aop){
aftertaskdisp(){
printf("eaop class ");
}
programmain{
aop obj;
obj =new();
obj.disp();
}
RESULTS
aop class
eaop class
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Search
Index
Introduction
Data Types
SystemVerilog
Linked List
OpenVera Predefined Methods ::
Verification
Operators Part 1
# Class Methods
Constructs
Operators Part 2
# String Methods
Operators Part 3
# Smart Queue Methods
Interface
Operator Precedence
# Functional Coverage
OOPS
Control Statements
OpenVera Class Methods ::
Randomization
Interprocess
# new()
Functional Coverage
Fork Join
# Randomize Methods
Shadow Variables
Assertion
# Object Print
Fork Join Control
#
Deep
Object
Compare
DPI
Wait Var
# Deep Object Copy
Event Sync
UVM Tutorial
# Pack and Unpack by Class Methods
Event Trigger
VMM Tutorial
Semaphore
Regions
OVM Tutorial
New():
Mailbox
Easy Labs : SV
In OpenVera, new() is a special method that allocates memory for an object and Timeouts
Oop
Easy Labs : UVM
assigns a handle to that object.
Casting
Easy Labs : OVM
Randomization
EXAMPLE : new()
Easy Labs : VMM
classDemo
Constraint Block
{
AVM Switch TB
integerx;
VMM Ethernet sample tasknew()
Variable Ordaring
Aop
{printf(" Object of Demo is created ");}
Predefined Methods
}
String Methods
Verilog
Queue Methods
programmain
{
Verification
Dut Communication
Demo D;
Functional Coverage
Verilog Switch TB
D =new();
}
Basic Constructs
RESULTS
TUTORIALS
OpenVera
Constructs
PREDEFINED METHODS
Predefined Methods:
Object of Demo is created .
Switch TB
Finalize()
RVM Switch TB
When the garbage collector determines that there are no more references to an
RVM Ethernet sample object, it will implicitly call finalize() just before the memory occupied by an object
is reclaimed.
Specman E
Interview Questions
Object_print
The entire object instance hierarchy can be sent to stdout or to a specified file using
the object_print() method. As the deep print routine recurses down the object
instance hierarchy, object members and array elements are indented as they are
printed. All the super object members are displayed with the same indentation.
EXAMPLE :object_print
#include <vera_defines.vrh>
enumcolors {red,green,black,white};
classembed{
http://testbench.in/OV_29_PREDEFINED_METHODS.html[9/26/2012 2:49:02 PM]

input is what keeps
with time!
integeri;
colors col;
reg[3:0]bits_mem;
stringstr_mem;
}
classsimple{
integera,b,c,d;// integers
colors col;// enum
reg[3:0]abc;// bit vector
embed e;
stringstr;// string_var
}
programmain{
simple abc =new;
abc.e =new;
abc.a =123;
abc.b =111111111;
abc.d =12345;
abc.col =red;
abc.abc[3:0]=4b1100;
abc.object_print();
}
RESULTS
a : dec: 123
b : dec: 111111111
c:X
d : dec: 12345
col : ENUM:red
abc : hex: c
e : OBJECT of CLASS embed
i:X
col : ENUM:X
bits_mem : bin: xxxx
str_mem : NULL
str : NULL
Deep Object Compare
Object_compare() is a predefined function for all Vera classes that performs a
comparison of two objects of the same class type. The compiler generates errors for
invalid types.All members of the two objects are compared. This includes the
comparison of contained objects.
EXAMPLE : object_compare()
classMyClass
{integerA;
}
programobject_compare_ex
{
MyClass object1,object2;
object1 =new();
object2 =object1.object_copy();
if(!object1.object_compare(object2))
error("Object compare failed\n");
else
printf("Objects are the same\n");
}
RESULTS
printf("Objects are the same\n");
Deep Object Copy
object_copy() is defined as a virtual function that copies the contents of a source
object into a destination object. The object copy is deep, replicating the entire data
structure including contained objects and the super object.
EXAMPLE : object_copy()
MyClass src_obj,dest_obj;
src_obj =new();
dest_obj =src_obj.object_copy();// dest_obj and
// src_object are now duplicates
if(dest_obj ==null)error("Copy failed\n");
elseprintf(" Copy done ");
RESULTS
Copy done
Pack And Unpack
Data packing is integrated into the object-oriented framework of OpenVera. OpenVera
defines several class methods that are used to pack and unpack data declared within
a class.
pre_pack and post_pack: OpenVera provides the pre_pack() and post_pack() methods.
These methods are called automatically before and after pack().
pre_unpack and post_unpack: OpenVera provides pre_unpack() and post_unpack()
methods. These called automatically before and after unpack().
EXAMPLE :
classSerial_Data_Type {
staticintegertotal_inst_count =0;
packed{
randreg[19:0]bit_data;
stringcomment;
}
tasknew(){
integerstatus;
status =this.randomize();
if(!status )
error("Randomize failed!\n");
comment =psprintf("comment_%0d",total_inst_count);
printf("inst
=
%-9d
,
data
=
%-25b
%0s\n",total_inst_count,bit_data,comment );
total_inst_count++;
}// new
}
programpacked_test {
Serial_Data_Type sdata_arr[5];
regdata_stream[];// does not have to be byte stream
integeri,offset,left,right;
printf("\n\nPacking data ...........\n");
offset =0;left =0;right =0;
for(i =0;i <5;i++){
sdata_arr[i]=new();
void=sdata_arr[i].pack(data_stream,offset,left,right );
}// for
printf("\n\nUnpacking data in order .....\n");
offset =0;left =0;right =0;
for(i =0;i <5;i++){
void=sdata_arr[i].unpack(data_stream,offset,left,right );
printf("inst
=
%-9d
,
data
=
%-25b
%0s\n",i,sdata_arr[i].bit_data,sdata_arr[i].comment );
}// for
}// packed_test
RESULTS
Packing data ...........
comment
comment
inst = 0 , data = 00010000111000000000comment

Unpacking data in order .....

<< PREVIOUS PAGE
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=
=
=
=
=
comment_0
comment_1
comment_2
comment_3
comment_4
=
=
=
=
=
comment_0
comment_1
comment_2
comment_3
comment_4
NEXT PAGE >>
Search
TUTORIALS
STRING METHODS
SystemVerilog
Vera provides a set of general methods to handle hidden values within string
variables.
Verification
Constructs
len(): The len() function returns the length of the string as an integer.
getc() : The getc() function returns an integer that is the ASCII equivalent to the
character at specified location.
OOPS
tolower(): The tolower() function changes upper case characters in a string to
lower case, and returns this new string.
Randomization
toupper(): The toupper() function changes lower case characters in a string to
Functional Coverage
upper case, and returns this new string.
Assertion
putc() : The putc() task assigns a given character to a specified location.
get_status() : The get_status() function returns the current status flag value as an
DPI
integer.
UVM Tutorial
get_status_msg(): The get_status_msg() function returns a string describing the
current status flag value.
VMM Tutorial
compare(): The compare() function compares two strings to determine if they are
OVM Tutorial
identical or not. The comparison is case sensitive . If the strings are identical, a 0 is
returned.
Easy Labs : SV
icompare() : The icompare() function is the same as compare() except that case is
Easy Labs : UVM
ignored. If the strings are identical, a 0 is returned. A non zero value is returned if
they are not identical.
Easy Labs : OVM
hash() : The hash() function hashes (or encodes) the string and returns a nonEasy Labs : VMM
negative integer that is less than the size specified.
substr() : The substr() function returns the sub-string of characters between two
AVM Switch TB
specified locations.
VMM Ethernet sample search() : The search() function searches for a pattern in the string and returns
the integer index to the beginning of the pattern.
match(): match() processes a regular expression pattern match.
prematch() :prematch() returns the string before a match, based on the result of
Verilog
the last match() function call.
Verification
postmatch(): postmatch() returns the string after a match, based on the result of
Verilog Switch TB
the last match() function call.
thismatch(): thismatch() returns the matched string, based on the result of the last
Basic Constructs
match() function call.
backref(): backref() returns matched patterns, based on the last match() function
call.
OpenVera
atoi() : atoi() returns the integer corresponding to the ASCII decimal
Constructs
representation of a string.
itoa() : The itoa() task converts an integer to an ASCII number in a string.
Switch TB
atooct() : atooct() handles a string as an ASCII octal number and converts it to a
RVM Switch TB
bit value.
RVM Ethernet sample atobin() : atobin() handles a string as an ASCII binary number and converts it to a
bit value.
Interface
Specman E
Interview Questions
EXAMPLE : string
programmain{
stringstr,str_1,str_2;
str ="This is a string";
str_1 =str ;
printf("String length = %0d\n",str.len());//
printf("The fourth character is the letter %c.\n",str.getc(3));
printf("Lower case string is $s \n",str.tolower());
printf("Upper case string is $s \n",str.toupper());
str.putc(0,"1");
printf(" Str after put 1 at 0 loc is %s \n",str);
printf(" Comparing str and str_1 resulted %d \n",str.compare(str_1));
http://testbench.in/OV_30_STRING_METHODS.html[9/26/2012 2:49:12 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
printf(" Substring from 2 to 4 of str is %s\n",str.substr(2,4));

printf(" searching for 'is a' in str resulted in %d",str.search("is a"));
printf(" matching for 'is' in str resulted in %d",str.match("is"));
str_2 ="123";
printf("After execute string.atoi method= %d\n",str_2.atoi());
}
RESULTS
String length = 16
The fourth character is the letter s.
Lower case string is this is a string
Upper case string is THIS IS A STRING
Str after put 1 at 0 loc is 1his is a string
Comparing str and str_1 resulted 0
Substring from 2 to 4 of str is is
searching for 'is a' in str resulted in 5
matching for 'is' in str resulted in 1
After execute string.atoi method= 123
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Index
Introduction
SystemVerilog
OpenVera provides the following types of built-in methods for analyzing and Data Types
Linked List
manipulating smart queue elements.
Verification
Operators Part 1
# Add/Delete
Constructs
Operators Part 2
- delete()
Operators Part 3
- insert()
Interface
Operator Precedence
# Order
OOPS
Control Statements
- reverse()
- rsort()
Randomization
Interprocess
- sort()
Functional Coverage
Fork Join
- sum()
Shadow Variables
Assertion
# Push/Pop
Fork Join Control
pop_back()
DPI
Wait Var
- pop_front()
Event Sync
UVM Tutorial
- push_back()
Event Trigger
- push_front()
VMM Tutorial
Semaphore
# Random
Regions
OVM Tutorial
- pick()
Mailbox
pick_index()
Easy Labs : SV
Timeouts
- unique()
Oop
Easy Labs : UVM
- unique_index()
Casting
#
Search
Easy Labs : OVM
Randomization
- find()
Easy Labs : VMM
- find_index()
Constraint Block
- first()
AVM Switch TB
- first_index()
VMM Ethernet sample - last()
Variable Ordaring
Aop
- last_index()
Predefined Methods
- max()
String Methods
- max_index()
Verilog
Queue Methods
min()
Verification
Dut Communication
- min_index()
Functional Coverage
Verilog Switch TB
# Size
- capacity()
Basic Constructs
- empty()
- reserve()
input is what keeps
- size()
OpenVera
TUTORIALS
QUEUE METHODS
with time!
Constructs
EXAMPLE :
Switch TB
programmain{
RVM Switch TB
integerque[$];
RVM Ethernet sample printf(" size of queue %d \n",que.size());
que.push_back(10);
que.push_front(2);
printf(" pop_back is %d \n",que.pop_back());
Specman E
printf(" pop_front is %d \n",que.pop_front());
Interview Questions
que.push_back(1);
que.push_back(2);
que.push_back(3);
printf(" size of queue %d \n",que.size());
que.insert(2,6);
}
RESULTS
http://testbench.in/OV_31_QUEUE_METHODS.html[9/26/2012 2:49:19 PM]
size of queue 0
pop_back is 10
pop_front is 2
size of queue 3
pop_back is 3
pop_back is 6
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TUTORIALS
SystemVerilog
DUT COMMUNICATION
Connecting To Hdl:
Verification
OpenVera can communicate to HDL in the following ways.
Constructs
#
#
#
#
#
#
#
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Interface Declaration
Interface Signal Connection
Virtual Port Signal Connection
signal_connect() System Function
Referencing Signals
Retrieving Signal Properties
HDL Tasks
Interface Declaration :
The interface specification is used to group Vera signals by clock domain. Each
interface may include, at most, one input signal of type CLOCK. The non-clock signals
defined in an interface are sampled and driven on the edges of this clock. If an input
signal of type CLOCK is not designated, then the interface signals are synchronized
using SystemClock.
These are examples of signal declarations with various signal types:
Easy Labs : VMM
EXAMPLE : interface declaration

interfaceabd {
inputclk CLOCK;
VMM Ethernet sample input[31:0]address PSAMPLE#-1;
inout[7:0]data PSAMPLE#-1PHOLD#1;
outputrdy PHOLD#1;
outputsig_out PHOLDNHOLD#1;
Verilog
inout[7:0]data PSAMPLENSAMPLE#-1PHOLDNHOLD#1;
Verification
}
AVM Switch TB
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB

A Vera interface signal can be connected to any user-specified HDL signal in a design input is what keeps
using the hdl_node option.
with time!
Direct Hdl Node Connection:
EXAMPLE : hdl_node
hdl_nodeCLOCK"hdl_path";
RVM Ethernet sample Blocking And Non-Blocking Drives:
Specman E
Interview Questions
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
Blocking drives suspend Vera execution until the statement completes. Note that the
clock edge (NHOLD or PHOLD) that the drive signal is associated with is used for
counting synchronized edges during suspension. Once the statement completes, Vera
execution resumes.Non-blocking drives schedule the drive at a future synchronized
edge and Vera execution continues. When the specified synchronized edge occurs, the
drive is executed.
EXAMPLE : Blocking and Nonblocking
@2ram_bus.data =1;// blocking drive
a =b;
@2ram_bus.data <=1;// non-blocking drive
a =b;
http://testbench.in/OV_32_DUT_COMMUNICATION.html[9/26/2012 2:49:28 PM]
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TUTORIALS
FUNCTIONAL COVERAGE
SystemVerilog
Functional Coverage :
Verification
Constructs
Interface
OOPS
Randomization
OpenVera is able to monitor all states and state transitions, as well as changes to
variables and expressions.By setting up a number of monitor bins that correspond to
states, transitions, and expression changes, Vera is able to track activity in the
simulation. Each time a user-specified activity occurs, a counter associated with the
bin is incremented.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Coverage Group
The coverage_group construct specifies the coverage model. It is defined either at the
top level (referred to as "standalone"), or defined in a class (referred to as
"embedded") The syntax is the same for both.
OVM Tutorial
EXAMPLE : Coverage group

classMyClass
{
Easy Labs : UVM
bit[0:7]m_x,m_y;
coverage_group cov1
Easy Labs : OVM
{
Easy Labs : VMM
sample_event =@(posedgeCLOCK);
sample m_x,m_y;
AVM Switch TB
}
Easy Labs : SV
Verilog
Verification
Verilog Switch TB
Basic Constructs
Sample_event:
sample_event defines when (or frequency at which) the coverage objects are
sampled.
EXAMPLE : Sampling event
sample_event =wait_var(open_vera_variable);
sample_event =sync(ALL|ANY,some_OpenVera_event);
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Coverage_point
Cover point define the points that are sampled by the coverage_group. They are
declared using the sample construct of a coverage_group.
EXAMPLE : Cover point
classMyClass
{
bit[0:7]m_x,m_y;
coverage_group cov1
{
sample m_x,m_y;
}
}
Cross Coverage :
cross coverage is crossing subsets of the coverage points being sampled by a
coverage_group. Crosses of coverage points of a coverage_group can be specified
http://testbench.in/OV_33_FUNCTIONAL_COVERAGE.html[9/26/2012 2:49:37 PM]
Index
Introduction
Data Types
Linked List
Operators Part 1
Operators Part 2
Operators Part 3
Operator Precedence
Control Statements
Interprocess
Fork Join
Shadow Variables
Fork Join Control
Wait Var
Event Sync
Event Trigger
Semaphore
Regions
Mailbox
Timeouts
Oop
Casting
Randomization
Constraint Block
Variable Ordaring
Aop
Predefined Methods
String Methods
Queue Methods
Dut Communication
Functional Coverage
input is what keeps
with time!
using the cross construct.

EXAMPLE : cross coverage:
classMyClass
{
bit[0:7]m_x,m_y;
coverage_group cov1
{
sample m_x,m_y;
cross cxy (m_x,m_y);
}
}
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Index
Dut Specification
Rtl
This DUT is a simple switch, which can drive the incoming packet to destination ports Top
Interface
Packet
The dut contain one input interface from which the packet enters the dut. It has four Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
DUT SPECIFICATION
Assertion

input is what keeps
with time!
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Packet format:
Switch TB
RVM Switch TB
Packet header:
RVM Ethernet sample Packet header contains three fields DA, SA and length.
Specman E
Interview Questions
header and data.
http://testbench.in/OS_01_DUT_SPECIFICATION.html[9/26/2012 2:49:44 PM]
Configuration:
Memory Interface:
Input Interface:
to become low after sending last byte of the packet.
When the dut is busy, and if it is not in a position to accept any more data, it will
assert busy signal. Data which is sent during this busy signal is lost if input is driving
when busy is high
Output Interface:
data signal.
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TUTORIALS
RTL
CODE: switch.v
SystemVerilog
module fifo (clk,
reset,
Verification
write_enb,
Constructs
read,
data_in,
Interface
data_out,
OOPS
empty,
full);
Randomization
input clk;
Functional Coverage
input reset;
Assertion
inputwrite_enb;
inputread;
DPI
input[7:0]data_in;
UVM Tutorial
outputempty;
VMM Tutorial
outputfull;
OVM Tutorial
wire clk;
wire write_enb;
Easy Labs : SV
wire read;
Easy Labs : UVM
wire [7:0]data_in;
reg[7:0]data_out;
Easy Labs : OVM
wire empty;
Easy Labs : VMM
wire full;
reg[7:0]ram[0:25];
AVM Switch TB
regtmp_empty;
VMM Ethernet sample regtmp_full;
integerwrite_ptr;
integerread_ptr;
Verilog
begin
Verification
data_out=8'b0000_0000;
Verilog Switch TB
tmp_empty =1'b1;
tmp_full=1'b0;
Basic Constructs
write_ptr =0;
read_ptr=0;
end
OpenVera
Constructs
assign empty =tmp_empty;
assign full=tmp_full;
Switch TB
always @(posedgeclk)begin
RVM Switch TB
if((write_enb ==1'b1)&&(tmp_full ==1'b0))begin
RVM Ethernet sample ram[write_ptr]=data_in;
tmp_empty <=1'b0;
Specman E
tmp_full <=1'b1;
end
Interview Questions
end
tmp_full <=1'b0;
tmp_empty <=1'b1;
end
end
http://testbench.in/OS_02_RTL.html[9/26/2012 2:49:52 PM]
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
end
endmodule //fifo
module port_fsm (clk,
reset,
write_enb,
ffee,
hold,
data_status,
data_in,
data_out,
mem0,
mem1,
mem2,
mem3,
addr);
inputclk;
inputreset;
input [7:0] mem0;
input [7:0] mem1;
input [7:0] mem2;
input [7:0] mem3;
inputffee;
inputhold;
inputdata_status;
input[7:0]data_in;
output[7:0] addr;
reg[7:0]data_out;
reg[7:0]addr;
regfsm_write_enb;
reg[3:0]state_r;
reg[3:0]state;
reg[7:0]parity;
parameter ADDR_WAIT =4'b0000;
parameter DATA_LOAD =4'b0001;
parameter PARITY_LOAD=4'b0010;
parameter HOLD_STATE=4'b0011;
parameter BUSY_STATE=4'b0100;
begin
error=1'b0;
data_out =8'b0000_0000;
addr =8'b00000000;
write_enb_r=3'b000;
fsm_write_enb=1'b0;
state_r=4'b0000;
state=4'b0000;
parity =8'b0000_0000;
sus_data_in=1'b0;
end
assign busy =sus_data_in;
always @(data_status)begin:addr_mux
case(data_in)
mem0 :begin
end
mem1 :begin
end
mem2 :begin
end
mem3 :begin
end
endcase
//$display("
data_inii
%d
,mem0
end//if
end//addr_mux;
always @(posedgeclk)begin:fsm_state
state_r <=state;
end//fsm_state;
%d
,mem1
always @(state_r ordata_status orffee orhold ordata_in)

begin:fsm_core
state=state_r; //Default state assignment
case(state_r)
ADDR_WAIT: begin
((mem0
==data_in)||(mem1
==data_in)||(mem2 ==data_in)))begin
state=DATA_LOAD;
end
elsebegin
state=BUSY_STATE;
end//if
end//if;
sus_data_in =!ffee;
((mem0
==data_in)||(mem1
==data_in)||(mem2 ==data_in))&&
(ffee ==1'b1))begin
addr =data_in;
data_out=data_in;
end
elsebegin
end//if
PARITY_LOAD:begin
state=ADDR_WAIT;
data_out =data_in;
DATA_LOAD: begin
(hold ==1'b0))begin
state=DATA_LOAD;
end
(hold ==1'b0))begin
state=PARITY_LOAD;
end
elsebegin
state=HOLD_STATE;
end//if
%d
,mem2
%d
==data_in)||(mem3
==data_in)||(mem3
sus_data_in =1'b0;
(hold ==1'b0))begin
data_out =data_in;
end
(hold ==1'b0))begin
data_out =data_in;
end
elsebegin
end//if
HOLD_STATE:begin
state=HOLD_STATE;
end
state=PARITY_LOAD;
end
elsebegin
state=DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out =data_in;
end//if
BUSY_STATE:begin
state=BUSY_STATE;
end
elsebegin
state=DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out=data_in;
end//if
endcase
end//fsm_core
assign
assign
assign
assign
write_enb[0]=write_enb_r[0]&fsm_write_enb;
endmodule //port_fsm
module switch (clk,
reset,
data_status,
data,
port0,
port1,
port2,
port3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3,
mem_en,
mem_rd_wr,
mem_add,
mem_data);
inputclk;
inputreset;
inputdata_status;
input[7:0]data;
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
wire ll0;
wire ll1;
wire ll2;
wire ll3;
wire empty_0;
wire empty_1;
wire empty_2;
wire empty_3;
wire ffee;
wire ffee0;
wire ffee1;
wire ffee2;
wire ffee3;
wire ld0;
wire ld1;
wire ld2;
wire ld3;
wire hold;
wire [7:0]addr;
reg[7:0]mem[3:0];
wire reset;
.reset (reset),
.read(read_0),
.empty (empty_0),
.full(ll0));
.reset (reset),
.read(read_1),
.empty (empty_1),
.full(ll1));
.reset (reset),
.read(read_2),
.empty (empty_2),
.full(ll2));
.reset (reset),
.read(read_3),
.empty (empty_3),
.full(ll3));

.reset (reset),
.ffee(ffee),
.hold(hold),
.data_in (data),
.mem0(mem[0]),
.mem1(mem[1]),
.mem2(mem[2]),
.mem3(mem[3]),
.addr(addr));
assign port0 =data_out_0; //make note assignment only for
assign port1 =data_out_1;
assign ready_0 =~empty_0;

assign
assign
assign
assign
ffee0 =(empty_0
ffee1 =(empty_1
ffee2 =(empty_2
ffee3 =(empty_3
|(addr
|(addr
|(addr
|(addr
!=mem[0]));
!=mem[1]));
!=mem[2]));
!=mem[3]));
assign ffee=ffee0 &ffee1 &ffee2 &ffee3;

assign
assign
assign
assign
ld0
ld1
ld2
ld3
=(ll0
=(ll1
=(ll2
=(ll3
&(addr
&(addr
&(addr
&(addr
==mem[0]));
==mem[1]));
==mem[2]));
==mem[3]));
assign hold =ld0 |ld1 |ld2 |ld3;

always@(posedgeclk)
begin
if(mem_en)
if(mem_rd_wr)
begin
end
end
endmodule //router
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Verification Environment:
Top
Interface
This is simple verification environment.
It has, packet, Packet generator, Driver, Scoreboard, Receiver, Coverage and Config Packet
Packet Generator
driver components.
Cfg Driver
Driver
Reciever
Scoreboard
Env
TOP
Assertion

input is what keeps
with time!
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VMM Ethernet sample
Verilog
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Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Top Module:
Top module contains the instance of the Dut and verification environment.
It also has the clock generator. For more information about clock generation, go
through TB_CONCEPTS in this website.
Creat an Interface and make an instance of the interface file.
Connect the interface instance to dut.
Creat an instance of the program block. Program block containg all the verification
component.
Switch TB
CODE: top
module top();
//Declare clock signal
RVM Ethernet sample regclock;
//Signals for Assertion and to view the class proprties in Waveform viewer
regpkt_status;
wiredata_status;
Specman E
wire[7:0]data_in;
Interview Questions
wire [3:0][7:0]data_out;
wire[3:0]ready;
wire[3:0]read;
wire [7:0]mem_data;
wire [1:0]mem_add;
wirereset;
wiremem_en;
wiremem_rd_wr;
RVM Switch TB
reg SystemClock ;
assignSystemClock =clock;
http://testbench.in/OS_03_TOP.html[9/26/2012 2:50:01 PM]
tb vshell(.SystemClock(SystemClock),
.\intf.clk(clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
.\intf.data_out_0 (data_out[0]),
.\intf.ready_0(ready[0]),
.\intf.read_0(read[0]),
.\intf.mem_data(mem_data),
.\intf.mem_add(mem_add),
.\intf.reset(reset),
.\intf.mem_en(mem_en),
.\intf.mem_rd_wr(mem_rd_wr)
);
switch switch1(.clk(clock),
.reset(reset),
.data_status (data_status),
.data (data_in),
.port0 (data_out[0]),
.ready_0 (ready[0]),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2(read[2]),
.read_3(read[3]),
.mem_en (mem_en),
.mem_rd_wr(mem_rd_wr),
.mem_add(mem_add),
.mem_data (mem_data));
initial begin
//If you are using always for clock generation, take care not have edge on time 0
clock =0;
forever begin
#5clock =!clock;
end
end
endmodule //top
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Define vera shell interface. For the reciver component, use ports. Defing a port and Rtl
Top
connect four binds.
Interface
Packet
CODE:interface.vr
Packet Generator
interfaceintf {
Cfg Driver
Driver
input clkCLOCK;
Reciever
outputdata_status PHOLD #1;
Scoreboard
output[7:0]data_in PHOLD #1;
Env
input[7:0]data_out_0 PSAMPLE #-1 ;
INTERFACE
inputready_0 PSAMPLE #-1 ;

OVM Tutorial
Easy Labs : SV
output read_0 PHOLD #1 ;
Easy Labs : UVM
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output[7:0] mem_data PHOLD #1;
output [1:0] mem_add PHOLD #1;
AVM Switch TB
outputreset PHOLD #1;
VMM Ethernet sample outputmem_en PHOLD #1;
outputmem_rd_wr PHOLD #1;
}
Verilog
portrec_ports {
Verification
data_out;
Verilog Switch TB
ready;
read;
Basic Constructs
}
VMM Tutorial
OpenVera
Constructs
Switch TB
RVM Switch TB
bindrec_ports rec_0 {
data_out intf.data_out_0;
ready intf.ready_0;
read intf.read_0;
}
RVM Ethernet sample bindrec_ports rec_1 {
Specman E
Interview Questions
ready intf.ready_1;
read intf.read_1;
}
ready intf.ready_2;
read intf.read_2;
}
ready intf.ready_3;
read intf.read_3;
http://testbench.in/OS_04_INTERFACE.html[9/26/2012 2:50:09 PM]
input is what keeps

with time!
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Packet is a class with all the fields in the packet randomly.

Types of possible packets :
Packet with DA with one of the configured port address..
Packets with DA which has unconfigured address.
Packets with valid and invalid length.
Packets with good and bad FCS.
Payload size types: SMALL, MEDIUM and LARGE
Use Constraints to get valid da.

Put packet id as the first feild in data. This is for debugging. Looking at the id ,its
easy to identyfy the packet.
A method to unpack the data. When the reciver recives data, it is at low level. Using input is what keeps
unpack, da,sa,length,data and fcs feilds can be separated.
with time!
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
CODE: packet.vr
////Define the enumerated types for packet payload size type
//typedef enum payload_size_t { SMALL, MEDIUM, LARGE } ;
//typedef enum packet_kind_t { GOOD, BAD };
Easy Labs : VMM
classpacket{
enumpayload_size_t =SMALL,MEDIUM,LARGE;
VMM Ethernet sample enumpacket_kind_t =GOOD,BAD;
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
randpayload_size_t payload_size;// Control field for the payload size

randpacket_kind_t packet_kind; // Control field for GOOD/BAD
bit[7:0]uid;// Unique id field to identify the packet
cfg_drvr cfg;
randbit[7:0]len;
randbit[7:0]da;
randbit[7:0]sa;
bit[7:0]data[*];//Payload using Dynamic array,size is generated on the fly
randbit[7:0]parity;
bit[7:0]mem [4];
constraintaddr_8bit {(da ==mem[3])||(da ==mem[0])||(da ==mem[1])||(da
==mem[2]);}
(payload_size ==SMALL)=>len in{5:6};
(payload_size ==MEDIUM)=>len in{7:8};
(payload_size ==LARGE)=>len in{9:10};}

portrandomize
(packet_kind ==GOOD)=>parity ==0;
(packet_kind ==BAD )=>parity !=0;}
taskpre_randomize(){
http://testbench.in/OS_05_PACKET.html[9/26/2012 2:50:17 PM]
this.mem[0]=cfg.mem[0];
}
//////////////////////////////////////////////////////////////
// parity_calc()
//
// Return the byte resulting from xor-ing among all data bytes
// and the byte resulting from concatenating addr and len
//////////////////////////////////////////////////////////////
functionbit[7:0]parity_cal(){
integeri;
bit[7:0]result ;
result =8'hff;
result =result ^da;
result =result ^sa;
result =result ^len;
data =new[len];
data[0]=uid ;
result =result ^data[0];
for(i =1;i<len;i++)
{
data[i]=random();
}
parity_cal=result;
}
printf("[PKT] da %h sa %h len %h parit %h \n",this.da,this.sa,this.len,this.parity);
}
//new task,uid is assigned when object is created
tasknew(bit[7:0]i,cfg_drvr cfg){
uid=i;
this.cfg =cfg;
}
//unpacking task for converting recived data to class properties

taskbyte_unpack(bit[7:0]bytes[$]){
void=bytes.pop_front();
printf("[UNPACKING] bytes size %d\n",bytes.size());
foreach(bytes,i)
printf("[UNPACKING] bytes %b :%0d\n",bytes[i],i);
da =bytes.pop_front();
sa =bytes.pop_front();
len =bytes.pop_front();
data =new[len];
parity =bytes.pop_back();
foreach(data,i)data[i]=bytes.pop_front();
}
}
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PACKET GENERATOR
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VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
Use a class to build packet generator. Make an instance of this class. Packet generator
generator generates packets and sends to driver using mailbox. Mailboxisis used to
connect the packet generator and driver. Packet generator generates the packet and
randomizes the packet. Then the packet is put into mailbox. Always check whether
the randomization is sucessful and display a message.
CODE: gen.vr
classgenerator{
cfg_drvr cfg;
integerno_of_pkts;
packet cur_packet;
tasknew(cfg_drvr cfg){
this.cfg =cfg;
}
taskgen_pkts(){
bit[7:0]l;
l =0;
no_of_pkts =5;
repeat(no_of_pkts)
{
l++;
printf("[GENERATOR] l = %d \n",l);
cur_packet =new(l,cfg);
//Always check whether randomization is sucessesful or not
if(cur_packet.randomize()==1)
{
printf("[GENERATOR] Randomization Sucessesfull.\n");
//Drive the packet if Randomization is Sucessesfull
mailbox_put(gen,cur_packet);
}
else
printf("[GENERATOR] Randomization failed.\n");
}
}
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/OS_06_PACKET_GENERATOR.html[9/26/2012 2:50:26 PM]
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
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Index
Dut Specification
Rtl
Cfg_driver generates unique address to the three output ports and writes in to dut Top
Interface
memory.
Packet
Packet Generator
Cfg Driver
CODE:cfg.vr
Driver
classcfg_drvr{
Reciever
// Declare port_address as randc
Scoreboard
randcbit[7:0]port_address;
Env
bit[7:0]mem [4];
tasknew();
taskgen_add();
taskdrive_add();
input is what keeps
}
CFG DRIVER
taskcfg_drvr::new(){
printf("created cfg object \n");
}
Easy Labs : UVM
//task to randomize the port_address

taskcfg_drvr::gen_add(){
if(this.randomize())
Easy Labs : VMM
printf("[CFG_DRVR] Randomization done mem add is %h \n",port_address);
else
AVM Switch TB
printf("[CFG_DRVR] Randomization failed \n");
Easy Labs : OVM
//Task to drive the port address to dut

taskcfg_drvr::drive_add(){
integeri;
Verification
for(i =0;i<4;i++)
Verilog Switch TB
{
intf.mem_en =1;
Basic Constructs
@(posedgeintf.clk);
intf.mem_rd_wr =1;
this.gen_add();
OpenVera
@(posedgeintf.clk);
Constructs
intf.mem_add =i;
intf.mem_data =port_address;
Switch TB
mem[i]=port_address;
RVM Switch TB
}
RVM Ethernet sample @(posedgeintf.clk);
intf.mem_en=0;
intf.mem_rd_wr =0;
intf.mem_add =0;
Specman E
intf.mem_data =0;
Verilog
Interview Questions
http://testbench.in/OS_07_CFG_DRIVER.html[9/26/2012 2:50:33 PM]
with time!
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Index
Dut Specification
Rtl
Driver is a class.
Top
Interface
Define a task which gets the packet from mailbox and calls the drive packet.
Packet
Drive_packet is a task which drives the packet on to interface. Call the coverage Packet Generator
Cfg Driver
sample task.
Do packing of the packet generate ,so all the packets feilds which are at high level Driver
Reciever
are converted in to lovel data.
Scoreboard
Then drive the packet on to dut.
Env
Add the sent packet to scoreboard expected packet queue.
DRIVER
CODE: driver.vr
//Define driver as class,so this block can be ext}ed if needed
Easy Labs : SV
classdriver{
Easy Labs : UVM
packet cur_packet;
Easy Labs : OVM

Easy Labs : VMM
tasknew(){
void=this.randomize();
printf("created driver object\n ");
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
//Define task to generate the packet and call the drive task
taskgen_and_drive(){
integerl;
l =0;
printf("[DRIVER] NUMBER PACKETS %d\n ",gen_rator.no_of_pkts);
repeat(gen_rator.no_of_pkts)
{
void=mailbox_get(WAIT,gen,cur_packet,CHECK);
@(posedgeintf.clk);
drive_packet(cur_packet);
}
}
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
taskdrive_packet(packet pkt){
bit[7:0]pkt_packed[*];
integeri;
printf("[DRIVER] Starting to drive packet to intf %0d len %0d \n",pkt.da,pkt.len);
//Do packing of generated packet
pkt_packed =new[pkt.len +4];
pkt_packed[0]=pkt.da;
pkt_packed[1]=pkt.sa;
pkt_packed[2]=pkt.len;
foreach(pkt.data,i)
pkt_packed[i+3]=pkt.data[i];
pkt_packed[pkt.len+3]=pkt.parity;
@(posedgeintf.clk);
http://testbench.in/OS_08_DRIVER.html[9/26/2012 2:50:41 PM]

input is what keeps
with time!
foreach(pkt_packed,i)
printf("[PKT drvr] pkt %h at %d\n",pkt_packed[i],i);
// Byte by byte packed data on to DUV
for(i=0;i<pkt.len+3;i++)
{
@(posedgeintf.clk);
intf.data_status =1;
intf.data_in[7:0]=pkt_packed[i];
printf("[PKT drved] pkt %h at %d\n",pkt_packed[i],i);
}
@(posedgeintf.clk);
intf.data_status =0;
intf.data_in[7:0]=pkt.parity ;
//Add the sent packet to scoreboard expected packet queue
score_board.add_exp_packet(pkt);
@(posedgeintf.clk);
}
}
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Index
Dut Specification
Rtl
Receiver receives the packet and unpacks the packet and sends the unpacked packet Top
Interface
to scoreboard.
Packet
Reciver is a class. Declare a port . ports allows the reciver to communicate to dut. Packet Generator
Cfg Driver
Take four instancess of the reciver.
Driver
Reciever
CODE:receiver.vr
Scoreboard
Env
classreceiver{
staticintegerid;
cfg_drvr cfg;
rec_ports ports;
input is what keeps
// declarepacket to storereceived packet
packet rcv_packet;
with time!
randintegerrcv_delay;
integerport_num;
RECIEVER
constraintrev_dela {rcv_delay in{1:5};}
tasknew(cfg_drvr cfg,rec_ports ports){

this.ports =ports;
Easy Labs : VMM
this.cfg =cfg;
id =0;
AVM Switch TB
void=this.randomize();
VMM Ethernet sample printf("[RECIVER] created reciver object\n ");
}
Easy Labs : OVM
Verilog
// Define a task to collect data and unpack

taskcollect_packets(){
//Define queue of byte that will hold the received bytes
Verilog Switch TB
bit[7:0]temp;
integeri;
Basic Constructs
bit[7:0]received_bytes[$];
while(1){
OpenVera
@(posedgeports.$ready);
Constructs
rcv_delay =random()%10;
repeat(rcv_delay)@(posedgeintf.clk);
Switch TB
RVM Switch TB
while(ports.$ready){
RVM Ethernet sample
ports.$read=1;
Verification
Specman E
Interview Questions
@(posedgeintf.clk);
received_bytes.push_back(ports.$data_out);
printf("[RECIVER]
chanel
valid
0
",ports.$data_out,received_bytes.size());
}
ports.$read=0;
data
%x
repeat(1)@(posedgeintf.clk);
rcv_packet=new(id,cfg);
id++;
printf("[RECIVER]pkt id is %d size is %d\n",id,received_bytes.size());
http://testbench.in/OS_09_RECIEVER.html[9/26/2012 2:50:49 PM]
num
%d\n
//void =received_bytes.pop_front();
//unpack the recived data
rcv_packet.byte_unpack(received_bytes);
//as queues are used,delete it
received_bytes.delete();
// call the scoreboard task to check the packets
score_board.checkpacket(rcv_packet);
}
}
}
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Index
Dut Specification
Rtl
Top
The expected packets are stored in scored board by driver.
When ever the receiver sends a actual packet on to score board, the score board gets Interface
the expected packet out from the storage, where the driver has stored expected Packet
Packet Generator
packets, using the packet id.
Then both expected packet and actual packet re compared. If any mismatch ,then the Cfg Driver
Driver
test failed is reported.
Reciever
Scoreboard
CODE: scoreboard.vr
Env
SCOREBOARD
classscoreboard{
//Declare a queue of packet to store the expected packets
packet exp_pkt[$];
taskadd_exp_packet(packet packet_in){
exp_pkt.push_back(packet_in);
}

input is what keeps
with time!
Easy Labs : UVM
taskcheckpacket(packet packet_out){
integeri;
packet packet_sent;
Easy Labs : VMM
packet_sent=exp_pkt.pop_front();
if(packet_sent.da==packet_out.da
&&packet_sent.sa==packet_out.sa
AVM Switch TB
&&packet_sent.len==packet_out.len &&packet_sent.parity==packet_out.parity){
VMM Ethernet sample integeri;
printf("[SCOREBOARD]Datasent = recived DA %h : %h :: SA%h : %h :: len %h
:%hparity
%h
:%h\n
",packet_sent.da,packet_out.da,packet_sent.sa,packet_out.sa,packet_sent.len,packet_out.len,packet_sent.parity,packet_out.parity
Verilog
);
Verification
for(i=0;i<packet_sent.len -1;i++)
Verilog Switch TB
{
if(packet_sent.data[i]!=packet_out.data[i])
Basic Constructs
{
printf("[SCOREBOARD]ERROR data missmatch sent byte %h recived byte
%h\n",packet_sent.data[i],packet_out.data[i]);
OpenVera
trigger(err);
Constructs
}
else
Switch TB
printf("[SCOREBOARD]
sent
byte
%h
recived
byte
RVM Switch TB
%h\n",packet_sent.data[i],packet_out.data[i]);
Easy Labs : OVM
RVM Ethernet sample
Specman E
Interview Questions
}
}
else
{
printf("[SCOREBOARD][ERROR]Data mismatch sent != recived DA %h : %h :: SA%h : %h
::
len
%h
:%hparity
%h
:%h
\n",packet_sent.da,packet_out.da,packet_sent.sa,packet_out.sa,packet_sent.len,packet_out.len,packet_sent.parity,packet_out.parity
);
trigger(err);
}
}
}
http://testbench.in/OS_10_SCOREBOARD.html[9/26/2012 2:50:57 PM]
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TUTORIALS
ENV
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Its a program block named tb.

Define the coverage group for the generated packet
creat abject of the coverage group
Use initial block to creat driver and recivers and scoreboards.
Call the tasks in these components.
Impliment a logic for error count.
Define final block. THis prints whether the test is passed or failed.
CODE:env.vr
programtb{
reg bad;
event err;
integerno_of_errors;
integergen ;
cfg_drvr cfg ;
generator gen_rator ;
driver driver_obj ;
scoreboard score_board;
receiver receiver_obj_0 ;
VMM Ethernet sample gen =alloc(MAILBOX,0,100);
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
cfg =new();
gen_rator=new(cfg);
driver_obj =new();
score_board =new();
receiver_obj_0
receiver_obj_1
receiver_obj_2
receiver_obj_3
=new(cfg,rec_0);
=new(cfg,rec_1);
=new(cfg,rec_2);
=new(cfg,rec_3);
Constructs
no_of_errors =0;
// Reset the dut
@(posedgeintf.clk);
RVM Switch TB
intf.reset =1;
RVM Ethernet sample @(posedgeintf.clk);
intf.reset =0;
Switch TB
Specman E
Interview Questions
delay(100);
//// Configure the dut.
cfg.drive_add();
delay(100);
//// Generate the packets
gen_rator.gen_pkts();
fork
// Forking error counter task
error_counter();
// Fork task to Drive the packets
driver_obj.gen_and_drive();
//// Fork task to collect packets
http://testbench.in/OS_11_ENV.html[9/26/2012 2:51:07 PM]
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
input is what keeps
with time!
receiver_obj_0.collect_packets();
joinnone
delay(10000);
printf("\n ***** END OF SIMULATION **** \n");
}
//Check for the error count
taskfinal(){
if(no_of_errors >0)
printf("\n************TEST FAILED with %d ERRORS************\n",no_of_errors);
else
printf("\n************TEST PASSED************\n");
}
taskerror_counter(){
while(1){
sync(ALL,err);
@(posedgeintf.clk);
no_of_errors++;
}
}
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http://testbench.in/OS_11_ENV.html[9/26/2012 2:51:07 PM]
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Index
Introduction
Rtl
Top
Interface
Program Block
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
TUTORIALS
INTRODUCTION
SystemVerilog
A model of a system or component at an abstraction level higher than RTL in which

the interface is defined in terms of transactions, rather than signals is called tranction
level modelling. By abstracting out the details transaction level models run faster and
can be written more easily. Transaction-level modeling is a high-level approach to
model digital systems where details of communication among modules are separated
from the details of the implementation of functional units or of the communication
architecture. Communication mechanisms such as busses or FIFOs are modeled as
channels, and are presented to modules using SystemVerilog interfaces. At the
transaction level, the emphasis is more on the functionality of the data transfers what data are transferred to and from what locations - and less on their actual
implementation, that is, on the actual protocol used for data transfer. This approach
makes it easier for reusability. Usually these tranctions are implimented using Report a Bug or Comment
subroutiens. Systemverilog supports tranctional level modelling. The following on This section - Your
input is what keeps
example uses TLM in SystemVerilog.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
with time!
Dut Specification:
This DUT is a simple switch, which can drive the incoming packet to destination ports
The dut contain one input interface from which the packet enters the dut. It has four
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Packet format:
Packet header:
http://testbench.in/RV_01_INTRODUCTION.html[9/26/2012 2:51:15 PM]
header and data.
Configuration:
Memory Interface:
Input Interface:
to become low after sending last byte of the packet. 2 clocks gap should be
maintained between packets.
Output Interface:
data signal.
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TUTORIALS
RTL
SystemVerilog
CODE:rtl.v
module fifo (clk,
reset,
Constructs
write_enb,
read,
Interface
data_in,
OOPS
data_out,
empty,
Randomization
full);
Functional Coverage
input clk;
Assertion
input reset;
inputwrite_enb;
DPI
inputread;
UVM Tutorial
input[7:0]data_in;
VMM Tutorial
outputempty;
OVM Tutorial
outputfull;
wire clk;
Easy Labs : SV
wire write_enb;
Easy Labs : UVM
wire read;
wire [7:0]data_in;
Easy Labs : OVM
reg[7:0]data_out;
Easy Labs : VMM
wire empty;
wire full;
AVM Switch TB
reg[7:0]ram[0:25];
VMM Ethernet sample regtmp_empty;
regtmp_full;
integerwrite_ptr;
integerread_ptr;
Verilog
Verification
begin
Verilog Switch TB
data_out=8'b0000_0000;
tmp_empty =1'b1;
Basic Constructs
tmp_full=1'b0;
write_ptr =0;
read_ptr=0;
OpenVera
end
Verification
Constructs
assign empty =tmp_empty;

assign full=tmp_full;
RVM Switch TB
always @(posedgeclk)begin
RVM Ethernet sample if((write_enb ==1'b1)&&(tmp_full ==1'b0))begin
tmp_empty <=1'b0;
Specman E
tmp_full <=1'b1;
Interview Questions
end
end
Switch TB

tmp_full <=1'b0;
tmp_empty <=1'b1;
end
http://testbench.in/RV_02_RTL.html[9/26/2012 2:51:23 PM]
Index
Introduction
Rtl
Top
Interface
Program Block
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
input is what keeps
with time!
end
end
endmodule //fifo
module port_fsm (clk,
reset,
write_enb,
ffee,
hold,
data_status,
data_in,
data_out,
mem0,
mem1,
mem2,
mem3,
addr);
inputclk;
inputreset;
input [7:0] mem0;
input [7:0] mem1;
input [7:0] mem2;
input [7:0] mem3;
inputffee;
inputhold;
inputdata_status;
input[7:0]data_in;
output[7:0] addr;
reg[7:0]data_out;
reg[7:0]addr;
regfsm_write_enb;
reg[3:0]state_r;
reg[3:0]state;
reg[7:0]parity;
parameter ADDR_WAIT =4'b0000;
parameter DATA_LOAD =4'b0001;
parameter PARITY_LOAD=4'b0010;
parameter HOLD_STATE=4'b0011;
parameter BUSY_STATE=4'b0100;
begin
error=1'b0;
data_out =8'b0000_0000;
addr =8'b00000000;
write_enb_r=3'b000;
fsm_write_enb=1'b0;
state_r=4'b0000;
state=4'b0000;
parity =8'b0000_0000;
sus_data_in=1'b0;
end
assign busy =sus_data_in;
always @(data_status)begin:addr_mux
case(data_in)
mem0 :begin
end
mem1 :begin
end
mem2 :begin
end
mem3 :begin
end
endcase
//$display("
data_inii
%d
,mem0
end//if
end//addr_mux;
always @(posedgeclk)begin:fsm_state
state_r <=state;
end//fsm_state;
%d
,mem1
always @(state_r ordata_status orffee orhold ordata_in)

begin:fsm_core
state=state_r; //Default state assignment
case(state_r)
ADDR_WAIT: begin
((mem0
==data_in)||(mem1
==data_in)||(mem2 ==data_in)))begin
state=DATA_LOAD;
end
elsebegin
state=BUSY_STATE;
end//if
end//if;
sus_data_in =!ffee;
((mem0
==data_in)||(mem1
==data_in)||(mem2 ==data_in))&&
(ffee ==1'b1))begin
addr =data_in;
data_out=data_in;
end
elsebegin
end//if
PARITY_LOAD:begin
state=ADDR_WAIT;
data_out =data_in;
DATA_LOAD: begin
(hold ==1'b0))begin
state=DATA_LOAD;
end
(hold ==1'b0))begin
state=PARITY_LOAD;
end
elsebegin
state=HOLD_STATE;
%d
,mem2
%d
==data_in)||(mem3
==data_in)||(mem3
end//if
sus_data_in =1'b0;
(hold ==1'b0))begin
data_out =data_in;
end
(hold ==1'b0))begin
data_out =data_in;
end
elsebegin
end//if
HOLD_STATE:begin
state=HOLD_STATE;
end
state=PARITY_LOAD;
end
elsebegin
state=DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out =data_in;
end//if
BUSY_STATE:begin
state=BUSY_STATE;
end
elsebegin
state=DATA_LOAD;
end//if
sus_data_in =1'b1;
end
elsebegin
data_out=data_in;
end//if
endcase
end//fsm_core
assign
assign
assign
assign
endmodule //port_fsm
module switch (clk,
reset,
data_status,
data,
port0,
port1,
port2,
port3,
ready_0,
ready_1,
ready_2,
ready_3,
read_0,
read_1,
read_2,
read_3,
mem_en,
mem_rd_wr,
mem_add,
mem_data);
inputclk;
inputreset;
inputdata_status;
input[7:0]data;
inputmem_en;
inputmem_rd_wr;
input[1:0]mem_add;
input[7:0]mem_data;
output [7:0]port0;
output [7:0]port1;
output [7:0]port2;
output [7:0]port3;
output ready_0;
output ready_1;
output ready_2;
output ready_3;
input read_0;
input read_1;
input read_2;
input read_3;
wire ll0;
wire ll1;
wire ll2;
wire ll3;
wire empty_0;
wire empty_1;
wire empty_2;
wire empty_3;
wire ffee;
wire ffee0;
wire ffee1;
wire ffee2;
wire ffee3;
wire ld0;
wire ld1;
wire ld2;
wire ld3;
wire hold;
wire [7:0]addr;
reg[7:0]mem[3:0];
wire reset;
.reset (reset),
.read(read_0),
.empty (empty_0),
.full(ll0));
.reset (reset),
.read(read_1),
.empty (empty_1),
.full(ll1));
.reset (reset),
.read(read_2),
.empty (empty_2),
.full(ll2));
.reset (reset),
.read(read_3),
.empty (empty_3),
.full(ll3));

.reset (reset),
.ffee(ffee),
.hold(hold),
.data_in (data),
.mem0(mem[0]),
.mem1(mem[1]),
.mem2(mem[2]),
.mem3(mem[3]),
.addr(addr));
assign port0 =data_out_0; //make note assignment only for

assign
assign
assign
assign
ffee0 =(empty_0
ffee1 =(empty_1
ffee2 =(empty_2
ffee3 =(empty_3
|(addr
|(addr
|(addr
|(addr
!=mem[0]));
!=mem[1]));
!=mem[2]));
!=mem[3]));
assign ffee=ffee0 &ffee1 &ffee2 &ffee3;

assign
assign
assign
assign
ld0
ld1
ld2
ld3
=(ll0
=(ll1
=(ll2
=(ll3
&(addr
&(addr
&(addr
&(addr
==mem[0]));
==mem[1]));
==mem[2]));
==mem[3]));
assign hold =ld0 |ld1 |ld2 |ld3;

always@(posedgeclk)
begin
if(mem_en)
if(mem_rd_wr)
begin
end
end
endmodule //router
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Index
Introduction
Rtl
Top level module containts the design and testbench instance. Top module also Top
Interface
contains clock generator. There is no need to instantiate the top module.
Program Block
Testbench and dut instances are connected using wires.
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
TOP
Assertion

input is what keeps
with time!
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
CODE: top.v
module top();
//Declare clock signal
regclock;
//Signals for Assertion and to view the class proprties in Waveform viewer
wiredata_status;
wire[7:0]data_in;
wire [7:0]data_out[0:3];
wire[3:0]ready;
wire[3:0]read;
wire [7:0]mem_data;
wire [1:0]mem_add;
wirereset;
wiremem_en;
wiremem_rd_wr;
wireSystemClock ;
assignSystemClock =clock;
main tb(.SystemClock(SystemClock),
.\intf.clk(clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
http://testbench.in/RV_03_TOP.html[9/26/2012 2:51:32 PM]
.\intf.mem_data(mem_data),
.\intf.mem_add(mem_add),
.\intf.reset(reset),
.\intf.mem_en(mem_en),
.\intf.mem_rd_wr(mem_rd_wr)
);
switch switch1(.clk(clock),
.reset(reset),
.data_status (data_status),
.data (data_in),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2(read[2]),
.read_3(read[3]),
.mem_en (mem_en),
.mem_rd_wr(mem_rd_wr),
.mem_add(mem_add),
.mem_data (mem_data));
initial begin
clock =0;
forever begin
#5clock =!clock;
end
end
endmodule //top
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http://testbench.in/RV_03_TOP.html[9/26/2012 2:51:32 PM]
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TUTORIALS
INTERFACE
SystemVerilog
Verification
Declare an inyerface. Declare ports for reciever block. Bind the four reciver port.
Constructs
CODE:interface
interfaceintf {
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
input clkCLOCK;
outputdata_status PHOLD #1;
output[7:0]data_in PHOLD #1;

OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
output[7:0] mem_data PHOLD #1;
output [1:0] mem_add PHOLD #1;
AVM Switch TB
outputreset PHOLD #1;
VMM Ethernet sample outputmem_en PHOLD #1;
outputmem_rd_wr PHOLD #1;
}
Verilog
portrec_ports {
Verification
data_out;
Verilog Switch TB
ready;
read;
Basic Constructs
}
VMM Tutorial
OpenVera
Constructs
Switch TB
RVM Switch TB
ready intf.ready_0;
read intf.read_0;
}
RVM Ethernet sample bindrec_ports rec_1 {
Specman E
Interview Questions
ready intf.ready_1;
read intf.read_1;
}
ready intf.ready_2;
read intf.read_2;
}
ready intf.ready_3;
read intf.read_3;
http://testbench.in/RV_04_INTERFACE.html[9/26/2012 2:51:40 PM]
Index
Introduction
Rtl
Top
Interface
Program Block
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Index
Introduction
Rtl
Testbench Program
Top
Program block contains the instance of testbench environment class. Testcases goes Interface
Program Block
hear. Call run() method of env instance.
Environment
Packet
CODE:test
Configuration
programmain{
Driver
Reciever
Environment env;
Scoreboard
env =new();
env.run_t();
PROGRAM BLOCK
printf(" END OF PROGRAM BLOCK \n");

}
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/RV_05_PROGRAM_BLOCK.html[9/26/2012 2:51:48 PM]

input is what keeps
with time!
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TUTORIALS
SystemVerilog
Verification
Constructs
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Randomization
Functional Coverage
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DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Index
Introduction
Rtl
Enviroment class contains instancess of all the verification components. Environment Top
Interface
class is extension on rvm_env class.
The testbench simulation needs some systamatic flow like reset,initilize etc. rvm_env Program Block
Environment
base class has methods to support this simulation flow.
The rvm_env class divides a simulation into the following steps, with corresponding Packet
Configuration
methods:
Driver
-- gen_cfg() : Randomize test configuration descriptor
Reciever
-- build() : Allocate and connect test environment components
Scoreboard
-- reset_dut_t() : Reset the DUT
-- cfg_dut_t() : Download test configuration into the DUT
-- start_t() : Start components
-- wait_for_end_t() : End of test detection
input is what keeps
-- stop_t() : Stop data generators and wait for DUT to drain
-- cleanup_t() : Check recorded statistics and sweep for lost data
with time!
-- report() : Print final report
ENVIRONMENT
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
CODE:env.vr
//A top-level source file shall include all ancillary source files
#include <rvm_std_lib.vrh>
#include "Configuration.vr"
#include "packet.vr"
#include "ports.vr"
ìfndefENV_CLASS
`defineENV_CLASS
Verification
//A channel class shall be declared for any class derived from the bu_data class
Verilog Switch TB
rvm_channel(packet)
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
//An instance of a rvm_channel object shall be used to pass transactions between two
transactors
rvm_atomic_gen(packet,"packet")
#include "drvr.vr"
#include "rcvr.vr"
#include "score_board.vr"
classEnvironment extendsrvm_env {
//All simulation log output shall be done through the message service.
rvm_loglog;
Configuration cfg;
packetpkt;
packet_atomic_gen gen;
packet_channelgen2drv_chan;
packet_channelrcv2sb_chan;
packet_channeldrv2sb_chan;
drvr_xtordrvr;
rcvr_xtor rcvr_0;
http://testbench.in/RV_06_ENVIRONMENT.html[9/26/2012 2:52:23 PM]
rcvr_xtor rcvr_1;
rcvr_xtor rcvr_2;
rcvr_xtor rcvr_3;
scoreboard sb;
tasknew();
virtualtaskgen_cfg();
virtualtaskbuild();
virtualtaskreset_dut_t();
virtualtaskcfg_dut_t();
virtualtaskstart_t();
virtualtaskwait_for_end_t();
virtualtaskstop_t();
virtualtaskcleanup_t();
}
taskEnvironment::new(){
super.new("Environment");
this.log =new("ENV_LOG","0");
this.cfg =new();
rvm_note(this.log," ENV CREATED \n");
}
//The return value of the randomize() method shall be checked
//and an error be reported if it is FALSE
taskEnvironment::gen_cfg(){
super.gen_cfg();
rvm_note(this.log," Starting... Gen_cfg \n");
if(!cfg.randomize())
rvm_fatal(this.log,"Configuration Randomization Failed!\n");
cfg.display();
}
taskEnvironment::build(){
super.build();
rvm_note(this.log," Starting... build \n");
pkt =new();
pkt.do_cfg(cfg);
gen =new("Generator","0");
gen2drv_chan =new("gen2drv","0");
rcv2sb_chan =new("rcv2sb","chan",10);
drv2sb_chan =new("drv2sb","chan",10);
gen.out_chan =this.gen2drv_chan;
drvr =new("driver",0,gen2drv_chan,drv2sb_chan);
rcvr_0 =new("reciver_0",0,rec_0,rcv2sb_chan);
sb =new(rcv2sb_chan,drv2sb_chan);
}
//Blocking methods shall have a name that ends with the "_t" suffix.
taskEnvironment::reset_dut_t(){
super.reset_dut_t();
rvm_note(this.log," Starting... reset_dut \n");
@(posedgeintf.clk);
intf.data_status<=0;
intf.data_in<=0;
intf.read_0 <=0;
intf.read_1 <=0;
intf.read_2 <=0;
intf.read_3 <=0;
intf.mem_data <=0;
intf.mem_add<=0;
intf.reset<=0;
intf.mem_en <=0;
intf.mem_rd_wr<=0;
@(posedgeintf.clk);
intf.reset <=1;
@(posedgeintf.clk);
intf.reset <=0;
@(posedgeintf.clk);
@(posedgeintf.clk);
rvm_note(this.log," Ending...reset_dut \n");
}
//The generated value of the configuration descriptor shall be
//downloaded into the DUT in the rvm_env::cfg_dut_t() method
taskEnvironment::cfg_dut_t(){
integeri;
super.cfg_dut_t();
rvm_note(this.log," Starting... cfg_dut \n");
for(i =0;i<4;i++)
{
intf.mem_en<=1;
@(posedgeintf.clk);
intf.mem_rd_wr <=1;
@(posedgeintf.clk);
intf.mem_add <=i;
intf.mem_data<=cfg.da_port[i];
}
@(posedgeintf.clk);
intf.mem_en<=0;
intf.mem_rd_wr <=0;
intf.mem_add <=0;
intf.mem_data<=0;
rvm_note(this.log," Ending...cfg_dut \n");
}
//The rvm_env::start_t() method shall start all transactors and generators
//The rvm_env::start_t() method should not block the execution thread
taskEnvironment::start_t(){
super.start_t();
rvm_note(this.log," Starting... start \n");
gen.start_xactor();
rcvr_0.start_xactor();
sb.start_xactor();
}
taskEnvironment::wait_for_end_t(){
super.wait_for_end_t();
rvm_note(this.log," Starting... wait_for_end \n");
fork//watchdog
{
void=gen.notify.wait_for_t(gen.DONE);
rvm_note(this.log," DONE:: packet_atomic_gen \n");
repeat(100)@(posedgeintf.clk);
rvm_error(this.log," Watchdog timeout occured \n");
}
{
while(sb.no_rcv_pkt !=20)@(posedgeintf.clk);
rvm_note(this.log," DONE:: total number of sent pkts are receved \n");
}
joinany
rvm_note(this.log," Ending ... wait_for_end \n");
}
taskEnvironment::stop_t(){
super.stop_t();
rvm_note(this.log," Starting... stop \n");
this.drvr.stop_xactor();
this.rcvr_0.stop_xactor();
this.sb.stop_xactor();
rvm_note(this.log," Ending ... stop \n");
}
taskEnvironment::cleanup_t(){
super.cleanup_t();
rvm_note(this.log," Starting... cleanup \n");
}
taskEnvironment::report(){
rvm_note(this.log," Starting... report \n");
super.report();
rvm_note(this.log," Ending...report \n");
}
èndif
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Index
Introduction
Rtl
In Vera terminology packets are called tranctions. Tranctions contains the physical Top
data that are to be sent to dut. It also contains some more properties which help in Interface
building tranctions. Tranctions are built by extending rvm_data. rvm_data has set of Program Block
Environment
standered methods like copy(),compare(),byte_pack(),byte_unp
Packet
ack() etc.
Configuration
Driver
CODE:packet.vr
Reciever
#ifndef PKT_CLASS
Scoreboard
#define PKT_CLASS
PACKET
DPI
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// Data units shall be modeled as objects

classpacket extendsrvm_data {
enumpayload_size_t =SMALL_P,MEDIUM_P,LARGE_P;
enumpacket_kind_t=GOOD_P,BAD_P;
randpacket_kind_t packet_kind ;
randpayload_size_t payload_size;//Control field for the payload size
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
staticrvm_log log =new("packet","class");

stringmsg;
randbit[7:0]len;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[*];//Payload using Dynamic array,size is generated on the fly
randbit[7:0]parity;
staticbit[7:0]mem [4];
==mem[2]);}
Constructs

(payload_size ==SMALL_P)=>len in{5:6};
RVM Switch TB
(payload_size ==MEDIUM_P)=>len in{7:8};
RVM Ethernet sample (payload_size ==LARGE_P)=>len in{9:10};}
Switch TB
Specman E
Interview Questions
// Constrain length of data== len

constraintdata_size {data.size()==len;}
constraintlen_siz {solve len beforedata.size();}
portrandomize
(packet_kind ==GOOD_P)=>parity ==0;
(packet_kind ==BAD_P )=>parity !=0;}
http://testbench.in/RV_07_PACKET.html[9/26/2012 2:52:31 PM]

input is what keeps
with time!
//All data object methods should be virtual

//All data object methods shall be nonblocking
tasknew();
taskdo_cfg(Configuration cfg);
virtualfunctionstringpsdisplay(stringprefix );
virtualfunctionrvm_data copy(rvm_data to);
virtualfunctionintegerbyte_unpack(bit[7:0]bytes[*],integeroffset
=0,integerkind =-1);
virtualfunctionbit[7:0]parity_cal();
virtualfunctionbitcompare(rvm_data to,varstringdiff,integerkind =-1);
virtualfunctionintegerbyte_pack(varbit[7:0]bytes[*],
integeroffset=0,
integer kind=-1);
taskpost_randomize();
}
taskpacket::new(){
}
taskpacket::do_cfg(Configuration cfg){
msg =psprintf(" packet new %x %x %x %x",mem[0],mem[1],mem[2],mem[3]);
rvm_note(this.log,msg);
}
functionstringpacket::psdisplay(stringprefix =""){
integeri;
sprintf(psdisplay,"%s
packet
#%0d.%0d.%0d\n",prefix,this.stream_id,this.scenario_id,this.object_id);
sprintf(psdisplay,"%s%s da:0x%hsa:0x%hlen:0x%h
\n",psdisplay,prefix,this.da,this.sa,this.len);
sprintf(psdisplay,"%s%s data:",psdisplay,prefix);
for(i
=0;i <this.len
-1;i++)sprintf(psdisplay,"%s
data[%0d]
0x%h",psdisplay,i,data[i]);
}
functionrvm_data packet::copy(rvm_data to =null){

packet cpy;

if(to ==null)
cpy =new;
else

if(!cast_assign(cpy,to,CHECK))
{
rvm_fatal(this.log,"Attempting to copy to a non packet instance");
copy =null;
return;
}
cpy.da =this.da;
cpy.sa =this.sa;
cpy.len =this.len;
cpy.data =new[this.len];
foreach(cpy.data,i)
copy =cpy;
}

functionintegerpacket::byte_unpack(bit[7:0]bytes[*],integeroffset
,integerkind){
sprintf(msg," bytes size %d",bytes.size());
da =bytes[1];
sa =bytes[2];
len =bytes[3];
sprintf(msg,"packet
#%0d.%0d.%0d\n",this.stream_id,this.scenario_id,this.object_id);
sprintf(msg,"da:0x%hsa:0x%hlen:0x%h \n",this.da,this.sa,this.len);
data =new[len -4];
parity =bytes[bytes.size()-1];
foreach(data,i)data[i]=bytes[i+4];
}
functionbit[7:0]packet::parity_cal(){
integeri;
bit[7:0]result ;
{
}
parity_cal =result;
}

taskpacket::post_randomize(){
sprintf(msg," %x %x %x %x",mem[0],mem[1],mem[2],mem[3]);
}
functionbitpacket::compare(rvm_data to,varstringdiff,integer kind){
packet cmp;
compare =1;// Assume success by default.

if(!cast_assign(cmp,to,CHECK))
{rvm_fatal(this.log,"Attempting to compare to a non packet instance");
compare =0;
return;
}

{
diff =psprintf("Different DA values: %b != %b",this.da,cmp.da);
compare =0;
return;
}
{
diff =psprintf("Different SA values: %b != %b",this.sa,cmp.sa);
compare =0;
return;
}
if(this.len !=cmp.len)
{
diff =psprintf("Different LEN values: %b != %b",this.len,cmp.len);
compare =0;
return;
}
foreach(data,i)
{
diff =psprintf("Different
data[%0d]
values:
0x%h
compare =0;
return;
}
if(this.parity !=cmp.parity)
{
diff =psprintf("Different PARITY values: %b != %b",this.parity,cmp.parity);
compare =0;
return;
}
}
!=
functionintegerpacket::byte_pack(varbit[7:0]bytes[*],integeroffset ,integer
kind){
byte_pack =0;
bytes =new[this.len +4];
bytes[0]=this.da;
bytes[1]=this.sa;
bytes[2]=this.len;
foreach(data,i)
bytes[3+i]=data[i];
bytes[this.len +3]=parity;
byte_pack =this.len +4;
}
#endif
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Index
Introduction
Rtl
Configuration class is a transctor. It is extention of rvm_xactor. This class genarates Top
Interface
addresses to configure the dut 4 output ports.
Program Block
Environment
CODE:CFG.vr
Packet
#ifndef PKT_CLASS
Configuration
#define PKT_CLASS
Driver
Reciever
Scoreboard
CONFIGURATION
// Data units shall be modeled as objects

classpacket extendsrvm_data {
enumpayload_size_t =SMALL_P,MEDIUM_P,LARGE_P;
enumpacket_kind_t=GOOD_P,BAD_P;
randpacket_kind_t packet_kind ;
randpayload_size_t payload_size;//Control field for the payload size
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
staticrvm_log log =new("packet","class");

stringmsg;
randbit[7:0]len;
randbit[7:0]da;
VMM Ethernet sample randbit[7:0]sa;
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
randbit[7:0]data[*];//Payload using Dynamic array,size is generated on the fly

randbit[7:0]parity;
staticbit[7:0]mem [4];
==mem[2]);}
Switch TB

(payload_size ==SMALL_P)=>len in{5:6};
(payload_size ==MEDIUM_P)=>len in{7:8};
(payload_size ==LARGE_P)=>len in{9:10};}
RVM Switch TB
// Constrain length of data== len
OpenVera
Constructs
RVM Ethernet sample constraintdata_size {data.size()==len;}
constraintlen_siz {solve len beforedata.size();}

Specman E
Interview Questions

portrandomize
(packet_kind ==GOOD_P)=>parity ==0;
(packet_kind ==BAD_P )=>parity !=0;}
//All data object methods should be virtual

//All data object methods shall be nonblocking
http://testbench.in/RV_08_CONFIGURATION.html[9/26/2012 2:52:42 PM]

input is what keeps
with time!
tasknew();
taskdo_cfg(Configuration cfg);
virtualfunctionstringpsdisplay(stringprefix );
virtualfunctionrvm_data copy(rvm_data to);
virtualfunctionintegerbyte_unpack(bit[7:0]bytes[*],integeroffset
=0,integerkind =-1);
virtualfunctionbit[7:0]parity_cal();
virtualfunctionbitcompare(rvm_data to,varstringdiff,integerkind =-1);
virtualfunctionintegerbyte_pack(varbit[7:0]bytes[*],
integeroffset=0,
integer kind=-1);
taskpost_randomize();
}
taskpacket::new(){
}
taskpacket::do_cfg(Configuration cfg){
msg =psprintf(" packet new %x %x %x %x",mem[0],mem[1],mem[2],mem[3]);
}
functionstringpacket::psdisplay(stringprefix =""){
integeri;
sprintf(psdisplay,"%s
packet
#%0d.%0d.%0d\n",prefix,this.stream_id,this.scenario_id,this.object_id);
sprintf(psdisplay,"%s%s da:0x%hsa:0x%hlen:0x%h
\n",psdisplay,prefix,this.da,this.sa,this.len);
sprintf(psdisplay,"%s%s data:",psdisplay,prefix);
for(i
=0;i <this.len
-1;i++)sprintf(psdisplay,"%s
data[%0d]
0x%h",psdisplay,i,data[i]);
}
functionrvm_data packet::copy(rvm_data to =null){

packet cpy;

if(to ==null)
cpy =new;
else

if(!cast_assign(cpy,to,CHECK))
{
rvm_fatal(this.log,"Attempting to copy to a non packet instance");
copy =null;
return;
}
cpy.da =this.da;
cpy.sa =this.sa;
cpy.len =this.len;
cpy.data =new[this.len];
foreach(cpy.data,i)
copy =cpy;
}

functionintegerpacket::byte_unpack(bit[7:0]bytes[*],integeroffset
,integerkind){
sprintf(msg," bytes size %d",bytes.size());
da =bytes[1];
sa =bytes[2];
len =bytes[3];
sprintf(msg,"packet
#%0d.%0d.%0d\n",this.stream_id,this.scenario_id,this.object_id);
sprintf(msg,"da:0x%hsa:0x%hlen:0x%h \n",this.da,this.sa,this.len);
data =new[len -4];
parity =bytes[bytes.size()-1];
foreach(data,i)data[i]=bytes[i+4];
}
functionbit[7:0]packet::parity_cal(){
integeri;
bit[7:0]result ;
{
}
parity_cal =result;
}

taskpacket::post_randomize(){
sprintf(msg," %x %x %x %x",mem[0],mem[1],mem[2],mem[3]);
}
functionbitpacket::compare(rvm_data to,varstringdiff,integer kind){
packet cmp;
compare =1;// Assume success by default.

if(!cast_assign(cmp,to,CHECK))
{rvm_fatal(this.log,"Attempting to compare to a non packet instance");
compare =0;
return;
}

{
diff =psprintf("Different DA values: %b != %b",this.da,cmp.da);
compare =0;
return;
}
{
diff =psprintf("Different SA values: %b != %b",this.sa,cmp.sa);
compare =0;
return;
}
if(this.len !=cmp.len)
{
diff =psprintf("Different LEN values: %b != %b",this.len,cmp.len);
compare =0;
return;
}
foreach(data,i)
{
diff =psprintf("Different
data[%0d]
values:
0x%h
compare =0;
return;
}
if(this.parity !=cmp.parity)
{
diff =psprintf("Different PARITY values: %b != %b",this.parity,cmp.parity);
compare =0;
return;
}
}
!=
functionintegerpacket::byte_pack(varbit[7:0]bytes[*],integeroffset ,integer
kind){
byte_pack =0;
bytes =new[this.len +4];
bytes[0]=this.da;
bytes[1]=this.sa;
bytes[2]=this.len;
foreach(data,i)
bytes[3+i]=data[i];
bytes[this.len +3]=parity;
byte_pack =this.len +4;
}
#endif
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Index
Introduction
Rtl
Driver is a tranctor. It is extension of rvm_xactor. Get the packets from gen2drv_chan Top
chennel and drive them on to dut interface. Put the packets in to drv2sb_chan Interface
Program Block
channel.
Environment
Packet
CODE:driver.vr
Configuration
#ifndef DRVR_CLASS
Driver
#define DRVR_CLASS
Reciever
//Transactors shall be implemented in classes derived from the rvm_xactor
Scoreboard
classdrvr_xtor extendsrvm_xactor{
packet_channel gen2drv_chan;
packet_channel drv2sb_chan;
input is what keeps
packet pkt,drv_pkt;
string msg;
DRIVER
with time!
OVM Tutorial
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AVM Switch TB
tasknew(stringinst ="class",
integerstream_id =-1,
packet_channel gen2drv_chan =null,
packet_channel drv2sb_chan =null);
virtualtaskmain_t();
virtualtaskdrive(packet pkt);
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
taskdrvr_xtor::new(stringinst,integerstream_id ,
packet_channel gen2drv_chan ,
packet_channel drv2sb_chan ){
this.gen2drv_chan =new("gen2drv_channel","chan",10);
else
this.drv2sb_chan =new("drv2sb_channel","chan",10);
else
rvm_note(log,"Driver created \n");
}
//All threads shall be started in the extension of the rvm_xactor::main_t() method
//Extensions of the rvm_xactor::main_t() method shall fork a call to super.main_t()
taskdrvr_xtor::main_t(){
super.main_t();
rvm_note(this.log," STARTED main task ");
while(1){
//wait_if_stopped_or_empty(this.gen2drv_chan);
pkt =this.gen2drv_chan.get_t();
sprintf(this.msg,"pkt da %x pkt sa %x pkt len %d \n",pkt.da,pkt.sa,pkt.len);
http://testbench.in/RV_09_DRIVER.html[9/26/2012 2:52:51 PM]
if(!cast_assign(drv_pkt,pkt.copy()))
rvm_fatal(this.log,"Attempting to copy to a non Packet instance");
drive(drv_pkt);
@(posedgeintf.clk);
this.drv2sb_chan.sneak(drv_pkt);
}
}
taskdrvr_xtor::drive(packet pkt){
bit[7:0]pack_pkt[*];
integerpkt_len,i;
pkt_len =pkt.byte_pack(pack_pkt,0,0);
sprintf(this.msg,"Packed packet length %d \n",pkt_len);
rvm_note(this.log,this.msg);
@(posedgeintf.clk);
for(i=0;i<pkt_len -1;i++)
{
@(posedgeintf.clk);
intf.data_in <=pack_pkt[i];
}
@(posedgeintf.clk);
intf.data_in <=0;
@(posedgeintf.clk);
}
#endif
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http://testbench.in/RV_09_DRIVER.html[9/26/2012 2:52:51 PM]
Search
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Index
Introduction
Rtl
Reciever is a tranctor. Start the collection of packet from dut in the main() task and Top
Interface
send them to score_board through rcv2sb_chan channel.
Program Block
Environment
CODE:reciever.vr
Packet
#include "ports.vr"
Configuration
#ifndef RCVR_CLASS
Driver
#define RCVR_CLASS
Reciever
Scoreboard
classrcvr_xtor extendsrvm_xactor{
packet_channel rcv2sb_chan;
packet pkt,rcv_pkt;
rec_portsport_;
input is what keeps
string msg;
staticbit[7:0] mem[4];
with time!
tasknew(stringinst ="class",integerstream_id =-1,rec_ports port_,
packet_channel rcv2sb_chan =null);
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RECIEVER
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Easy Labs : VMM
taskrcvr_xtor::new(stringinst ,integerstream_id ,rec_ports port_,packet_channel

rcv2sb_chan ){
super.new("reciver",inst,stream_id);
VMM Ethernet sample this.port_ =port_;
if(rcv2sb_chan ==null)
this.rcv2sb_chan =new("rcv2sb_channel","channel",10);
else
Verilog
this.rcv2sb_chan =rcv2sb_chan;
Verification
rvm_note(this.log,"Receiver created \n");
Verilog Switch TB
pkt =new();
}
Basic Constructs
AVM Switch TB
taskrcvr_xtor::main_t(){
bit[7:0]received_bytes[*];
Constructs
super.main_t();
Switch TB
while(1){
RVM Switch TB
@(posedgeport_.$ready);
RVM Ethernet sample while(port_.$ready){
port_.$read<=1;
@(posedgeintf.clk);
received_bytes =new[received_bytes.size()+1](received_bytes);
Specman E
received_bytes[received_bytes.size()-1]=port_.$data_out;
}
Interview Questions
port_.$read<=0;
OpenVera
void=pkt.byte_unpack(received_bytes);
received_bytes.delete();
rcv_pkt =newpkt;
rcv2sb_chan.put_t(rcv_pkt);
}
}
#endif
http://testbench.in/RV_10_RECIEVER.html[9/26/2012 2:52:59 PM]
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Index
Introduction
Rtl
When the packet comes from reciever, the scoreboard gets the expected packet from Top
Interface
drv2sb_chan channel and compare them.
Program Block
Environment
CODE:scoreboard.vr
Packet
ìfndefSB_CLASS
Configuration
`defineSB_CLASS
Driver
Reciever
classscoreboard extendsrvm_xactor{
Scoreboard
packet exp_pkt;
packet rcv_pkt;
integerno_drv_pkt;
integerno_rcv_pkt;
input is what keeps
stringmsg;
packet_channel rcv2sb_chan;
with time!
packet_channel drv2sb_chan;
SCOREBOARD
tasknew(packet_channel rcv2sb_chan =null,packet_channel drv2sb_chan =null);

}
Easy Labs : VMM
taskscoreboard::new(packet_channel rcv2sb_chan ,packet_channel drv2sb_chan ){

super.new("Scoreboard","sb");
VMM Ethernet sample this.rcv2sb_chan =rcv2sb_chan;
no_drv_pkt =0;
no_rcv_pkt =0;
Verilog
rvm_note(log,"Scoreboard created");
Verification
}
AVM Switch TB
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
taskscoreboard::main_t(){
super.main_t();
while(1){
rcv_pkt =rcv2sb_chan.get_t();
this.no_rcv_pkt++;
exp_pkt =drv2sb_chan.get_t();
this.no_drv_pkt++;
if(rcv_pkt.compare(exp_pkt,msg,0))
else
rvm_error(this.log,msg);
}
}
èndif
http://testbench.in/RV_11_SCOREBOARD.html[9/26/2012 2:53:06 PM]
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http://testbench.in/RV_11_SCOREBOARD.html[9/26/2012 2:53:06 PM]
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About the author:
UVM/OVM Killing Sequences on Sequencer Abruptly
Vishnu Prasanth
is ovm/uvm expert. He is
Sometimes you may need to drive input until you see come condition or some timer currently working with
expires. Once you meet that condition, you need to stop generating stimulus. The Vitesse, Hyderabad,
India.
code for this scenario look like below
//Test
begin
fork
begin
wait(rtl_linkup == 1);
end
begin
forever
idles_transmit.start(Sequencer);
end
join_any
disable fork;
end
Easy Labs : OVM

Easy Labs : VMM
In the above code we are driving idles until rtl_linkup condition is observed. But here
there is a problem, As we are trying kill idles_transmit sequence abruptly when
condition is met, this may cause the sequencer to be in intermittent state. This will
VMM Ethernet sample cause the problem on the next sequences which trigger on the same sequencer. As
sequencer is in intermittent state it may not get grant and will wait for for grant
forever. To avoid this problem we need to reset the sequencer after killing threads.
The code look like below.
Verilog
AVM Switch TB
Verification
Verilog Switch TB
//Test
begin
fork
begin
OpenVera
end
Constructs
begin
forever
Switch TB
RVM Switch TB
end
RVM Ethernet sample join_any
disable fork;
Sequencer.stop_sequence();
end
Basic Constructs
Specman E
Interview Questions
In the above code the stop_sequences call will reset the sequencer variables and
won't cause any problem for the next sequences which are triggered on same
sequencer. Here also we have another problem with the sequence thread which is
killed with disable fork. Sometimes by the time thread is killed request might have
been sent to driver. if thread is killed and stop_sequence is called before receiving
the item_done, item_done will cause fatal error as request fifo is empty. So we need
to kill thread and call of stop_sequence only after receiving item_done from driver.
The code will look like below.
http://testbench.in/killing_sequences.html[9/26/2012 2:53:15 PM]
Connect to Vishnu @

input is what keeps
with time!
WWW.TESTBENCH.IN
//Sequence .
class idles_transmit extends ovm_sequence #(REQ= packet);
bit received_item_done;
task body();
wait_for_grant();
assert(req.randomize());
send_req(req);
received_item_done = 0;
received_item_done = 1;
endtask
endclass
//Test
begin
fork
begin
end
begin
forever
end
join_any
@(posedge idles_transmit.received_item_done);
disable fork;
Sequencer.stop_sequence();
end
In the above code we are trying to kill the thread and reseting sequencer state only
after receiving the ite_done for the request sent, which is the idle way to stop
thread.
http://testbench.in/killing_sequences.html[9/26/2012 2:53:15 PM]
WWW.TESTBENCH.IN
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Ankit Gopani
is ASIC Engineer at
eInfochips,
Do not rely on illegal_bins for checking purpose. If you rely on cover group where you Ahmedabad,India.
have written illegal_bins, what happens when you turn off the coverage??
He is a specialties in SoC
That is where Assertions coming in picture...! If you really want to ignore values then Verification and VIP
development in System
use ignore_bins. If you really want to throw errors then use an assertions checkers.
Verilog VMM.
While illegal_bins removes values from coverage calculations, it also throws errors.
Visit Ankit's Blog for
Philosophically, you need to ask yourself the questions,
more SV stuff
(1) "Should a passive component like a cover group be actively throwing errors?" and AsicWithAnkit.BlogSpot.com
(2) "If you rely on the cover group for checking, then what happens when you turn
coverage off?"
covergroup cg @ (posedge clk iff decode);
coverpoint opcode {
bins move_op[] = {3'b000, 3'b001};
Easy Labs : VMM
bins alu_op = {[3'b010:3'b011], [3'b101:3'b110]};
bins jump_op = {3'b111};
AVM Switch TB
illegal_bins unused_op = {3'b100};
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
From the example given above, you can see 3'b100 is an illegal op code and as per
protocol if that value occurs then its an error. So here instead of writing and
illegal_bins you can have a assert property with coverage to check specifically this
scenario.
It is actually a debatable point because illegal bins will stops simulation if it hits, and
from the last message or from debugging engineer can debug the reason for failure.
The mail point is as it is not allowing the simulation forward, you can not check the
functionality in error case. So to avoid this constraint we have assertions with cover
property which allows us to go ahead with simulation with error indication.
So usually I would prefer to have an assertions (with cover property) where strong
protocol check requires instead of writing illegal_bins.
RVM Ethernet sample
Specman E
About the author:
Do not rely on illegal_bins
Easy Labs : OVM
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Search
Enjoy...!
-ASIC with Ankit
Interview Questions
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input is what keeps
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About the author:
PASS and FAIL Messages with Colors...!
Ankit Gopani
is ASIC Engineer at
Constructs
eInfochips,
How many among you know that you can actually display color messages using Verilog Ahmedabad,India.
Interface
and SystemVerilog?
OOPS
He is a specialties in SoC
Randomization
You can implement a logic in your testbench to have nicely colored display messages Verification and VIP
at the end of your simulation which will give you a PASS/FAIL messages. I have development in System
Functional Coverage
written a piece of code given below and you can refer the same. I have captured a Verilog VMM.
Assertion
snapshot of output which you can see below.
Visit Ankit's Blog for
DPI
more SV stuff
AsicWithAnkit.BlogSpot.com
UVM Tutorial
programclr_display();
VMM Tutorial
classcolor ;
OVM Tutorial
taskdisplay ();
$display("%c[1;34m",27);
Easy Labs : SV
$display("***************************************");
Easy Labs : UVM
$display("*********** TEST CASE PASS ************");
input is what keeps
$display("***************************************");
Easy Labs : OVM
$write("%c[0m",27);
Easy Labs : VMM
with time!
$display("%c[1;31m",27);
AVM Switch TB
$display("***************************************");
VMM Ethernet sample $display("*********** TEST CASE FAIL ************");
$display("***************************************");
endtask
Verilog
endclass
Verification
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
initial
begin
color clr;
clr =new();
clr.display ();
end
endprogram
Switch TB
RVM Switch TB
OUTPUT:
RVM Ethernet sample
Specman E
Interview Questions
The message to be printed is ("%c[TYPE;COLOURm",27);.

TYPE specifies how the message should be?
1 set bold
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2
4
5
7
set half-bright (simulated with color on a color display)

set underscore (simulated with color on a color display)
set blink
set reverse video
COLOR specifies the message color.

30
31
32
33
34
35
36
37
set black foreground

set red foreground
set green foreground
set brown foreground
set blue foreground
set magenta foreground
set cyan foreground
set white foreground
With an above example you can have a display messages with colors. So this way you
can have nicely and colored messages on your terminal.
Enjoy...!
-ASIC with Ankit
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About the author:
Whats new in Systemverilog 2009 ?
Ankit Shah
is working at Sibridge
In 2005 there were separate standards for Verilog and SystemVerilog which are Technologies Pvt. Ltd,
merged here with SystemVerilog 2009. There are 30+ noticeable new constructs and Ahmedabad,India.
25+ system task are introduced in SystemVerilog 2009.
Your feedback / input /
thought on this article,
I listed out following new constructs which are added in SV-2009.
send to Ankit @
mail2ajshah@gmail.com
DPI
timeunit and timeprecision
UVM Tutorial
You can specify timeunit and timeprecision inside the module with single keyword.
VMM Tutorial
OVM Tutorial
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VMM Ethernet sample
Verilog
moduleE (...);
timeunit100ps /10fs;// timeunit with optional second argument
...
endmodule
(Ch. 3.14.2.2 of LRM)
checker - endchecker
The checker is specifically created to encapsulate assertions. It can be added with the
modeling code and can be instantiationed. Formal arguments of checker are inputs.
Verification
(Ch. 17)
Verilog Switch TB
checker my_check1 (logictest_sig);

a1:assertproperty(p (test_sig));
c1:coverproperty(!test_sig ##1test_sig);
endchecker :my_check1
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
global clocking
Global clocking block is declared as the global clocking block for an entire elaborated
SystemVerilog model.
RVM Ethernet sample global clocking@(clk1 orclk2);
endclocking
Specman E
Interview Questions
Search
(Ch. 14.14)
Printing format
%p - displays as an assignment format.
(Ch 21.2.1.2)
%x - displays in hexadecimal format.
(Ch 21.2.1.2)
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edge
It is equivalent to posedge+negedge
(Ch. 31.5)
let
This local score compiler directive replaces the other test macro like `define. A let
construct may be instantiated in other expressions.
let declarations can be used for customization and can replace the text macros in
many cases.
let check_grant(a,b)=assert(a ##2b));
check_grant(req,gnt);
(Ch. 11.13)
localparam in ANSI style header
moduledriver #(parameterAWIDTH=8,
parameterDWIDTH=8,
localparamPORT=1>>data
);
(Ch. 22.2.3)
unique0
Keyword unique will issue a violation report if no condition matches. while keyword
unique0 will not issue a violation report if no condition matches.
(Ch. 12.4.2)
Associative array size()
size() method is introduced to return number of entries in associative array like num()
method.
(Ch. 7.9.1)
Queue delete()
Now you can pass specific index number inside the delete function to delete that
particular index. If index is not specified then it will delete entire Q.
(Ch. 7.10.2)
Bit select and part select of an expression
Instead of...
assignt =(a &b)|(c &d);
assignval =t[7:4];
you can do...
assignval ={(a &b)|(c &d)}[7:4];
(Ch. 7.2.1)
Import package into design
packagebit_pkg;
bitclk;
bitreset;
endpackage
moduledut(
inputbit_pkg::reset rst;
inputbit_pkg::clk clock;
...
endmodule
Packet chaining, automatic package and multiple package export is also introduced in
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SV-2009.
(Ch. 23)
pure virtual methods
SV-2009 allows to declare pure virtual methods as well as class. It must be written in
abstract class & it must be only a prototype, It must not contain any statement and
must with without endtask/endfunction.
virtualclassBasePacket;
purevirtualfunctionintegersend(bit[31:0]data);// No implementation
endclass
(Ch. 8.20)
pure constraint
It is allowd to declare pure constraint in abstract class. This must be implemented in
extended class with the same constraint name.
virtualclassC;
pureconstrainttest;
endclass
(Ch. 18.5.2)
Time consuming functions
Using fork/join_none, now time consuming constructs can be used inside function.
functionvoiddisp;
fork
#0$display("%t: This is #0",$time);
#3$display("%t: This is #3 and A = %x",$time,a);
a <=8'hbb;// It allows non-blocking assignment
join_none
endfunction
(Ch. 9.3.2)
covergroup with sample arguments
covergroup withfunctionsample(bita,intx);
coverpointx;
crossx,a;
endgroup:
cg cg1 =new;
functionvoidF(intj);
bitd;
...
cg1.sample(d,j );
endfunction
(Ch. 19.8.1)
weak - strong
These sequence operators are introduced to simulate assertion efficiently. Assert may
produce wrong message if there is a glitch in the signal. strong require that some
terminating condition happen in the future, and this includes the requirement that
the property clock ticks enough time to enable the condition to happen. weak do not
impose any requirement on the terminating condition, and do not require the clock to
tick. If the strong or weak operator is omitted, then the evaluation of the
sequence_expr depends on the assertion statement in which it is used. If the assertion
statement is assert property or assume property, then the sequence_expr is evaluated
as weak(sequence_expr). Otherwise, the sequence_expr is evaluated as
strong(sequence_expr).
The default in SV-2005 was strong while in SV-2009 is weak unless you. specified
strong.
(Ch. 16.13)
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Implies and iff properties

A property is an implies if it has the following form:
property_expr1 implies property_expr2
Above form evaluates to true if property_expr1 evaluates to true, if not then
property_expr2 evaluates to true.
A property is an iff if it has the following form:
property_expr1 iff property_expr2
A property of this form evaluates to true if, and only if, either both
property_expr1 evaluates to false and property_expr2 evaluates to false or both
property_expr1 evaluates to true and property_expr2 evaluates to true.
(Ch. 16.13)
followed-by (#-#, #=#)
propertys1;
##[0:5]done #-#always!rst;
endproperty
propertys2;
##[0:5]done #=#always!rst;
endproperty
Property s1 says that done shall be asserted at some clock tick during the first 6 clock
ticks, and starting from one of the clock ticks when done is asserted, rst shall always
be low. Property s2 says that done shall be asserted at some clock tick during the first
6 clock ticks, and starting the clock tick after one of the clock ticks when done is
asserted, rst shall always be low.
(Ch. 16.13)
The property operators
s_nexttime, s_always, s_eventually, s_until, s_until_with, and sequence operator
strong are strong.
The property operators nexttime, always, until, eventually, until_with, and sequence
operator
weak are weak.
nexttime and s_nexttime
// if the clock ticks once more, then a shall be true at the next clock tick
propertys1;
nexttime a;
endproperty
// the clock shall tick once more and a shall be true at the next clock tick.
propertys2;
s_nexttime a;
endproperty
(Ch. 16.13)
always - s_always
propertys1;
a ##1b |=>alwaysc;
endproperty
property s1 evaluates to true provided that if a is true at the first clock tick and b is
true at the second clock tick, then c shall be true at every clock tick that follows the
second.
(Ch. 16.13)
until - until_with - s_until - s_until_with
propertys1;
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a until b;
endproperty
propertyp3;
a until_with b;
endproperty
Property s1 evaluates to true if, and only if, a is true at every clock tick beginning
with the starting clock tick of the evaluation attempt and continuing
until, but not necessarily including, a clock tick at which b is true.
(Ch. 16.13)
The property p3 evaluates to true provided that a is true at every clock tick beginning
with the starting clock tick of the evaluation attempt and continuing
until and including a clock tick at which b is true.
(Ch. 16.13)
eventually - s_eventually
propertys1;
s_eventually a;
endproperty
The property s1 evaluates to true if, and only if, there exists a current or future clock
tick at which a is true.
(Ch. 16.13.13)
not - accept_on - reject_on - sync_accept_on - sync_reject_on
propertyp;(accept_on(a)s1);endproperty
If a becomes true during the evaluation of s1, then p evaluates to true.
propertyp;(reject_on(b)s2);endproperty
If b becomes true during the evaluation of s2 then p evaluates to false.
propertyp;not(reject_on(b)s2);endproperty
not inverts the effect of operator, so if b becomes true during the evaluation of s2
then p evaluates to true.
(Ch. 16.13.14)
case
case can be used inside the property.
(Ch. 16.13.16)
restrict
It is constraint to the formal verification tool to do not check the property.
untyped
It is allowed to use untyped datatype inside properties.
(Deferred assertion)assert#0-assume#0-cover#0
Deferred immediate assertion evaluates after signal have stabilized in a time step.
Shortcut operators
##[+]is equivalent to ##[1:$]
##[*]is equivalent to ##[0:$]
<signal>[+]is equivalent to <signal>[*1:$]
<signal>[*]is equivalent to <signal>[*0:$]
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(Ch. 16.7)
`define
you can pass default value in define macro.
`defineMACRO1(a=5)$display(a);
(Ch. 22.5)
ùndefineall
It undefines all the defined test macro which is previously declared.
`defineFPGASIM
`defineGATESIM
module...
....
....
endmodule
ùndefineall
(Ch. 22.5)
`begin_keywords and ènd_keywords
It is used to specify reserved keywords, it will give an error if implementain does not
matched with version_specifier. e.g if you have specified "1800-2009" then all the
previous versions of Verilog/SystemVerilog keywords can be used but if you have
specified "1800-2005" then those keywords which are introduced specifically in SV2009 those can not be used.
(Ch. 22.14)
FILE name and LINE numbers
It keeps track of the filenames of SystemVerilog source files and line nunbers in the
files. which can be helpfull to source error messages and the file name. `__FILE__
expands to the name of the current input file, in the form of a string literal constant.
This is the path by which the compiler opened the file, notthe short name specified
in ìnclude or as the command line argument. `__LINE__ expands to the current input
line number, in the form of a decimal
integerconstant.
$display("Internal error: null handle at %s, line %d.",`__FILE__,`__LINE__);
file path and line number will be return which contain above message.
(Ch. 22.12, 22.13)
SYSTEM TASK
$syatem - allows operation system commands.
(Ch 20.18.1)
$global_clock returns the event statement which is written global clocking block
declaration. Here it will return "clk1 or clk2".
(Ch. 14.14)
$sformatf - this system function returns the message into string. Thus string can be
passed into valid function.
$fatel - $error - $warning - $info can be used outside assertion.
$assertpasson - enable execution of pass statement.
$assertpassoff - stop execution of pass statement.
$assertfailon - enable execution of pass statement.
$assertfailoff - stop execution of fail statement.
$assertnonvacuouson - enable execution of pass statement when assertion is vacuous.
$assertvacuousoff - stop execution of pass statement when assertion is non vacuous.
(Ch 20.14, 16.15.8)
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$changed
It detect changes in values between two adjscent clock tics.
(Ch 20.13)
$past_gclk-$rose_gclk-$fell_gclk-$stable_gclk-$changed_gclk
It will give past sampled value of the signal with respect to global clock.
(Ch 20.13)
$future_gclk-$rosing_gclk-$falling_gclk-$steady_gclk-$changing_gclk
It will give future sampled value of the signal with respect to global clock.
(Ch 20.13, 16.15.8)
$inferred_clock-$inferred_disable-$inferred_enable
These system function are available to query assertion
(Ch. 16.15.7)
Protected envelopes
It specify a region of text that shall be transformed prior to analysis by the source
language processor.
(Ch. 34)
Still there could be many enhancement behind the curtain. It always GOOD to KNOW
more. Your feedback/input/thought are welcomed which can help me to update
contain. Reach me at mail2ajshah@gmail.com
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About the authors:
Introduction to Ethernet Frames : Part - 1
Bhavani shankar is VLSI

engineer at Kacper
This tutorial is divided into two parts. Part-1 will be on Ethernet Frames and Part-2 Technologies Pvt. Ltd.
Bhavani shankar is an
will be on Simple Ethernet Testplan.
master in VLSI-CAD from
For Part-2 , Click
Manipal Centre for
Information Science,
Manipal.
1.Ethernet Protocol Layer
The Ethernet protocol basically implements the bottom two layers of the Open Gopi Krishna He is the
Systems Interconnection (OSI) 7-layer model, i.e., the data link and physical sub Author of testbench.in.
layers. Following Figure depicts the typical Ethernet protocol stack and the
relationship to the OSI model.
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VMM Ethernet sample
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Switch TB
2.Ethernet Frame Structure
RVM Switch TB
The following illustrates the format of an Ethernet frame as defined in the original
RVM Ethernet sample IEEE 802.3 standard
Specman E
Interview Questions
Preamble
A sequence of 56 bits having alternating 1 and 0 values that are used for
synchronization. They serve to give components in the network time to detect the
presence of a signal, and read it before the frame data arrives.
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Destination MAC Address
The Destination MAC Address field addresses destination stations. This may addresses
single or multiple stations.
Destination Address (6bytes) of all 1 bits refers to all stations on the LAN and is called
a "Broadcast address".
Start Frame Delimiter
Sequence of 8 bits having the bit configuration 10101011 indicates the start of the
frame.
Source MAC Address
The Source MAC Address addresses the station at which it originated. The 802.3
standard permits these address fields to be either 2-bytes or 6-bytes in length.
Length/Type (2bytes)
If the value of this field is less than or equal to 1500, then the Length/Type field
indicates the number of bytes in the subsequent MAC Client Data field. If the value of
this field is greater than or equal to 1536, then the Length/Type field indicates the
nature of the MAC client protocol (protocol type)
MAC Client Data
This field contains the actual data transferred from the source station to the
destination station or stations. The maximum size of this field is 1500 bytes. If the
size of this field is less than 46 bytes, then use of the subsequent "Pad" field is
necessary to bring the frame size up to the minimum length.
Pad
If necessary, extra data bytes are appended in this field to bring the frame length up
to its minimum size. A minimum Ethernet frame size is 64 bytes from Destination MAC
Address(DA) field through the Frame Check Sequence(FCS).
Frame Check Sequence (FCS)
This field contains a 4-byte Cyclic Redundancy Check (CRC) value used for error
checking.
When a source station assembles a MAC frame, it calculates a CRC checksum on all
the bits in the frame from Destination MAC Address (DA) to the Pad fields (that is, all
fields except the preamble, start frame delimiter, and frame check sequence).
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The source station stores this CRC value in this field and transmits it as part of the
frame. When the frame is received at destination station, it calculates CRC of
received data and compares it with FCS. If it does not match then destination station
assumes an error occurred during transmission and discards the frame.
The original Ethernet standards defined the minimum frame size as 64-bytes and the
maximum as 1518-bytes. These numbers include all bytes from the Destination MAC
Address field through the Frame Check Sequence field. The Preamble and Start Frame
Delimiter fields are not included when quoting the size of a frame. The IEEE 802.3ac
standard released in 1998 extended the maximum allowable frame size to 1522-bytes
to allow a "VLAN tag" to be inserted into the Ethernet frame format.
Interframe Gap
Ethernet devices must allow a minimum idle period between transmission of frames
known as the interframe gap (IFG) or interpacket gap (IPG). It provides the time for
devices to recover and prepare to receive next frame. The minimum interframe gap is
96 bit times.
3.Frame Format Extensions

VLAN Tagging
The VLAN protocol permits insertion of an identifier, or "tag", into the Ethernet frame
format to identify the VLAN to which the frame belongs. It allows frames from
stations to be assigned to logical groups. This provides various benefits such as easing
network administration, allowing formation of work groups, enhancing network
security, and providing a means of limiting broadcast domains, The 802.3ac standard
defines only the implementation details of the VLAN protocol those are specific to
Ethernet. The 4-byte VLAN tag is inserted into the Ethernet frame between the Source
MAC Address field and the Length/Type field. The first 2-bytes of the VLAN tag consist
of the "802.1Q Tag Type" and are always set to a value of 0x8100. The 0x8100 value is
actually a reserved Length/Type field assignment that indicates the presence of the
VLAN tag, and signals that the traditional Length/Type field can be found at an offset
of 4-bytes further into the frame.
The last 2-bytes of the VLAN tag contain the following information
The first 3-bits are a User Priority Field that may be used to
Assign a priority level to the Ethernet frame.
The next 1-bit is a Canonical Format Indicator (CFI) used in Ethernet frames to
indicate the presence of a Routing Information Field (RIF).
The last 12-bits are the VLAN Identifier (VID) which uniquely identifies the VLAN to
which the Ethernet frame belongs.
JUMBO Frames
JUMBO frames are introduced in order to Increase the maximum size of the MAC Client
Data field, larger frames would provide more efficient use of the network Bandwidth
while reducing the number of frames that have to be processed.
JUMBO frames has the capacity to carry bytes from 64bytes (min size) to 9000bytes
(max size)
The 8870 value is actually a reserved Length/Type field assignment that indicates
frame as JUMBO.
PAUSE Frames
Flow control operation known as "PAUSE" frames are included in 10GBE as it supports
the full duplex mode.
The 8808 value is actually a reserved Length/Type field assignment that indicates
frame as PAUSE. Length/Type field is followed by 2 bytes of MAC control Opcode (0001) and 2bytes of MAC control Parameter (timer=00-00toFF-FF) with a unique DA (0180-c2-00-00-01) in MAC DA field
PAUSE frame considers 64bytes as Minimum size and 1518bytes as Maximum size for
Normal frame and 1522bytes when tagged.
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Transmitter Mac should not transmit the frames once it receives Pause frames from
receiver until the time duration specified in the Pause timer
Transmitter Mac should reset/replace the current pause timer with newly arrived
pause time when a Pause frame arrives from receiver before the current Pause time
expires.
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Introduction to Ethernet Frames : Part - 2
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In part-2 , we will see a simple testplan for 10G Ethernet Frames.

For Part-1 , Click
TEST PLAN FOR MAC FRAME

MAC FRAME FORMAT
DPI
Bhavani shankar is VLSI

engineer at Kacper
Technologies Pvt. Ltd.
Bhavani shankar is an
master in VLSI-CAD from
Manipal Centre for
Information Science,
Manipal.
Gopi Krishna He is the
Author of testbench.in.
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PREAMBLE
Discussion:
The frame begins with the 64-bit preamble field which allows 10G Ethernet
interfaces on the network to synchronize themselves with the incoming data stream
before the arrival of important data fields.
[Need for Synchronization: In LAN implementation, most of the physical layer
components are allowed to provide valid output only after some number of bit times
prior to the valid input signals. So this condition necessities a Preamble which is to be
sent before the start of the data .This allows the PLS circuitry to reach its steady
state with the received frames timing. So Preamble is used for physical medium
stabilization and synchronization followed by SFD.]
Preamble is not used by the MAC layer, so the minimum amount of preamble
required for a device to function properly depends up on which physical layer is
implemented and not up on the MAC layer.
The preamble bits are transmitted in order from left to right and it should be noted
that PRE ends with a 0.
Up on the reception of a Frame Physical signal Decapsulation procedure discards
RVM Ethernet sample every bit of preamble until a valid SFD.
Specman E
Interview Questions
IEEE Standard does not define the minimum PRE size, PRE size is handled depending
up on the PHY as it is the function of physical medium. So min PRE size is considered
as 1byte .Even though Standard defines as PRE as 7bytes,Mac should tolerate large
amounts of Preamble
[The PRE is maintained in the fast Ethernet and gigabit systems to provide
compatibility with the original Ethernet frame. However, both systems use more
complex mechanisms for encoding the signals that avoid any signal startup losses, so
they dont need preamble to protect the frame signals]
Valid PRE
1) A frame with PRE of 7octets in PRE field with the bit pattern shown below and
should always end with a 0.
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10101010 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx10101010

2) A frame with variable PRE octets like 1, 2, 3,4,5,6 by using pattern shown in 1st
case
Invalid PRE
1) A frame with variable PRE octets
Generate a frame with PRE octets greater than required i.e. 8, 9,10,12
2) A frame with variable PRE pattern
3) Generate a frame with varying bit patterns using following cases and observe the
results.
(1st byte)...(7th byte)
00000000.....00000000
11111111.....11111111
10101111.....10101111
01010101.....11000011
10101011.....10101011
4) A frame consisting only PRE [i.e. Sop PRE Eop]
5) Repeat bad frames mentioned above with each frame followed and preceded by a
Good Frame separated by required minimum Inter Frame Gap (96 bits).
References:
IEEE STD 802.3,2005 Edition, subclasses 3.2.1, 4.2.5, 4.2.9
OREILY-Ethernet Definitive Guide. PDF
START FRAME DELIMITER [SFD]

Discussion:
SFD field is the sequence 10101011 which immediately follows the PRE pattern and
indicates the start of the frame.
The last two bits indicates the receiving interface that the end of the preamble
and SFD has been reached and that the bits that follow are actual fields of the frame
Any successive bits following the transmission of SFD are recognized as data bits
and are passed on to the LLC sub layer
Valid SFD
1) A frame of one octet size SFD with bit pattern 10101011 and placed after PRE.
2) Any frame with invalid SFD pattern is considered as Bad frame and discarded
Invalid SFD
1) A Frame with variable SFD bit pattern
Generate a frame with variable bit patterns using following cases
10101010
10101111
11111111
00000000
01010111
11000011
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2) A Frame consisting only PRE and Good SFD [i.e. Sop PRE SFD Eop]
References:
IEEE STD 802.3,2005 Edition, subclasses 3.2.2, 4.2.6.
FRAME CHECK SEQUENCE (FCS)

Discussion:
FCS field contains a 4-byte cyclical redundancy check (CRC) value used for error
checking. CRC is a polynomial that is calculated using the contents of the destination,
source, type (or length), and data fields except PRE, SFD and FCS. As the frame is
generated by the transmitting station, the CRC value is simultaneously being
calculated.
The source station stores 32 bits of the CRC value (x31 term is the most bit of the
first octet and the x0term is the right most of the last octet) that are the result of
this calculation in the FCS field and transmits it as a part of the frame. The x31
coefficient of the CRC polynomial is sent as the first bit of the field and the x0
coefficient as the last bit.
When the frame is received by the destination station, it performs an identical
check. If the calculated value does not match the value in this field, the destination
station assumes an error has occurred during transmission and discards the frame.
Valid CRC
1) The 32bit CRC value in FCS field of received frame should match the 32bit CRC
value computed on received frame.
2) Frames with incorrect CRC(mismatch) values should be discarded
Invalid CRC
1) A frame with incorrect CRC value
a) Generate a frame by keeping incorrect CRC values in FCS field and observe the
results
b) Repeat (a) for JUMBO,PAUSE and VLAN frames and observe the results Mac
should discard the frames in both the cases as CRC error
References:
IEEE STD 802.3,2005 Edition, subclasses 3.2.8, 4.2.4.1.2.
LENGTH/TYPE FIELD
Discussion:
10GB Ethernet supports the following frame sizes
a) In case of untagged
Maximum untagged frame size is 1518 bytes(from DA to FCS)
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Minimum frame size is 64bytes(from DA to FCS)

b) In case of tag
Maximum tagged frame size is 1522bytes (Untagged size + tag prefix size)
If the value in the Length/type field is less than or equal to 1500 then the Value
indicates the number of bytes in the subsequent MAC Client Data field. (Length
Interpretation)
If the value in the length/type field is greater than or equal to 1536 then the value
Indicates the nature of the MAC client protocol (protocol type like jumbo, pause etc)
All other values are undefined. (Type Interpretation)
The minimum length of the Data/Pad field is 46 bytes, if the length of the frame in
the length/type field is less than 46 then all extra bytes are considered as
padded/appended in this field to bring the frame length up to its minimum size
The maximum length of the Data/pad field is 1500bytes, if the length of the frame
in the length /type field is greater than 1500 and less than 1536, frame is discarded.
10GE supports the VLAN Tagging which is inserted in to the Ethernet frame
between the source MAC address and Length/Type field. The first 2-bytes of the VLAN
tag consist of the "802.1Q Tag Type" and are always set to the value of 0x8100.
a) VLAN tagged frames takes 64bytes as minimum size and 1522 bytes as maximum
size (max size may vary depending up on VLAN count).
b) The 0x8100 value is actually a reserved Length/Type field assignment that
indicates the presence of the VLAN tag.
Note: As the Standard does not define the min tagged frame size, it is considered as
64bytes which is common to all types of frames. This min size constraint may vary
depending up on the Company, (CISCO defined the minimum size of the Ethernet
frame with 802.1Q tagging is 68 bytes)
JUMBO frames are introduced in order to Increase the maximum size of the MAC
Client Data field, larger frames would provide more efficient use of the network
Bandwidth while reducing the number of frames that have to be processed.
a) JUMBO frames has the capacity to carry bytes from 64bytes (min size) to
9000bytes (max size)
b) The 8870 value is actually a reserved Length/Type field assignment that
indicates frame as JUMBO.
Flow control operation known as "PAUSE" frames are included in 10GBE as it
supports the full duplex mode.
a) The 8808 value is actually a reserved Length/Type field assignment that
indicates frame as PAUSE. Length/Type field is followed by 2 bytes of MAC control
Opcode (00-01) and 2bytes of MAC control Parameter (timer=00-00toFF-FF) with a
unique DA (01-80-c2-00-00-01) in MAC DA field
b) PAUSE frame considers 64bytes as Minimum size and 1518bytes as Maximum size
for Normal frame and 1522bytes when tagged.
c) Transmitter Mac should not transmit the frames once it receives Pause frames
from receiver until the time duration specified in the Pause timer
d) Transmitter Mac should reset/replace the current pause timer with newly
arrived pause time when a Pause frame arrives from receiver before the current
Pause time expires.
Valid Frames
1) A frame(untagged) size between 64 and 1518 bytes [Valid size Normal untagged
frame]
Generate a frame with the following acceptable sizes and observe the results. Mac
should accept these frames
64,65,67,100,512,1500,1516,1517,1518
2) A tagged frame size between 64 and 1522 bytes [Valid size Normal tagged frame]
Generate a frame with the following acceptable sizes and observe the results, Mac
should accept these frames
64,65,67,100,512,1500,1516,1517,1518, 1520,1522
3) A frame less than min length (<46) with padded values [Length (<46) untagged
padded Normal frame]
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Generate a frame with the following lengths in length field along with proper
Padding and observe the results, Mac should accept the frames
1,2,3,4,5,6,7,40,42,44,45
4) A frame greater than min length (with out padding) but less than max
length(1500bytes) [Length (>46) untagged Normal frame]
Generate a frame with the following lengths in length field and observe the
results, Mac should accept the frames
47,50,100,512,1497,1498,1499,1500
5) A frame greater than or equal to1536 bytes i.e. Type interpretation Generate a
frame with the following values in length/Type field and observe the results, Mac
should interpret the frame as one of the following types
5.1) A frame with VLAN tag ( 8100/9100--VLAN tagged )
Generate a tagged frame by placing 8100/9100 in the first two bytes of tagged
length/type field that indicates the presence of VLAN tag and replaces the normal
"Length/Type" field repeat with 3. (a) & 4. (a) Valid frame cases. Mac should accept
the frame as normal VLAN tagged frame [Length (<46) tagged padded Normal frame,
Length (>46) tagged Normal frame]
5.2) JUMBO frame Type ( 8870 - JUMBO Type)
5.2.1 ) JUMBO frame of size >64 bytes with VLAN tag
Generate a Jumbo Tagged frame of size (>64) by placing8870 in regular
Length/Type field and repeat with 2nd valid frame cases; Mac should accept the
frame as JUMBO frame with VLAN tag. [JUMBO (size>64) tagged frame]
5.2.2) JUMBO frame of size (<=9k+22) with VLAN tag
Generate a Jumbo frame of size (< =9k+22); Mac should accept the frame as JUMBO
frame with VLAN tag. [JUMBO (size<=9k+22) tagged frame]
5.2.3) JUMBO frame with out VLAN tag
a) Generate a frame of size (>64) by placing 8870 in the regular Length/type field
and repeat with 1st valid frame case including 1519, 1520, 1522. Mac should accept
the frame as JUMBO untagged frame. [JUMBO (size>64) untagged frame]
b) Generate a frame of size (<=9k+18) by placing 8870 in the regular Length/type
field and repeat with 1st valid frame case; Mac should accept the frame as JUMBO
untagged frame. [JUMBO (size<=9k+18) untagged frame]
5.3) PAUSE Frame Type (8808 - PAUSE Type)
5.3.1) PAUSE frame of size (>64) and (<1522) with VLAN tag
Generate a Tagged Pause frame by placing 8808 in the regular Length/type field
and next 2bytes of opcode field with (00-01) and repeat with 2nd valid frame cases
(64,65,67,100,512,1500,1516,1517,1518, 1520,1522) ; Mac should accept the frame as
Pause frame with VLAN tag. [PAUSE (size>64) and (<1522) Tagged Frame]
5.3.2) PAUSE frame with out VLAN tag
Generate a untagged pause frame and repeat with 1st valid frame cases
(64,65,67,100,512,1500,1516,1517,1518); Mac should accept the frame as Pause
frame with out VLAN tag. [PAUSE (size>64) and (<1518) untagged Frame]
5.3.3) PAUSE frame with MAC control Parameters (zero & Non-zero Timer)
a) Generate a untagged Pause frame by placing (00-01) in opcode field and vary
timer values from 00-00 to FF-FF(hex) [Untagged PAUSE with Zero & non-zero Timer]
b) Repeat (a) for tagged Pause frame [Tagged PAUSE with Zero & non-zero Timer]
c) Repeat (a),(b) with different pause times before the completion of current
pause_timer [Multiple Pause frames with different timers]
Invalid Frames
1) A Frame which is less than min frame size (<64) with bad CRC(Runt frames) [Runt
size (<64) common to Normal, JUMBO&VLAN tagged/untagged Runt frames]
a) Generate a frame (both tagged and untagged) with the following sizes which are
less than min frame size (<64) and observe the results, MAC should discard these
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frames
(1) 1, 2,3,4,5,6,7,8,45,46,47
(2) 50, 61, 62, 63
b) Repeat (a) for PAUSE frame and observe the results, Mac should not accept the
frame as VALID [PAUSE Runt frame]
2) Repeat (1) for SHORT frames [SHORT Frames]
3) A untagged Frame greater than max frame size (>1518) [Over size (>1518) untagged
Normal frame]
3.1) Generate a frame with the following sizes which are greater than Max frame
size
a) 1519, 1520, 1521, 1522
b) 1526, 1530, 1534,1535,1536,1537
3.2) Repeat (a) for untagged PAUSE frame [Over size (>1518) untagged PAUSE
frame]
4) A tagged (VLAN) Frame greater than max frame size (>1522)
(a) Generate a frame using 3.A (b) Invalid frame cases [Over size (>1522) tagged
Normal frame]
(b) Repeat (a) for tagged PAUSE frame [Over size (>1522) tagged PAUSE frame]
5) A frame less than min length (<46) without padding
a) Generate a frame with the following lengths in length field without padding and
observe the results, Mac should discard the frames as
1,2,3,4,5,6,7,40,42,44,45 [Runt Length (<46) not padded Normal frame]
b) Repeat (a) with tagged frame [Runt Length (<46) not padded tagged Normal
frame]
6) A frame greater than max length (>1500) and( <1536)
a) Generate a frame with the following lengths in length field and observe the
results, Mac should discard the frames [Invalid Length (>1500&<1536) untagged Normal
frame]
1501,1505,1518,1522,1526,1530,1535
b) Repeat (a) with tagged frame [Invalid Length (>1500&<1536) tagged Normal
frame]
7) A frame with invalid value in Length/Type field( i.e. Type interpretation)
a) Generate a frame with the following values in length/Type field and observe the
results, Mac should identify these frame types
1536,1537, 1540, 8000.8101,8110,8807,8809,8880 [Invalid Type (>1536) untagged
Normal/Pause frame]
b) Repeat (a) with Tagged frame [Invalid Type (>1536) tagged Normal/Pause frame]
8) A JUMBO frame of size > (9k+18)
a) Generate a Jumbo frame of size (>9k+18); Mac should discard the frame as
Invalid size JUMBO untagged frame [Over size JUMBO (size>9k+18) untagged frame]
b) Generate a Jumbo frame of size (>9k+22); Mac should discard the frame as
Invalid size JUMBO tagged frame [Over size JUMBO (size>9k+22) tagged frame]
9) PAUSE frame with invalid value in opcode field
a) Generate an untagged Pause frame with invalid opcode (other than 00-01) values
with following opcode values 00-10, 01-00, 00-02 to 00-07, 00-00, 00-FF,01-01 etc.
[Invalid opcode PAUSE untagged frame]
b) Repeat (a) for Tagged PAUSE frame[Invalid opcode PAUSE tagged frame]
10) Multiple PAUSE frames
Generate a pause frame by varying Pause timer values such that Transmit MAC should
not affect the Min IFG gap required between frames after the completion of PAUSE
duration
[Example: suppose current pause timer is set to 8sec and if other frame arrives with
pause time 0sec, then Mac should transmit the frames with out violating the min IFG]
Repeat bad frames mentioned above with each frame followed and preceded by a
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References:
IEEE Std 802.3, 2002 Edition - subclasses 3.1.1, Figure 3-1 - MAC frame format,3.2.6,
3.5, Figure 3-3 Tagged MAC frame format, 4.4.2-allowable Implementations
IEEE STD 802.3-2005 - Subclasses 31.3 and 31B.3.3, 31B.3.7
IEEE STD 802.3-2005 - Subclasses 3.5, 31.4, 31.5.1, and 31.5.2
IEEE STD 802.3-2005 - Subclasses 4.2.9, and 4.2.4.2.2
DESTINATION FIELD (DA)

Discussion:
The Destination MAC Address field identifies the station or stations that are to
receive the frame. DA field follows the preamble and Each Ethernet interface is
assigned a unique 48-bit address, called the interface's physical or hardware address.
The DA field contains the 48-bit Ethernet address that corresponds to the address
of the interface in the station that is the destination of the frame.
The DA field may specify either an "Individual address" destined for a single station
or "Multicast address" destined for a group of stations or the standard broadcast
address
If the LSB(1st bit) is 0---indicates Individual address 1---indicates Multicast address
(including Broadcast)
If the 2nd bit is 0---indicates globally administered 1---indicates locally administered
(including Broadcast)
The IEEE 802.3 version of the frame adds significance to the second bit of the
destination address, which is used to distinguish between locally and globally
administered addresses.
1) A globally administered address is a physical address assigned to the interface by
the manufacturer, which is indicated by setting the second bit to zero.
2) If the address of the Ethernet interface is administered locally for some reason,
then the second bit is supposed to be set to a value of one. In the case of a broadcast
address, the second bit is also a one.
Remaining 46bits are a uniquely assigned value that identifies a single station or
group of stations or all stations on the network
[Locally administered addresses are very rarely used on Ethernet systems, since the
vast majority of Ethernet interfaces are assigned their own unique 48-bit address.
Locally administered addresses, However, have been commonly used on some Token
Ring systems.]
Valid Frame
1) A Frame with 6bytes of DA [valid DA field Normal frame]
a) Generate a frame by placing 6 bytes of following valid address values
Unicast MAC address
Multicasting MAC address
Broadcasting MAC address
b) Repeat (a) for tagged normal frame
2) A Frame with PAUSE Multicast unique DA
a) Repeat 5.3.C (a), (b),(c) Valid paused Type frame cases by placing unique
multicast address reserved for PAUSE transactions (01-80-C2-00-00-01) [Un tagged
Pause with Unique (DA) reserved Multicast Address]
b) Repeat (a) for tagged PAUSE frame [Tagged Pause with Unique (DA) reserved
Multicast Address]
Invalid Frame
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1) A Frame with 6bytes of invalid DA [Invalid DA field Normal frame]

a) Generate a frame by placing following invalid address values(only when they are
not valid MAC address)
All zeros (000000...)
All ones (1111111...)
SFD pattern(10101011)
Random value
2) A Frame with 6bytes of PAUSE Multicast DA [Invalid DA field Normal frame]
a) Generate a frame by placing Pause unique address (01-80-C2-00-00-01);
Mac should discard this frame (should not be a PAUSE frame type)
2) PAUSE frame with invalid DA (only when addresses are not valid )
a) Generate a Pause frame with DA other than pause unique Multicast address (0180-C2-00-00-01) by placing following address values in DA field
[Invalid DA PAUSE tagged frame]
All zeros(0000000000000)
All ones(11111111111111)
SFD or PRE pattern(10101011)
Random values
b) Repeat (a) for untagged PAUSE frame [Invalid DA PAUSE untagged frame]
Repeat bad frames mentioned above with each frame followed and preceded by a
References:
IEEE STD 802.3-2005 - Subclasses 3.2.3.1,3.2.4
O-REILY-Ethernet Definitive Guide. PDF
SOURCE ADDRESS (SA)

Discussion:
The Source MAC Address (6 bytes) identifies the station that originated the frame
and it is always an individual address. The 1st bit (LSB) is reserved and always set
to"0".
This is the physical address of the interface that sends the frame. The source
address is not interpreted in any way by the Ethernet MAC protocol. Instead, it is
provided for the use of high-level protocols. An Ethernet station uses its physical
address as the source address in any frame it transmits.
[IEEE standard does not specifically state that an interface may have the ability to
override the 48-bit physical address assigned by the manufacturer. However, all
Ethernet interfaces in use these days appear to allow the physical address to be
changed, which makes it possible for the network administrator or the high level
network software to modify the Ethernet interface address]
Valid Frame
Generate a frame by placing valid 6bytes of source address ensuring first bit with "0"
Invalid Frame
1) A Frame with 6bytes of invalid SA(only when following are invalid addresses)
[Invalid SA field Normal frame]
a) Generate a frame by placing following invalid address values
All zeros (000000...)
All ones (1111111...)
Random value
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3) A frame with invalid SA by making 0th bit as 1 ,Receiving MAC should discard
packet
References:
IEEE STD 802.3-2005 - Subclasses 3.2.3,3.2.5
DATA / PAD Field

Discussion:
Data Field contains the data transferred from the source station to the destination
station or stations
The maximum size of this field is 1500 bytes
The minimum size of this field is 46bytes
The maximum size of the data field is determined by the maximum frame size and
address size parameters of the particular implementation
PAD
If the size < 46 bytes, then use of the subsequent "Pad" field is necessary to bring
the frame size up to the minimum length.
If necessary, extra data bytes are appended in this field to bring the frame length up
to its minimum size.
The size of the pad, if any is determined by the size of the data field supplied by the
MAC client and the minimum frame size and address size parameters.
Full data transparency is provided in the sense that any arbitrary sequence of octet
values may appear in the data field up to a maximum number specified by the
implementation of the standard that is used.
Length value indicated in Length/Type field is compared with the Data length in
Data field
Length>Data length - Length error (loss of Data bits)
Length
Length=Data length - no padding required
For a padded Frame of Length (<46) in Length/Type field then data length should
be always greater than the value in length field.
Padding is always performed only using all zero values.
Valid Frame
1) A Frame with data length (>=46) and (<=1500)
Generate a frame with data range between min and max Data lengths by placing
the following data in Data field
All zeros (000000...)
All ones (1111111...)
Random values
Invalid Frame
1) Generate a Tagged frame of length (<46) in Length/Type field but data field length
shows value (<46) even after padding is performed by transmitter Mac. [Padded
Tagged frame < min size]
2) A Frame with excess Padding [Frame with Excess Padding]
a) Generate a frame of length (<46) in Length/Type field but data field length
shows value (>46-excess) even after padding is performed by transmitter Mac
b) Generate a frame of length (<46) in Length/Type but data field length shows
value(>46-excess) and it has violated the maximam size
(Mac should discard the packet if excess padding violates the maximam size)
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3) A Frame of length (>46) in Length/Type field but data field shows the length less
than the length shown in Length field. [Frame with Length error(loss of Data bits)]
{Suppose length field has 70 but data length is 60bytes then what about remaining
10bytes?}
4) A Frame with invalid padding
Generate a frame of length (<46 bytes) in Length field and pad with the following
values
All ones (1111111...)
Random values
References:
IEEE STD 802.3-2005 - Subclasses 3.1.1,3.2.7 Mac Frame Format
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About the author:
Introduction to PCI Express
Arjun Shetty
is perusing Master of
We will start with a conceptual understanding of PCI Express. This will let us Technology in VLSI &
appreciate the importance of PCI Express. This will be followed by a brief study of the Embedded Systems in
PCI Express protocol. Then we will look at the enhancements and improvements of the International Institute
Of Information
protocol in the newer 3.0 specs.
Technology, Hyderabad
1 Basic PC system architecture
Arjuns Blog
We will start by looking at the basic layout of a PC system. Logically, an average PC

system is laid out in something like shown in the figure.
The core logic chipset acts as a switch or router, and routes I/O traffic among the Report a Bug or Comment
different devices that make up the system.
input is what keeps
In reality, the core logic chipset is split into two parts: the northbridge and the Testbench.in improving
southbridge (or I/O bridge). This split is there for a couple of reasons, the most with time!
important of which is the fact that there are three types of devices that naturally
work very closely together, and so they need to have faster access to each other: the
CPU, the main memory, and the video card. In a modern system, the video card's GPU
is functionally a second (or third) CPU, so it needs to share privileged access to main
memory with the CPU(s). As a result, these three devices are all clustered together
off of the northbridge.
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The northbridge is tied to a secondary bridge, the southbridge, which routes traffic
from the different I/O devices on the system: the hard drives, USB ports, Ethernet
ports, etc. The traffic from these devices is routed through the southbridge to the
northbridge and then on to the CPU and/or memory.
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As is evident from the diagram above, the PCI bus is attached to the southbridge. This
bus is usually the oldest, slowest bus in a modern system, and is the one most in need
of an upgrade.
The main thing that we should take away from the previous diagram is that the
modern PC is a motley collection of specialized buses of different protocols and
bandwidth capabilities. This mix of specialized buses designed to attach different
types of hardware directly to the southbridge is something of a continuously evolving
hack that has been gradually and collectively engineered by the PC industry as it tries
to get around the limitations of the aging PCI bus. Because the PCI bus can't really cut
it for things like Serial ATA, Firewire, etc., the trend has been to attach interfaces
for both internal and external I/O directly to the southbridge. So today's southbridge
is sort of the Swiss Army Knife of I/O switches, and thanks to Moore's Curves it has
been able to keep adding functionality in the form of new interfaces that keep
bandwidth-hungry devices from starving on the PCI bus.
In an ideal world, there would be one primary type of bus and one bus protocol that
connects all of these different I/O devices ? including the video card/GPU ? to the
CPU and main memory. Of course, this "one bus to rule them all" ideal is never, ever
going to happen in the real world. It won't happen with PCI Express, and it won't
happen with Infiniband (although it technically could happen with Infiniband if we
threw away all of today's PC hardware and started over from scratch with a round of
natively Infiniband-compliant devices).
Still, even though the utopian ideal of one bus and one bus protocol for every device
will never be achieved, there has to be way bring some order to the chaos. Luckily for
us, that way has finally arrived in the form of PCI Express (a.k.a. PCIe).
2 A primer on PCI
Before we go into detail on PCIe, it helps to understand how PCI works and what its
limitations are.
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The PCI bus debuted over a decade ago at 33MHz, with a 32-bit bus and a peak
theoretical bandwidth of 132MB/s. This was pretty good for the time, but as the rest
of the system got more bandwidth hungry both the bus speed and bus width were
cranked up in a effort keep pace. Later flavors of PCI included a 64-bit, 33MHz bus
combination with a peak bandwidth of 264MB/s; a more recent 64-bit, 66MHz
combination with a bandwidth of 512MB/s.
PCI uses a shared bus topology to allow for communication among the different
devices on the bus; the different PCI devices (i.e., a network card, a sound card, a
RAID card, etc.) are all attached to the same bus, which they use to communicate
with the CPU. Take a look at the following diagram to get a feel for what a shared
bus looks like.
Because all of the devices attached to the bus must share it among themselves, there
has to be some kind of bus arbitration scheme in place for deciding who gets access
to the bus and when, especially in situations where multiple devices need to use the
bus at the same time. Once a device has control of the bus, it becomes the bus
master, which means that it can use the PCI bus to talk to the CPU or memory via the
chipset's southbridge.
The shared bus topology's main advantages are that it's simple, cheap, and easy to
implement ? or at least, that's the case as long as you're not trying to do anything too
fancy with it. Once you start demanding more performance and functionality from a
shared bus, then you run into its limitations. Let's take a look at some of those
limitations, in order to motivate our discussion of PCI Express's improvements.
This scheme works fine when there are only a few devices attached to the bus,
listening to it for addresses and data. But the nature of a bus is that any device that's
attached to it and is "listening" to it injects a certain amount of noise onto the bus.
Thus the more devices that listen to the bus ? and thereby place an electrical load on
the bus ? the more noise there is on the bus and the harder it becomes to get a clean
signal through.
2.1 Summary of PCI's shortcomings

To summarize, PCI as it exists today has some serious shortcomings that prevent it
from providing the bandwidth and features needed by current and future generations
of I/O and storage devices. Specifically, its highly parallel shared-bus architecture
holds it back by limiting its bus speed and scalability, and its simple, load-store, flat
memory-based communications model is less robust and extensible than a routed,
packet-based model.
3 PCI-X: wider and faster, but still outdated

The PCI-X spec was an attempt to update PCI as painlessly as possible and allow it to
hobble along for a few more years. This being the case, the spec doesn't really fix any
of the inherent problems outlined above. In fact, it actually makes some of the
problems worse.
The PCI-X spec essentially doubled the bus width from 32 bits to 64 bits, thereby
increasing PCI's parallel data transmission abilities and enlarging its address space.
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The spec also ups PCI's basic clock rate to 66MHz with a 133MHz variety on the high
end, providing yet another boost to PCI's bandwidth and bringing it up to 1GB/s (at
133MHz).
The latest version of the PCI-X spec (PCI-X 266) also double-pumps the bus, so that
data is transmitted on the rising and falling edges of the clock. While this improves
PCI-X's peak theoretical bandwidth, its real-world sustained bandwidth gains are more
modest.
While both of these moves significantly increased PCI's bandwidth and its usefulness,
they also made it more expensive to implement. The faster a bus runs, the sensitive it
becomes to noise; manufacturing standards for high-speed buses are exceptionally
strict for this very reason; shoddy materials and/or wide margins of error translate
directly into noise at higher clock speeds. This means that the higher-speed PCI-X bus
is more expensive to make.
The higher clock speed isn't the only thing that increases PCI-X's noise problems and
manufacturing costs. The other factor is the increased bus width. Because the bus is
wider and consists of more wires, there's more noise in the form of crosstalk.
Furthermore, all of those new wires are connected at their endpoints to multiple PCI
devices, which means an even larger load on the bus and thus more noise injected
into the bus by attached devices. And then there's the fact that the PCI devices
themselves need 32 extra pins, which increases the manufacturing cost of each
individual device and of the connectors on the motherboard.
All of these factors, when taken together with the increased clock rate, combine to
make the PCI-X a more expensive proposition than PCI, which keeps it out of
mainstream PCs. And it should also be noted that most of the problems with
increasing bus parallelism and double-pumping the bus also plague recent forms of
DDR, and especially the DDR-II spec.
And after all of that pain, you still have to deal with PCI's shared-bus topology and all
of its attendant ills. Fortunately, there's a better way.
4 PCI Express: the next generation

PCI Express (PCIe) is the newest name for the technology formerly known as 3GIO.
Though the PCIe specification was finalized in 2002, PCIe-based devices have just now
started to debut on the market.
PCIe's most drastic and obvious improvement over PCI is its point-to-point bus
topology. Take a look at the following diagram, and compare it to the layout of the
PCI bus.
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In a point-to-point bus topology, a shared switch replaces the shared bus as the
single shared resource by means of which all of the devices communicate. Unlike in a
shared bus topology, where the devices must collectively arbitrate among themselves
for use of the bus, each device in the system has direct and exclusive access to the
switch. In other words, each device sits on its own dedicated bus, which in PCIe lingo
is called a link.
Like a router in a network or a telephone switchbox, the switch routes bus traffic and
establishes point-to-point connections between any two communicating devices on a
system.
4.1 Enabling Quality of Service

The overall effect of the switched fabric topology is that it allows the "smarts" needed
to manage and route traffic to be centralized in one single chip ? the switch. With a
shared bus, the devices on the bus must use an arbitration scheme to decide among
themselves how to distribute a shared resource (i.e., the bus). With a switched
fabric, the switch makes all the resource-sharing decisions.
By centralizing the traffic-routing and resource-management functions in a single
unit, PCIe also enables another important and long overdue next-generation function:
quality of service (QoS). PCIe's switch can prioritize packets, so that real-time
streaming packets (i.e., a video stream or an audio stream) can take priority over
packets that aren't as time critical. This should mean fewer dropped frames in your
first-person shooter and lower audio latency in your digital recording software.
4.2 Traffic runs in lanes

When PCIe's designers started thinking about a true next-generation upgrade for PCI,
one of the issues that they needed to tackle was pin count. In the section on PCI
above, I covered some of the problems with the kind of large-scale data parallelism
that PCI exhibits (i.e. noise, cost, poor frequency scaling, etc.). PCIe solves this
problem by taking a serial approach.
As I noted previously, a connection between two a PCIe device and a PCIe switch is
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called a link. Each link is composed of one or more lanes, and each lane is capable of
transmitting one byte at a time in both directions at once. This full-duplex
communication is possible because each lane is itself composed of one pair of signals:
send and receive.
In order to transmit PCIe packets, which are composed of multiple bytes, a one-lane
link must break down each packet into a series of bytes, and then transmit the bytes
in rapid succession. The device on the receiving end must collect all of the bytes and
then reassemble them into a complete packet. This disassembly and reassembly
happens must happen rapidly enough to where it's transparent to the next layer up in
the stack. This means that it requires some processing power on each end of the link.
The upside, though, is that because each lane is only one byte wide, very few pins are
needed to transmit the data. You might say that this serial transmission scheme is a
way of turning processing power into bandwidth; this is in contrast to the old PCI
parallel approach, which turns bus width (and hence pin counts) into bandwidth. It so
happens that thanks to Moore's Curves, processing power is cheaper than bus width,
hence PCIe's tradeoff makes a lot of sense.
We saw earlier that a link can be composed of "one or more lanes", so us clarify that
now. One of PCIe's nicest features is the ability to aggregate multiple individual lanes
together to form a single link. In other words, two lanes could be coupled together to
form a single link capable of transmitting two bytes at a time, thus doubling the link
bandwidth. Likewise, you could combine four lanes, or eight lanes, and so on.
A link that's composed of a single lane is called an x1 link; a link composed of two
lanes is called an x2 link; a link composed of four lanes is called an x4 link, etc. PCIe
supports x1, x2, x4, x8, x12, x16, and x32 link widths.
PCIe's bandwidth gains over PCI are considerable. A single lane is capable of
transmitting 2.5Gbps in each direction, simultaneously. Add two lanes together to
form an x2 link and you've got 5 Gbps, and so on with each link width. These high
transfer speeds are good, good news, and will enable a new class of applications, like
SLI video card rendering.
5 PCIe Protocol Details

Till now we were concerned with the system level impact of PCIe. We did not look at
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the protocol itself. The following material will make an attempt to explain the details
of PCIe protocol, its layers and the functions of each of the layers in a brief way.
PCI Express is a high performance, general purpose I/O interconnect defined for a
wide variety of future computing and communication platforms.
5.1 PCIe Link

A Link represents a dual-simplex communications channel between two components.
The fundamental PCI Express Link consists of two, low-voltage, differentially driven
signal pairs: a Transmit pair and a Receive pair
5.2 PCIe Fabric Topology
5.2.1 Root Complex

A Root Complex (RC) denotes the root of an I/O hierarchy that connects the
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CPU/memory subsystem to the I/O.

5.2.2 Endpoints
Endpoint refers to a type of Function that can be the Requester or Completer of a PCI
Express transaction either on its own behalf or on behalf of a distinct non-PCI Express
device (other than a PCI device or Host CPU), e.g., a PCI Express attached graphics
controller or a PCI Express-USB host controller. Endpoints are classified as either
legacy, PCI Express, or Root Complex Integrated Endpoints.
5.2.3 PCI Express to PCI/PCI-X Bridge
A PCI Express to PCI/PCI-X Bridge provides a connection between a PCI Express fabric
and a PCI/PCI-X hierarchy.
5.3 PCI Express Layering Overview
PCI Express can be divided into three discrete logical layers: the Transaction Layer,
the Data Link Layer, and the Physical Layer. Each of these layers is divided into two
sections: one that processes outbound (to be transmitted) information and one that
processes inbound (received) information.
PCI Express uses packets to communicate information between components. Packets

are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can
be processed by the Transaction Layer of the receiving device. Figure below shows the
conceptual flow of transaction level packet information through the layers.
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Note that a simpler form of packet communication is supported between two Data
Link Layers (connected to the same Link) for the purpose of Link management.
5.4 Layers of the Protocol
We take a brief look at the functions of each of the 3 layers.
5.4.1 Transaction Layer
This is the top layer that interacts with the software above.
Functions of Transaction Layer:
1. Mechanisms for differentiating the ordering and processing requirements of
Transaction Layer Packets (TLPs)
2. Credit-based flow control
3. TLP construction and processing
4. Association of transaction-level mechanisms with device resources including Flow
Control and Virtual Channel management
5.4.2 Data Link Layer
The Data Link Layer acts as an intermediate stage between the Transaction Layer and
the Physical Layer. Its primary responsibility is to provide a reliable mechanism for
exchanging Transaction Layer Packets (TLPs) between the two components on a Link.
Functions of Transaction Layer:
1. Data Exchange:
2. Error Detection and Retry:
3. Initialization and power management:
5.4.3 Physical Layer
The Physical Layer isolates the Transaction and Data Link Layers from the signaling
technology used for Link data interchange. The Physical Layer is divided into the
logical and electrical subblocks.
Logical Sub-block
Takes care of Symbol Encoding, framing, data scrambling, Link initialization and
training, Lane to lane de-skew
Electrical Sub-block
The electrical sub-block section defines the physical layer of PCI Express 5.0 GT/s
that consists of a reference clock source, Transmitter, channel, and Receiver. This
section defines the electrical-layer parameters required to guarantee interoperability
among the above-listed PCI Express components. This section comprehends both 2.5
GT/s and 5.0 GT/s electricals. In many cases the parameter definitions between 2.5
and 5.0 GT/s are identical, even though their respective values may differ. However,
the need at 5.0 GT/s to minimize guardbanding, while simultaneously comprehending
all phenomena affecting signal integrity, requires that all the PCI Express system
components - Transmitter, Receiver, channel, and Refclk, be explicitly defined in the
specification. For this reason, each of these four components has a separate
specification section for 5.0 GT/s.
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6 Changes in PCIe 3.0 (GEN3)
The goal of the PCI-SIG work group defining this next-generation interface was to
double the bandwidth of PCIe Gen 2, which is 5 gigatransfers per second (GT/s)
signaling but 4GT/s effective bandwidth after 8b/10b encoding overhead. The group
had two choices: either to increase the signaling rate to 10GT/s with 20 percent
encoding overhead or select a lower signaling rate (8GT/s) for better signal integrity
and reduced encoding overhead with a different set of challenges. The PCI-SIG
decided to go with 8GT/s and reduce the encoding overhead to offer approximately
7.99GT/s of effective bandwidth, approximately double that of PCIe Gen 2. The
increase in signaling rate from PCIe Gen 2's 5GT/s to PCIe Gen 3's 8GT/s provides a
sixty percent increase in data rate and the remainder of the effective bandwidth
increase comes from replacing the 8b/10b encoding (20 percent inefficiency) with
128b/130b coding (1-2 percent inefficiency). The challenge of moving from PCIe Gen 2
to Gen 3 is to accommodate the signaling rate where clock timing goes from 200ps to
125ps, jitter tolerance goes from 44ps to 14ps and the total sharable band (for SSC)
goes down from 80ps to 35ps. These are enormous challenges to overcome but the
PCI-SIG has already completed board, package, and system modeling to make sure
designers are able to develop systems that support these rates. The table below
highlights some key aspects of PCIe Gen 2 and Gen 3. The beauty of the Gen 3 solution
is that it will support twice the data rate with equal or lower power consumption than
PCIe Gen 2. Additionally, applications using PCIe Gen 2 would be able to migrate
seamlessly as the reference clock remains at 100MHz and the channel reach for
mobiles (8 inches), clients (14 inches), and volume servers (20 inches) stay the same.
More complex equalizers, such as decision feedback equalization, may be
implemented optionally for extended reach needed in a backplane environment. The
Gen 3 specification will enhance signaling by adding transmitter de-emphasis,
receiver equalization, and optimization of Tx/Rx Phase Lock Loops and Clock Data
Recovery. The Gen 3 specification also requires devices that support Gen 3 rate to
dynamically negotiate up or down to/from Gen 1 and Gen 2 data rates based on
signal/line conditions.
6.1 Benefits from the newer specs:6.1.1 Higher Speed

Goal: improve performance. Each successive generation doubles the bit rate of the
previous generation, and that holds true for Gen3, too, but theres a significant
difference this time. Since the previous speed was 5.0 GT/s, the new speed would
normally have been 10.0 GT/s, but the spec writers considered a signal that used a
10GHz clock problematic because of the board design and signal integrity issues that
many vendors would face. Constrained to stay under that frequency, they were forced
to consider other options. The solution they chose was to move away from the 8b/10b
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encoding scheme that PCIe and most other serial transports have used because it adds
a 20% overhead from the receivers perspective. Instead, they chose a modified
scrambling method that effectively creates a 128/130 encoding method. This gain in
efficiency meant that an increase in frequency to only 8.0GHz would be enough to
achieve a doubling of the bandwidth and meet this goal
6.1.2 Resizable BAR Capability
Goal: allow the system to select how much system resource is allocated to a device.
This new optional set of registers allows functions to communicate their resources
size options to system software, which can then select the optimal size and
communicate that back to the function. Ideally, the software would use the largest
setting reported, since that would give the best performance, but it might choose a
smaller size to accommodate constrained resources. Currently, sizes from 1MB to
512GB are possible. If these registers are implemented, there is one capability
register to report the possible sizes, and one control register to select the desired size
for each BAR. Note that devices might report a smaller size by default to help them
be compatible in many systems, but using the smaller size would also reduce its
performance.
6.1.3 Dynamic Power Allocation
Goal: provide more software-controlled power states to improve power management
(PM). Some endpoint devices dont have a device-specific driver to manage their
power efficiently, and DPA provides a means to fill that gap. DPA only applies when
the device is in the D0 state, and it defines up to 32 substates. Substate0 (default)
defines the max power, and successive sub-states have a power allocation equal to or
lower than the previous one. Software is permitted to change the sub-states in any
order. The Substate Control Enabled bit can be used to disable this capability. Any
time the device is changing between substates, it must always report the highest
power requirement of the two until the transition has been completed, and the time
needed to make the change is implementation specific.
To allow software to set up PM policies, functions define two transition latency values
and every substate associates its max transition time (longest time it takes to enter
that substate from any other substate) with one of those.
6.1.4 Alternative Routing-ID Interpretation
Goal: support a much larger number of functions inside devices. For requesters and
completers, this means treating the device number value as though it was really just
an extension of the function field to give an 8-bit value for the function number.
Since the device number is no longer included, its always assumed to be 0. The spec
also defines a new set of optional registers that can be used to assign a function
group number to each function. Within an ARI device, several functions can be
associated with a single group number, and that can serve as the basis for arbitration
or access control.
References:
www.arstechnica.com
www.pcisig.com
www.pcstats.com
www.digitalhomedesignline.com
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VCSMX Separate compilation example
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AVM Switch TB
When I started to use VCSMX along with system Verilog, one main problem came up: I
had to generate one executable for each program.
Coming up with VCSMX version 2008.12, the separate compile feature was introduced
to solve the problem; anyway the working model is quite strict. I used as a starting
point "switch" example from www.testbench.in to illustrate the separate compile
flow. The idea is to generate a partition of your program file that would be loaded
when you launch your executable. A single image of your design is needed; if you
change your program file, you would only need to analyze it and generate a new
partition. Please have a look to the Makefile provided along with the testcase. The
version 2008.12-2 of VCSMX was used to set up the testcase.
1. Compile your DUT
comp_dut
2. Compile the testbench components for a given package.
comp_pack
- Analyze the code with vlogan..
- Generate shared object libraries for each package with VCS.
- Repeat these steps for each package.
In VMM methodology, a class should be defined within a package, Driver.sv, packet.sv
VMM Ethernet sample and environment.sv are now system verilog packages.
Partition should also be generated for packages [separate compile feature steps]
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Verification
3. Compile the testcases.

comp_prg
Verilog Switch TB
- Analyze the code with vlogan and specify a unique partition name for each testcase.
Basic Constructs
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- Generate shared object libraries for different program partitions with VCS.
4. Generate a program shell file from the program block.
gen_shell
This shell file is used for compiling the main simv in order to provide a hook for
dynamic linking of the testbench at runtime. The testcases must have the same
program block name so that only one shell file is required to load the testcases.
5. Analyze the top level testbench file:
comp_top
You must compile in different libraries the test bench files and the design part. rtl.sv '
current Driver.sv, packet.sv, environment.sv and interface.sv ' testcase Top.sv
interface.sv ' current Interface.sv is analyzed twice but in current and testcases
libraries. This is due to the separate compile feature and also because environment.sv
and top.sv instantiates interfaces.
6. Generate simv, which includes the DUT, program shell file, and top module to link
the DUT with the program shell file.
elab
7. Run simulations using the generated simv, specifying the partitions that need to be
loaded
http://testbench.in/vcsmx_separate_compilation.html[9/26/2012 2:54:22 PM]
Emmanuelle Chu
is EDA support engineer
at Texas Instruments
(Nice Area, France). She
is with TI from 2004.
Emmanuelle Chu is an
master in Electronics
and computers from
ENSSAT.

input is what keeps
with time!
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run
Repeat steps 3 or 4 followed by step 7 to further develop the testbench or testcases,
and later in the testing cycle, to run your tests and regressions.
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PSYCHOLOGY OF VERIFICATION ENGINEER
Gopi Krishna He is the

Broadly speaking, we can view Verification Engineer as having two kinds of skills: one Author of testbench.in.
set used to perform basic duties at work, and another set of skills used to approach
work. The former can be categorized as technical skills and the latter as soft skills.
While the technical skills are absolutely important for a Verification Engineer, there
are certain soft skills that should complement the technical abilities. A
comprehensive Verification engineer should have a blend of the technical and soft
skills.
DPI
To elaborate more on soft skills, these are the ones that define one's approach
towards work, life, problems, etc. Soft skills are people skills. The best part about
mastering them is that the application of these skills is not limited to one's profession,
VMM Tutorial
but their scope reaches all aspects of life. Technical skills may teach one how to meet
OVM Tutorial
the expectations of the job, but soft skills teach one to succeed, and to exceed
expectations. There are many situations that we come across on the day-to-day work
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life as a Verification engineer in which one person perform better than the others just
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on the basis of Soft skills- be it winning an argument with RTL designer on the basis of
his/her communication or finding handling multiple tasks effectively because if
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superior organizational abilities etc.
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Soft skills are extremely important for the people in Verification and this is something
AVM Switch TB
that is often found to be neglected by the upcoming Verification engineers. It is
VMM Ethernet sample surprising that we spend our time educating almost exclusively in technical skills.
UVM Tutorial
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
About the author:
Human beings reaction in this complex world of happenings varies widely with respect
to situations, surroundings, emotions, need, requirements, time frame, money,
visualization, belief, education, knowledge, expertise, intuition and so on. Such
complex is the nature of human being and certainly there's no exception at work place
too. Therefore it's cynical to say that the job being done by a Verification Engineer is
simple & complete.
The quality of the job done by the verification engineer is directly proportional to his
or her psychological maturity and profoundness acquired, adopted and developed with
age and experience.
Let's examine the psychology of the verification engineer by describing the definition
of Verification under three circumstances.
"Functional Verification is the process to prove that the RTL works as per the
specification"
"Functional verification is the process to find all the bugs present in the RTL design"
"Functional Verification is the process to detect the defects and minimize the risks
associated with the residual defects"
Above three definitions are upside-down. Understanding the true definition of
Functional verification can make a profound difference in the success of your efforts.
1)
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input is what keeps
with time!
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"Functional Verification is the process to prove that the RTL works as per the
specification"
Generally this definition is given by the RTL designers or the new verification
engineers with prior RTL design experience. The above definition sounds good if the
RTL designer itself is trying to verify his implementation .RTL designer intentions
would mostly revolve around the point to prove that the RTL meets the specification.
RTL designer will exercise only those inputs for which the correct results are obtained
and are specified in the specification and the DUT can still contain bugs which will not
be visible.
2)
"Functional verification is the process to find all the bugs present in the RTL design"
This definition sounds good epically if the main aim of the verification engineer is to
prove that the RTL work for what it's supposed to do and not what is not supposed to
do. This type of psychology would bring out the most of the bugs in the RTL.This goal
is impossible to achieve.
3)
"Functional Verification is the process to detect the defects and minimize the risks
associated with the residual defects"
This definition appears to sound realistic. Practically, if at any point, the RTL
development starts, the verification should start and keep in track the number of bugs
being detected while correcting.
At some stage of a planned verification, there would be a stage where no bugs are
identified after many days or weeks or sometimes months of verification which
statistically allows you to conclude that the RTL is "good enough" to be released to
next step. i.e. there may still exist some bugs undetected, but the risk associated with
the residual defects is not very high or are tolerable.
From the above three definitions, we can understand that the psychology of a
verification engineer plays a vital role throughout the ASIC development cycle.
Role And Characteristics Of A Verification Engineer
Verification Engineer requires technical skills similar to RTL designers, but Verification
engineers need to acquire other skills, as well.
Most engineers that I've talked to over the years believe that the mind-set and
personality of a good Verification engineer are different from those of a good RTL
designers. For example Verification engineer are more experimental then RTL
designers.
Keen Observation
Detective Skills
Deduction skills
Destructive Creativity and Negative Thinking
Understanding the DUT as an integration of its parts
Cynical but Affable Attitude
Organized, Flexible and Patience at Job
Objective and Neutral Attitude
Discipline and Perseverance
Communication Skills
Learning from Past
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Eagerness to embrace new technologies, methods and flows

Keen Observation
The Verification engineer must possess the qualities of an 'eye for detail'. A keen
observation is the prime quality any Verification engineer must possess. Not all bugs
are visible clearly to the naked eye. With keen observation, the Verification engineer
can easily identify or detect many critical bugs. Verification engineer should learn
how to look for details, how to analyze the things from different possible dimensions.
The more observant a verification engineer is, the more likely he is detecting more
bugs.
Without observation, it is impossible to tell the outcome of a test or an experiment.
Although this makes sense, it is tempting to design tests and experiments that are
difficult if not impossible to observe. We may want to prove or test something, but
real-world constraints prevent constructing an accurate experiment. That's why you
can't verify everything and not everything is verifiable.
Detective Skills
Ideally the Design under development would be documented before, after and
throughout the development process. Unfortunately, there is every chance of not
updating the documentation (specification, defect reports etc) due to time and
resource constraints.
The Verification engineer should therefore apply his knowledge of rationalization in
knowing about the DUT from formal system like system specifications, design &
functional specifications, review notes etc. From this information, the Verification
engineer should look for researching more analytical information through other
sources called non-formal sources of information like RTL designers, previous version
test plans, bugs and related product documents, reviews of related and (seemingly)
unrelated documents.
A Verification engineer should therefore possess the quality of a 'detective' to explore
the product under test, more rationally
Deduction Skills
A Verification engineer with deduction skills is also likely to be good at issue solving.
Deduction skill is an ability to analyze the meanings of the signs and deriving of a
conclusion by reasoning. It's a logical thinking, which helps a Verification engineer to
differentiate a bug from a false one. Deduction skills may come from practice of
cognitive information processing, power of interpretation and can help a Verification
engineer in differencing and decision making.
Deduction skills play major role while debugging. Not all the verification engineers
can debug an issue at same speed. Looking at some waveform signals, log messages,
he has to isolate or locate it. In Verification life cycle, everything can be planned and
can meet the schedule in time except debugging. Time spent in debugging is
unpredictable and cannot be planned ahead.
Destructive Creativity Or Negative Thinking
Most human beings are constructive in nature rather than destructive.
The Verification engineer need to develop destructive skills ,means skills to perturb
and crash RTL functionality. In other words, the Verification engineer should 'not
hesitate to break the RTL functionality. In the world of functional verification,
boundaries are meant to be crossed not obeyed.
A creative oriented but destructive approach is necessary while verifying a RTL by the
Verification engineer to make the RTL Design evolve more robustly and reliably.
Negative Thinking is a art. While mentioning the risks involved in the project, a
Verification engineer has to consider all the things that can go wrong. Training the
mind to think negatively in required situations helps Verification engineer develop an
efficient contingency plan.
A word of caution here; distractive skills are useful only for specific situations. A
Verification engineer has to be smart enough to identify such situations and wear an
appropriate thinking hat to deal with the situation.
Understanding The Dut As An Integration Of Its Parts
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The RTL design is a culmination of lines of code interacting with data through user
interfaces. It is an integration of separate group of code interacting with other groups
assembled together to function as a whole chip. The developers might be working on
a respective piece of code module focusing more on those modules under work, at a
time.
It is no wonder if the developer sometimes may not even know the complete workflow
of the RTL and not necessary too. Whereas, in the case of a Verification engineer,
being the rider of the DUT, should understand and know about the complete
specifications of the DUT.
The Verification engineer may not be the best expert on any one module of the RTL
but definitely he/she should gain expertise on the overall operation of the RTL
Design. In fact, the Verification engineer should possess a 'Systems' view of the RTL
design because they are the only people to see and verify the complete functionality
of interdependent modules and compatibility.
Cynical But Affable Attitude
Irrespective of the nature of the RTL design, the Verification engineer need to be
tenacious in questioning even the smallest ambiguity until it is proved.
There may arise some situations during the course of verification , a large number of
bugs might be encountered unusually which might compel to further delay in RTL
freezing. This may lead to heat up the relation between the Verification engineer and
RTL design teams. The Verification engineer should balance this relationship not at
the cost of the bugs but by convincing and upholding their intentions to "assault the
RTL design but not the RTL developers".
Organized, Flexible And Patience At Job
Verification engineer must remember the fact that not all the tests planned are
performed completely and some tests dependent on other tests has to be blocked for
later testing. We manage ourselves, our tasks, so that we make the most of our time.
Verification engineer have to juggle a lot of tasks.
This needs an organized approach by the Verification engineer in attempting to phase
out the bugs. Sometimes, significant tests has to be rerun which would change the
fundamental functionality of the RTL design. The Verification engineer should
therefore have patience to retest the planned bugs and any new bugs that may arise.
It is even more important to the Verification engineer to be patient and keep
prepared in the event of a dynamic development and test model. Development keeps
changing continuously as requirements and technology keeps changing rapidly and so
should Verification. The Verification engineer must take these changes into account
and plan to perform tests while maintaining the control of Verification environment to
ensure valid test results.
Objective And Neutral Attitude
Nobody would like to hear and believe bad news, right? Well, Verification engineer
are sometimes viewed as messengers of bad news in a team. No wonder, how good
the Verification engineer is (meaning very negative) and brilliant in doing his job
(identifying bugs-no one likes to do it but most human beings are taken for granted to
be naturally very good at it, at least from childhood), he/she might always be a
messenger of communicating the bad part, which, the creators (developers) doesn't
like it.
The Verification engineer must be able to deal with the situation where he/she is
blamed for doing his/her job (detecting bugs) too good. The Verification engineer's
jobs must be appreciated and the bugs should be welcomed by the RTL design team
because every potential bug found by the Verification engineer would mean a
reduction of one bug that would potentially might have been encountered in later
stage.
Irrespective of the negative aspects of doing such a highly skillful job, the role of a
Verification engineer is to report honestly every known bug encountered in the
product with always an objective and a neutral attitude.
Discipline And Perseverance
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One obvious aspect of verification is that it can be extremely repetitive and may
require a lot of manual effort. Consider the following situations:
A Verification engineer is struck with a bug that is not reproducible at all the
instances. In order to reproduce the bug he goes through the whole series of steps
again and again.
As part of a daily routine, a Verification engineer has been asked to collect data
about test cases executed, bugs reported, etc.
There can be numerous examples that prove the reiterative nature of the job.
A very predictable reaction to this repetition is to simply get tired of the job. But soft
skills include the psychological tools to persevere, and to find ways to make effort
more productive and interesting. This attitude difference helps a Verification
engineer maintain focus and higher levels of quality work. It brings the ability to carry
out task at hand in spite of difficulty.
Communication Skills
Communication skills form the necessary ingredients for success in any profession.
Communication is something that we always do in our personal lives as well as
professional life. Communication is a very basic human skill and one cannot go very far
without it. Communication in this context does not involve any body language; so it's
the pure word power, which rules the situation. Though most of us agree that these
skills are important, very few of us give these skills a high enough priority. For a VE,
both verbal and written communication is crucial.
If your written communication is bad, you'll miss the salient points - the audience
won't know the important stuff - or you'll put the audience to sleep. This means your
bug reports will bounce back as "invalid" / "unable to reproduce" / "won't fix."
Many instances can be thought of in the day-to-day work of Verification engineer,
where a Verification engineer can make a difference to the situations with effective
communications skills.
Learn From Past
Keep learning from past experience and try not getting caught in any mistakes that
have been made earlier. A common saying is "Never repeat the same mistake again". A
verification engineer should know not only his mistakes, but also the RTL Designers
mistakes. If RTL designers does the same mistake, Verification engineer past
experience on catching the same mistake increases the possibility of the finding the
mistake easily.
Mistakes can be categorizes into 4 categories:
Stupid:
Absurdly dumb things that just happen.
Simple:
Mistakes that are avoidable but your sequence of decisions made inevitable.
Involved:
Mistakes that are understood but require effort to prevent.
Complex:
Mistakes that have complicated causes and no obvious way to avoid next time.
Eagerness To Embrace New Technologies, Methods And Flows
A Verification engineer should have enthusiasm to learn new technologies, methods
and flows and eagerness to progress further. Today's functional verification is still in
research stage. Even most of the terminology is not stable across the industry. As the
research is going on, companies are adopting new technologies and the Verification
engineers should be able to learn them.
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TUTORIALS
SystemVerilog
About the author:
Graphical Test Bench Generation
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Test bench code is often difficult to understand, even when written using modular
programming techniques, because of the large amount of parallel activity occurring in
the test bench that is not apparent when just reading through the code. However,
when that same parallel activity is displayed as waveforms in a timing diagram the
interaction between the signals is obvious from just glancing at the timing diagram.
Timing diagrams allow a much clearer and concise description of the interaction of
parallel processes and signal activity than can be achieved by writing code. A
graphical representation also facilitates the collaboration of many engineers on a
single test bench by removing the need to interpret source code. Any engineer
familiar with the design specifications is able to look at a given timing diagram and
have an immediate understanding of what the transactor does, dramatically Report a Bug or Comment
simplifying test bench maintenance.
input is what keeps
There are several tools on the market that can take basic waveforms and generate Testbench.in improving
simple VHDL and Verilog models. This article will discuss the tools offered by with time!
SynaptiCAD, because they offer three different levels of test bench generation ranging
from simple stimulus test benches, test benches that monitor system reaction during
simulation, to full bus-functional models that behaviorally model the outside system.
We will show examples of timing diagrams and some of the code that they can
generate.
AVM Switch TB
VMM Ethernet sample Level 1: Basic Stimulus Generation
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Donna Mitchell
is Vice President of
Marketing and CoFounder of SynaptiCAD
Sales Inc. Mitchell's
industry experience
includes 20 years of
hardware and software
development.
The most basic of the graphical testbench generation tools can take drawn waveforms
and generate VHDL or Verilog stimulus. This level of test bench generation is great for
generating quick small test benches, because the temporal relationships between
edges are easier to see in a graphical timing diagram then in raw VHDL or Verilog
code. This simple graphical test bench generation can be found in many timing
diagram editors and several graphical simulator-debugging environments. SynaptiCAD
offers it in their WaveFormer Pro timing diagram editor and in their BugHunter Pro
simulation debugging environment.
Below is an image of a simple timing diagram that was drawn in WaveFormer Pro. This
shows how different types of signals, buses, and clocks will generate stimulus code.
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Once a timing diagram is finished, the test bench code can be generated via a simple
http://testbench.in/graphicaltestbench.html[9/26/2012 2:54:38 PM]
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file save operation. WaveFormer generates either a Verilog module or a VHDL

entity/architecture model for the stimulus test bench. This test bench model can then
be instantiated in a user's project and compiled and simulated with the rest of the
design. Below is an example of a timing diagram and some of the VHDL code that was
generated from the timing diagram.
-- Generated by WaveFormer Pro Version
libraryieee,std;
useieee.std_logic_1164.all;
entitystimulus is
port(
SIG0 :outstd_logic:='Z';
SIG1 :outstd_logic_vector(3downto0):="ZZZZ";
SIG2 :outinteger;
SIG3 :outMyColor;
CLK0 :outstd_logic:='Z');
-- more entity code
endstimulus;
architectureSTIMULATOR ofstimulus is
-- some signal and parameter declarations
begin
-- clock and status setup code
-- Clock Process
CLK0_process :process
variableCLK0_low :real;
variableCLK0_high :real;
begin
tb_mainloop :loop
waituntil(tb_status =TB_ONCE)
or(tb_status =TB_LOOPING);
CLK0_high :=CLK0_Period *CLK0_Duty /100.0;
CLK0_low :=CLK0_Period -CLK0_high;
-- more clock code
endloop;
endprocess;
-- Sequence: Unclocked
Unclocked :process
begin
SIG0_driver <='0';
SIG1_driver <=x"3";
SIG2_driver <=1;
SIG3_driver <=Yellow;
waitfor45.0 ns;
SIG1_driver <=x"F";
waitfor5.0 ns;
-- more signal statements
wait;
endprocess;
endSTIMULATOR;
In the generated code, notice that the clock is a parameterized process. Not all tools
generate clock signals this way, but it makes it easy for the user to modify the
operation of the test bench by changing the values of the clock variables.
WaveFormer also supports complex data types and user-defined types. Notice that
SIG1 has a VHDL type of integer. In WaveFormer, the VHDL and Verilog types of signals
can be changed using the Signals Properties dialog. VHDL user-defined types can also
be entered through the same interface as demonstrated by the SIG3 signal.
For larger test benches, the waveform data can be imported from an outside source
like a logic analyzer, simulator, or spreadsheet. For example, if you are designing a
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new ASIC to upgrade an existing communications system, then you can use a logic
analyzer to capture stimulus vectors from the communications system and use
WaveFormer to translate the data into a VHDL test bench to test the new ASIC design.
It is important to investigate whether the test bench tool you are using can read the
type of files that your waveform data is in.
Level 2: Reactive Test Bench Generation
The next level up in graphical test bench generation is to add elements to the timing
diagram that will generate code to check the behavior of the model under test (MUT)
during simulation. In the SynaptiCAD tool line, you can add the Reactive Test Bench
Option to any of the tools that support basic stimulus generation.
In the timing diagram, the user draws both the stimulus waveforms (black) and the
expected output of the model under test (blue waveforms). Samples are added to the
blue expected waveforms to generate specific tests at those points in the diagram.
During simulation if the actual value is different from the expected value at the
sample point, then a report will be generated that describes the discrepancy between
the expected and actual value from the model under test.
Below is a picture of the generated code for the sample that is used to check the
output of the read cycle.
Often reactive test bench tools include a method for repeating sections of the
waveforms. With SynaptiCADs tools the user places marker lines on the diagram to
define the beginning and ending of loops. Loops can also depend on the sampled
values of expected output from the model under test. This way the test bench can be
made to "react" to the behavior of the model under test during simulation.
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Reactive test bench generation often allows the option of creating "clock-based" test
benches as well as the "time-based" test benches currently supported by the stimulus
based generation models. Clock-based test benches delay in clock cycles instead of
times, allowing the user to change his clock frequency without needing to change his
timing diagram. Clock-based test benches are also required when testing using highspeed "cycle-based" simulators.
Level 3: Bus-Functional Model (BFM) Generation
As your test benches become more and more complicated, it will become more
difficult to model them using a single timing diagram as described in the previous two
levels. SynaptiCAD offers TestBencher Pro to overcome this problem. At the time of
this writing TestBencher is the only graphical test bench generator that can take
multiple timing diagrams and generate a complete bus functional model from them.
TestBencher generates a transactor for each timing diagram in the project. A

transactor represents a reusable interface specification of the bus-functional model
that you are creating (e.g., read cycle, write cycle, interrupt cycle). These
transactors are modules for Verilog, entity/architecture pairs for VHDL and classes
for TestBuilder. Regardless of the language, the transactors use the same general
architecture.
Once the transactions are defined, the user writes a sequencer process to apply the
timing diagrams to the model under test. Inside the sequencer process the user can
write behavioral VHDL or Verilog code to pass in variables and process information to
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the transactions. TestBencher also has a graphical interface for assisting the user in
writing the apply calls. Below is an example of a sequencer process that repetitively
applies a write transaction followed by a read transaction. Each time the loop is
performed the delay value is changed so that model is tested over different delay
times.
// Sequencer Process
realdelay0;// delay0 will serve as the index and the delay value
initial
begin
for(delay0 =32.0;delay0 >5.0;delay0 =delay0 -5.0)
begin
// Apply_Tbwrite( addr , data , $realtobits(delay0_min) );
Apply_Tbwrite('hF0,'hAE,$realtobits(delay0));
// Apply_tbread( addr , data , $realtobits(delay0_min) );
Apply_tbread('hF0,'hAE,$realtobits(delay0));
end
Abort_tbglobal_clock;
$fclose(logfile);
end
TestBencher Pro also supports hierarchical BFM design by allowing projects to be

instantiated inside other projects. This lets you develop and verify complex test
benches in an incremental manor. For example, if you are designing a test bench for
an ATM switch, you can develop a project that can transmit an ATM cell to an
interface port on the ATM switch. After you have tested your transmitter project, you
can make it a sub-project and instantiate a copy of it for each different port of the
ATM switch.
Summary of Graphical Test Bench Generation
You can free yourself from the time-consuming process of writing Verilog and VHDL
test benches by hand and instead generate them graphically from timing diagrams
using a timing diagram editor. By using timing diagrams, the engineer can work at a
higher level abstraction, free from the tedious details of the underlying code. This
graphical representation facilitates the collaboration of many engineers on a single
test bench by removing the need to interpret HDL source code. Any engineer familiar
with the design specifications is able to look at a given timing diagram and have an
immediate understanding of what the transaction is doing. This level of abstraction
also provides a great aid in terms of maintainability. The first step in choosing a test
bench generator is to determine the complexity of your expected test bench and then
to pick a tool that can generate that code. This article described the functionality of
test bench tools offered by SynaptiCAD. If you would like to experiment with these
tools you can find more information on the http://www.syncad.com/syn_tb_diff.htm
page of the SynaptiCAD web site.
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Search
TUTORIALS
SystemVerilog
About the author:
Verilog Basic Examples
Nithin Singani
is perusing Master of
Technology in VLSI &
Embedded Systems in
Manipal University,
India.
Verification
Constructs
Interface
OOPS
Randomization
AND GATE
Truth Table
Functional Coverage
input is what keeps
with time!
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog design
//in data flow model
moduleand_gate(
inputa,b,
outputy);
//Above style of declaring ports is ANSI style.Verilog2001 Feature
assigny =a &b;
endmodule
TestBench
Verilog Switch TB
moduletb_and_gate;
regA,B;
wireY;
OpenVera
and_gate a1 (.a(A),.b(B),.y(Y));
Constructs
//Above style is connecting by names

Switch TB
RVM Switch TB
initialbegin
RVM Ethernet sample A =1'b0;
B=1'b0;
#45$finish;
end
Specman E
always#6A =~A;
Interview Questions
always#3B =~B;
always@(Y)
$display("time =%0t \tINPUT VALUES:
Y=%b",$time,A,B,Y);
endmodule
Basic Constructs
\t
A=%b
output
time =0 INPUT VALUES:A=0 B =0output value Y=0
http://testbench.in/verilog_basic_examples.html[9/26/2012 2:54:49 PM]
=%b
\t
output value
WWW.TESTBENCH.IN
time =6 INPUT VALUES:A=1 B=0output value Y =0

time =9 INPUT VALUES:A=1 B =1output value Y =1
time =12INPUT VALUES:A=0 B =0output value Y =0
time =18INPUT VALUES:a=1 b =0output value y =0
XOR GATE
Truth Table
Verilog design
//in Structural model
modulexor_gate (
inputa,b,
outputy);
xorx1(y,a,b);//xor is a built in primitive. While using these primitives you should
follow the connection rules. First signal should be output and then inputs.
endmodule
TestBench
moduletb_and_gate;
regA,B;
wireY;
xor_gate a1 (.a(A),.b(B),.y(Y));
initialbegin
A =1'b0;
B=1'b0;
#45$finish;
end
always#6A =~A;
always#3B =~B;
always@(Y)
$display("time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value Y
=%b",$time,A,B,Y);
endmodule
output
time =0 INPUT VALUES:A=0 B =0output
OR GATE
value
value
value
value
Y =0
Y =1
Y =1
Y =0
WWW.TESTBENCH.IN
Truth Table
Verilog design
//in Behaviour model
moduleor_gate(
inputa,b,
outputregy);
always@(a,b)
y =a |b;
endmodule
TestBench
moduletb_and_gate;
regA,B;
wireY;
or_gate a1 (.a(A),.b(B),.y(Y));
initialbegin
A =1'b0;
B=1'b0;
#45$finish;
end
always#6A =~A;
always#3B =~B;
always@(Y)
$display("time =%0t
=%b",$time,A,B,Y);
\tINPUT
VALUES:
\t
A=%b
=%b
endmodule
output
Half Adder
Truth Table
Verilog design
\t
output
value
WWW.TESTBENCH.IN
modulehalf_adder(
inputa,b,
outputsum,carry);
assignsum=a^b;
assigncarry =a &b;
endmodule
TestBench
moduletb_half_adder;
regA,B;
wireSUM,CARRY;
half_adder HA(.a(A),.b(B),.sum(SUM),.carry(CARRY))
initialbegin
A =1'b0;
B=1'b0;
#45$finish;
end
always#6A =~A;
always#3B =~B;
always@(SUM,CARRY)
$display("time =%0t \tINPUT VALUES: \t A=%b B =%b \t output value SUM =%b CARRY
=%b ",$time,A,B,SUM,CARRY);
endmodule
output
Full Adder
Verilog design
modulefull_adder(
inputa,b,cin,
outputregsum,cout);
always@(*)begin
sum=a^b^cin;
cout =(a&b)+(b&cin)+(cin&a);
end
value
value
value
value
SUM
SUM
SUM
SUM
=0
=1
=1
=0
CARRY =0
CARRY =0
CARRY =0
CARRY =1
WWW.TESTBENCH.IN
endmodule
TestBench
moduletb_full_adder;
regA,B,CIN;
wireSUM,COUT;
full_adder FA(.a(A),.b(B),.sum(SUM),.cin(CIN),.cout(COUT));
initialbegin
A =1'b0;
B=1'b0;
CIN=1'b0;
#45$finish;
end
always#6A =~A;
always#3B =~B;
always#12CIN=~CIN;
always@(SUM,COUT)
$display("time =%0t \tINPUT VALUES: \t A =%b B =%b CIN =%b \t output value
SUM
=%b COUT =%b ",$time,A,B,CIN,SUM,COUT);
endmodule
output
time =0 INPUT VALUES:A =0 B =0 CIN =0output value SUM =0 COUT =0
time =12INPUT VALUES:A =0 B =0 CIN =1output value SUM =1 COUT =0
time =15INPUT VALUES:A =0 B =1 CIN =1output value SUM =0 COUT =1
Ripple CarryAdder(Parameterized and using generate )
Verilog design
ìnclude"full_adder.v"
//Full_added.v contains above defined(Full ADDER) program
moduleripple_carry(a,b,cin,cout,sum);
parameterN=4;
input [N-1:0]a,b;
input cin;
output[N-1:0]sum;
outputcout;
wire[N:0]carry;
assigncarry[0]=cin;
//generate statement without using label is verilog-2005 feature. Generate

statement is verilog-2001 feature.
genvari;
generatefor(i=0;i<N;i=i+1)begin
full_adder FA(.a(a[i]),.b(b[i]),.cin(carry[i]),.sum(sum[i]),.cout(carry[i+1]));
end
endgenerate
assigncout =carry[N];
endmodule
TestBenchUsing $random
WWW.TESTBENCH.IN
moduletb_ripple_carry;
parameterN=4;
reg[N-1:0]A,B;
regCIN;
wire[N-1:0]SUM;
wireCOUT;
ripple_carry RCA(.a(A),.b(B),.cin(CIN),.sum(SUM),.cout(COUT));
initialbegin
A=4'b0000;
B=4'b0000;
CIN=1'b0;
repeat(10)
input_generate(A,B,CIN);
#45$finish;
end
taskinput_generate;
output[N-1:0]A_t,B_t;
outputCIN_t;
begin
#4;
A_t =$random%4;
//Above statement will generate Random values from -3 to +3.
B_t =$random%4;
CIN_t =$random;
end
endtask
taskdisplay;
input[N-1:0]A_td,B_td,SUM_td;
inputCIN_td,COUT_td;
$strobe("Time =%0t \t INPUT VALUES A=%b B=%b CIN =%b \t OUTPUT VALUES SUM
=%b COUT =%b",$time,A_td,B_td,CIN_td,SUM_td,COUT_td);
endtask
always@(SUM,A,COUT)
$display(A,B,SUM,CIN,COUT);
endmodule
output
Time
Time
Time
Time
Time
Time
Time
Time
Time
Time
=0 INPUT VALUES A=0000 B=0000 CIN =0 OUTPUT

Multiplexer(2:1)
Truth Table
VALUES SUM =0000 COUT

=0
=0
=1
=1
=0
=0
=1
=1
=0
=0
WWW.TESTBENCH.IN
Verilog design
modulemux21(
inputa,b,sel,
outputy);
assigny =sel ?b:a;
endmodule
TestBench
moduletb_mux21;
regA,B,SEL;
wireY;
mux21 MUX(.a(A),.b(B),.sel(SEL),.y(Y));
initialbegin
A =1'b0;
B=1'b0;
SEL=1'b0;
#45$finish;
end
always#6A =~A;
always#3B =~B;
always#5SEL=~SEL;
always@(Y)
$display("time =%0t \tINPUT VALUES: \t A=%b B =%b SEL =%b \t output value Y =%b
",$time,A,B,SEL,Y);
endmodule
output
time =0INPUT VALUES: A=0 B =0
SEL
SEL
SEL
SEL
=0 output
=1 output
=1 output
=1 output
value
value
value
value
Y =0
Y =1
Y =0
Y =1
Multiplexer(4:1)
Verilog design
modulemux41(
inputi0,i1,i2,i3,sel0,sel1,
outputregy);
always@(*) //It includes all Inputs. You can use this instead of specifying all
inputs in //sensivity list.Verilog-2001 Feature
begin
case({sel0,sel1})
2'b00:y =i0;
2'b01:y =i1;
2'b10:y =i2;
2'b11:y =i3;
endcase
end
endmodule
WWW.TESTBENCH.IN
TestBench
moduletb_mux41;
regI0,I1,I2,I3,SEL0,SEL1;
wireY;
mux41 MUX(.i0(I0),.i1(I1),.i2(I2),.i3(I3),.sel0(SEL0),.sel1(SEL1),.y(Y));
initialbegin
I0=1'b0;
I1=1'b0;
I2=1'b0;
I3=1'b0;
SEL0=1'b0;
SEL1=1'b0;
#45$finish;
end
always#2I0=~I0;
always#4I1=~I1;
always#6I2=~I1;
always#8I3=~I1;
always#3SEL0=~SEL0;
always#3SEL1=~SEL1;
always@(Y)
$display("time =%0t INPUT VALUES: \t I0=%b I1 =%b I2 =%b I3 =%b SEL0 =%b SEL1 =%b
\t output value Y =%b ",$time,I0,I1,I2,I3,SEL0,SEL1,Y);
endmodule
output
time
time
time
time
time
time
=1
time
=0
=0 INPUT VALUES:I0=0 I1 =0 I2 =0 I3 =0 SEL0 =0 SEL1 =0output value Y =0

=14 INPUT VALUES: I0=1 I1 =1 I2 =1 I3 =0 SEL0 =0 SEL1 =0output value Y
=15 INPUT VALUES: I0=1 I1 =1 I2 =1 I3 =0 SEL0 =1 SEL1 =1output value Y
Encoder(8:3)
*Disadvantage of Encoder is that at a time only one Input is active.

*Output is zero for when all inputs are zero and when enable is zero
Verilog design
WWW.TESTBENCH.IN
moduleencoder83(
inputen,
input[7:0]in,
outputreg[2:0]out);
always@(*)
begin
if(!en)//Active low enable
out =0;
elsebegin
case({in})
8'b0000_0001:out =3'b000;
8'b0000_0010:out =3'b001;
8'b0000_0100:out =3'b010;
8'b0000_1000:out =3'b011;
8'b0001_0000:out =3'b100;
8'b0010_0000:out =3'b101;
8'b0100_0000:out =3'b110;
8'b1000_0000:out =3'b110;
default:out =3'bxxx;
endcase
end
end
endmodule
TestBench using $random and Tasks

moduletb_encoder83;
regen;
reg[7:0]in;
wire[2:0]out;
encoder83 ENC(.en(en),.in(in),.out(out));
initialbegin
en =0;
in =0;
repeat(10)
random_generation(in,en);
#45$finish;
end
taskrandom_generation;
output[7:0]in_t;
outputen_t;
begin
#4;
in_t =$random%8;
en_t =$random;
end
endtask
taskdisplay;
inputen_t;
input[7:0]in_t;
input[2:0]out_t;
$display("time =%0t \t INPUT VALUES \t en =%b in =%b \t OUTPUT VALUES out
=%b",$time,en_t,in_t,out_t);
endtask
always@(out)
display(en,in,out);
endmodule
output
time =0INPUT VALUESen =0 in =00000000OUTPUT VALUES out =000
time =4INPUT VALUESen =1 in =00000100OUTPUT VALUES out =010
WWW.TESTBENCH.IN
time
time
time
time
time
=8INPUT VALUESen =1 in =11111001OUTPUT VALUES out =xxx

=16 INPUT VALUESen =0 in =11111101OUTPUT VALUES out =000
=24 INPUT VALUESen =1 in =00000110OUTPUT VALUES out =xxx
=28 INPUT VALUESen =0 in =00000101OUTPUT VALUES out =000
=40 INPUT VALUESen =1 in =00000101OUTPUT VALUES out =xxx
Priority Encoder(8:3)
Priority Encoder overcomes all drawbacks of encoder.

* At a time more than one input can be active, Based on priority output will come.
* "v" is a valid Indicator, it become HIGH only when at least one input is active. You
candifferentiate the output when enable is zero and when only LSB (in0) is active
Verilog design
modulepriority_enco(
inputen,
input[3:0]in,
outputregv,
outputreg[1:0]out );
integeri;
always@(*)begin
if(!en)begin
out =2'b00;
v =1'b0;
end
else
begin:block1
for(i=3;i>=0;i=i-1)begin
//Priority Logic. each Time It will check Whether the MSB bit is active, If so
it will break //the loop. Otherwise It will decrement and continue the same
if(in[i]==1'b1)begin
case(i)
3:beginout =2'b11;v=1'b1;end
default:beginout =2'bxx;v=1'bx;end
endcase
disableblock1;
//Disable statement is synthesizible
end
end
end
end
endmodule

moduletb_prior_enco ;
WWW.TESTBENCH.IN
regen;
reg[2:0]in;
wire[1:0]out;
wirev;
priority_encoPRIOR_ENC(.en(en),.in(in),.out(out),.v(v));
initialbegin
en =0;
in =0;
repeat(19)
random_generation(in,en);
#65$finish;
end
output[3:0]in_t;
outputen_t;
begin
#4;
in_t =$random%4;
en_t =$random;
end
endtask
taskdisplay;
inputen_t;
input[3:0]in_t;
input[1:0]out_t;
inputv_t;
$display("time =%0t \t INPUT VALUES \t en =%b in =%b \t OUTPUT VALUES out =%b
v =%b",$time,en_t,in_t,out_t,v_t);
endtask
always@(out)
display(en,in,out,v);
endmodule
output
time
time
time
time
time
time
time
time
time
time
time
=0INPUT VALUESen =0 in =0000OUTPUT VALUES out =00 v =0

=8INPUT VALUESen =1 in =1101OUTPUT VALUES out =11 v =1
=12 INPUT VALUESen =1 in =0001OUTPUT VALUES out =00 v =1
Decoder(8:3)
WWW.TESTBENCH.IN
Verilog design
moduledecoder38(
inputen,
input[2:0]in,
outputreg[7:0]out);
always@(*)
begin
if(!en)
out=0;
elsebegin
case({in})
3'b000:out =8'b0000_0001;
3'b001:out =8'b0000_0010;
3'b010:out =8'b0000_0100;
3'b011:out =8'b0000_1000;
3'b100:out =8'b0001_0000;
3'b101:out =8'b0010_0000;
3'b110:out =8'b0100_0000;
3'b111:out =8'b1000_0000;
default:out =8'bxxxx_xxxx;
endcase
end
end
endmodule
moduletb_decoder38;
regen_tb;
reg[2:0]in_tb;
wire[7:0]out_d;
reg[7:0]out_tb;
decoder38DEC(.en(en_tb),.in(in_tb),.out(out_d));
initialbegin
en_tb=0;
in_tb=0;
repeat(10)
random_generation(in_tb,en_tb);
#45$finish;
end
//Below Block is used to generate expected outputs in Test bench only. These
outputs //are used to compare with DUT output. You have Checker task (ScoreBoard
in SV), for //that you need Reference output
always@(in_tb,en_tb)
begin
if(!en_tb)
out_tb =0;
elsebegin
case({in_tb})
3'b000:out_tb=8'b0000_0001;
WWW.TESTBENCH.IN
3'b001:out_tb=8'b0000_0010;
3'b010:out_tb=8'b0000_0100;
3'b011:out_tb=8'b0000_1000;
3'b100:out_tb=8'b0001_0000;
3'b101:out_tb=8'b0010_0000;
3'b110:out_tb=8'b0100_0000;
3'b111:out_tb=8'b1000_0000;
default:out_tb=8'bxxxx_xxxx;
endcase
end
end
output[2:0]in_t;
outputen_t;
begin
#4;
in_t =$random%3;
en_t =$random;
end
endtask
taskchecker;
//In this block reference value and generated output are compared
input[7:0]outd_t;
input[7:0]outtb_t;
begin
if(outd_t ===outtb_t)
$display("time =%0t \tDUT VALUE =%b TB VALUE =%b \tDUT and TB VALUES
ARE MATCHED ",$time,outd_t,outtb_t);
else
$display("time =%0t \tDUT and TB VALUES ARE NOTMATCHED ",$time);
end
endtask
always@(out_d,out_tb)
checker(out_d,out_tb);
endmodule
time =0 DUT VALUE =00000000 TB VALUE =00000000 DUT and TB VALUES ARE
MATCHED
MATCHED
MATCHED
MATCHED
MATCHED
MATCHED
MATCHED
D-Latch
Verilog design
moduled_latch(
inputen,d,
outputregq);
WWW.TESTBENCH.IN
always@(en,d)
begin
if(en)
q <=d;
end
endmodule
TestBench
moduletb_latch;
regen,d;
wireq;
d_latch DLATCH(.en(en),.d(d),.q(q));
initialbegin
en =1'b0;
d =1'b1;
#45$finish;
end
always#6en =~en;
always#3d =~d;
always@(q ,en )
$display("time =%0t \t INPUT VALUES \t en =%b d =%b \t OUTPUT VALUES
q=%b",$time,en,d,q);
endmodule
output
time =0 INPUT VALUES en =0 d =1OUTPUT VALUES q=x
time =6 INPUT VALUES en =1 d =1OUTPUT VALUES q=1
time =9 INPUT VALUES en =1 d =0OUTPUT VALUES q=0
time =12INPUT VALUES en =0 d =1OUTPUT VALUES q=0
D-FlipFlop(Asynchronous Reset)
Verilog design
moduled_ff (
inputclk,d,rst_n,
outputregq);
//Here is reset is Asynchronous, You have include in sensitivity list
always@(posedgeclk ,negedgerst_n)
begin
if(!rst_n)
q <=1'b0;
else
q <=d;
end
endmodule
TestBench
moduletb_dff;
WWW.TESTBENCH.IN
regRST_n,CLK,D;
wireQ;
d_ff DFF(.clk(CLK),.rst_n(RST_n),.q(Q),.d(D));
initialbegin
RST_n =1'b0;
CLK=1'b0;
D =1'b0;
#5RST_n =1'b1;
#13RST_n =1'b0;
#7RST_n =1'b1;
#45$finish;
end
always#3CLK=~CLK;
always#6D =~D;
always@(posedgeCLK,negedgeRST_n)
$strobe("time =%0t \t INPUD VALUES \t D =%b RST_n =%b \t OUDPUD VALUES Q
=%d",$time,D,RST_n,Q);
//$strobe will execute as a last statement in current simulation.
endmodule
output
time
time
time
time
time
time
time
time
time
=0 INPUT VALUES D =0 RST_n =0 OUTPUT VALUES Q =0

=15INPUT VALUES D =0 RST_n =1 OUTPUT VALUES Q =0
D-FlipFlop(Synchronous Reset)
Verilog design
moduled_ff (
inputclk,d,rst_n,
outputregq);
//In Synchronous Reset, Reset condition is verified wrt to clk.Here It is verified at

every //posedge of clk.
always@(posedgeclk )
begin
if(!rst_n)
q <=1'b0;
else
q <=d;
end
endmodule
TestBench
moduletb_dff;
regRST_n,CLK,D;
wireQ;
d_ff DFF(.clk(CLK),.rst_n(RST_n),.q(Q),.d(D));
WWW.TESTBENCH.IN
initialbegin
RST_n =1'b0;
CLK=1'b0;
D =1'b1;
#5RST_n =1'b1;
#7RST_n =1'b0;
#7RST_n =1'b1;
#45$finish;
end
always#4CLK=~CLK;
always#6D =~D;
always@(posedgeCLK)
$strobe("time =%0t \t INPUT VALUES \t D =%b RST_n =%b \t OUDPUT VALUES Q
=%d",$time,D,RST_n,Q);
endmodule
output
time =4INPUT VALUESD =1 RST_n =0 OUTPUT VALUES Q =0
time =12 INPUT VALUESD =1 RST_n =0 OUTPUT VALUES Q =0
T-FlipFlop
Verilog design
modulet_ff (
inputclk,t,rst_n,
outputregq);
always@(posedgeclk ,negedgerst_n)
begin
if(!rst_n)
q <=1'b0;
elseif(t)
q <=~q;
else
q <=q;
end
endmodule
TestBench
moduletb_tff;
regRST_n,CLK,T;
wireQ;
t_ff TFF(.clk(CLK),.rst_n(RST_n),.q(Q ),.t(T));
initialbegin
RST_n =1'b0;
CLK=1'b0;
T =1'b0;
#5RST_n =1'b1;
#13RST_n =1'b0;
WWW.TESTBENCH.IN
#7RST_n =1'b1;
#45$finish;
end
always#3CLK=~CLK;
always#6T =~T;
always@(posedgeCLK,negedgeRST_n)
$strobe("time =%0t \t INPUT VALUES \t T =%b RST_n =%b \t OUTPUT VALUES Q
=%d",$time,T,RST_n,Q);
endmodule
output
time
time
time
time
time
time
time
time
=0 INPUT VALUES T =0 RST_n =0 OUTPUT VALUES Q =0

=15INPUT VALUES T =0 RST_n =1 OUTPUT VALUES Q =1
3-Bit Counter
//Used Structural Model in RTL and Behavior Model in Test bench

Verilog design
modulet_ff(
outputregq,
inputt,rst_n,clk);
always@(posedgeclk ornegedgerst_n)
if(!rst_n)q <=1'b0;
elseif(t)q <=~q;
endmodule
//Standard counters are designed using either T or JK F/F.
modulecounter (
output[2:0]q,
inputrst_n,clk);
wiret2;
t_ff ff0 (q[0],1'b1,rst_n,clk);

t_ff ff1 (q[1],q[0],rst_n,clk);
t_ff ff2 (q[2],t2, rst_n,clk);
anda1 (t2,q[0],q[1]);
endmodule
TestBench
moduletb_counter_3bit;
regclk,rst_n;
wire[2:0]q;
reg[2:0]count;
counter CNTR(.clk(clk),.rst_n(rst_n),.q(q));
initialbegin
clk <=1'b0;
forever#5clk <=~clk;
end
initial
begin
rst_n <=0;
WWW.TESTBENCH.IN
@(posedgeclk);
@(negedgeclk);
rst_n <=1;
repeat(10) @(posedgeclk);
$finish;
end
//Below always block represents the 3-bit counter in behavior style.

//Here it is used to generate reference output
always@(posedgeclk ornegedgerst_n)begin
if(!rst_n)
count <=0;
else
count <=(count +1);
end
always@(q )scoreboard(count);
//Below task is used to compare reference and generated output. Similar to score
board //in SV Test bench
taskscoreboard;
input[2:0]count;
input[2:0]q;
begin
if(count ==q)
$display("time =%4t q = %3b count = %b match!-:)",
$time,q,count);
else
$display("time =%4t q = %3b count = %b <-- no match",
$time,q,count);
end
endtask
endmodule
output
time
time
time
time
time
time
time
time
time
time
= 0 q = 000 count = 000 match!-:)

=15 q = 001 count = 001 match!-:)
=25 q = 010 count = 010 match!-:)
=35 q = 011 count = 011 match!-:)
=45 q = 100 count = 100 match!-:)
=55 q = 101 count = 101 match!-:)
=65 q = 110 count = 110 match!-:)
=75 q = 111 count = 111 match!-:)
=85 q = 000 count = 000 match!-:)
=95 q = 001 count = 001 match!-:)
17.Gray code counter (3-bit) Using FSM.

It will have following sequence of states. It can be implemented without FSM also.
000
001
011
010
110
111
101
100
FSM Design IN VERILOG
There are many ways of designing FSM.Most efficient are
(i)Using Three always Block (ex: Gray code counter)
(ii)Using Two always block (Ex: divide by 3 counter)
Verilog Code
modulegreycode_counter_3bit(
inputclk,rst_n,
WWW.TESTBENCH.IN
outputreg[2:0]count);
reg[2:0]pr_state,nx_state;
parametercnt0 =3'b000,
cnt1 =3'b001,
cnt2 =3'b011,
cnt3 =3'b010,
cnt4 =3'b110,
cnt5 =3'b111,
cnt6 =3'b101,
cnt7 =3'b100;
always@(posedgeclk,negedgerst_n)begin// FIRST ALWAYS BLOCK

//This always block is used for State assignment. Sequential always block.
if(!rst_n)
pr_state <=cnt0;
else
pr_state <=nx_state;
end
always@(pr_state)begin//SECOND ALWAYS BLOCK

//this always block used for next state logic, Combinational
case(pr_state)
cnt0 :nx_state =cnt1;
default:nx_state =cnt0;
endcase
end
always@(posedgeclk ,negedgerst_n)begin//THIRD ALWAYS BLOCK

//this always block used for output assignment,Sequential
if(!rst_n)
count <=3'b000;
elsebegin
case(pr_state)
cnt0 :count <=3'b000;
default:count <=3'bxxx;
endcase
end
end
endmodule
TestBench
moduletb_greycode_counter;
regclk,rst_n;
wire[2:0]count;
greycode_counter_3bit COUNTER(.clk(clk),.rst_n(rst_n),.count(count));
initialbegin
clk =1'b0;
rst_n =1'b0;
@(posedgeclk);
@(posedgeclk);
rst_n =1'b1;
repeat(9)@(posedgeclk);
$finish;
end
always#5clk =~clk;
WWW.TESTBENCH.IN
always@(count)
$display("time =%0t \t rst_n =%b count =%b",$time,rst_n,count);
endmodule
output
time
time
time
time
time
time
time
time
time
=0rst_n =0 count =000

=25 rst_n =1 count =001
=35 rst_n =1 count =011
=45 rst_n =1 count =010
=55 rst_n =1 count =110
=65 rst_n =1 count =111
=75 rst_n =1 count =101
=85 rst_n =1 count =100
=95 rst_n =1 count =000
Divide by 2 clk
modulediv_2clk(
inputclk,rst_n,
outputregclk_out);
always@(posedgeclk,negedgerst_n)begin
if(rst_n)
clk_out <=1'b0;
else
clk_out <=~clk_out;
end
endmodule
TestBench
moduletb_div_2clk;
regclk,rst_n;
wireclk_out;
div2_clk clkby2 (.clk(clk),.rst_n(rst_n),.clk_out(clk_out));
initialbegin
clk =1'b0;
rst_n =1'b0;
@(posedgeclk);
@(posedgeclk);
rst_n =1'b1;
//It will run till 15 clock cycles
$finish;
end
always#5clk =~clk;
always@(clk_out)
$display("time = %0t \t Inputclk =%b \t output clk=%b ",$time,clk,clk_out);
endmodule
output
WWW.TESTBENCH.IN
Divide by 3 clk
This is an example for two always block FSM
in this Example you have Two FSMs, one is operating at posedge clk and other
//operating at negedge clk. In Double Data Rate (DDR2) also data transfer occur at
both //the edges. It is synthesizable
Verilog Code
modulediv_3clk(
inputclk,rst_n,
outputclk_by_3);
parameterST10=2'b00,
ST11=2'b01,
ST12=2'b10;
parameterST20=2'b00,
ST21=2'b01,
ST22=2'b10;
regclk_temp1,clk_temp2;
reg[1:0]pr_state1,nx_state1;
reg[1:0]pr_state2,nx_state2;
always@(posedgeclk ,negedgerst_n)begin
if(!rst_n)
pr_state1 <=ST10;
else
pr_state1 <=nx_state1;
end
always@(pr_state1)begin
//In second always block only we have output logic and next state logic
case(pr_state1)
ST10 :beginclk_temp1 =1'b1;nx_state1 =ST11;end
default:beginclk_temp1 =1'bx;nx_state1 =ST10;end
endcase
WWW.TESTBENCH.IN
end
always@(negedgeclk ,posedgerst_n)begin
if(!rst_n)
pr_state2 <=ST20;
else
pr_state2 <=nx_state2;
end
always@(pr_state2)begin
case(pr_state2)
default:beginclk_temp2 =1'bx;nx_state1 =ST20;end
endcase
end
assignclk_divby3 =clk_temp1||clk_temp1;
endmodule
TestBench
moduletb_div_2clk;
regclk,rst_n;
wireclk_out;
div_3clkclkby3 (.clk(clk),.rst_n(rst_n),.clk_by_3(clk_out));
initialbegin
clk =1'b0;
rst_n =1'b0;
@(posedgeclk);
@(posedgeclk);
rst_n =1'b1;
$finish;
end
always#5clk =~clk;
always@(clk_out)
$display("time = %0t \t Inputclk =%b \t output clk=%b ",$time,clk,clk_out);
endmodule
output
WWW.TESTBENCH.IN
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TUTORIALS
INTRODUCTION
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
The Specman automates verification processes, provides functional coverage analysis,

and raises the level of abstraction for functional coverage analysis from the RTL to the
architectural/specification level. This means that you can:
Easily capture your design specifications to set up an accurate and appropriate
verification environment
Quickly and effectively create as many tests as you need
Create self-checking modules that include protocols checking
Accurately identify when your verification cycle is complete
The Specman Elite system provides three main enabling technologies that enhance
your productivity:
--Constraint-driven test generation : You control automatic test generation by
capturing constraints from the interface specifications and the functional test plan.
Capturing the constraints is easy and straightforward.
--Data and temporal checking : You can create self-checking modules that ensure
data correctness and temporal conformance. For data checking, you can use a
reference model or a rule-based approach.
--Functional coverage analysis : You avoid creating redundant tests that waste
simulation cycles, because you can measure the progress of your verification effort
against a functional test plan.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
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Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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TUTORIALS
E BASICS
SystemVerilog
Code Segments
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
A code segment is enclosed with a begin-code marker <' and an end-code marker '>.
Both the begin-code and the end-code markers must be placed at the beginning of a
line (left most), with no other text on that same line (no code and no comments). For
example, the following three lines of code form a code segment:
EXAMPLE
<'
importeth_env;
'>
DPI
UVM Tutorial
VMM Tutorial
Several code segments can appear in one le. Each code segment consists of one or
more statements.
OVM Tutorial
Easy Labs : SV
Comments
Easy Labs : UVM
e les begin as a comment which ends when the rst begin-code marker <' is
encountered.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
Comments within code segments can be marked with double dashes (--) or double
slashes (//)
VMM Ethernet sample The end-code '> and the begin-code <' markers can be used in the middle of code
sections, to write several consecutive lines of comment:
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
<'
importeth_env;
'>
This is
several
consecutive
lines of comment
Switch TB
<'
min=46;
RVM Switch TB
-- This is an inline comment
RVM Ethernet sample
Specman E
Interview Questions
max=1500;
// This is also an inline comment
'>
Literals And Constants
Literals are numeric, character and string values specied literally in e. Operators
can be applied to literals to create compound expressions. The following categories of
literals and constants are supported in e:
------------------------------------------------------------
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Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
Unsized Numbers12, 55_32, -764

Decimal integer10, 23_23 .-444
Binary integer 0b100111,0b1100_0101
Hexadecimal integer0x99_aa_bb_cc
Octal integer0o66_123
K (kilo: multiply by 1024) 32K, 32k, 128k
M (mega: multiply by 1024*1024)1m, 4m, 4M
-------------------------------------------------------------
Sized Numbers
-------------------------------------------------------------BinaryA leading 'b or 'B 8'b11001010

Octal A leading 'o or 'O 6'o45
Decimal A leading 'd or 'D 16'd63453
Hexadecimal A leading 'h or 'H or 'x or 'X 32'h12ffab04
--------------------------------------------------------------
PredeNed Constants
--------------------------------------------------------Constant Description
--------------------------------------------------------TRUE For Boolean variables and expressions.
FALSEFor Boolean variables and expressions.
NULL For structs, species a NULL pointer. For
character strings, species an empty string.
UNDEFUNDEF indicates NONE where an index is expected.
MAX_INTRepresents the largest 32-bit int (231 -1)
MIN_INTRepresents the smallest 32-bit int (-231).
MAX_UINT Represents the largest 32-bit uint (232-1).
--------------------------------------------------------
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Index
Introduction
E Basics
SystemVerilog
Most e expressions have an explicit data type. These data types are described in the Data Types
Verification
Operators
following sections:
Constructs
Struct
Units
Interface
---------------------------------------------------------------List
NameDescription Example
OOPS
Methods
---------------------------------------------------------------boolBoolean value: TRUE or FALSE valid : bool;
Concurrency Actions
Randomization
int Integer, default 32 bits length: int;
Constraints
uintUnsigned
integer,default
32
bits
addr:
uint(bits:8);
Functional Coverage
Extend
bit 1-bit unsigned integer valid : bit;
When And Like
byte8-bit unsigned integer data: byte;
Assertion
time64-bit unsigned integerdelay : time;
Events
stringString of ASCII characters prompt: string;
DPI
listResizablepayload:list of byte;
UVM Tutorial
---------------------------------------------------------------Temporal Operators 2
VMM Tutorial
Simulator
OVM Tutorial
Wait And Sync
Enumerated
Types
Easy Labs : SV
Easy Labs : UVM
You can define the valid values for a variable or field as a list of symbolic constants. Packing N Unpacking
These are referred to as enumerated types.
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Syntax: type enum-type: [name1[=exp],][(bits|bytes: width-exp)];
Extendable Methods
AVM Switch TB
VMM Ethernet sample
And Gate Evc
EXAMPLE
TUTORIALS
DATA TYPES
Verilog
typepriority_t:[high,medium,low];
typepacket_kind_t:[good,bad];
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample

input is what keeps
By default, the new enumerated type is 32 bits, but it can be sized according to the with time!
number of bits required.
EXAMPLE:
typedirection_t:[READ,WRITE](bits:1);
Default first enum value is 0. Subsequent enum values are increment by 1.This
internal value is used for comparisons(with strong type matching maintained).
Values can be explicitly assigned with the syntax:
EXAMPLE:
typeopcode_t:[ADD=4,SUB=6];
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Index
Introduction
E Basics
SystemVerilog
Unary Bitwise Operators
Data Types
Verification
Operators
Constructs
Unary bitwise negation( ~ ) operator Sets each 1 bit of an expression to 0 and each 0 Struct
Units
bits to 1. Each bit of the result expression is the opposite
Interface
List
of the same bit in the original expression.
OOPS
Methods
Concurrency Actions
Randomization
Constraints
EXAMPLE:
Functional Coverage
Extend
<'
When And Like
Assertion
extendsys{
Events
run()isalso{
DPI
varx :int=0x0000ff;
UVM Tutorial
print~x usinghex;
};
VMM Tutorial
};
Simulator
OVM Tutorial
'>
Wait And Sync
RESULT
Easy Labs : SV
Packing N Unpacking
Easy Labs : UVM
~x = 0xffffff00
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Binary Bitwise Operations
Extendable Methods
AVM Switch TB
VMM Ethernet sample
And Gate Evc
TUTORIALS
Verilog
OPERATORS
&--Performs an AND operation.

|--Performs an OR operation.
^--Performs an XOR operation.
Verification
Verilog Switch TB
EXAMPLE:
<'
extendsys{
run()isalso{
OpenVera
varx:uint=0xff03;
Constructs
vary:uint=0x70f6;
varz :uint;
Switch TB
z=x &y ;
RVM Switch TB
outf("%b & %b is %b \n",x,y,z);
RVM Ethernet sample z=x |y ;
outf("%b | %b is %b \n",x,y,z);
z=x ^y ;
outf("%b ^ %b is %b \n",x,y,z);
Specman E
Basic Constructs
Interview Questions
};
};
'>
RESULT:
1111111100000011 & 111000011110110 is 111000000000010
1111111100000011 | 111000011110110 is 1111111111110111
1111111100000011 ^ 111000011110110 is 1000111111110101
http://testbench.in/SP_04_OPERATORS.html[9/26/2012 2:55:24 PM]

input is what keeps
with time!
Shift Operators
<<--Performs a shift-left operation.

>>--Performs a shift-right operation.
EXAMPLE
<'
extendsys{
run()isalso{
varx:int=0x123456;
outf("%x\n",x >>2);
vary:uint=0x654321;
outf("%x\n",y >>3);
};
};
'>
RESULT
48d15
ca864
Boolean Operators
! (not)-- Returns TRUE when an expression evaluates to FALSE, and vice

versa.
&& (and) -- Returns TRUE if two expressions are both TRUE.
|| (or)-- Returns TRUE if one of two expressions is TRUE.
=> -- Returns TRUE when the rst expression of two expressions
is FALSE, or when both expressions are TRUE.
now-- Returns TRUE if an event has occurred in the current cycle.
EXAMPLE
<'
extendsys{
run()isalso{
varx:int=2;
if(x >1)
{out(" (X > 1) ");};
if((x >1)&&(x <3))
{out(" (x > 1) && (x < 3) ");};
if((x >1)||(x <3))
{out(" (x > 1) || (x < 3) ");};
if((x >1)=>(x <3))
{out(" (x > 1) => (x < 3) ");};
if((x >1)and(x <3))
{out(" (x > 1) and (x < 3) ");};

if((x >1)or(x <3))
{out(" (x > 1) or (x < 3) ");};
};
};
'>
RESULT
(X >
(x >
(x >
(x >
(x >
(x >
1)
1)
1)
1)
1)
1)
&& (x < 3)
|| (x < 3)
=> (x < 3)
and (x < 3)
or (x < 3)
Arithmetic Operators
+---*-/-%--
Performs
Performs
Performs
Performs
Performs
addition.
subtraction.
multiplication.
division and returns the quotient, rounded down.
division and returns the remainder.
EXAMPLE:
<'
extendsys{
run()isalso{
out(1+4);
out(3-4);
out(41*3);
out(27/4);
out(53%7);
};
};
'>
RESULTS
5
-1
123
6
4
Comparison Operators
< -
<=-
> -
>=-
==-
!=-
=== -
!== -
==-
!=-
exp -
Returns TRUE if the rst expression is smaller than

the second expression.
Returns TRUE if the rst expression is not larger
than the second expression.
Returns TRUE if the rst expression is larger than
the second expression.
Returns TRUE if the rst expression is not smaller
than the second expression.
Returns TRUE if the rst expression evaluates to
the same value as the second expression.
Returns TRUE if the rst expression does not
evaluate to the same value as the second expression.
Determines identity, as in Verilog. Returns TRUE if
the left and right operands have identical values,
considering also the x and z values.
Determines non-identity, as in Verilog. TRUE if the
left and right operands differ in at least 1 bit,
considering also the x and z values.
Returns TRUE if after translating all x values to 0
andall z values to 1, the left and right operands
are equal.
Returns TRUE if after translating all x values to 0
and all z values to 1, the left and right operands
are non-equal.
Either a literal with four-state values, a numeric
expression, or another HDL pathname.
~ -
!~-
IN-
Returns TRUE if the pattern string can be matched

to the whole string.
Returns TRUE if the pattern string cannot be
matched to the whole string.
Check for value in a list or specify a range for
a constraint.
EXAMPLE
<'
extendsys{
run()isalso{
out(5< 6);
out(5<=6);
out(5> 6);
out(5>=6);
out(5==6);
out(5!=6);
out(5==6);
out(5!=6);
out("gg"~"gg");
out("gg"!~"gg");
out(5in{4;5;6});
};
};
'>
RESULT
TRUE
TRUE
FALSE
FALSE
FALSE
TRUE
FALSE
TRUE
TRUE
FALSE
TRUE
Extraction And Concatenation Operators

The following sections describe the e extraction and concatenation operators:
[ ]-- Extracts or sets a single item from a list.
[ : ]-- Extracts or sets consecutive bits or slices of
a scalar, a list of bits, or a list of bytes.
[ .. ] -- List slicing operator
[ range,...] -- Range list operator
{ ; }-- List concatenation
%{ , } -- Bit concatenation
Special-Purpose Operators
Specman Elite supports the following special purpose operators:
is [not] -new-.-'-? :--
Identify the subtype of a struct instance

Allocate a new struct
Refer to elds in structs
Used in names of e entities
Conditional operator
EXAMPLE:is[not]
<'
typepack_kind :[long,short];
structpacket {
kind:pack_kind;
whenlong packet {
a:int;
};
check_my_type()is{
ifmeisa long packet (l){
printl;
};
ifmeisnota long packet {
printkind;
};
};
};
extendsys{
p:packet;
run()isalso{
p.check_my_type();
}
};
'>
RESULT
l = packet-@0: packet
--------------------------------------------------@test
0 kind: long
1 long'a: 2129590818
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TUTORIALS
STRUCT
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Structs are the basis building blocks for any e language based testbenches. This are
similar to class in C++ and thus are used for constructing compound data structures.
Like in C++ and C, we can use this compound data structures in all the places like, it
Can be used as regular data types in any context where a type is required. The
default value for a struct is NULL . Struct can be passed to/from methods just as in C
methods. Struct Can be used in another struct as normal data type . You can also
define a variable using a struct type.
Functional Coverage
Assertion
EXAMPLE:
<'
structdata {
UVM Tutorial
addr :uint(bits:32);
data :uint(bytes:8);
VMM Tutorial
rdwr :bit;
OVM Tutorial
};
extendsys{
Easy Labs : SV
d :data;
Easy Labs : UVM
run()isalso{
gend;
Easy Labs : OVM
printd;
Easy Labs : VMM
gend;
printd;
AVM Switch TB
};
VMM Ethernet sample };
'>
DPI
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RESULT
d = data-@0: data
@11
0 addr: 1956082095
1 data: 5743609808327112738
2 rdwr: 0
d = data-@1: data
@11
0 addr: 3861093091
1 data: 8956857106270623639
2 rdwr: 0
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_05_STRUCT.html[9/26/2012 2:55:33 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
<< PREVIOUS PAGE
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TUTORIALS
UNITS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Units are similar to structs. It also contain all struct members, i.e. fields, methods,
etc. Units are static. It is created during start of the simulation and stays until the
end of simulation. Units are generated in Pre-run generation phase. We will task
about the generation phases in more detailed later. Units are associated with an HDL
hierarchy instance. Predefine method hdl_path() is used for setting the unit's
associated HDL path. For accessing parent enclosing unit , predefined method
get_enclosing_unit() is used.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Syntax:unitunit-type[like base-unit-type]{[unit-member;...]};
EXAMPLE:
unitXYZ_router {
channels:listofXYZ_channel isinstance;
keepchannels.size()==3;
keepforeachinchannels {.hdl_path()==
append("chan",index);};
};
Units Vs Structs
Easy Labs : VMM
The decision of whether to model a DUT component with a unit or a struct often
depends on your verification strategy. You intend to test the DUT component both
standalone and integrated into a larger system. Modeling the DUT component with a
VMM Ethernet sample unit instead of a struct allows you to use relative path names when referencing HDL
objects. Your e program has methods that access many signals at runtime. The
correctness of all signal references within units are determined and checked during
pre-run generation. If your e program does not contain user units, the absolute HDL
Verilog
references within structs are also checked during pre-run generation. However, if
Verification
your e program does contain user units, the relative HDL references within structs are
Verilog Switch TB
checked at run time. In this case, using units rather than structs can enhance runtime
performance
Basic Constructs
AVM Switch TB
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_06_UNITS.html[9/26/2012 2:55:42 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
<< PREVIOUS PAGE
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Index
Introduction
E Basics
SystemVerilog
There are two of lists in e language
Data Types
-- Regular list
Verification
Operators
-- Keyed list Regular
Constructs
Struct
Units
Interface
List
Regular List
OOPS
Methods
Concurrency Actions
Randomization
-List types hold ordered collections of data elements.
Constraints
-All
items
in
a
list
must
be
of
the
same
type.
Functional Coverage
Extend
-List elements can be of any type.
Assertion
-Items in a list can be indexed with the subscript operator [ ], by placing a non- When And Like
Events
negative integer expression in thebrackets.
DPI
-List indexes start at zero. You can select an item from a list by specifying its index.
UVM Tutorial
-Lists are dynamically resizable.
-Lists contain many predefined methods.
VMM Tutorial
-Lists are defined by using the list of keyword in a variable or a field definition.
Simulator
OVM Tutorial
Wait And Sync
Easy Labs : SV
EXAMPLE:
Packing N Unpacking
Easy Labs : UVM
lis :listofint;
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
List Operations
Extendable Methods
AVM Switch TB
size() : This is used to set the size of the list.
VMM Ethernet sample add(item or list) : Add an item to the end of a list
And Gate Evc
add0(item or list) : Add an item to the head of a list
clear(): Delete all items from a list
delete(index) : Delete an item from a list
Verilog
input is what keeps
insert(index,item)
:
Insert
an
item
in
a
list
at
a
specified
index
Verification
pop(item) : Remove and return the last list item
Verilog Switch TB
with time!
pop0(item) : Remove and return the first list item
push(item) : Add an item to the end of a list
Basic Constructs
push0(item) : Add an item to the head of a list
resize() : Change the size of a list
TUTORIALS
LIST
OpenVera
Constructs
EXAMPLE:
<'
RVM Switch TB
extendsys{
RVM Ethernet sample run()isalso{
vara_list:listofint={1;2;3;4};
varb_list:listofint={5;5};
printa_list;
Specman E
printa_list.pop();
a_list.add(9);
Interview Questions
printa_list;
a_list.insert(2,33);
printa_list;
a_list.add(b_list);
printa_list;
a_list.delete(4);
printa_list;
a_list.add0(22);
printa_list;
printa_list.pop0();
Switch TB
http://testbench.in/SP_07_LIST.html[9/26/2012 2:55:52 PM]
a_list.push(44);
printa_list;
a_list.push0(55);
printa_list;
a_list.resize(4);
printa_list;
a_list.clear();
printa_list;
}
};
'>
RESULT:
a_list =
0.1
1.2
2.3
3.4
a_list.pop() = 4
a_list =
0.1
1.2
2.3
3.9
a_list =
0.1
1.2
2.33
3.3
4.9
a_list =
0.1
1.2
2.33
3.3
4.9
5.5
6.5
a_list =
0.1
1.2
2.33
3.3
4.5
5.5
a_list =
0.22
1.1
2.2
3.33
4.3
5.5
6.5
a_list.pop0() = 22
a_list =
0.1
1.2
2.33
3.3
4.5
5.5
6.44
a_list =
0.55
1.1
2.2
3.33
4.3
5.5
6.5
7.44
a_list =
0.0
1.0
2.0
3.0
a_list = (empty)
Keyed List:
A keyed list data type is similar to hash tables or association lists found in other
programming languages. If the element type of the list is a scalar type or a string
type, then the hash key must be the predefined implicit variable it.
A keyed list is a distinct type, different from a regular list. This means that you
cannot assign a keyed list to a regular list, nor assign a regular list to a keyed list: if
list_a is a keyed list and list_b is a regular list, list_a = list_b is a syntax error.
EXAMPLE:
<'
extendsys{
!a:list(key:it)ofint(bits:3);
run()isalso{
varb:int(bits:4);
fori from0to10{
genb;
a.add(b);
};
ifa.key_exists(2)then{
printa;
printa.key_index(4);
};
};
};
'>
RESULT:
a =(11 items, dec):
-3 -3 -2 1 -22 -1 0 -40 -3.0
a.key_index(4) = 2
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Index
Introduction
E Basics
SystemVerilog
e methods are similar to C functions, Verilog tasks, and VHDL processes.
Methods can contain actions (procedural code). User can declare and use local Data Types
Verification
variables and parameters. Methods can have zero to fourteen input Operators
Constructs
arguments/parameters. You can work around this restriction by passing a compound Struct
Units
parameter such as a struct or a list. It can aslo optionally return a value .
Interface
List
OOPS
Methods
Concurrency Actions
EXAMPLE:
Randomization
Constraints
<'
Functional Coverage
Extend
structA {my_type()is{out("I am type A")}};
When And Like
Assertion
extendsys{
Events
a:A;
DPI
run()isalso{
UVM Tutorial
a.my_type();
};
VMM Tutorial
};
Simulator
OVM Tutorial
'>
Wait And Sync
Easy Labs : SV
RESULT:
Packing N Unpacking
Easy Labs : UVM
I
am
type
A
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Extendable Methods
AVM Switch TB
Time-Consuming Methods(Tcms)
VMM Ethernet sample
And Gate Evc
A TCM is a time-consuming method that is distinguished from a regular method by the
presence of @event and can use time-consuming actions such as sync and wait.
Verilog
input is what keeps
EXAMPLE:
Verification
<'
Verilog Switch TB
with time!
structdata_drive {
eventclk isrise('top.clk')@sim;
Basic Constructs
data:listofint;
driver()@clk is{
foreachindata {
OpenVera
waittrue('top.data_ready'==1);
Constructs
// Will not fall through, even if the condition
// holds when the wait is reached.
Switch TB
'top.in_reg' =it;
RVM Switch TB
};
RVM Ethernet sample stop_run();
};
shadow()@clk is{
whileTRUE{
Specman E
synctrue('top.data_ready' ==0);
// If the condition holds, the sync falls through.
Interview Questions
out("Shadow read ",'top.in_reg');
waitcycle;
// This wait is necessary to prevent
// an infinite loop.
};
};
run()isalso{
startdriver();
startshadow();
};
TUTORIALS
METHODS
http://testbench.in/SP_08_METHODS.html[9/26/2012 2:56:02 PM]
};
'>
Invoking Tcms:
start tcm() Syntax start [[struct-exp].]method-name([parameter-list])
A start action can be used within another method, either a TCM or a regular method.
A started TCM begins execution either when its sampling event occurs or immediately,
if the sampling event has already occurred for the current Specman tick.A started
TCM runs in parallel with the TCM that started it on a separate thread. Notes. A TCM
that has a return value cannot be started with a start action.. You cannot start a TCM
before the run phase begins or after the check phase begins.
EXAMPLE:
<'
structmeth {
eventclk isrise('top.clk');
run()isalso{
out("Starting main");
startmain();
};
};
'>
Execution Flow
Specman Elite provides a predetermined execution flow composed of test phases
.
Each test phase is called in a specific order.

Each test phase is represented by a predefined method.
Most predefined methods are meant to be extended.
Extend a predefined method to call your method(s) at the appropriate time.
--------------------Execution Phases
----------------------Initialization
--Pre-run generation
--Simulation run
--Post-run check
--Finalization
---------------------
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TUTORIALS
CONCURRENCY ACTIONS
SystemVerilog
All Of
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Execute multiple action blocks concurrently, as separate branches of a fork. The

action following the all of action will be reached only when all branches of the all of
have been fully executed. All branches of the fork are automatically joined at the
termination of the all of action block.
First Of
Execute multiple action blocks concurrently, as separate branches of a fork. The
action following the first of action will be reached when any of the branches in the
first of has been fully executed. All branches of the fork are automatically joined at
the termination of the first of action block.
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_09_Concurrency_Actions.html[9/26/2012 2:56:09 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
<< PREVIOUS PAGE
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Search
TUTORIALS
CONSTRAINTS
SystemVerilog
ConstraintsConstraints are directives that influence the behavior of the Specman test
generator. They are declared within a struct and influence the generation of values
for data items within the struct and its subtree.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
1.Hard Constraints
2.Soft Constraints
For constraints that might need to be overridden, we use soft constraints. Soft
constraints are obeyed if not contradicted by hard constraints. The last loaded soft
constraint prevails if there is a contradiction with other soft constraints. Soft
constraints are used to define the default range of values of fields. Soft constraints
are used to set initial settings for tests.
EXAMPLE:
keepkind !=tx orlen ==16;
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_10_CONSTRAINTS.html[9/26/2012 2:56:18 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
<< PREVIOUS PAGE
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Index
Introduction
E Basics
SystemVerilog
Is Also
Data Types
Verification
"is also" is used for extending existing method/TCM. When we use "is also" it adds new Operators
Constructs
Struct
lines of code/functionality after the existing code as shown in below example.
Units
Interface
List
OOPS
Methods
EXAMPLE:
Concurrency Actions
Randomization
<'
Constraints
Functional Coverage
Extend
structexam {
When And Like
Assertion
from_exam()is{
Events
out("This
is
BASE");
DPI
};
UVM Tutorial
};
VMM Tutorial
Simulator
OVM Tutorial
structe_exam like exam{
Wait And Sync
from_exam()isalso{
Easy Labs : SV
out("This is EXTENDED");
Packing N Unpacking
Easy Labs : UVM
};
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
};
Extendable Methods
AVM Switch TB
extendsys{
VMM Ethernet sample exam :exam;
And Gate Evc
e_exam :e_exam;
run()isalso{
exam.from_exam();
Verilog
input is what keeps
e_exam.from_exam();
Verification
};
TUTORIALS
EXTEND
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
with time!
};
'>
RESULT:
This is BASE
This is BASE
This is EXTENDED
RVM Ethernet sample
Is First
Specman E
Interview Questions
"is first" is used for extending existing method/TCM. When we use "is first" it adds new
lines of code/functionality before existing code shown in below example.
EXAMPLE:
<'
structexam {
from_exam()is{
out("This is BASE");
};
http://testbench.in/SP_11_EXTEND.html[9/26/2012 2:56:27 PM]
};
from_exam()isfirst{
};
};
extendsys{
exam :exam;
e_exam :e_exam;
run()isalso{
exam.from_exam();
e_exam.from_exam();
};
};
'>
RESULT
This is BASE
This is EXTENDED
This is BASE
Is Only
"is only"is used for over riding existing method/TCM. When we use "is only" it over
rides the existing code/functionality before existing code and replaces with new code
as shown in below example.
EXAMPLE:
<'
structexam {
from_exam()is{
};
};
from_exam()isonly{
};
};
extendsys{
exam :exam;
e_exam :e_exam;
run()isalso{
exam.from_exam();
e_exam.from_exam();
};
};
'>
RESULT:
This is BASE
This is EXTENDED
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Index
Introduction
SystemVerilog
There are two ways to implement object-oriented inheritance in e: like inheritance E Basics
Data Types
and when inheritance
Verification
Operators
Constructs
Struct
Units
Like
Interface
List
OOPS
Like inheritance is the classical, single inheritance familiar to users of all object- Methods
Concurrency Actions
Randomization
oriented languages and is specified with the like clause in new struct definitions.
Constraints
Functional Coverage
Extend
When And Like
Assertion
Events
EXAMPLE:
DPI
<'
UVM Tutorial
structexam {
VMM Tutorial
from_exam()is{
Simulator
OVM Tutorial
Wait And Sync
};
Easy Labs : SV
Packing N Unpacking
Easy Labs : UVM
};
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
from_exam()isonly{
Extendable Methods
AVM Switch TB
And Gate Evc
TUTORIALS
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
WHEN AND LIKE
};
extendsys{
exam :exam;
e_exam :e_exam;
run()isalso{
exam.from_exam();
e_exam.from_exam();
};
};
'>
RVM Switch TB
RVM Ethernet sample RESULT:
Specman E
This is BASE
This is EXTENDED
Interview Questions
When
When inheritance is a concept unique to e and is specified by defining subtypes with
when struct members. When inheritance provides the following advantages
comparedto like inheritance:
-Ability to have explicit reference to the when fields
-Ability to have multiple, orthogonal subtypes
-Ability to extend the struct later
http://testbench.in/SP_12_When_and_Like.html[9/26/2012 2:56:37 PM]

input is what keeps
with time!
EXAMPLE:when
<'
typepack_kind :[long,short];
structpacket {
kind:pack_kind;
whenlong packet {
a:int;
};
check_my_type()is{
ifmeisa long packet (l){
printl;
};
ifmeisnota long packet {
printkind;
};
};
};
extendsys{
p:packet;
run()isalso{
p.check_my_type();
}
};
'>
RESULT
l = packet-@0: packet
--------------------------------------------------@test
0 kind: long
1 long'a: 2129590818
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Index
Introduction
SystemVerilog
The e language provides temporal constructs for specifying and verifying behavior E Basics
over time. All e temporal language features depend on the occurrence of events, Data Types
Verification
Operators
which are used to synchronize activity with a simulator and within Specman.
Constructs
Struct
Units
Defining and Emitting Named Events
Interface
List
OOPS
Methods
eventSyntax eventevent-type[is[only]temporal-expression]
Concurrency Actions
Randomization
Constraints
EXAMPLE:
Functional Coverage
Extend
expect{[1];true(chk)@rclk};
When And Like
Assertion
onrclk {...};
Events
set_chk()@rclk
is{...};
DPI
UVM Tutorial
VMM Tutorial
Simulator
OVM Tutorial
Wait And Sync
Easy Labs : SV
Packing N Unpacking
Easy Labs : UVM
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Extendable Methods
AVM Switch TB
VMM Ethernet sample
And Gate Evc
TUTORIALS
EVENTS
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_13_EVENTS.html[9/26/2012 2:56:44 PM]

input is what keeps
with time!
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TUTORIALS
TEMPORAL EXPRESSIONS
SystemVerilog
Temporal expressions provide a declarative way to describe temporal behavior. The e

language provides a set of temporal operators and keywords that can be use to
construct temporal expressions. Every temporal expression has a default clock, called
its sampling event .The temporal language is the basis for capturing behavior over
time for:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
--Synchronizing with the DUT

--Debugging
--Protocol checking
--Functional coverage
The language is built of:
--Temporal expressions (TEs).
--Temporal operators, for defining complex expressions.
--Event struct members, for defining occurrences of events during the run.
--Expect struct members, for checking temporal behavio
Basic Temporal Expressions
Each TE is associated with a sampling event that indicates when the TE should be
evaluated by Specman Elite.
----------------------------------------------------------------------Temporal Expression Sampling Event
----------------------------------------------------------------------true(boolean-exp)@sample-eventEvery sample-event at which boolean
exp is true
rise/fall/change(exp)@sample eventEvery sample-event at which exp had
risen/fallen/changed since previous
sample-event
cycle @sample-event Every sample-event
[num] * TEAbove TEs repeated num times
----------------------------------------------------------------------
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Temporal Checking
1. The temporal expressions we saw for defining events and using in wait actions in
TCMs can also be used for checking behavior through time.
2. The struct member expect spawns a thread that reports an error if a temporal
expression does not succeed.
Interview Questions
http://testbench.in/SP_14_TEMPORAL_EXPRESSIONS.html[9/26/2012 2:56:58 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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TUTORIALS
TEMPORAL OPERATORS 1
SystemVerilog
Not
Verification
Constructs
Interface
The not temporal expression succeeds if the evaluation of the subexpression does not
succeed during the sampling period. Thus not TE succeeds on every occurrence of the
sampling event if TE does not succeed.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
Fail
A fail succeeds whenever the temporal expression fails. If the temporal expression has
multiple interpretations (for example, fail (TE1 or TE2)), the expression succeeds if
and only if all the interpretations fail. The expression fail TE succeeds at the point
where all possibilities to satisfy TE have been exhausted. Any TE can fail at most once
per sampling event.
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
And
The temporal and succeeds when both temporal expressions start evaluating in the
same sampling period, and succeed in the same sampling period.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
Or
The or temporal expression succeeds when either temporal expression succeeds. An or
VMM Ethernet sample operator creates a parallel evaluation for each of its subexpressions. It can create
multiple successes for a single temporal expression evaluation.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
{ Exp ; Exp }
The semicolon (;) sequence operator evaluates a series of temporal expressions over
successive occurrences of a specified sampling event. Each temporal expression
following a ; starts evaluating in the sampling period following that in which
the preceding temporal expression succeeded. The sequence succeeds whenever its
final expression succeeds.
Eventually
RVM Ethernet sample Used to indicate that the temporal expression should succeed at some unspecified
Specman E
Interview Questions
time. Typically, eventually is used in an expect struct member to specify that a

temporal expression is expected to succeed sometime before the quit event occurs
for the struct.
[ Exp ]
Repetition of a temporal expression is frequently used to describe cyclic or periodic

temporal behavior. The [exp] fixed repeat operator specifies a fixed number of
occurrences of the same temporal expression. If the numeric expression evaluates to
zero, the temporal expression succeeds immediately.
[ Exp..Exp ]
http://testbench.in/SP_15_Temporal_operators_1.html[9/26/2012 2:57:07 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
The first match repeat operator is only valid in a temporal sequence {TE; TE; TE}. The
first match repeat expression succeeds on the first success of the match-expression
between the lower and upper bounds specified for the repeat-expression. First match
repeat also enables specification of behavior over infinite sequences by allowing an
infinite number of repetitions of the repeat-expression to occur before the matchexpression succeeds.
Where @ev_a is an event occurrence, {[..]*TE1;@ev_a} is equivalent to:
{@ev_a} or {[1]*TE1; @ev_a} or {[2]*TE1; @ev_a} or {[3]*TE1; @ev_a}
~[ Exp..Exp ]
You can use the true match repeat operator to specify a variable number of
consecutive successes of a temporal expression.True match variable repeat succeeds
every time the subexpression succeeds. This expression creates a number of parallel
repeat evaluations within the range. True match repeat also enables specification of
behavior over infinite sequences by repeating an infinite number of occurrences of a
temporal expression. The expression ~[..]*TE is equivalent to:
[0] or [1]*TE or [2]*TE
Temporal Yield Operator
=>
The yield operator is used to assert that success of one temporal expression depends
on the success of another temporal expression. The yield expression TE1 => TE2 is
equivalent to (fail TE1) or {TE1 ; TE2}.The yield expression succeeds without
evaluating the second expression if the first expression fails. If
the first expression succeeds, then the second expression must succeed in sequence.
Yield is typically used in conjunction with the expect struct member to express
temporal rules. The sampling event from the context applies to both sides of the yield
operator expression. The entire expression is essentially a single temporal expression,
so that (TE1 => TE2)@sampling_event is effectively (TE)@sampling_event where TE is
the temporal expression made up of TE1 => TE2.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
TEMPORAL OPERATORS 2
Detach
A detached temporal expression is evaluated independently of the expression in which

it is used. It starts evaluation when the main expression does. Whenever the detached
TE succeeds it emits an implicit event which will only be recognized by the
main TE. The detached temporal expression inherits the sampling event from the
main temporal expression.
Delay
Succeeds after a specified simulation time delay elapses. A callback to Specman Elite
occurs after the specified time. A delay of zero succeeds immediately.
Attaching a sampling event to delay has no effect. The delay ignores the sampling
event and succeeds as soon as the delay period elapses.
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
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Easy Labs : VMM
@ Unary Event Operator

An event can be used as the simplest form of a temporal expression. The temporal
expression @event-type succeeds every time the event occurs. Success of the
expression is simultaneous with the occurrence of the event. The struct-exp is an
expression that evaluates to the struct instance that contains the event instance. If
no struct expression is specified, the default is the current struct instance.
AVM Switch TB
VMM Ethernet sample @ Sampling Operator
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Used to specify the sampling event for a temporal expression. The specified sampling
event overrides the default sampling event. Every temporal expression has a sampling
event. The sampling event applies to all subexpressions of the temporal expression. It
can be overridden for a subexpression by attaching a different sampling event to the
subexpression. A sampled temporal expression succeeds when its sampling event
occurs with or after the success of the temporal expression.
Cycle
Represents one cycle of some sampling event.With no explicit sampling event
specified, this represents one cycle of the default sampling event. With a sampling
event specified, cycle is equivalent to @sys.any@sampling-event.
True(Exp)
Use a Boolean expression as a temporal expression. Each occurrence of the sampling
event causes an evaluation of the Boolean expression. The Boolean expression is
evaluated only at the sampling point. The temporal expression succeeds each time the
expression evaluates to TRUE.
Change(Exp), Fall(Exp), Rise(Exp)
Detects a change in the sampled value of an expression.
Consume
http://testbench.in/SP_16_TEMPORAL_OPERATORS_2.html[9/26/2012 2:57:17 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
Removes the occurrence of an event so that it is not available for other temporal
expressions. The consume expression succeeds whenever the event occurs. If the
event occurs more than once during any given cycle, all occurrences are consumed.
After an event occurrence is consumed, that occurrence will not be recognized by any
temporal expression during the current Specman Elite tick, unless the event is
emitted again. An event cannot be consumed by more then one consume expression.
Care should be used to avoid creating race conditions between multiple events that
use an event that is consumed.
Exec
Invokes an action block when a temporal expression succeeds. The actions are
executed immediately upon the success of the expression, but not more than once per
Specman Elite tick.
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Index
Introduction
E Basics
SystemVerilog
To synchronize Specman Elite with a simulator, we need to define callbacks.
Data Types
Verification
Operators
Start of callback: When the simulator pauses and gives control to Specman Elite.
Constructs
Struct
Pauses are triggered by @sim events in e.
Units
Interface
List
End of callback: When Specman Elite pauses and gives control back to the simulator.
OOPS
Methods
Pauses are caused by wait/sync actions in e.
Concurrency Actions
Randomization
Constraints
Functional Coverage
The @sim EventThe simulator will apuse and give control to Specman Elite when it Extend
Assertion
sees change in a signmal in an @sim event.event clock_e is rise(~/top/clk When And Like
Events
)@sim;
DPI
UVM Tutorial
VMM Tutorial
Simulator
OVM Tutorial
Wait And Sync
Easy Labs : SV
Packing N Unpacking
Easy Labs : UVM
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Extendable Methods
AVM Switch TB
VMM Ethernet sample
And Gate Evc
TUTORIALS
SYNCHRONIZING WITH THE SIMULATOR
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_17_SYNCHRONIZING_WITH_THE_SIMULATOR.html[9/26/2012 2:57:27 PM]

input is what keeps
with time!
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TUTORIALS
WAIT AND SYNC
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
There are two actions that are used to synchronize temporal activities within e and
between the Design under test and specman simulator.
Wait Action
The wait action suspends the execution of the current TCM until a given temporal
expression succeeds. A TCM can't continue during the same cycle in which it reaches a
wait. Even if the temporal execution succeeds in the current simulator callback, the
TCM won't proceed. The TCM has to wait at least until the next simulator callback.
Therefore, the wait action always requires at least one cycle of TCM's sampling event
before execution continues.
Sync Action
The sync action suspends the execution of the current TCM until a given temporal
expression succeeds. With a sync action, execution can continue in the same
simulator callback.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
Difference Between Wait And Sync

- Wait action will not proceed in the same callback in which it is encountered.
VMM Ethernet sample - Sync action may proceed in the same callback(if the condition is currently valid).
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_18_WAIT_AND_SYNC.html[9/26/2012 2:57:34 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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TUTORIALS
PHYSICAL VIRUAL FEILDS
SystemVerilog
Physical Fields
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
A field defined as a physical field (with the % option) is packed when the struct
is packed. Fields that represent data that is to be sent to the HDL device in the
simulator or that are to be used for memories in the simulator or in Specman Elite,
need to be physical fields. Nonphysical fields are called virtual fields and are not
packed automatically when the struct is packed, although they can be packed
individually. If no range is specified, the width of the field is determined by the field
s type. For a physical field, if the fields type does not have a known width, you
must use the (bits | bytes : num) syntax to specify the width.
Ungenerated Fields
A field defined as ungenerated (with the ! option) is not generated
automatically. This is useful for fields that are to be explicitly assigned during the
test, or whose values involve computations that cannot be expressed in constraints.
Ungenerated fields get default initial values (0 for scalars, NULL for structs, empty
list for lists). An ungenerated field whose value is a range (such as [0..100]) gets the
first value in the range. If the field is a struct, it will not be allocated and none of the
fields in it will be generated.
The ! and % options can be used together, in either order.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_19_PHYSICAL_VIRUAL_FEILDS.html[9/26/2012 2:57:43 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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Index
Introduction
SystemVerilog
Packing and Unpacking Packing performs concatenation of scalars, strings, list E Basics
elements, or struct fields in the order that you specifyUnpacking performs the reverse Data Types
Verification
Operators
operation, splitting a single expression into multiple expressions.
Constructs
Struct
Units
Interface
List
OOPS
Methods
Packing.High
Concurrency Actions
Randomization
Constraints
Places
the
least
significant
bit
of
the
last
physical
field
declared
or
the
highest
list
Functional Coverage
Extend
item at index [0] in the resulting list of bit.
When And Like
Assertion
Events
DPI
EXAMPLE:
UVM Tutorial
<'
structinstruction {
VMM Tutorial
%opcode :uint(bits:3);
Simulator
OVM Tutorial
%operand :uint(bits:5);
Wait And Sync
%address
:uint(bits:8);
Easy Labs : SV
!data_packed_high :listofbit;
Packing N Unpacking
Easy Labs : UVM
keepopcode ==0b100;
keepoperand
==0b11001;
Easy Labs : OVM
Coverage
keepaddress ==0b00001111;
Easy Labs : VMM
Commands
Extendable Methods
do_packs ()is{
AVM Switch TB
data_packed_high =pack(packing.high,opcode,operand);
And Gate Evc
};
TUTORIALS
PACKING N UNPACKING
Verilog
extendsys{
instruction :instruction;
run()isalso{
instruction.do_packs();
printinstruction;
print"----------------------------";
out(" %b \n",instruction.data_packed_high );
}
};
'>
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
RESULT:
instruction = instruction-@0: instruction
@test
0 %opcode:4
1 %operand: 25
2 %address: 15
3 !data_packed_high:(8 items)
"----------------------------" = "----------------------------"
%b
10011001
Packing.Low
Places the least significant bit of the first physical field declared or lowest list item at
index [0] in the resulting list of bit.
http://testbench.in/SP_20_PACKING_N_UNPACKING.html[9/26/2012 2:57:53 PM]

input is what keeps
with time!
Syntax Examplei_stream = pack(packing.high, opcode, operand1, operand2);

EXAMPLE:
<'
structinstruction {
%opcode :uint(bits:3);
%operand :uint(bits:5);
%address :uint(bits:8);
!data_packed_low :listofbit;
keepopcode ==0b100;
keepoperand ==0b11001;
keepaddress ==0b00001111;
do_packs ()is{
data_packed_low =pack(packing.low,opcode,operand);
};
};
extendsys{
instruction :instruction;
run()isalso{
instruction.do_packs();
printinstruction;
print"----------------------------";
out(" %b \n",instruction.data_packed_low );
}
};
'>
RESULT:
instruction = instruction-@0: instruction
@test
0 %opcode:4
1 %operand: 25
2 %address: 15
3 !data_packed_low: (8 items)
"----------------------------" = "----------------------------"
%b
00110011
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Index
Introduction
E Basics
SystemVerilog
There are two ways to generate data:
Data Types
1.Pre-run generation
Verification
Operators
2.On-the-fly generation
Constructs
Struct
Units
Interface
List
Pre-Run Generation
OOPS
Methods
Randomization
-Specman Elite solves the constraints for each field under sys and randomly generates Concurrency Actions
Constraints
values for them when the Test command is issued.
Functional Coverage
-Pre-run generation is automatic for every struct and unit whose instance is under sys. Extend
When And Like
Assertion
-Structs and units generated in this way are static in nature.
Events
-User
can
also
suppress
pre-run
generation
using
!
(do
not
generate)
DPI
-Advantage: Quickly shows what the generator will produce
UVM Tutorial
VMM Tutorial
Simulator
OVM Tutorial
On-The-Fly Generation
Wait And Sync
Easy Labs : SV
-Is activated explicitly using gen action.
Packing N Unpacking
Easy Labs : UVM
-Can be used to generate fields or method variables.
-Saves
memory
when
generated
structs
are
disposable.
Easy Labs : OVM
Coverage
-Is recommended for generating stimulus data structs.
Easy Labs : VMM
Commands
-Cannot be used to generate units.
-On-the-fly generation is done with the gen action, which canbe called from Extendable Methods
AVM Switch TB
methods or TCMs.gen expression [keeping {constraint-block}];
VMM Ethernet sample -Lets the generator react to the DUT current state
And Gate Evc
TUTORIALS
PRE RUN N ON THE FLY
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_21_PRE_RUN_N_ON_THE_FLY.html[9/26/2012 2:58:03 PM]

input is what keeps
with time!
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TUTORIALS
COVERAGE
SystemVerilog
Functional coverage is a method which allows the verification engineer to objectively

evaluate how well a user defined abstraction space is covered. This space can be
internal or external to the DUT and can occur at any abstraction level.
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
Functional coverage indicates how well your testbase fulfills the test plan goals.Test
plan goals might include:
-Testing a complete range of interesting input stimuli
-Testing a complete set of key internal states
-Testing a complete set of sequences of stimuli or states
-Evaluating performance
The three types of coverage data that you might want to collect are:
--Coverage data for the finite state machine (FSM).
--Coverage data for the generated instructions.
--Coverage data for the corner case.
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Coverage Groups
Coverage groups are struct(or unit) members They have an associated event to know when to sample data. The event must be
Easy Labs : VMM
declared in the same struct or unit as the coverage group. Coverage groups can be
defined with coverage group options. Controls collection, grading, and display
AVM Switch TB
of the group. Coverage groups contains coverage items. The value of each coverage
VMM Ethernet sample item is recorded when the coverage event occurs.
Easy Labs : OVM
Verilog
Verification
Syntax cover event-type [using coverage-group-option, ...] is {coverage-item- Report a Bug or Comment
definition; ...};
input is what keeps
cover event_type is empty;
with time!
Verilog Switch TB
Basic Constructs
Cover Group Options

OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
--------------------------------------------------------------------OptionDescription
--------------------------------------------------------------------count-onlyReduces memory usage:no time info stored
and no post-process cross.
text = string Text description for this coverage group
shown in coverage report.
when = bool-exp Collects coverage only when boolean
expression evaluates to TRUE
radix = DEC\HEX\BIN Displays radix for each items bucets.
weight = uint Specifies grading weight relative to other
groups. Default is 1.
at_least = uint Minimum number of samples for each bucket.
If less reports a coverage hole.
ignore = bool_exp Ignores sample if bool_exp is TRUE
illegal = bool_expCauses dut_error() if bool_exp is TRUE
ranges = {range(parameters);
Specifies interesting ranges for int/uint types.
---------------------------------------------------------------------
http://testbench.in/SP_22_COVERAGE.html[9/26/2012 2:58:12 PM]
Cross-Coverage
ItemA cross coverage item is the cross product(matrix) of two or more previously
declared basuic items. It Can cross any number of items declared in the same
coveragegroup. This can also be done in e code or interactively, using Coverage
GUI. Options for cross aresameas for basic items are available, except using ranges.
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TUTORIALS
COMMANDS
SystemVerilog
To run a simple hello.e file
Verification
Constructs
Interface
OOPS
Randomization
$ specman c load hello.e;test;

To change seed,
specman c load enumerate.e;test;test seed=random
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_23_COMMANDS.html[9/26/2012 2:58:22 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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TUTORIALS
EXTENDABLE METHODS
SystemVerilog
global.init() - actions that relate to interactive work before test execution

global.setup_test() - configuration and preparation for the run
struct.init() -initialization within structs that are instantiated using the new
expression
struct.pre_generate() - preparations for generation
struct.post_generate() - actions that concern generation and require the struct's
generated data
global.start_test() - actions at the beginning of simulation that require all the
generated data
struct.run() - invocation of TCMs and explicit emission of events
global.extract_test() - global preparation of data after simulation and before checking
struct.extract() - struct-specific preparation of data after simulation and before
checking
struct.check() - post-run checking
global.finalize_test() - post-test actions
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_24_Extendable_Methods.html[9/26/2012 2:58:29 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
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Index
Introduction
E Basics
SystemVerilog
global.generate_test() - generates the tree of structs
Data Types
struct.generate() - generates a specific struct
Verification
global.run_test() - executes the run() method and starts event threads for all the Operators
Constructs
Struct
structs
global.stop_run() - ends the simulation run and calls the quit() method for all the Units
Interface
List
structs
OOPS
Methods
struct.quit() - deactivates all TCMs and events of the struct
Concurrency Actions
global.check_test() - executes the check() method for all the structs
Randomization
Constraints
Functional Coverage
Extend
When And Like
Assertion
Events
DPI
UVM Tutorial
VMM Tutorial
Simulator
OVM Tutorial
Wait And Sync
Easy Labs : SV
Packing N Unpacking
Easy Labs : UVM
Easy Labs : OVM
Coverage
Easy Labs : VMM
Commands
Extendable Methods
AVM Switch TB
Non Extendable
VMM Ethernet sample
Methods
And Gate Evc
TUTORIALS
NON EXTENDABLE METHODS
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
http://testbench.in/SP_25_Non_Extendable_Methods.html[9/26/2012 2:58:38 PM]

input is what keeps
with time!
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TUTORIALS
AND GATE EVC
SystemVerilog
CODE : item.e
<'
typevector_kind:[INPUT,OUTPUT];
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
structvector_slike any_sequence_item{
kind :vector_kind;
a:bit;
b:bit;
output :bit;
};
'>
CODE : sequence.e
<'
sequence vector_sequence usingitem=vector_s,
created_driver =seq_driver,
created_kind =seq_kind_t;
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
extendvector_sequence {
!vector :vector_s;
};
'>
CODE : main_seq.e
<'
extendMAINvector_sequence {
// Limit the no. of sequences (use predefined count)
keepsoftcount==10;
// Start start assertion ...
pre_body()@sys.any isfirst{
driver.raise_objection(TEST_DONE);
};
// Call's stop_run after end of all sequences (refer erm)

post_body()@sys.any isalso{
RVM Switch TB
wait[20]*cycle@driver.clock;
RVM Ethernet sample driver.drop_objection(TEST_DONE);
};
};
Switch TB
Specman E
Interview Questions
'>
CODE : seq_driver_h.e
<'
extendseq_driver {
agent :agent_u;
};
'>
CODE : seq_driver.e
<'
http://testbench.in/SP_26_AND_GATE_EVC.html[9/26/2012 2:58:47 PM]
Index
Introduction
E Basics
Data Types
Operators
Struct
Units
List
Methods
Concurrency Actions
Constraints
Extend
When And Like
Events
Simulator
Wait And Sync
Packing N Unpacking
Coverage
Commands
Extendable Methods
And Gate Evc
input is what keeps
with time!
extendseq_driver {
eventclock isonly@agent.clk;
keepbfm_interaction_mode ==PULL_MODE;
send_items()@clock is{
varitem:vector_s;
whileTRUE{
item=get_next_item();
agent.bfm.send_vector(item);
emititem_done;
};
};
run()isalso{
startsend_items();
};
};
'>
CODE : testcase.e
<'
extendMAINvector_sequence {
body()@driver.clock isonly{
//for i from 0 to 9 {
dovector keeping{
.kind ==INPUT;
};
printvector.a;
printvector.b;
dovector keeping{
.kind ==OUTPUT;
};
printvector.output;
//};
};
};
'>
CODE : agent_h.e
<'
unitagent_u {
};
'>
CODE : agent.e
<'
extendagent_u {
keephdl_path()=="~/and_gate_tb";
bfm:bfm_u isinstance;
driver :seq_driver isinstance;

coverage :coverage_u isinstance;
sb:scoreboard_u isinstance;
monitor:monitor_u isinstance;
sig_a:string;
sig_b:string;
sig_c:string;
sig_clk:string;
verilogtask '$shm_close'();
verilogvariable'a' usingwire;
verilogvariable'b' usingwire;
verilogvariable'c' usingwire;
keepbfm.agent ==me;
keepdriver.agent ==me;
keepcoverage.agent ==me;
keepmonitor.agent ==me;
keepsig_a =="a";
keepsig_b =="b";
keepsig_c =="c";
keepsig_clk =="clk";
eventclk isrise('(sig_clk)')@sim;
close_waveform()@clk is{
'$shm_close'();
wait[2]*cycle;
sys.drop_objection(TEST_DONE);
};
};
'>
CODE : coverage_h.e
<'
unitcoverage_u {
agent:agent_u;
eventcover_event;
};
'>
~
CODE : coverage.e
<'
extendcoverage_u {
covercover_event usingtext="coverage for inputs a,b"is{
itema :bit=agent.sb.a;
itemb :bit=agent.sb.b;
crossa,b usingtext="cross coverage";
};
};
'>
CODE : scoreboard_h.e
<'
unitscoreboard_u {
};
'>
CODE : scoreboard.e
'
extendscoreboard_u {
a:bit;
b:bit;
output:bit;
};
'>
CODE : monitor_h.e
<'
unitmonitor_u {
agent:agent_u;
};
'>
CODE : monitor.e
<'
extendmonitor_u {
checker()is{
if((agent.sb.a &agent.sb.b)==agent.sb.output){
}
else{
dut_error("output mismatch");
};
};
};
'>
CODE : bfm_h.e
<'
unitbfm_u {
agent:agent_u;
};
'>
CODE : bfm.e
<'
extendbfm_u {
eventclk is@agent.clk;
send_vector(vec:vector_s)@clk is{
ifvec.kind ==INPUT{
'(agent.sig_a)'=vec.a;
'(agent.sig_b)'=vec.b;
wait[1];
agent.sb.a=vec.a;
agent.sb.b=vec.b;
emitagent.coverage.cover_event;
};
ifvec.kind ==OUTPUT{
vec.output='(agent.sig_c)';
agent.sb.output=vec.output ;
wait[1];
agent.monitor.checker();
};
};
};
'>
CODE : env.e
<'
unitenv_u{
agent:agent_u isinstance;
};
'>
CODE : top.e
<'
importimport_files.e;
extendsys{
env :env_u isinstance;
stop_wave:bool;
keepsoftstop_wave ==FALSE;
all_objections_dropped(kind:objection_kind)isalso{
ifkind ==TEST_DONEand!stop_wave {
raise_objection(TEST_DONE);
startenv.agent.close_waveform();
message(LOW,"close_waveform()");
stop_wave =TRUE;
};
};
};
'>
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TUTORIALS
FUNCTIONAL VERIFICATION QUESTIONS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i1)Explaino ehowi tooinject qare crc ierroroq jinre a ipacket owhichqhas justz
datau yande ocrczx fields.
Ans:
Crc ierroro einjecttioni canobe qdonere by imodifyingoq jthere crc ivalue oonly.q
If idatao eisi modifiedoto qinjectre crc ierror,oq jthenre it imay oendqup inz au
ysituatione othatzx the new modified packet may have the same crc.
For iexampleo e,i aopacket qofre length i5oq jbitsre with i3 obitsqof dataz andu y2e
obitszx of crc value.
Then ithereo ewilli beo8 qpacketsre of idifferentoq jdata.re There iare oonlyq4
possiblez crcu yvalues.e o
So, iforo eonei crcovalue, qtherere could ibeoq jmorere than ione odataqvalues
whichz areu ycorrect.
www.testbench.in
If iyouo emodifyi theodata, qthenre the inewoq jdatare may ihave otheqsame crcz
value,u ywhiche owillzx not be resulted as crc error.
For ioneo edatai field,othere qwillre one ionlyoq jonere crc ivalue, obyqchanging
thez crcu yvalue,e ocrczx error will be injected for sure.
(Q i2)o eHowi dooyou qknowre when iverificationoq jcompleted?
Ans: i
VMM Ethernet sample Verification iiso eneveri completedoas qperre me. i
Verilog
I icano eonlyi sayothat qmyre verification itaskoq jisre completed iwhen oIqverified
allz theu ypointse omentionszx in test plan.
Verification
(Q i3)o eHowi toodetect qdeadlockre conditions iinoq jFSMsre ?
Verilog Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Basic Constructs
(Q i4)o eHowi tooavoid qracere condition ibetweenoq jTestbenchre and iDUT o?

www.testbench.in
Ans:
OpenVera
In iverilogo eori VHDL,o
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave oaqphase
Switch TB
difference.z
RVM Switch TB
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iwork
RVM Ethernet sample oonqnegedge ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven iusing
ononqblocking statements.
Constructs
Specman E
Interview Questions
In iSV,o e
1)The iaboveo edefinei 3otechniques.
2)Clocking iblocks.
www.testbench.in
3)Program iblock.
(Q i5)o eWhati isomutex?
Ans:
A imutualo eexclusioni oroMUTEXessential qfunctionre is itooq jmakere it ipossible
oforqa multiplez processesu ytoe omakezx use of a single resource.
http://testbench.in/IQ_01_FUNCTIONAL_VERIFICATION_QUESTIONS.html[9/26/2012 2:58:56 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
When iao esinglei resourceois qrequiredre by imultipleoq jprocesses,re MUTEX iwill

omakeqsure thatz onlyu yonee oprocesszx will be granted the access at a time.
For iexample,
A iDUTo ehasi aomemory qtore store itheoq jconfigurationre registers. iTo
oaccessqthe memory,z letsu ysay,e oazx protocol is defined to read the memory of
one location at a time.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Testbench imayo erequirei tooaccess qthere configuration/status/interrupt

iregistersoq jatre times ifrom odifferentqplaces. Forz example,u yae omonitorzx is
reading register location of status bit, while the testcase is reading a configuration
register.
To iaccesso ethei memory,oTestcase qandre monitor iwilloq jsendre the iaddress
oofqthe locationsz andu yreade ocommand.zx But the DUT can accept only one read
request at a time.
www.testbench.in
By iusingo eMUTEX,i accessoto qmemoryre interface icanoq jbere granted ionce

oatqa time,z sou ythee oreadzx operations by monitor and testcases will not collide.
In iSV,o etoi createoa qMUTEX,re construct iaoq jsemaphorere with ione okey.
A ikeyo eisi giventooeither qmonitorre or itestcaseoq jtore read ioperation
obasedqon whoz comesu yfirst.e oOncezx the key is returned, other waiting
component can take the key and start its operation.
Some itimes,o ethei keyowhich qisre consumed imayoq jnotre be iretuned
owhichqleads toz deadu ylocke ocondition.zx So if a key is not returned, then a
timeout should happen and a error message should be triggered.
(Q i6)o eWhati isosemaphore?
Ans:
Conceptually, iao esemaphorei isoa qbucket.re When iaoq jsemaphorere is iallocated,
oaqbucket thatz containsu yae ofixedzx number of keys is created. Processes using
semaphores must first procure a key from the bucket before they can continue to
execute. If a specific process requires a key, only a fixed number of occurrences of
that process can be in progress simultaneously. All others must wait until a sufficient
number of keys is returned to the bucket. Semaphores are typically used for mutual
exclusion, access control to shared resources, and basic synchronization.
www.testbench.in
(Q i7)o eWhati isothe qneedre of iregression?

Ans:
1) iChangeso eini theoRTL q(re development, ienhancementoq jorre bug ifix)
omayqcause existingz functionalityu ytoe obreak.zx
2) iToo ecreatei newoscenarios qbyre giving idifferentoq jseedsre to irandomization
oengine.q
(Q i8)o eWhati isorandomization?
Ans:
It iiso enoti possibleoto qlistre out ieveryoq jpossiblere real itime oscenarioqwhile
verifyingz DUT.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
If iweo etryi toolist qoutre the iscenarios,oq jthenre we imay omissqsome ofz them.u
ySo,e ousingzx randomization, based on the specification, scenarios are generated in
a randomfashion.
For iexample,o etoi generateoa qpacketre of ilengthoq jwhichre ranges ifrom0
otoq9, inz verilogu y{$random()}e o%zx 10 should be used.
With ithis,o epacketsi ofolength qarere generated irandomly.oq j
www.testbench.in
(Q i9)o eWhati isothe qsignificancere of iseedoq jinre randomization?

Ans:
Seed iiso eusedi toochange qthere sequence iofoq jrandomre numbers igenerated.
The iseedo einitializesthei randomonumber qgenerator.re
All itheo erandomi numbersowhich qarere generated ifromaoq jparticularre seed
ivalue ocanqbe recreatedbyz givingu ythee osamezx seed.

input is what keeps
with time!
In iouro eregressions,i stimulusogeneration qisre done irandomly.oq jRunningre the

icomplete oregressionqwill generatez sameu yrandome onumberszx if we use same
seed.
So iouro eregressioni usesothe qtimere of itestoq jcasere simulation istarted oasqthe
seedz tou yrandome onumberzx generator, with this we are able to generate
different stimulus for each regressions.
(Q i10)o eWhati isothe qdifferencere between icodeoq jcoveragere and ifunctional
ocoverage?
Ans:
www.testbench.in
Coverage iiso eusedi toocheck qwhetherre the iTestbenchoq jhasre satisfactory

iexercised otheqdesign orz not?u y
Code icoverageo ewilli giveoinformation qaboutre how imanyoq jlinesre are
iexecuted, ohowqmany timesz expressions,u ybranchese oexecuted.zx This coverage
is collected by the simulation tools. Users use this coverage to reach those corner
cases which are not hit by the random testcases. Users have to write the directed
testcases to reach the missing code coverage areas.
Functional icoverageo e,i byothe qnamere itself i,oq jisre related ito
otheqfunctionality ofz theu ydesigne oandzx it is defined by the user. User will define
the coverage points for the functions to be covered in DUT. This is completely under
user control.
Both iofo ethemi haveoequal qimportancere in itheoq jverification.re
1000.000000unctional icoverage odoesqnot meanz thatu ythee oDUTzx is completely
exercised and vice-versa. Verification engineers will consider both coverages to
measure the verification progress.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i11)o eIfi CodeoCoverage qisre 100% iandoq jfunctionalre coverage iis onot,qwhat
doesz itu ymeane o?
Ans:
The ireasono ecouldi beoany qonere of itheoq jfollowing.
www.testbench.in
1)User ididnoto eexercisei allothe qscenarios.re User ineedoq jtore write itestcases
otoqfill thez functionalu ycoveragee oholes.
2)There icouldo ebei aobug qinre the ifunctionaloq jcoveragere block iwhich oisqnot
recordingz theu yexecutede oscenario.zx User need to debug to find and fix the issue.
(Q i12)o eIfi Functionalocoverage qisre 100% iandoq jcodere coverage iis onot,qthen
whatz doesu yite omean?
Ans:
1) iIfo etherei isoa qbugre in itestoq jenvironment,re due ito othisqtest mayz falseu
yPass.e oThezx functional coverage will hit due to this false pass but some of the dut
code may not get exercised.
2) iIfo ethei dutois qare legacy icodeoroq jIP,re it imay ohaveqsome usez lessu
yblockse otozx support extra functionality. Due to this code coverage will not be 100%
achieved.
3) iIno emyi firstocompany,there qwasre some iuseoq jlessre logic iwhich odidqnot
getz exercised.u yWhene oIzx approached the RTL designer, he said that fixing this
use less code will break the whole design. So he did not fix it. In this situation ,
functional coverage is 100%, but not the code coverage.
4)My ifriendso eexperience,i onceoRTL qdesignerre added iaoq jcodere for ia
onewqfeature.Because ofz missu ycommunication,e omyzx friend didnt know that
RTL designer added this new functionality.
When imyo efriendi didothe qcodere coverage, iheoq jfoundre some iunexercised
ologicqwhich hez didntu yunderstoode oandzx approached RTL designer. Then they
figured out that because of miscommunication,they found a feature in the spec
which was implemented, but not verified.
www.testbench.in
I idonto ethinki ,opoint q2)re can ibeoq javoided.re Point i1), o3)qand 4)z canu ybee
osolved.zx
(Q i13)o eWhati isothe qdifferencere between ipassiveoq jmonitorre and iactive
omonitor.
Ans:
Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere

transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive monitors
do not drive any signals, all the signals are inputs.Active monitors can drive the DUT
signals. Sometimes this is also refered as receiver.Monitor converts the state of the
design and its outputs to a transaction abstraction level so it can be stored in a 'scoreboards' database to be checked later on.Monitor converts the pin level activities in
to high level.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i14)o eIni simulationoenvironment, qunderre what iconditionoq jthere simulation

ishould oend?
Ans:
1) iPacketo ecounti match.
2) iError
3) iErroro ecount
www.testbench.in
4) iInterfaceo eidlei count

5) iGlobalo etimeout
(Q i15)o eWhati isoscoreboard?
Ans:
The itermo eSCOREBOARDi isonot qwell-definedre in itheoq jindustry.re It isometimes
orefersqto thez storageu ydatae ostructurezx only, sometimes it includes the transfer
function as well, and sometimes it includes the comparison function. In vmm
methodology, the term scoreboard is used to refer to the entire dynamic responsechecking structure.
(Q i16)o eHowi theotest qcasesre are iincludedoq jinre to isimulation oenvironment?
Ans:
There iareo emultiplei waysoto qdore this. i
Two iveryo esimplei stylesoare qdiscussedre in ibelowoq jlink.
Click
on
the
below
http://www.testbench.in/TB_29_HANDLING_TESTCASE_FILES.html
link
www.testbench.in
(Q i17)o eWhati areothe qdifferentre ways itestcaseoq jarere included ifor

osimulationsq?
Ans:
1)Compile ionce,o esimulatei multipleotimes qwithre different itestcases:oq j
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Compile iTestbencho e+i Allotestcases qatre once iandoq jduringre the isimulation,
ousingqthe $plusargs,z selectu ythee ologiczx of a particular testcase and execute it.
This istyleo eisi suedoin qOVMre and iUVM.oq j
This istyleo eshouldi makeosure qthat,re when itheoq jtestre is iexecuted
ofromqcommand line,onlyz Testbenchu y+e orequiredzx testcase should be
compiled. Other wise, compiling all the testcases will consume huge time.
In iregression,o eCompilingi allothe qtestcasesre + itestbenchsoq jatre once iwill
osaveqtime.
2)Separate icompilation:
www.testbench.in
Compile itheo etestbenchi once.Toorun qare testcase, icompileoq jthere testcase i,

olinkqthe testcasez tou ytestbenche ocompiledzx code and simulate.
3)Compile ionce,o esimulatei once:o
All itestcaseso ewithi similaroconfiguration qsettingre and itestbenchoq jarere
compiled ionce oandqsimulated inz oneu ysinglee orun.Afterzx executing each
testcase logic, HARD reset should be applied to DUT and BFMs, so that the simulation
looks as if it started fresh for the next testcase code.
This istyleo eisi usedoin qVMMre 1.2.This istyleoq jsavesre lot iof otimeqin
regressions.
4)Compile ionce,o esimulatei multipleotimes qwithre different idata:oq j
In isomeo everificationi environments,otestcase qcodere doesnt ineedoq jtore be
icompiles. oTestcaseqfile containsz someu ydatae owhichzx is read by testbench to
create different scenarios. Testcase file can be read using $fopen or $plusargs in
Verilog.
There icouldo ebei manyomore qwaysre to idooq jthis.re

www.testbench.in
If iyouo eknowi somethingowhich qisre not imentionedoq jabovere , iplease otakeqa

minutez tou ymaile oitzx to gopi@testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i18)o eExplaini howomessages qarere implemented iinoq jyourre testbench?

Ans:
In
iVMM/RVM/AVM/OVM/UVM/ERM/Truss&Tealo
emethodologies,messagei
handlingologic qisre predefined. iUseoq jcanre use ithese opredefinedqmessage
servicesz andu yprinte omessageszx as required by testbench. If above methodology
base classes are not used, then user can define his own message handling logic.
I ihaveo edefinedi aosimple qverilogre logic, ilookoq jforre Message iControl
oSystemqtopic inz theu ybelowe olink
Click on the below link http://www.testbench.in/TB_23_DEBUGGING.html
www.testbench.in
(Q i19)o eWritei codeofor qclockre generator?

Ans:
reg iclk;
initial iclko e=i 0;o
always i#10o eclki =o~clk; q
(Q i20)o eHowi toopass qare value itooq jtestbenchre from icommand oline?
Ans:
Click on the below link
http://www.testbench.in/TB_22_COMPILATION_N_SIMULATION_SWITCHS.html
(Q i21)o eWhati isotest qplanre ? iWhatoq jitre contains i?
Ans:
www.testbench.in

http://www.testbench.in/TS_24_VERIFICATION_PLAN.html
(Q i22)o eExplaini someocoding qguidelinesre which iyouoq jfollowedre in iyour
oenvironment?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i23)o eExplaini aboutowhite qbox/blockre box iandoq jgrayre box itesting.

Ans:
http://www.testbench.in/TB_34_WHITE_GRAY_BLACK_BOX.html
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TUTORIALS
FUNCTIONAL VERIFICATION QUESTIONS 2
SystemVerilog
(Q i24)o eWhati areothe qadvantagesre and idisadvantagesoq jofre State imachine

obasedqand taskz basedu yverificatione oenvironment.
Ans:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
state imachineo ebasedi BFMouses qare state imachineoq jtore generate ithe
obusqcycles. SMz wouldu ygeneratee omemoryzx read, memory write, I/O read, and
I/O write cycles.
State imachineso earei alsoogood qatre handling iburstingoq jandre early
itermination. oItqcould alsoz beu ysetupe otozx handle special cycles like interrupt
acknowledge or shutdown.
Use itasko ebasedi BFMofor qunitre testing. iUnitsoq jarere often iless
ocomplexqthan thez wholeu ysystem,e oandzx hence, do not need a robust test
bench. A simple BFM can facilitate the early testing of a complex block especially if
the unit has a simple interface or just one bus interface. The task based BFM is
extremely efficient if the device under test performs many calculations but uses
relatively few bus access cycles to keep it going. The reason for this is, the BFM is not
looping through an idle state every clock cycle. The BFM does not toggle any signals
when a task is not active. Nor, does it make any decisions based on input when a task
is not active.
(Q i25)o eIni aopacket qprotocol,re where itheoq jpacketre comparison iis odone?
Ans:
In iscoreboard.
www.testbench.in
(Q i26)o eWhati areotypes qofre code icoveragesoq jarere there?

Ans:
http://www.testbench.in/TS_11_TYPES_OF_CODE_COVERAGE.html
(Q i27)o eWhati typesoof qfunctionalre coverages iareoq jthere?
Ans:
http://www.testbench.in/TS_20_FUNCTIONAL_COVERAGE.html
Switch TB
(Q i28)o eExplaini aboutodriver qandre monitor i?

Ans:
RVM Switch TB
Driver:
RVM Ethernet sample
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Specman E
Interview Questions
The idriverso etranslatei theooperations qproducedre by itheoq jgeneratorre into ithe

oactualqinputs forz theu ydesigne ounderzx verification. Generators create inputs at
a high level of abstraction namely, as transactions like read write operation. The
drivers convert this input into actual design inputs, as defined in the specification of
the designs interface. If the generator generates read operation, then read task is
called, in that, the DUT input pin "read_write" is asserted.
www.testbench.in
Monitor:
Monitor ireportso ethei protocoloviolation qandre identifies ialloq jthere
transactions. iMonitors oareqtwo types,z Passiveu yande oactive.zx Passive monitors
do not drive any signals.Active monitors can drive the DUT signals. Sometimes this is
also refered as receiver.Monitor converts the state of the design and its outputs to a
transaction abstraction level so it can be stored in a 'score-boards' database to be
checked later on.Monitor converts the pin level activities in to high level.
http://testbench.in/IQ_02_FUNCTIONAL_VERIFICATION_QUESTIONS_2.html[9/26/2012 2:59:08 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
(Q i29)o eWhati
ostimulusqstorage?
Ans:
typeoof
qdatare
structure
iisoq
jusedre
to
iimplement on This section - Your
input is what keeps

with time!
1) iIno eSV,i Queueois qbestre to ido.oq j

2) iIno everai ,olinked qlistre is itheoq jbestre one ito ouse.
3) iDatao ecani alsoobe qstoredre in iexternaloq jfilesre also iusing ofileIOqor
externalz languageu yinterface.
www.testbench.in
I ilikeo epointi 3.oThe qexternalre file iwilloq jbere availabe iafter osimulation.qSo
,z thisu yfilee ocouldzx be used for debugging.
(Q i30)o eHowi registers(configurationoregisters) qarere verified?
Ans:
In iVMM,o ereadi aboutoRAL.
Read ithiso etopici also:
Click
on
the
below
http://www.testbench.in/TB_32_REGISTER_VERIFICATION.html
link
(Q i31)o eWhati isoBFM?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i32)o eWhati isoshadow qregister?

www.testbench.in
Ans:
Analogous istructureo eofDUTi configuration,ostatus, qinterruptre registers iareoq

jimplementedre in itestbench. oTheseqare calledz shadowu yregisters.
These
iareo
erequiredi
fororegister
qverification.re
In
inormaloq
jverification,Testbenchre requires ithe oDUTregisterqinformation forz takingu
ydecisions.e o
(Q i33)o eExplaini aboutothe qbackre door iaccessoq jtore registers.
Ans:
DUT iConfiguration,o estatusi andointerrupt qregisterre can ibeoq jaccessedre as iper
otheqprotocol.
To iaccesso ethesei registersousing qthere protocol iwilloq jconsumere cycles. i
Generally i,o eonlyi onceoregister qisre allowed itooq jaccessre as iper oprotocol.
www.testbench.in
To iovero ethei aboveomentioned qdisadvantage,hierarchalre path icanoq jbere

used. iThis oisqcalled backdoorz access.
While iverifyingo ethei registers,oa qwritere operation iisoq jdonere to ia
olocationqand thenz au yreade oiszx done. Then the written data is compared against
the read data to verify the access path.
But iwhato eifi theoaddress qdecoderre and iencoderoq jhasre the isame obugq? Toz
findu youte othis,zx write operation is done as per the protocol and read is done using
backdoor.Then the written data is compared against the read data to verify the
access path.
(Q i34)o eWhati areoReference qandre behavioral imodelsoq j?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The itermo e'Referencei Model'odefines qwhatre it's iusedoq jfor,re whereas

i'Behavioral oModel'qdefines howz it'su ybeene oimplemented.zx
(Q i35)o eWhati isothe qusere of ilintingoq jtoolre ?
Ans:
www.testbench.in
Linting itoolso earei theotools qthatre flag isuspiciousoq jlanguagere usage iand
oerror-proneqsyntactical constructs.z Lintingu ytoolse ogenerallyzx perform static
analysis of source code. Linting tools can help programmer find dangerous code before
a compiler turns them into run-time bugs.
Sone ilintingo etools:i Leda,oHDLint, qnLint,re Surelite ietc
(Q i36)o eWhati areothe qkeyre tools iforoq jfunctionalre verification?
Ans:
Version
icontrolo
esystem,makei
utility,scriptingolanguages,bug
qtracker,Simulatorre ,debugger.
(Q i37)Whato edoesi TestoAutomation qmean?
Ans:
Building iano eenvironmenti thatotests qthere DUT iautomaticallyoq jInsteadre of
ichecking otheqDUT byz eye,u ygete ocomputerszx to do the work for us.
www.testbench.in
(Q i38)o eHowi tooassure qyourre verification ienvironmentoq jisre correct/complete

i?
Ans:
Im inoto esure.i Ifou qknowre send imeoq janswerre to igopi@testbench.in
What iIo ecani thinkoare:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
1)Connect imonitoro etoi driverosuch qthatre driver icyclesoq jarere monitored iby
omonitor.Injectqerror fromz driveru yande ocheckzx whether monitor an catch the
error.
2)If iyouo ehaveRTL,i thenochange qsomere lines iofoq jRTLre code iand
oseeqwhether testbenchz canu ycatche othezx errors.
(Q i39)o eWhoi shouldodo qthere rtl idebugoq j?re The idesigner o?qThe VEz ?
Ans:
www.testbench.in
RTL icano ebei debuggedoby qdesignerre or iverificationoq jengineer.re I ipersonally

ofeelqthat Verificationz shouldu ydebuge oRTLzx issues.
Designer icano edebugi theortl qfasterre than iVerificationoq jengineerre as ithe
odesignerqhas morez knowledgeu yone othezx RTL architecture.
More itimeo eisi requiredoby qverificationre engineer itooq jdebug.
If iVerificationo eengineeri isodebugging, qhere gets ichanceoq jtore think iabout
omoreqscenarios toz verifyu ythee oRTLzx by looking at RTL architecture.
<< PREVIOUS PAGE
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TUTORIALS
TEST YOUR SYSTEMVERILOG SKILLS 1
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
(Q i1)o eWhati isothe qnamere of itheoq jmethodre in iwhich ocovergroupqis

constructedz inu yyoure oprojectzx ?
(Q i2)o eAi methodois qdefinedre a ivirtual.oq jUsingre extended
ohandle/object,qhow toz callu ythee ovirtualzx method defined in base class?
iclass
(Q i3)o eWhati isothe qdifferencere B/W itheoq jvariablere in imodel oandqstatic

variablez inu yclasse o?
(Q i4)o eWhati isothe qdifferencere B/W istatic,oq jautomaticre and idynamic
ovariablesq?
www.testbench.in
VMM Tutorial
(Q i5)o eWhati isothe qdifferencere B/W iverilogoq jfunctionre and iSV ofunctionq?
OVM Tutorial
(Q i6)o eWhati isothe qoutputre of itheoq jfollowingre program i?
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
programmain();
iinitialbegin
ifork
#25$display("time i=o e0i #oT25 q",$time);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
ijoin_none
www.testbench.in
ifork
#20$display(" itimeo e=i 0o# qT20",$time);
ijoin_any
disablefork;
end
iinitial
i#100$finish;
www.testbench.in
Switch TB
endprogram
RVM Switch TB
(Q i7)o eWhyi Constructorois qnotre virtual i?
RVM Ethernet sample
(Q i8)o eDoi weoneed q"virtualre constructor" ifunctionalityoq j?re If iyes, othenqwhy

isz itu yrequirede o?
Specman E
(Q i9)o eHowi tooachieve q"virtualre constructor" ifunctionalityoq j?
Interview Questions
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i10)o eLetsi sayoI qhavere transactions ia,b,c,d,e.

www.testbench.in
iIo ewouldi likeoto qgeneratere transaction iseriesoq jlike

i(1)A,o e
i(2)o eBi oroC,
i(3)D,
i(4)o eifi Bois qgeneratedre in isecondoq jpositionre then igenerate oDqand nextz
gou ytoe o(5)zx or jump to (1) again,
http://testbench.in/IQ_03_TEST_YOUR_SYSTEMVERILOG_SKILLS_1.html[9/26/2012 2:59:21 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
i(5)o eE,i gooback qtore (1)

input is what keeps
(Q i11)o eWritei ao$display qstamenre to iprintoq jthere value iin oaqenumerated with time!
iHowo etoi implementothis q?
variable.z
www.testbench.in
(Q i12)o eWhati isothe qdifferentre between i`defineoq jandre "let" i?

(Q i13)o eWhyi defaultoclocking qblockre is irequiredoq j?
(Q i14)o eWhati isothe qoutputre of itheoq jfollowingre ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
moduleques();
stringstrin[7];
www.testbench.in
inti,j,k,file;
initialbegin
strings;
file i=$fopen("file.txt","r");
while(!$feof(file))begin
k=$fscanf(file,"",s);
strin[i]=s;
i++;
end
www.testbench.in
$fclose(file);
foreach(strin[j])
$display("index ij=o e0stringi =",j,strin[j]);
$finish;
end
endmodule
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
content iino efile.txt

www.testbench.in
================
aa
bb
cc
================
Ans:
Index ij=0stringo e=i aa
Index ij=1stringo e=i bb
Index ij=2stringo e=i cc
www.testbench.in
Index ij=3stringo e=i cc

The idatao e"cc"i isoread qtwice.re
This iiso ebecausei ofo$feof. q
(Q i15)o eHowi toodeallocate qanre object i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
When iano eobjecti isono qlongerre needed, iSystemVerilogoq jautomaticallyre

reclaims ithe omemory,qmaking itz availableu yfore oreuse.zx The automatic memory
management system is an integral part of SystemVerilog.
If iusero ewanti toodeallocate, qhere can ijustoq jassignre null ito otheqobject.
www.testbench.in
EXAMPLE:
testclass ib;//Declareo eai handleob qforre testclass
b i=new;//o eConstructai testclassoobject qandre stores itheoq jaddressre in ib
o."new"qallocate spacez foru ytestclass
b=null; i//Deallocateo ethei object.MeansoDeallocate qthere memory ispaceoq
jforre object.
(Q i16)o eWhati isocallback q?
Ans:
Testbenchesmust iprovideo eai "hook"owhere qthere test iprogramoq jcanre inject
inew ocodeqwithout modifyingz theu yoriginale oclasses.
Take iano eexample:i Supposeou qwantre to iinjectoq jare new ifunctionalityin
otheqdriver withoutz modifyingu ythee ocode.zx You can add the new functionality in
pre_callback taskor post-callback task,without modifying Driver task.
taskDriver::run;
www.testbench.in
foreverbegin
...
<pre_callback>//It icallso ethei functionopre_callback.
i
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
transmit(tr);
end
endtask
taskpre_callback;
www.testbench.in
endtask
For imoreo einformation,i
Click on the below link http://www.testbench.in/VM_08_VMM_CALLBACK.html
(Q i17)o eWhati isofactory qpatternre ?
Ans:
EXAMPLE::
classGenerator;
Transaction itr;
mailboxmbx;
www.testbench.in
tr i=new;
taskrun;
repeat(10)
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
begin
assert(tr.randomize);
mbx.put(tr);// iSendo eouti transaction
end
endtask
endclass
Bug::Here iObjecto e"tr"i isoconstructed qoncere outside itheoq jloop.re Then i"tr"
oisqrandomized andz putu ytheme ointozx mailbox "mbx".But mailbox "mbx" holds
only handles,not objects.Therefore Mailbox contains multiple handles pointing to
single object.Here code gets the last set of random values.
www.testbench.in
Solution::Loop ishouldo econtaini

1)Constructing iobjecto e
2)Randomizing iobject
3)Puttting iintoo emailbox
taskrun;
repeat(10)
begin
tr i=new();o e//1.Constructing
assert(tr.randomize);//2.Randomize
www.testbench.in
mbx.put(tr); i//3.Puttingo eintoi mailbox

end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endtask
Second iBug:o eThei runotask qconstructsre atransaction iandoq jimmediatelyre

randomizes iit. oMeansqtransaction "tr"z usesu ywhatevere oconstraintszx are turned
on by default.
Solution i:o eSeparatei theoconstruction qofre tr ifromoq jitsre randomization iby
ousingqa methodz called"Factoryu yPattern".
Factory iPattern:
1)construct iao eblueprinti objecto
2)Randomize ithiso eblueprint(i Itohas qcorrectre random ivaluesoq j)
3)Make iao ecopyi ofothis qobjectre
www.testbench.in
4)Put iintoo emailbox

classGenerator;
mailboxmbx;
Transaction iblueprint;
blueprint i=new;//1.Constructingo eBluei print
taskrun;
Transaction itr;
Repeat(10}
begin
www.testbench.in
assert(blueprint.randomize);//2.Randomizing iBlueo eprint

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
tr i=blueprint.copy;//3.Copyo ethei blueprint

mbx.put(tr);// i4.Puto eintoi mailbox
end
endtask
endclass
(Q i18)o eExplaini theodifference qbetweenre data itypesoq jlogicre and ireg

oandqwire .
Ans:
www.testbench.in
WIRE:
1. iWireo eisi justoan qinterconnectionre between itwooq jelementsre which idoes
onotqhave anyz drivingu ystrength
2. iIto eisi usedofor qmodelingre combinational icircuitoq jasre it icannot ostoreqa
value.
3. iWireo ehasi aodefault qvaluere of i"z""oq jandre get ivalues ocontinuouslyqfrom
thez outputsu yofe odeviceszx to which they are connected to.
4.Example:
wireA;
assignA i=b&c;
Note:wire iAo eisi evaluatedofor qeveryre simulation ideltaoq jtime.re So ithere
oisqno needz tou ystoree othezx value.
REG
www.testbench.in
1. iRego eisi ao4 qstatere unsigned ivariableoq jthatre can ihold oaqvalue andz
retainsu yuntile oazx new value is assigned to it.
2. iRegistero edatai typeocan qbere used iforoq jmodelingre both icombinational
oandqsequential logic
3. iDefaulto evaluei fororegister qisre "x" iandoq jitre doesn't irequire oanyqdriver
toz assignu yvaluee olikezx wire. It can be driven from initial and always block.
Values of the register can be changed anytime in the simulation by assigning a new
value to register.
4.Example: i
regA;
always@(b iorc)
begin
A=b&c;
end
Note:A iiso edeclaredi asoreg qwhichre can ibeoq jevaluatedre only iwhen othereqis
az changeu yine oanyzx of the signal in the sensitivity list. So reg needs to store the
value until there is a change in sensitivity list.
www.testbench.in
LOGIC: i
1. i4o estatei unsignedodata qtypere introduced iinoq jSystemre verilog.
2.System iVerilogo eimprovesi theoclassic qregre data itypeoq jsore that iit ocanqbe
drivenz by
a. iContinuouso eassignments,(ex:assigni crc=~crc;)
b. iGates,o e(ex:i andog1(q_out, qd);re )
c. iModules,o e(ex:i Flp_fopsof1 q(q,re q_out, iclk,rst);oq j)
3.In iadditiono etoi beingoa qvariable.re It iisoq jgivenre the isynonym ologicqso
thatz itu ydoese onotzx look
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
ilikeo eai registerodeclaration. q

www.testbench.in
4.If iyouo eonlyi madeoprocedural qassignmentsre to i'logic'oq jthenre it iwas

osemanticallyqequivalent toz 'reg'.u y
5.A ilogicsignalo ecani beoused qanywherere a inetoq jisre used, iexcept othatqa
logicz variableu ycannote obezx driven by
imultipleo estructurali drivers,osuch qasre when iyouoq jarere modeling ia
obidirectionalqbus.
6.Example: i
modulesample1;
logiccrc,sa i,d,q_out;
logicclk,rst;
initial
begin
clk=1'b0;//procedural iassignment
www.testbench.in
i#10clko e=1'b1;
end
assigncrc=~crc;//continuous iassignment
andg1(q_out, id);o e//q_outi isodriven qbyre gate
Flp_fops if1o e(q,i q_out,oclk,rst); q//qre is idrivenoq jbyre module
endmodule
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i19)o eWhati isothe qneedre of iclockingoq jblocksre ?

www.testbench.in
Ans:
Any isignalo eini aoclocking qblockre is idrivenoq jorre sampled isynchronously,

oensuringqthat yourz testbenchu yinteractse owiththezx signals at the right time.
The i"skew"o eavoidsi raceoconditions qbetweenre Testbench iandoq jDUT.
EXAMPLE:
clockingcb i@(posedgeclk);//clockingo eblocki cbodeclares, qsignalsre inside
iractiveoq jonpositivere edge iof oclk.
defaultinput#1ns ioutput#2ns;//o eInputi skewoand qoutputre skew, i
outputrequest;//output ifromDUTtoo etestbench
inputgrant i;//Inputo efromi testbenchoto qDUT
endclocking
Note: iIinputo esignals(grant)arei sampledoat q1nsre before iclockoq jeventre and
ioutput(request) oareqdriven atz 2nsu ytimeaftere ocorrespondingzx clock event
www.testbench.in
If iskewo eisi notospecified, qdefaultre input iskewoq jisre 1step iand ooutputqskew
isz 0.
(Q i20)o eWhati areothe qwaysre to iavoidoq jracere condition ibetween otestqbench

andz RTLu yusingSystemVeriloge o?
Ans:
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave oaqphase
difference.z
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iwork
oonqnegedge ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven iusing
ononqblocking statements.
4)Clocking iblocks.
www.testbench.in
5)Program iblock.
(Q i21)o eExplaini Eventoregions qinre SV i.
(Q i22)o eWhati areothe qtypesre of icoveragesoq javailablere in iSV o?
(Q i23)o eCani aoconstructor qbere qualified iasoq jprotectedre or ilocal oinqSV ?
(Q i24)o eHowi toohave qare #delay istatementoq jwhichre is iindependent
oofqtimescale ?z Iu yveriloge o,zx the #delay is dependent on timescale.
www.testbench.in
(Q i25)o eIsi itopossible qtore pass istructoq jorre union ifrom oSVqto Cz usingu yDPIe
o?zx If yes, then how is it done ?
(Q i26)o eWhati isoOOPS?
(Q i27)o eWhati isoinheritance q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i28)o eHowi toowrite qare message itooq jare string i?

(Q i29)o eSignalsi insideothe qinterfacere should ibeoq jwiresre or ilogic o?
www.testbench.in
(Q i30)o eGivei examplesoof qstaticre cast iandoq jdynamicre cast i.

(Q i31)o eHowi theoStatic qcastre and iDynamicoq jcastre errors iare oreportedq?
(Q i32)o eHowi Parameterizedomacros qcanre be idebuggedoq j?
(Q i33)o eWhati isoTLM q?
(Q i34)o eWhati willobe qthere values iofoq jrandre and irandc ovariablesqif
randomizationz failsu y?
www.testbench.in
(Q i35)o eExplaini aboutotheTimeunit, qTimeprecisionre and i`timescaleoq j.

(Q i36)o eIsi itopossible qtore access iaoq jmemberre of ia ostructqthat isz returnedu
ybye oazx function in side the function ?
(Q i37)o eHowi toorandomize qare real idataoq jtypere variable i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i38)o eWhati iso$ qinre SV i?

(Q i39)o eWhati areothe qtypesre of iparameterizedoq jclass?
www.testbench.in
(Q i40)o eWhati isothe qdefaultre value iofoq jenumeratedre data itype o?

(Q i41)o eWhati isopolymorphism q?
(Q i42)o eGivei anoexample qofre polymorphism i.
(Q i43)o eWhati areothe qtypesre of ipolymorphismoq j?
(Q i44)o eHowi tooconvert qare command ilineoq jdefinedre value ito oaqstring inz
SystemVerilogu y?
www.testbench.in
(Q i45)o eWhati areovirtual qmethodsre ?

(Q i46)o ewhati isoan qinstancere of iaoq jclassre ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i47)o ewhati isoa qvirtualre class?
(Q i48)o eWhati isoa qscopere resolution ioperator?

(Q i49)o eWhati isodeep qcopyre ?
www.testbench.in
(Q i50)o eWhati isoshallow qcopyre ?

(Q i51)o ewhati isoMethod qOverloading?
(Q i52)o ewhati isoMethod qOverRidingd?
(Q i53)o eWhati isomeant qbyre abstraction?
(Q i54)o eWhati isoa qbasere class? i
www.testbench.in
(Q i55)o eWhati isoa qsuperclass?re

(Q i56)o eWhati isothe qdifferencere between iAggregationoq jandre Composition?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i57)o eWhati isothe qneedre of ivirtualoq jinterfacesre ? i

(Q i58)o eWhati areothe qadvantagesre of iOOP?
Ans:
Data ihidingo ehelpsi createosecure qprograms.
Redundant icodeo ecani beoavoided qbyre using iinheritance.
www.testbench.in
Multiple iinstanceso eofi objectsocan qbere created.

Work icano ebei dividedoeasily qbasedre on iobjects.
Inheritance ihelpso etoi saveotime qandre cost.
(Q i59)o eIni whatocontext q,re you iuseoq jforeachre loop i?
(Q i60)o eWritei codeotoprint qthere contents iofarray_2doq j[][]re using iforeach
oloopq?
(Q i61)o eImplementedi codeoto qmergere double ilinkedoq jlist.Definere each
ielement oofqlinked listz usingu yclass.e o
www.testbench.in
(Q i62)o eWhati willothe qprintedre value i?

iBito e[7:0]a,b;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
iAo e=8<92>hff;Bi =8<92>h01;

i$display("0",Ao e+B);
(Q i63)o eWhyi checker...endcheckerois qusedre ?

(Q i64)o eIi wantoto qdelayre simulation ibyoq jsmallestre unit iof otime.qi.e
minimumz ofu yalle othezx timeprecision. How to do it ?
(Q i65)o eExplaini stratifiedoevent qqueuere ?
www.testbench.in
(Q i66)o eDefinei enumeratedodata qtypere ,with ioneoq jofre its ielements

ovalueqto bez X.
(Q i67)o eIsi thisoa qvalidre syntax i?
enum{a=0,b=7,c,d=8}alphabet;
(Q i68)o eWhati areothe qdifferentre types iofoq jparametersre available iin oSV?
(Q i69)o eWhati isothe qusere of i"type"oq joperatorre ?
www.testbench.in
(Q i70)o eWhati typeois qthere index iforoq jintre array_name i[*]? o

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i71)o eIni aoArray, qIfindexre is ioutoq jofre the iaddress obounds,qthen whatz
willu ybee othezx return value ?
(Q i72)o eWhati isothe qreturnre type iofoq jArrayre locator imethod ofind_indexq?
(Q i73)o eWritei aoprogram qtore choose ielementsoq jrandomlyre from iQueue.
oNoqelement shouldz beu yreputede ountilzx all elements are chosen. Queue may
have elements repeated.
(Q i74)o eDeclarei aoqueue qofre integers iwithoq jmaximumre number iof

oelementsqto 256.
www.testbench.in
(Q i75)o eExplaini howoyou qdebuggedre randomization ifailure.

(Q i76)o eWhati isozero qdelayre loop iandoq jWhatre is ithe oproblemqwith zeroz
delayu yloope o?
(Q i77)o eWhati isothe qdifferencere between izerooq jdelayre loop iin odesignqand
testbenchz ?
(Q i78)o eIsi randomize()omethod qisre virtual i?
(Q i79)o eWritei codeofor qthere below ispec:oq j
i2o evariblesi a,boare qdeclaredre in imodule.oq j
www.testbench.in
iGenerateo erandomi runbersosuch qthatre a i>oq jb.re

iDoo enoti useo$random qorre $urandom. i
(Q i80)o eIni aoclass, qare variable iisoq jdeclaredre as irandc. oButqwhen
randomized,z theu yrandome ovaluezx doesn<92>t seem to be cyclic. What could
be the reason ?
(Q i81)o ePre_randomize()i isovirtual qorre not i?
iIfo e"yes",i didoyou qusere the ikeywordoq j"virtual"re in ifront
oofqpre_randomize() ?
iIfo e"not",i thenowhat qaboutre the ipre_randomize()oq jdefinitionre defined iin
oextendedqclass ?
(Q i82)o eHowi toogenerate qrandomre numbers ibwoq jare range iof ovalues?
www.testbench.in
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TUTORIALS
SystemVerilog
Verification
(Q i83)o eWritei codeofor qthere below irequiremnt.
Constructs
DUT ihaso edatai busoof q64re bit iwhichoq jisre driven ion oposedgeqof clock.
TESTBENCH ihaso edatai busoof q32re bit iwhichoq jcanre sample ion
obothqposedge andz negedge.
On iposedge,o eDrivei [0oto q31]re bits iofoq jDUTre to iTB obusqand onz
negedgeu ydrivee o[32zx to 63] bits of DUT to TB bus.
Interface
OOPS
Randomization
Functional Coverage
Assertion
Write icodeo efori theoabove qrequirement.re All itheoq jabovere logic ishould
obeqdone insidez theu yinterfacee oitself.
DPI
UVM Tutorial
(Q i84)o eWritei aoStatemechine qwithoutre using ialwaysoq jblockre .
VMM Tutorial
www.testbench.in
OVM Tutorial
(Q i85)o eWhati isoan qbindre statement?
Easy Labs : SV
Easy Labs : UVM
(Q i86)o eExplaini aboutothe qvirtualre task iandoq jmethodsre .
Easy Labs : OVM
(Q i87)o eWhati isothe qusere of itheoq jabstractre class i?
Easy Labs : VMM
(Q i88)o eWhati isothe qdifferencere between imailboxoq jandre queue i?
AVM Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
VMM Ethernet sample (Q i89)o eWhati dataostructure qyoure used itooq jbuildre score iboard o?
www.testbench.in
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
(Q i90)o eWhati areothe qadvantagesre of ilinkedoq jlistre over ithe oqueueq?

(Q i91)o eHowi parallelocase qandre full icaseoq jproblemsre are iavoided oinqSV ?
(Q i92)o eWhati isothe qdifferencere between ipureoq jfunctionre and iordinary
ofunctionq?
(Q i93)o eWhati isothe qdifferencere between i$randomoq jandre $urandom i?
Constructs
(Q i94)o eWhati isoscope qrandomizationre ?
Switch TB
www.testbench.in
RVM Switch TB
(Q i95)o eListi theopredefined qrandomizationre methods.
RVM Ethernet sample
Specman E
Interview Questions
(Q i96)What'so eai Class?

(Q i97)What'so eani Object?
(Q i98)What'so ethei relationobetween qClassesre and iObjects?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i99)Whato
jsystems?
earei
differentoproperties
qprovidedre
by
iObject-orientedoq
www.testbench.in
(Q i100)What'so edifferencei betweenoStatic qandre Non-Static ifieldsoq jofre a

iclass?
(Q i101)o eWhati areopackages?
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4

input is what keeps
with time!
(Q i102)o eWhati isoa qconstructorre in iclass?

(Q i103)o eExplaini aboutoparameterised qclass.
(Q i104)o eExplaingi aboutothe qNestedre class.
www.testbench.in
(Q i105)o eDefinei casting?oWhat qarere the idifferentoq jtypesre of iCasting?

(Q i106)o eGivei exampleoof qStaticre and iDynamicoq jcasting.
(Q i107)o eWhati isothe qdifferencere between ialways_combooq jandre always@(*)
i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i108)o eWhati isothe qusere of ipackagesoq j?
(Q i109)o eWhati isodifference qbetweenre void iandoq jnullre pointer?

www.testbench.in
(Q i110)o eWhati isodifference qbetweenre overloading iandoq joverriding?

(Q i111)Whato eisi theodifference qbetweenre class iandoq jstructure?
(Q i112)o eWhati dooyou qmeanre by ipureoq jvirtualre functions?
(Q i113)o eWhati isothe qusere of i$castoq j?
(Q i114)o eHowi toocall qthere task iwhichoq jisre defined iin oparentqobject intoz
derivedu yclasse o?zx
www.testbench.in
(Q i115)o eWhati isoan qexpectre statement?

(Q i116)o eWhati isothe qdifferencere between irandoq jandre randc i?
(Q i117)o eWhati iso$root q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i118)o eWhati iso$unit q?

(Q i119)o eWhati areobi-directional qconstraints?
www.testbench.in
(Q i120)o eWhati isosolve...before qconstraintre ?

(Q i121)o eWithouti usingorandomize qmethodre or irandc,oq jgeneratere an iarray
oofqunique values?
(Q i122)o eExplaini aboutopass qbyre ref iandoq jpassre by ivalue o?
(Q i123)o eWhati isothe qdifferencere between i
bit[7:0]sig_1;
byte isig_2;
www.testbench.in
(Q i124)o eWhati isothe qdifferencere between iprogramoq jblockre and imodule o?
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TUTORIALS
SystemVerilog
(Q i125)o eHowi tooconvert qreadre data itooq jintegerre data i?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
(Q i126)o eIi haveoa qobjectre of iaoq jclass.re I iwould olikeqto printz theu yclasse
oname.zx How to print the class name using object handle?
(Q i127)o eIi haveoa qmultire dimensional iarray.oq jIre don<92>t iknow otheqnumber
ofz dimensionsu yite ohas.zx How to know the number of dimensions of multi
dimensional array?
(Q i128)o eHowi programoblock qisre different ifromoq jmodule?re
(Q i129)o eWhati isoan qinterfacere and iwhyoq jitre is iused?
www.testbench.in
VMM Tutorial
(Q i130)Ifo eclockingi blockois qnotre used ithenoq jwhathappens?re
OVM Tutorial
(Q i131)o eWhati isofinal qblockre ?
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i132)o eHowi tooimplement qare always iblockoq jlogicre in iprogram oblockq?

(Q i133)o eWhati isothe qdifferencere between ifor/joinoq j,re fork/join_none iand
ofork/join_anyq?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i134)o eWhati isothe qusere of imodoq jportsre ?

www.testbench.in
(Q i135)o eWritei aoclock qgeneratorre without iusingoq jalwaysre block.

(Q i136)o ewhati isomodports q?re difference ibetweenoq jmodportsre and iinterface?
o
(Q i137)o eHowi dooyou qusesre classes itooq jrandomize?re
(Q i138)o eStatici andoautomatic qfunctions?
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i139)o eWhati isoforward qreferencingre and ihowoq jtore avoid ithis oproblem?
www.testbench.in
(Q i140)o eWhati isocircular qdependencyre and ihowoq jtore avoid ithis oproblemq?
RVM Ethernet sample (Q i141)o eWhati isocross qcoveragere ?
Specman E
Interview Questions
(Q i142)o eDescribei theodifference qbetweenre Code iCoverageoq jandre Functional

iCoverage oWhichqis morez importantu yande oWhyzx we need them
(Q i143)o eHowi tookill qare process iinoq jare fork/join i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i144)o eDifferencei betweenoAssociative qarrayre and iDynamicoq jarrayre ?

www.testbench.in
(Q i145)o eWhati areothe qadvantagesre of iSystemoq jVerilogre DPI i?

(Q i146)o ehowi toorandomize qare dynamic iarrayoq jofre objects?
(Q i147)o eWhati isorandsequence qandre what iisoq jitsre use i?
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4

input is what keeps
with time!
(Q i148)o eWhati isobin q?

(Q i149)o e
www.testbench.in
Initial i
wait_order(a,b,c);
Which ifromo ebelowi initialprocessowill qcausere that iaboveoq jwaitorderre will
ipass.
a)
initialbegin
#1;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i->a;
i->b;
i->c;
www.testbench.in
end
b)
initialbegin
#1;
i->a;
end
ialways@ao e->b;
ialways@bo e->c;
www.testbench.in
c)
initialbegin
#1;
i->a;
i#0->b;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
i->>c;
end
d)
www.testbench.in
initialbegin
i#1->a;
i#1->b;
i#1->c;
end
(Q i150)o eWhyi alwaysoblock qisre not iallowedoq jinre program iblock o?
www.testbench.in
(Q i151)o eWhichi isobest qtore use itooq jmodelre a itransaction o?qStruct orz classu
y?
(Q i152)o eHowi SVois qmorere random istableoq jthenre Verilog i?
(Q i153)o eWhati isothe qdifferencere between i"staticoq jtaskre abc()" iand
otaskqstatic abd()"z ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i154)o eHowi tooadd qare new

orandomqnumber generatorz stateu y?
iprocessoq
(Q i155)o eWhati isothe qneedre of ialiasoq jinre SV i?

www.testbench.in
jwithoutre
disturbing
ithe
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TUTORIALS
SystemVerilog
(Q i156)o eWhati wouldobe qthere output iofoq jthere following icode oandqhow toz
avoidu yite o?
for(inti=0;i<N;i++)begin
fork
intj i=i;
begin
i#10$display("o eJi valueois q0re ",j);
end
join_none
end
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
www.testbench.in
Easy Labs : OVM
J iiso ealwaysNi ,Byousing qautomaticKeyre word,This iproblemoq jcanre be

iavoided o.
for(inti=0;i<N;i++)begin
fork
automaticintj i=i;
begin
i#10$display("o eJi valueois q0re ",j);
end
join_none
Easy Labs : VMM
end
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
AVM Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
VMM Ethernet sample (Q i157)o eIsi itopossible qforre a ifunctionoq jtore return ia oarray(qmemory) ?
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
(Q i158)o eHowi toocheck qwhetherre randomization iisoq jsuccessfulre or inot?
(Q i159)o eDoi weoneed qtore call isuper.new()oq jwhenre extending ia oclassq?

Whatz happensu yife owezx don't call ?
(Q i160)o eWhati isothe qneedre to iimplementoq jexplicitlyre a icopy()
omethodqinside az transactionu y,e owhenzx we can simple assign one object to
other ?
(Q i161)o eHowi differentois qthere implementation iofoq jare struct iand ounionqin
SV.z
Switch TB
www.testbench.in
RVM Switch TB
(Q i162)o eWhati iso"this" q?
RVM Ethernet sample
Specman E
Interview Questions
(Q i163)o eWhati isotagged qunionre ?

(Q i164)o eWhati iso"scope qresolutionre operator" i?
(Q i165)o eWheni aoSequence qMatches?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i166)o eWhati isoa qProperty?

www.testbench.in
(Q i167)o eWhati isothe qdifferencere between iVerilogoq jParameterizedre Macros

iand oSystemVerilogqParameterized Macrosz ?
(Q i168)o eWhati isothe qdifferencere between i

logicdata_1;
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
varlogicdata_2;
wirelogicdata_3 i;
bitdata_4;
varbitdata_5;

input is what keeps
with time!
www.testbench.in
(Q i169)o eWhati isothe qdifferencere between ibitoq jandre logic i?

(Q i170)o eWritei aoState qmachinere in iSVoq jstylere .
(Q i171)o eWhati isoadvantage qofre program iblockoq joverre clock iblocks
ow.r.tqrace conditionz ?
(Q i172)o eHowi tooavoid qthere race iconditionoq jbetweenre 2 iprogram oblockq?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i173)o eWhati isocoverage qdrivenre verification i?

www.testbench.in
(Q i174)o eWhati isolayered qarchitecturere ?

(Q i175)o eWhati
ienvironment o?
areothe
qsimulationre
phases
iinoq
jyourre
verification
(Q i176)o eHowi toopick qare element iwhichoq jisre in iqueue ofromqrandom indexz
?
(Q i177)o eWhati dataostructure
oyourqenvironment andz whyu y?
qisre
used
itooq
jstorere
data
iin
(Q i178)o eWhati isocasting q?re Explain iaboutoq jthere various itypes oofqcasting
availablez inu ySVe o.
www.testbench.in
(Q i179)o eHowi tooimport qallre the iitemsoq jdeclaredre inside ia opackageq?

(Q i180)o eExplaini howothe qtimescalere unit iandoq jprecisionre are itaken
owhenqa modulez doesu ynote ohavezx any timescale declaration in RTL ?
(Q i181)o eWhati isostreaming qoperatorre and iwhatoq jisre its iuse o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i182)o eWhati areovoid qfunctionsre ?
(Q i183)o eHowi toomake qsurere that iaoq jfunctionre argument ipassed oasqref isz
notu ychangede obyzx the function ?
www.testbench.in
(Q i184)o eWhati isothe qusere of i"extern"oq j?

(Q i185)o eWhati isothe qdifferencere between iinitialoq jblockre and ifinal oblock?
Ans:
iYouo ecan'ti scheduleoan qeventre or ihaveoq jdelaysre in ifinal oblock.
(Q i186)o eHowi toocheck qwhetherre a ihandleoq jisre holding iobject oorqnot ?
(Q i187)o eHowi toodisable qmultiplere threads iwhichoq jarere spawned iby
ofork...joinq
www.testbench.in
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TUTORIALS
TEST YOUR SVA SKILLS
SystemVerilog
(Q i188)o eWhati isothe qdifferencere between i$roseoq jandre posedge i?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
(Q i189)o eWheni anoassert qpropertyre or iassumeoq jpropertyre matches?

(Q i190)Tello eoni AssertionoSeverity qLevels?
(Q i191)o eExplaingi aboutoSVA qLayers?
(Q i192)o eWheni aocover qpropertyre matches?
www.testbench.in
DPI
(Q i193)o eDifferencei b/woProcedural qandre Concurrent iAssertionsoq j?
UVM Tutorial
(Q i194)o eHowi manyotypes qofre assertions? iExplain?
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
(Q i195)o eEquivalenti constructoto q|->re 1 i?oq j

Ans:|=>
(Q i196)o eWhati isoSequence?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i197)o eWhati isothe qdifferencere between iassumeoq jandre assert i?

(Q i198)o eHowi toocheck qforre only ioneoq jsuccessre in iassertions o?q
(Q i199)o eWritei anoassertion qforre Glitch idetectionoq j.
Verilog
(Q i200)o ewhati isothe qdifferencere between iexpectoq jandre assert istatement? o
Verification
Verilog Switch TB
"Write itheo eSVAi assertionocode qforre the ifollowingoq jdescription"
Basic Constructs
www.testbench.in
(Q i201)o eAsi longoas qsig_are is istilloq jup,re sig_b ishould onotqbe asserted.
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i202)o eThei signalosig_a qisre a ipulse:oq jItre can ionly obeqasserted forz oneu
ycycle,e oandzx must be deasserted in the next cycle.
(Q i203)o esig_ai isoa qpulse,re unless isig_boq jisre asserted.
RVM Ethernet sample (Q i204)o esig_ai andosig_b qcanre only ibeoq jassertedre together ifor ooneqcycle;
inz theu ynexte ocycle,zx at least one of them must be deasserted.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Specman E
Interview Questions
(Q i205)o eIfi sig_aois qassertedre for itheoq jfirstre time, ithen oitqmust havez
beenu yprecedede obyzx a sig_b.
www.testbench.in
(Q i206)o esig_ai mustonot qbere asserted ibeforeoq jthere first isig_b o(mayqbe
assertedz onu ythee osamezx cycle as sig_b).
(Q i207)o eWheni sig_aois qasserted,re sig_b imustoq jbere asserted, iand
omustqremain upz untilu yonee oofzx the signals sig_c or sig_d is asserted.
(Q i208)o eAfteri oneoof qthere signals isig_aoq jisre asserted, isig_b omustqbe
deasserted,z andu ymuste ostayzx down until the next sig_a.
http://testbench.in/IQ_07_TEST_YOUR_SVA_SKILLS.html[9/26/2012 2:59:58 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
(Q i209)o eThei signalsosig_a qandre sig_b imayoq jonlyre be iasserted oifqsig_c isz Report a Bug or Comment
asserted.
input is what keeps
(Q i210)o eTherei existsoa qtransactionre that ireachesoq jitsre endeithersig_aor Testbench.in improving
with time!
isig_b.
www.testbench.in
(Q i211)o eIfi sig_aois qreceivedre while isig_boq jisre inactive, ithen oonqthe nextz
cycleu ysig_ce omustzx be inactive, and sig_b must be asserted.
(Q i212)o esig_ai mustonot qrisere before itheoq jfirstre sig_b.
(Q i213)o esig_ai mustonot qbere asserted itogetheroq jwithre sig_bor iwith osig_c.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i214)o esig_ai mustonot qbere asserted ibetweenoq janre sig_b iand

otheqfollowing sig_cz (fromu yonee ocyclezx after the sig_b until one cycle after the
sig_c).
(Q i215)o esig_ai mustonot qbere asserted itogetheroq jwithre sig_b ior owithqsig_c.
www.testbench.in
(Q i216)o eIfi weoare qatre the iendoq jofre a itransaction o(sig_aqis down,z sig_bu
yise oup),zx and sig_c is down, then sig_c must be asserted before the next time that
sig_a is asserted.
(Q i217)o eIfi sig_aois qdown,re sig_b imayoq jonlyre rise ifor ooneqcycle beforez
theu ynexte otimezx that sig_a is asserted.
(Q i218)o esig_ai mustonot qrisere if iweoq jhavere seen isig_b oandqhavent seenz
theu ynexte osig_czx yet (from the cycle after the sig_b until the cycle of the sig_c).
(Q i219)o eThei auxiliaryosignal qsig_are indicates ithatoq jwere have iseen oaqsig_b,
andz haventu yseene oazx sig_c since then. It rises one cycle after the sig_b, and falls
one cycle after the sig_c.
(Q i220)o esig_ai mayobe qassertedre only iwhileoq jsig_bre is itrue, oi.e.,qwe arez
atu yleaste oonezx cycle after a sig_c and havent seen a sig_d since then (except
perhaps in the current cycle)
www.testbench.in
(Q i221)o esig_ai mayobe qassertedre only iduringoq jthere time iframe

obeginningqwith sig_bz (inclusive)u yande ocontinuingzx until sig_c rises (inclusive).
(Q i222)o esig_ai mustonot qrisere if iweoq jhavere seen isig_b oandqhavent seenz
theu ynexte osig_czx yet (from the cycle after the sig_b until the cycle before the
sig_c).
(Q i223)o eWhilei sig_aois qdown,re sig_b imayoq jrisere only iif osig_cqis down.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i224)o eIfi sig_aois qassertedre with isig_boq jinactive,re and isig_c owasqinactive
inz theu ypreviouse ocyclezx and remains inactive in the next cycle, then sig_a must
be deasserted in the next cycle.
(Q i225)o eIfi thereoare qarere two ioccurencesoq jofre sig_a irising
owithqSTATE=active1, andz nou ysig_be ooccurszx between them, then within 3
cycles of the second rise of sig_a, START must occur.
www.testbench.in
(Q i226)o eShowi aosequence qwithre 3 itransactionsoq j(inre which isig_a

oisqasserted 3z times).
(Q i227)o eIfi theostate qmachinere reaches iSTATE=active1,oq jitre will ieventually
oreachqSTATE=active2.
(Q i228)o esig_ai isoeventually qasserted,re after isig_boq jhasre fallen.
(Q i229)o esig_ai isoeventually qassertedre without isig_boq jindication,re after isig_c

ohasqfallen.
(Q i230)o eIfi sig_aois qactive,re then isig_boq jwasre active i3 ocyclesqago.
www.testbench.in
(Q i231)o eIfi sig_aois qactive,re then isig_boq jwasre active isomewhere oinqthe
past.
(Q i232)o eIfi thereois qare sig_a, ifollowedoq jbyre 3 iconsecutive osig_b,qthen inz
eachu yofe othezx 3 cycles the data written (DO) is equal to the data read (DI).
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i233)o eAlways,i ifoon q3re consecutive isig_a,oq jsig_bre appears, ithen oonqthe
nextz sig_cu ycycle,e osig_azx holds.
(Q i234)o eEveryi sig_aomust qeventuallyre be iacknowledgedoq jbyre sig_b, iunless
osig_cqappears
(Q i235)o esig_ai occurson qcyclesre after isig_b.
www.testbench.in
(Q i236)o esig_ai andosig_b qarere environment isignals,oq jwhichre can ibe

ogivenqat anyz time,u ybute oshouldzx never be given together.
(Q i237)o eIfi sig_aois qactive,re it imustoq jbere deactivated ione ocycleqafter
sig_bz arrives.u yNotee othatzx sig_a may already be active when sig_b is asserted.
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TUTORIALS
TEST YOUR VERILOG SKILLS 1
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
(Q i1)o eIdentifyi theoerror qinre the ifollowingoq jcode.

b[7:0]={2{5}};
(Q i2)Wheno earei instanceonames qoptional?
(Q i3)o eIni theofollowing qprogram,whatre is itheoq jproblemre and ihow otoqavoid
itz ?
taskdriver;
inputread;
www.testbench.in
input[7:0]write_d;
begin
#30date_valid i=1'b1;
wait(read i==1'b1);
#20cpu_data i=write_data;
$display("End iofo etask");
end
endtask
Easy Labs : OVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : VMM
www.testbench.in
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i4)o eHowi manyolevels qcanre be inestedoq jusingre ìnclude i?

Ans:
You icano enesti theoìncludecompiler qdirectivere to iatoq jleastre 16levels.
(Q i5)o eWhati isothe qusere of i$countdriversoq j?
Ans:
The i$countdriverso esystemi functionois qprovidedre to icountoq jthere number iof
odriversqon az specifiedu ynete osozx that bus contention can be identified.
(Q i6)o eWhati isothe qusere of i$getpatternoq j?
Ans:
The isystemo efunctioni $getpatternoprovides qforre fast iprocessingoq jofre stimulus
ipatterns othatqhave toz beu ypropagatede otozx a large number of scalar inputs.
The function reads stimulus patterns that have been loaded into a memory using the
$readmemb or $readmemh system tasks.
www.testbench.in
RVM Ethernet sample
Specman E
Interview Questions
reg[1:in_width]in_mem[1:patterns];
integerindex;
assign{i1,i2,i3,i4,i5,i6,i7,i8,i9,i10}=$getpattern(in_mem[index]);
(Q i7)o eWhati isothe qfunctionalityre of i&&&(notoq j&&re , inot o&)q?
(Q i8)o eHowi tooget qcopyre of ialloq jthere text ithat oisqprinted toz theu
ystandarde ooutputzx in a log file ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: i
Using i$log("filename");
www.testbench.in
(Q i9)o eWhati isothe qusere of iPATHPULSE$?
http://testbench.in/IQ_08_TEST_YOUR_VERILOG_SKILLS_1.html[9/26/2012 3:00:08 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
1
10
11
12
13
14
15
16
17
1
2
3
4
Ans:
PATHPULSE$ ispecparamiso eusedi toocontrol qpulsere handling ionoq
modulepath.
jare

(Q i10)ino estatementi (o(a==b) q&&re (c i==oq jd)re ) i, owhatqis thez expressionu input is what keeps
ycoveragee oifzx always a=0,b=0,c=0,d=0 ?
with time!
(Q i11)o eDifferencei betweenoReduction qandre Bitwise ioperators?

Ans:
The idifferenceo eisi thatobitwise qoperationsre are ionoq jbitsre from itwo
odifferentqoperands, whereasz reductionu yoperationse oarezx on the bits of the
same operand. Reduction operators work bit by bit from right to left. Reduction
operators perform a bitwise operation on a single vector operand and yield a 1-bit
result Bitwise operators perform a bit-by-bit operation on two operands. They take
each bit in one operand and perform the operation with the corresponding bit in the
other operand.
www.testbench.in
(Q i12)Whato eisi theodifference qbetweenre the ifollowingoq jtwore lines iof

oVerilogqcode?
#5a i=b;
a i=#5b;
Ans:
#5a i=b;
Wait ifiveo etimei unitsobefore qdoingre the iactionoq jforre "a i= ob;".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The ivalueo eassignedi tooa qwillre be itheoq jvaluere of ib o5qtime unitsz hence.
a i=#5b;
The ivalueo eofi bois qcalculatedre and istoredoq jinre an iinternal otemp
www.testbench.in
register. iAftero efivei timeounits, qassignre this istoredoq jvaluere to ia.

(Q i13)Whato eisi theodifference qbetween:re c i=oq jfoore ? ia o:qb; andz ifu
y(foo)e oczx = a; else c = b;
Ans: i
The i?o emergesi answersoif qthere condition iisoq j"x",re so ifor oinstanceqif fooz =u
y1'bx,e oazx = 'b10, and b = 'b11, you'd get c = 'b1x.
On itheo eotheri hand,oif qtreatsre X's ioroq jZsre as iFALSE, osoqyou'd alwaysz getu
yce o=zx b.
(Q i14)o eHowi isoVerilog qimplementationre independent iandoq jwhyre is ithis
oanqadvantage?
www.testbench.in
(Q i15)o eWhati leveloof qVerilogre is iusedoq jin:

a.Test ibenches
b.Synthesized idesign
c.Net ilist
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i16)whato eisi theodifference

j$fopen("filename","w");
Ans:
qbetweenre
$fopen("filename");
iandoq
If itypeo eisi omitted,othe qfilere is iopenedoq jforre writing, iand oaqmulti channelz
descriptoru ymcde oiszx returned. If type is supplied, the file is opened as specified
by the value of type, and a file descriptor fd is returned. So in first statements , type
is omitted and mcd is returned and in the second statement, fd is returned.

www.testbench.in
In itheo efirsti statement,othe qfilere is iopenedoq jforre read iand owrite.

But iino esecondi statement,o"w" qisre specified, isooq jthere file iis oopenedqfor
onlyz writing.u y
(Q i17)Whato eisi theodifference qbetweenre multi ichanneloq jdescriptors(mcd)re
and ifile odescriptors(fd)?
Ans:
The imultio echanneli descriptoromcd qisre a i32oq jbitre reg iin owhichqa singlez
bitu yise osetzx indicating which file is opened. Unlike multi channel descriptors, file
descriptors can not be combined via bitwise or in order to direct output to multiple
files. Instead, files are opened via file descriptor for input, output, input and output,
as well as for append operations, based on the value of type.
(Q i18)Howo etoi generateoa qrandomre number?
www.testbench.in
(Q i19)o eHowi toogenerate qare random inumberoq jwhichre is iless otheq100 ?

(Q i20)o eHowi toogenerate qare random inumberoq jwhichre is ibetween o0qto 100z
?
(Q i21)Whato eisi theoadvantage qofre Named iPortoq jConnectionre over iOrdered
oPortqConnection ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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TUTORIALS
SystemVerilog
(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
(Q i23)o eHowi tooget qdifferentre random inumbersoq jinre different isimulations?

(Q i24)whato eisi theodifferent qbetweenre $sformat iandoq j$swrite?
Ans:
The isystemo etaski $sformatois qsimilarre to itheoq jsystemre task i$swrite, owithqa
onez majoru ydifference.e oUnlikezx the display and write family of output system
tasks, $sformat always interprets its second argument, and only its second argument
as a format string. This format argument can be a static string, such as "data is 0" , or
can be a reg variable whose content is interpreted as the format string. No other
arguments are interpreted as format strings. $sformat supports all the format
specifiers supported by $display,
VMM Tutorial
OVM Tutorial
(Q i25)Whato eisi theodifference qbetweenre wire iandoq jreg?
Easy Labs : SV
www.testbench.in
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Ans:
Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements.

iValueoq jassignedre by ia ocontinuousqassignment orz au ygatee ooutput.
Register itype:o e(reg,i integer,otime, qreal,re real itime)oq jrepresentsre abstract
idata ostorageqelement. Assignedz valuesu yonlye owithinzx an always statement or
an initial statement.
Verification
The imaino edifferencei betweenowire qandre reg iisoq jwirere cannot ihold
o(store)qthe valuez whenu ythee onozx connection between a and b like
a-------------b, iifo etherei isono qconnectionre in iaoq jandre b, iwire olooseqvalue
wherez asu yrege ocanzx hold the value even if there in no connection.
Verilog Switch TB
Default ivalues:wireo eisi Z,regois qx.
Verilog
Basic Constructs
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
OpenVera
Constructs
(Q i26)o eWhati happensoif qare port iisoq junconnectedre ?

www.testbench.in
Ans:
Switch TB
Unconnected iinputo eportsi initializeoto qzre and ifeedoq jthatre value iinto
otheqcomponent, whichz canu ycausee oproblems.zx More common are redundant or
RVM Ethernet sample unwanted outputs which are left unconnected to be optimized away in synthesis.
RVM Switch TB
Specman E
Interview Questions
(Q i27)Whato eisi theodifference qbetweenre === iandoq j==re ?

Ans i:
output iofo e"=="i canobe q1,re 0 ioroq jX.
output iofo e"==="i canoonly qbere 0 ioroq j1.
When iyouo earei comparingo2 qnosre using i"=="oq jandre if ione/both
otheqnumbers havez oneu yore omorezx bits as "x" then the output would be "X" . But
if use "===" output would be 0 or 1.
www.testbench.in
e.g iAo e=i 3'b1x0

B i=o e3'b10x
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
2
10
11
12
13
14
15
16
17
1
2
3
4
A i==o eBi willogive qXre as ioutput.

A i===o eBi willogive q0re as ioutput.
"==" iiso eusedi forocomparison qofre only i1'soq jandre 0's i.It ocan'tqcompare X's.z Report a Bug or Comment
Ifu yanye obitzx of the input is X output will be X
input is what keeps
"===" iiso eusedi forocomparison qofre X ialso...
with time!
"==" icano ebei synthesized,owhere qasre "===" icannot.

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i28)Whato eisi theodifference qamongre case,casex iandoq jcasez?

Ans:
case itreatso eonlyi 0oor q1re values iinoq jcasere alternative iand oisqis notz
dealingu ywithe odon'tzx care condition.
casex itreatso ealli xoand qzre values iinoq jcasere alternative ior ocaseqexpression
asz au ydon'te ocare.
casez itreatso ealli zovalues qinre case ialternatives.oq jallre bit ipositions owithqz
canz treatu yase oazx don't care
(Q i29)o eWhati isothe qdifferencere between i@(aoq jorre b) iand o@(aq| b)
(Q i30)o eWhati isofull qcasere and iparalleloq jcase.??
www.testbench.in
(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re event

ibased oandqcycle basedz simulatoru y?
(Q i32)o eWhati isocompilation q?
Ans:
To isimulateo eai Verilogomodel, qwere must ifirstoq jconvertre our isource
ofilesqinto az binaryu yforme othatzx can be recognized by the simulator. The
process of checking the syntax and producing the binary file is known as compilation.
(Q i33)o eWhati dataotypes qcanre be iusedoq jforre input iport, ooututqport andz
inoutu yporte o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?

www.testbench.in
(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i?

(Q i36)o eDifferencei betweenoconditional qcompilationre and i$plusargs??
(Q i37)o eWhati isothe qbenefitre of iusingoq jBehaviorre modeling istyle ooverqRTL
modeling?
(Q i38)o eWhati isothe qdifferencere between itaskoq jandre function?
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TUTORIALS
SystemVerilog
(Q i39)Whato eisi theodifference qbetweenre static ifunctionoq jandre automatic

ifunction?
Ans:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40)Whato eisi theodifference qbetweenre static itaskoq jandre automatic itask?
DPI
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o?
UVM Tutorial
Ans:
VMM Tutorial
OVM Tutorial
Easy Labs : SV
www.testbench.in
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i

wired-AND iforo eopeni collector
wired-OR iforo eECL
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.

a[7:0]={4{'b10}};
AVM Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
VMM Ethernet sample (Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany?
www.testbench.in
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
(Q i44)o eIsi itosynthesysable q?

always@(negedgeclk iorrst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilog
oSynthesisqslandered.
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itask

ofunctions?
www.testbench.in
(Q i47)o eDifferencei betweenoparameter qandre define i?

(Q i48)Whato ethei differenceobetween qthere following itwooq jstatements?
@(val i==2)
wait(val i==2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusing
otheqdefparam constructz vs.u yspecifyinge oduringzx instantiation?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)Differenceo ebetweeni Vectoredoand qscalaredre nets?

www.testbench.in
(Q i51)Differenceo ebwi realoand qrealtimere ?
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
3
10
11
12
13
14
15
16
17
1
2
3
4
(Q i52)whato eisi theodifference qbetweenre arthamatic iandoq jlogicalre shift

iregister?
(Q i53)Whato eisi theodifference qbwre following itwooq jregisters??
reg[1:n]rega;// iAno en-biti registerois qnotre the isame
regmema i[1:n];//o easi aomemory qofre n i1-bitoq jregisters
www.testbench.in
(Q i54)Howo ethei aboveotwo qarere handled iinassignments,oq jports,functionsre

and itask o?
(Q i55)Whato eisi theodifference qbetweenre parameters iandoq jspecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre beSynthesized i

(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation?
www.testbench.in
(Q i58)o eNamei threeomethods qofre timing icontrol?

(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61)Whato eisi theodifference qbetweenre force ireleaseoq jandre assign
ideassign?
(Q i62)Whato eisi theodifference qbetweenre posedge iandoq jnegedge?re
www.testbench.in
And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,u
yande ofromzx x or z to 0 where asposedge shall be detected on the transition from
0 to x, z, or 1, and from x or z to 1
(Q i63)whato eisi theodifference qbetweenre $display iandoq j$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomatically
oaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task
does not. The $display task, when invoked without arguments, simply prints a newline
character. A $write task supplied without parameters prints nothing at all.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64)Whato eisi theodifference qbetweenre $display iandoq j$monitor?
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input is what keeps
with time!
Search
TUTORIALS
SystemVerilog
(Q i65)Whato eisi theodifference qbetweenre $display iandoq j$strobe?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
(Q i66)Whato eisi theodifference qbetweenre 0 iandoq j%zre format ispecification?

Ans:
0 ioro e0i Unformattedo2 qvaluere data
%z ioro e%Zi Unformattedo4 qvaluere data
(Q i67)o eWhati isothe qdifferencere between i0.000000e+00,0.000000oq janre d0?
Ans:
DPI
www.testbench.in
UVM Tutorial
0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat

0.000000 ioro e0.000000i Displayoreal qinre a idecimaloq jformat
0 ioro e0i Displayoreal qinre exponential ioroq jdecimalre format, iwhichever
oformatqresults inz theu yshortere oprintedzx output
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i68)Whato eisi theodifference qbetweenre $finish iadoq j$stop?

The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass
ocontrolqback toz theu yhoste ooperatingzx system.
The i$stopo esystemi taskocauses qsimulationre to ibeoq jsuspended.
VMM Ethernet sample
(Q i69)Whato eisi theodifference qbetweenre PLI iandoq jVPI?

Verilog
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Verification
www.testbench.in
Verilog Switch TB
Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere third

igeneration oofqthe PLI.
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i70)o eWhati sortoof qhardwarere structure iareoq jinferredre by iboth ocaseqand

ifz statements,u ybye odefault,zx in Verilog?
(Q i71)o eHowi couldoyou qchangere a icaseoq jstatementre in iorder othatqits
implementationz doesu ynote oresultzx in a priority structure?
RVM Ethernet sample (Q i72)o eIfi youoare qnotre using iaoq jsynthesisre attribute i"full ocase",qhow canz
youu yassuree ocoveragezx of all conditions for a case statement ?
Specman E
Interview Questions
(Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?

www.testbench.in
(Q i74)o eCani aotask qsynthesizedre ?

(Q i75)o eWhati isothe qdifferencere between i$finish(0),oq j$finiash(1)re and
i$finish(2) o?
Ans:
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass
ocontrolqback toz theu yhoste ooperatingzx system.
If iano eexpressioni isosupplied qtore this itask,oq jthenre its ivalue o(0,q1, orz 2)u
ydeterminese othezx diagnostic messages that
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
4
10
11
12
13
14
15
16
17
1
2
3
4
are iprintedo ebeforei theoprompt qisre issued. iIfoq

osupplied,qthen az valueu yofe o1zx is taken as the default.
jnore
argument
iis
input is what keeps
with time!
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$finish(0) iPrintso enothing

$finish(1) iPrintso esimulationi timeoand qlocation
www.testbench.in
$finish(2) iPrintso esimulationi time,olocation, qandre statistics iaboutoq jthere

memory iand oCPUqtime usedz inu ysimulation
(Q i76)Whato eisi theodifference qb/wre $time i,oq j$stimere and i$realtime o?
Ans:
The i$timeo esystemi functionoreturns qanre integer ithatoq jisre a i64-bit
otime,qscaled toz theu ytimescalee ounitzx of the module that invoked it.
The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32bitqtime, scaledz tou ythee otimescalezx unit of the module that invoked it. If the
actual simulation time does not fit in 32 bits, the low order 32 bits of the current
simulation time are returned.
The i$realtimeo esystemi functionoreturns qare real inumberoq jtimere that, ilike
o$time,qis scaledz tou ythee otimezx unit of the module that invoked it.
www.testbench.in
(Q i77)Differenceo ebetweeni !oAnd q~re ?

(Q
i78)Whato
eisi
j$value$plusargsre ?
theodifference
qbetweenre
$test$plusargs
iandoq
(Q i79)Whato eisi theodifference qDifferencere between itheoq jtwore statement i?

oWhetherqa andz bu yvaluese oarezx equal?
reg[1:0]data;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i=data[0]||data[1];
b i=|data;
www.testbench.in
(Q i80)Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs?

a)initial
#10a i=0;
always@(a)
a<=~a;
b)initial
#10a i=0;
www.testbench.in
always@(a)
a i=~a;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imust

oagreeqthat executionz isu y*not*e ostalledzx at the @aevent control. When
execution reaches the @a event control,'a' has already changed. It will not change
again. So the event control will stall forever; its event of interest hasalready
occurred, earlier in the same time slot, and can no longer have any effect.
(Q i81)whato eis/arei theodifferences qbetweenre SIMULATION iandoq jSYNTHESISre
Ans:

www.testbench.in
Simulation i<=o everifyi yourodesign. q

synthesis i<=o eChecki foroyour qtimingre
Simulation iiso eusedi tooverify qthere functionality iofoq jthere circuit..
ia)Functional oSimulation:studyqof ckt'sz operationu yindependente oofzx timing
parameters and gate delays. b) Timing Simulation :study including estimated delays,
verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One iofo ethei foremostoin qbackre end istepsoq jwherere by isynthesizing
oisqnothing butz convertingu yVHDLe oorzx VERILOG description to a set of
primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target
technology. Basically the synthesis tools convert the design description into equations
or components .
(Q i82)Whato eisi theodifferent qbetweenre $setup iandoq j$display?
Ans:
$setup iiso eai timingocheck qtaskre and i$displayoq jisre system itask.
www.testbench.in
Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasks

ocannotqbe overridden.
i.e. iUsero ecani changeothe qdefinitionre of itheoq j$displayre but inot o$setup.
(Q i83)Whato eisi theodifference qbetweenre parameter iandoq jlocalre parameter?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i84)Whyo eisi itorecommended qnotre to imixoq jblockingre and inon-blocking

oassignmentsqin thez sameu yblock?
(Q i85)Declareo eparametersi fororepresenting qthere state imachineoq jstatesre
using ione ohotqencoding.
(Q i86)o eWhati doesoa qfunctionre synthesize ito?
www.testbench.in
(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe followingz codeu
y?
`definewidth i7
(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j?

Ans:
The i$inputo esystemi taskoallows qcommandre input itextoq jtore come ifrom
oaqnamed filez insteadu yofe ofromzx the terminal. At the end of the command file,
the input is switched back to the terminal.
www.testbench.in
(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i?

0000000000000000000000000000001
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i90)Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?
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TUTORIALS
SystemVerilog
(Q i91)Too emodifyi aobehavioral qVerilogre wait istatementoq jtore make iit

osynthesizedq
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Original icode:
command1;
wait(x i!=0);
command3;
Ans:
www.testbench.in
Synthesized iVerilog:
case(state)
0:begin
command1;
if(x i!=0)command3;
elsestate i<=1;
end
Easy Labs : UVM
1:if(x i!=0)//o ewaiti untilothis qisre true
Easy Labs : OVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : VMM
www.testbench.in
AVM Switch TB
command3;
endcase
VMM Ethernet sample
(Q i92)Whato earei theotypes qofre race iconditions?

Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
(Q i93)Howo etoi avoiderorace qconditionre between idutoq jandre testbench?

(Q i94)Giveo ethei guideolines qwhichre avoids iraceoq jcondition.
(Q i95)Whato eisi theouse qofre linting itool?
www.testbench.in
(Q i96)Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q
Constructs
Switch TB
RVM Switch TB
(Q i97)Whato eisi configurationoblock?

Ans:
RVM Ethernet sample Verilog-2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionre
Specman E
and isource olocationqof eachz Verilogu ymodulee otozx be specified as part of the
Verilog language. For portability, virtual model libraries are used in configuration
blocks, and separate library map files associate virtual libraries with physical
locations. Configuration blocks are specified outside of module definitions.
Interview Questions
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i98)Howo emanyi filesocan

multichannel idescriptor o?
Ans:
qbere
opened(without
iclosing)oq
jusingre
www.testbench.in
31files.
(Q i99)Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re using

imultichannel odescriptorqwhile integerz canu yholee o32zx bits?
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
5
10
11
12
13
14
15
16
17
1
2
3
4
Ans:
The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptor Report a Bug or Comment
oisqreserved, andz shallu yalwayse obezx cleared, limiting an implementation to at on This section - Your
input is what keeps
most 31 files opened for output via multi channel descriptors.
with time!
(Q i100)Ifo emcd(multichanneli descriptor)ois q00000000000000000000000000001re ,

ithenoq jwhatre does iit omean?
Ans:
The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe
standardz output.
www.testbench.in
(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor
$strobe?
(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?
(Q i103)o eWhati
ospecifyqblock?
Ans:
areothe
qtypicalre
tasks
iyouoq
jperformre
inside
ia
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays ito

othoseqpaths.
- iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iof
otheqdevice arez met.
- iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior
oforqparticular pathsz withinu yae omodule.
www.testbench.in
(Q i104)Findo ethei bugoin qthere following icode.

always@(posedgeclk)
a i=b;
always@(posedgeclk)
b i=a;
www.testbench.in
if(a=b)
match i=1;
else
match i=0;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe correctz
codeu yis
if i(a==b)o e
match i=o e1;
else
www.testbench.in
match i=o e0;
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Index
Questions
SystemVerilog
for(............);
Verification
Questions 2
begin
Constructs
.....
Skills 1
end
Interface
Ans:
OOPS
Skills 2
Misplaced isemicolonso eini for-loops
Randomization
Skills 3
Functional Coverage
www.testbench.in
Skills 4
Assertion
automatictaskintra_assign();
DPI
begin
UVM Tutorial
a i<=#10b;
end
VMM Tutorial
OVM Tutorial
ANS:
Easy Labs : SV
Intra iassignmento enonblockingi statementsoare qnotre allowed iinoq jautomaticre 6
Easy Labs : UVM
tasks.
Easy Labs : OVM
Easy Labs : VMM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
10
AVM Switch TB
www.testbench.in
VMM Ethernet sample always@(in)
11
if(ena)
12
out i=in;
else
Verilog
13
out
i=1<92>b1;
Verification
14
Verilog Switch TB
Ans:
Basic Constructs
15
simulation imismatcho emighti occur.
To iassureo ethei simulationowill qmatchre the isynthesizedoq jlogic,re add i"ena" Test Your Verilog Skills
16
otoqthe eventz listu ysoe othezx event list reads: always @ (in or ena)
OpenVera
17
Constructs
www.testbench.in
Switch TB
1
RVM Switch TB
always@(in1 iorin2o eorsel)
2
out i=in1;
3
if(sel)
out i<=in2;
4
Specman E
end
Interview Questions
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Not isupported,o ecannoti mixoblocking qandre nonblocking iassignmentsoq jinre an Test Your Sta Skills 5
ialways ostatement.
www.testbench.in
reg[1:0]select;
TUTORIALS
always@(select)
begin
case(select)
00:y i=1;
01:y i=2;
10:y i=3;
11:y i=4;

input is what keeps
with time!
www.testbench.in
endcase
end
Ans:
branches i01o eandi 11oare qconsideredre as iintegersoq jandre they iwill oneverqbe
selected.
(Q i111)Fillo ethei ????
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
fd i=$fopen("filename",r);
if(????)
www.testbench.in
$display("file icannoto ebei opened");

(Q i112)Howo etoi modeloa qperfectre buffer iofoq j10unitsre delay?
a)#10a i=b;
b)a i=#10b;
c)#10a i<=b;
d)a i<=#10b;
(Q i113)o eWhati isoverilog qconfiguration?
www.testbench.in
(Q i114)o eWritei aocode qforre clock igenerator.

(Q i115)o eWritei aocode qforre clock igeneratoroq jwhichre can igenerate
oclockqfrequency ofz 156MHZ.
(Q i116)o ewritei aoverilog qcodere to igenerateoq j40MHzre clock iwith o60q0uty
cycle
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i117)o eWhati pointsoneed qtore be iconsideredoq

oclockqgenerator???
jwhilere
writing
ia
(Q i118)o eExplaini verilogoevent qqueue.

www.testbench.in
(Q i119)o ehowi theoscope qofre a ivariableoq jisre realized iin overilog.qIllustrate

withz example.?
(Q i120)o eWhati isoincremental qcompilation?
(Q i121)o eWhati isoPLI?
Ans:
PLI iiso eai mechanismoto qinvokere C isubroutinesoq jtore Verilog. i
(Q i122)o eIni whatoregion qofre the ieventoq jqueuere , iPLI ocallsqare executed?
www.testbench.in
(Q i123)o eWhati isocalltf qinre Verilog iPLI?

Ans:
Calltf iiso esimilari toomain() qfunctionre in iC.calltfoq jcanre call iother
osubqmethods toz differentu yjobs.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i124)o eWhati isothe qdifferencere between iParalleloq jandre Full iConnection

oModuleqPath delaysz ?
Ans:
A iparallelo econnectioni establishesoa qconnectionre between ieachoq jbitre in ithe
osourceqto eachz correspondingu ybite oinzx the destination. Parallel module paths
can be created only between one source and one destination where each signal
contains the same number of bits.
www.testbench.in
A ifullo econnectioni establishesoa qconnectionre between ieveryoq jbitre in ithe

osourceqand everyz bitu yine othezx destination. The module path source does not
need to have the same number of bits as the module path destination.
(Q i125)o eCani $setupoand q$holdre check ireportoq jare violation ifor oaqlimit ofz
zero?
(Q i126)o eExplaini abouto$recovery qandre $removal i?
(Q i127)o eWhichi timingocheck(s) qacceptre a inegativeoq jlimit?

(Q i128)o eCani youoqualify qallre events iinoq jallre timing ichecks owithqedge
specifiersz suchu yase oedgezx 01?
www.testbench.in
(Q i129)o eFori whichotiming qcheck(s)re must iyouoq jalwaysre qualify ievents?

(Q i130)o eWheni doeso$skew qreportre a iviolation?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i131)o eWhati isomisctf q?

Ans:
Misctf iiso etoi doohousekeeping qjobs.re This iisoq jcanre be icalled omanyqtimes
unlikez otheru ypredefinede ofunctionszx which are called once per instance.
www.testbench.in
(Q i132)o eWhati isoUDP? qCanre we iwriteoq jUDPre including iclock oalso?

(Q i133)o eHowi dooI qpreventre selected iparametersoq jofre
ofromqbeing overriddenz duringu yinstantiation?
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imodule
Search
TUTORIALS
SystemVerilog
(Q i134)o ecani Iouse qare Verilog ifunctionoq jtore define ithe owidthqof az multibitu yport,e owire,zx or reg type?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
(Q i135)o eWhati constructoin qVerilogre can

oaqcapacitive storagez nodeu yine oazx circuit?
Ans:
ibeoq
jusedre
to
isimulate
the itrirego estatementi isoused qtore simulate iaoq jwirere with ia ocapacitiveqhold
value.
(Q i136)o eDescribei theobasic qstrengthre system iinoq jVerilog.
Ans:
OVM Tutorial
The istrengtho esystemi haso8 qvaluesre 0 ithroughoq j7,re with ithe

ostrongestqstrength beingz knownu yase o"supply"zx and the weakest strength as high
impedance.
Easy Labs : SV
www.testbench.in
VMM Tutorial
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i137)o e#definei cat(x,y)ox y qconcatenatesre x itooq jy.re But icat(cat(1,2),3)

odoesqnot expandz butu ygivese opreprocessorzx warning. Why?
Ans:
Because iparameterizedo emacrosi areonot qrecursive.
(Q i138)o eWhati areothe qtypesre of istrengthsoq jthatre can ibe ospecifiedqon az
netu y??
Ans:
There iareo etwoi typesoof qstrengthsre that icanoq jbere specified iin oaqnet
declaration.z Theyu yaree oaszx follows:
charge istrengtho eshalli onlyobe qusedre when ideclaringoq jare net iof otypeqtrireg
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
OpenVera
Constructs
drive istrengtho eshalli onlyobe qusedre when iplacingoq jare continuous iassignment
oonqa netz inu ythee osamezx statement that declares the net
www.testbench.in
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
(Q i139)Howo etoi resolveoa qtristatere driver iinoq jVerilogre ?

(Q i140)WHATo eAREi THEoTYPES qOFre CHARGE iSTRENGTHS?
Ans:
SMALL, iMEDIUM,o eLARGE
Interview Questions
(Q i141)o eHowi toomodel qpowerre supply istrengthsoq jinre verilog?

Ans:
The isupply0o eandi supply1onets qmayre be iusedoq jtore model
opowerqsupplies inz au ycircuit.e oThesezx nets shall have supply strengths.
www.testbench.in
ithe
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
7
10
11
12
13
14
15
16
17
1
2
3
4
(Q i142)o eHowi toomodify qare parameter ivalue?

Ans:
A iparametero ecani beomodified qwithre the idefparamoq jstatementre or iin on This section - Your
input is what keeps
otheqmodule instancez statement.
with time!
(Q i143)o eWhati isolocalparam?

Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
local iparameter(s)o earei identicaloto qparametersre except ithatoq jtheyre can

inot odirectlyqbe modifiedz withu ythee odefparamzx statement or by the ordered or
named parameter value assignment.
www.testbench.in
(Q i144)o eHowi toomodifya qlocalparam?

Ans:
Local iparameterso ecani beoassigned qtore a iconstantoq jexpressionre containing ia
oparameterqwhich canz beu ymodifiede owithzx the defparam statement or by the
ordered or named parameter value assignment.
ParameterWID=3;
Localparam iWIDTH=2*WID;
(Q i145)o eWHATi ISospecparam?

Ans:
www.testbench.in
specparam ideclareso eai specialotype qofre parameter iwhichoq jisre intended ionly
oforqproviding timingz andu ydelaye ovalues,zx but can appear in any expression that
is not assigned to a parameter and is not part of the range specification of a
declaration. Unlike a module parameter, a specify parameter cannot be modified
from within the language, but it may be modified through SDF annotation
(Q i146)Whato earei >>>oand q<<<re operators i?
(Q i147)o ewhati doesothe qfollowingre code imean?
Reg i[22:0]sig;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always@(|sig)
begin
www.testbench.in
......
end
(Q i148)o eWhati isothe qfunctionre of iforceoq j&re release?

Ans:
Force iando ereleasei statementsoare qusedre to ioverrideoq jassignmentsre on
iboth oregistersqand nets.z Theyu yaree otypicallyzx used in the interactive
debugging process, where certain registers or nets are forced to a value and the
effect on other registers and nets is noted.
They ishouldo eoccuri onlyoin qsimulationre block.
(Q i149)o eWhati isothe qpurposere of
oasqautomatic?
Ans:
ideclaringoq
jtasksre
or
ifunctions
www.testbench.in
Declaration iofo etasksi andofunctions qasre Automatic iwilloq jcreatere
dynamic istorage oforqeach taskz oru yfunctione ocall.zx

(Q i150)o eWhati isoSynthesis?
Ans:
Synthesis iiso ethei stageoin qthere design iflowoq jwhichre is iconcerned
owithqtranslating yourz Verilogu ycodee ointozx gates - and that's putting it very
simply! First of all, the Verilog must be written in a particular way for the synthesis
tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it
will output a netlist of the design that you have synthesized that represents the chip
which can be fabricated through an ASIC or FPGA vendor.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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TUTORIALS
SystemVerilog
(Q i151)o eWhetheri initialoblock qcanre be isynthesized?

Ans:
YES
According itoo eIEEE
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i152)o eHowi tooread qdatare from iaoq jfile?

Ans:
Using i$readmemhand$readmem0.Fileo eio
www.testbench.in
(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinside

oaqbegin ...endz block?
Ans:
TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishould
obeqnamed.
begin:name_
integervarib;
....
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout ofz phaseu yande
VMM Ethernet sample ohavingzx same frequency, how to find which input clk signal is leading? Write verilog
code for this.
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
www.testbench.in
Ans:
Here iiso ethei simpleosolution qforre this. i

All iito eneedsi isoa qflipre flop. i
if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof flipz flopu
yande ootherzx to CLK input of FF.
if iclk1o eisi leadingothe qoutputre is ihigh.oq j
if iclk2o eisi leadingothe qoutputre is ilow.oq j
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ione

ostatementqin verilog?
Ans:
www.testbench.in
moduledecoder(
// iOutputso e
dout,
// iInputso e
din i
);
input[3:0]din;
output[15:0]dout;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assigndout i={dino e==15,dini ==14,dino==13,din q==12,

idino e==11,dini ==10,dino==9,din q==8,
www.testbench.in
idino e==7,dini ==6,dino==5,din q==4,

idino e==3,dini ==2,dino==1,din q==0};
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
8
10
11
12
13
14
15
16
17
1
2
3
4
endmodule// idecodero e
(Q i156)Verilogo ecodei toodetect qifre
oexpressedqusing powerz ofu y2e o
Ans:
modulepat_det i(data_in,patDetectedo e);
i64bitoq
jpatternre
can
ibe Report a Bug or Comment
input[31:0]data_in;
outputpatDetected;
www.testbench.in
wire[4:0]patSum i=data_in[0]+data_in[1]+data_in[2]+
data_in[3]+data_in[4]+data_in[5]+
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
data_in[29]+data_in[30]+data_in[31];
wirepatDetected i=(patSumo e==1)?1'b1:1'b0;
endmodule
(Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder?
(Q i158)o eWhati isothe qusere of i$printtimescaleoq j?
www.testbench.in
Ans:
The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision

ifor oaqparticular module.
When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit
iand oprecisionqof thez moduleu ythate oiszx the current scope.
When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit
iand oprecisionqof thez moduleu ypassede otozx it.
(Q i159)Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog
ocode?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always@(*)
if(enable)
q i<=d;
Ans:
www.testbench.in
A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iis

odeasserted,qq willz holdu yitse ovalue.
(Q i160)Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog
ocode?
always@(enable iord)
if(enable)
q i<=d;
else
q i<='b0;
Ans:
www.testbench.in
A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete,

i.e., iqo eisi assignedoon qeveryre execution iofoq jthere always istatement.

input is what keeps
with time!
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TUTORIALS
SystemVerilog
(Q i161)o eHowi toomodel qare sequential icircuit?

Ans:
Verification
Constructs
Interface
Sequential ilogico eshalli beomodeled qusingre an ialwaysoq jstatementre that ihas

ooneqor morez edgeu yeventse oinzx the event list.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i162)o eWhati isothe qusere of i$timeformatoq j?

Ans:
The i$timeformato esystemi taskoperforms qthere following itwooq joperations:
It isetso ethei timeounit qforre all ilater-enteredoq jdelaysre entered iinteractively.
It isetso ethei timeounit, qprecisionre number, isuffixoq jstring,re and iminimum
ofieldqwidth forz allu y%te oformatszx specified in all modules that follow in the
source description until another $timeformat system task is invoked.
www.testbench.in
(Q i163)o eWhati isothe qsignificancere of idefparamoq jinre verilog?

Ans:
Parameter ivalueso ecani beochanged qinre any imoduleoq jinstancere in ithe
odesignqwith thez keywordu ydefparam.e oThezx hierarchical name of the module
instance can be used to override parameter values.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
(Q i164)o eWritei programofor qD-FFre with isynchronousoq jandre asynchronous

ireset.
(Q i165)o eWhatsi theonotation qtore see ihierarchyoq jinre display?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
%m
www.testbench.in
(Q i166)o eHowi toodescribe qdelaysre for istructuraloq jmodelsre such ias

oASICqcells?
Ans:
Switch TB
Two itypeso eofi HDLoconstructs qarere often iusedoq jtore describe idelays
oforqstructural modelsz suchu yase oASICzx cells.
RVM Ethernet sample They iareo easi follows:
Distributed idelays,o ewhichi specifyothe qtimere it itakesoq jeventsre to ipropagate
othroughqgates andz netsu yinsidee othezx module
Module ipatho edelays,i whichodescribe qthere time iitoq jtakesre an ievent oatqa
Specman E
sourcez (inputu yporte oorzx inout port) to propagate to a destination (output port or
inout port)
Interview Questions
RVM Switch TB
(Q i167)o eHowi toomodel qare tri istateoq jdriver?

Ans:
www.testbench.in
Three-state ilogico eshalli beomodeled qwhenre a ivariableoq jisre assigned ithe

ovalueqz. Thez assignmentu yofe ozzx can be conditional or unconditional. If any
driver of a signal contains an assignment to the value z, then all the drivers shall
contain such an assignment.
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
9
10
11
12
13
14
15
16
17
1
2
3
4

input is what keeps
with time!
moduleztest i(test2,test1,test3,ena);
input[0:1]ena;
input[7:0]test1,test3;
output[7:0]test2;
wire[7:0]test2;
assigntest2 i=(enao e==2'b01)?test1i :8'bz;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assigntest2 i=(enao e==2'b10)?test3i :8'bz;

// itest2o eisi three-stateowhen qenare is i2<92>b00oq jorre 2<92>b11.
www.testbench.in
Endmodule
(Q i168)o eHowi toomodel qare ROM?

Ans:
An iasynchronouso eROMi shallobe qmodeledre as icombinationaloq jlogicre using
ione oofqthe followingz styles:
a) iOne-dimensionalo earrayi withodata qinre case istatementoq j.
b) iTwo-dimensionalo earrayi withodata qinre initial istatementoq j.
c) iTwo-dimensionalo earrayi withodata qinre text ifileoq j.
(Q i169)o eHowi toomodel qare RAM?
www.testbench.in
Ans:
A iRAMo eshalli beomodeled qusingre a iVerilogoq jmemoryre (a itwo-dimensional

oregqarray) thatz hasu ythee oattributezx ram_block associated with it. A RAM
element may either be modeled as an edge-sensitive storage element or as a levelsensitive storage element. A RAM data value may be read synchronously or
asynchronously.
// iAo eRAMi elementois qanre edge-sensitive istorageoq jelement:
moduleram_test(
outputwire[7:0]q,
inputwire[7:0]d,
inputwire[6:0]a,
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
inputwireclk,we);
(*synthesis,ram_block i*)reg[7:0]memo e[127:0];
always@(posedgeclk)if(we)mem[a]<=d;
www.testbench.in
assignq i=mem[a];
endmodule
(Q i170)o eWhati isofull qcase?
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TUTORIALS
SystemVerilog
(Q i171)o eHowi toomodel qare full icaseoq jblock?

Ans:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
Adding iao edefaulti statementoto qare case istatementoq jnullifiesre the ieffect
oofqthe full_casez attribute.
(* isynthesis,o efull_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jforre all iunspecified
ocaseqchoices, thez outputsu yassignede owithinzx the case statement may be
treated as synthesis don<92>t-care assignments.
(Q i172)o eWhati isoparallel qcasere ?
www.testbench.in
(Q i173)o eHowi toomodel qare parallel icase?

Ans:
Its isyntaxo eis:
(* isynthesis,o eparallel_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jallre case iitems
oareqto bez tested,u yevene oifzx more than one case item could potentially match
the case expression.
AVM Switch TB
VMM Ethernet sample (Q
i174)o eWhati
ocaseqstatement?
Verilog
areorules
qneedre
to
ibeoq
while
iusing
(Q i175)Iso eiti possibleoto qsynthesizere power ioperator(**)?
Verification
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Verilog Switch TB
www.testbench.in
Basic Constructs
jfollowedre
Ans:
The ipowero eoperatori (**)oshall qbere supported ionlyoq jwhenre both ioperands
oareqconstants orz ifu ythee ofirstzx operand is 2.
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i176)o eHowi tooModel qare capacitor? i

(Q i177)o ewhati isothe qusere of i$timeformat();
RVM Ethernet sample (Q i178)o eHowi oodisable qthisre block???
Specman E
Interview Questions
begin
...
www.testbench.in
...
end
Ans:
Name itheo eblock.i Disableocan qbere used iforoq jnamedre blocks
otasksqonly.
(Q i179)o eWhati areothe qtypesre of i$displayoq jtasks?
$display$display,$displayh,$displayo
iand
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i180)o eWhati isothe qusere of i$Monitoroq jANDre $monitor ioff o?

www.testbench.in
(Q i181)o eWhati doeso`timescale q1re ns/ i1oq jpsre signify iin oaqverilog code?
Ans:
'timescale idirectiveo eisi aocompiler qdirectivere .It iisoq jusedre to imeasure
osimulationqtime orz delayu ytime.
Usage i:o e`timescalei <reference_time_unit>/o<time_precision>
reference_time_unit i:o eSpecifiesi theounit qofre measurement iforoq jtimesre and
idelays.
time_precision: ispecifieso ethei precisionoto qwhichre the idelaysoq jarere rounded
ioff
(Q i182)o eHowi toodeclare qstringsre in iverilog?
www.testbench.in
(Q i183)o eWritei codeofor qclockre divider iandoq jclockre multiplier?

(Q i184)o eListi outothe qsimulationre and isynthesisoq jmismatches.
(Q i185)o eModeli ao3 qbitre shift iregister?
(Q i186)o ehowi tooovercome qracingre condition?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i187)o eWhati isothe qusere Always@(*) i?

www.testbench.in
(Q i188)o eWhati isocode qcoverage?

(Q i189)o eListi outothe qtypesre of icodeoq jcoverage.
(Q i190)o eListi outosome qpointsre to ispeedoq jupre simulation.
(Q i191)o eWhati isouse qofre Escape isequencesoq jforre special icharacter o\dddq?
Ans:
\ddd iAo echaracteri specifiedoby q1tore 3octal idigits
www.testbench.in
moduledisp;
initialbegin
$display("\\\t\\\n\"\123");
end
endmodule
Simulating ithiso eexamplei shallodisplay qthere following:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
\ i\
"S
(Q i192)o eWhati isothe qformatre specification itooq jDisplayre in

ocharacterqformat
iASCII
www.testbench.in
Ans:
^@ ior%C
(Q i193)o eWhati isothe qformatre specification itoDisplayoq jlibraryre binding

iinformation
Ans:
%l ior%L
(Q i194)o eWhati isothe qformatre specification itoDisplayoq jnetre signal istrength
Ans:
%v ior%V
www.testbench.in

input is what keeps
with time!
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TUTORIALS
SystemVerilog
(Q i195)o eWhati isothe qformatre specification itooq jDisplayre hierarchical iname

Ans:
%m ior%M
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
(Q i196)o eWhati isothe qformatre specification itooq jDisplayre in icurrent

otimeqformat
Ans:
%t ior%T
(Q i197)o eWhati isoVCD q?
www.testbench.in
DPI
Ans:
UVM Tutorial
A ivalueo echangei dumpo(VCD) qfilere contains iinformationoq jaboutre value

ichanges oonqselected variablesz inu ythee odesignzx stored by value change dump
system tasks.
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
a) iFouro estate:i toorepresent qvariablere changes iinoq j0,re 1, ix, oandqz withz
nou ystrengthe oinformation.
b) iExtended:o etoi representovariable qchangesre in ialloq jstatesre and istrength
oinformation.
Easy Labs : VMM

AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i198)o eWhati isothe qneedre of i`defaultoq jnettypere ?

Ans:
The idirectiveo e`default_nettypei controlsothe qnetre type icreatedoq jforre
implicit inet odeclarationsq. Itz canu ybee ousedzx only outside of module
definitions. It affects all modules that follow the directive, even across source file
boundaries. Multiple `default_nettype directives are allowed.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When inoo e`default_nettypei directiveois qpresentre or iifoq jthere `resetall

idirective oisqspecified, implicitz netsu yaree oofzx type wire.
www.testbench.in
(Q i199)o eWhati happensowhen`default_nettype qisre set itooq jnonere ?

Ans:
When itheo e`default_nettypei isoset qtore none, ialloq jnetsre must ibe
oexplicitlyqdeclared. Ifz au ynete oiszx not explicitly declared, an error is generated.
RVM Ethernet sample
Specman E
Interview Questions
(Q i200)o eWhati isoùndef q?

Ans:
The idirectiveo eùndefi shalloundefine qare previously idefinedoq jtextre macro. iAn
oattemptqto undefinedz au ytexte omacrozx that was not previously defined using a
`define compiler directive can result in a warning.
(Q i201)o eWhati isoùnconnected_drive qandre `nounconnected_drive i?
www.testbench.in
Ans:
All iunconnectedo einputi portsoof qare module iappearingoq jbetweenre the

idirectives oùnconnected_driveqand `nounconnected_drivez areu ypullede oupzx or
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
pulled down instead of the normal default.

The idirectiveo eùnconnected_drivei takesoone qofre two iargumentsoq jpull1re or
ipull0. oWhenqpull1 isz specified,u yalle ounconnectedzx input ports are
automatically pulled up. When pull0 is specified, unconnected ports are pulled down.
These directives shall be specified in pairs, and outside of the module declarations.
(Q i202)o eIsi itopossible qtore override ibuiltoq jinre system itasks oandqfunctions?
Ans:
Yes.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i203)o eWhati isothe qdifferencere between imetaoq jcommentre and ipragmas?

Ans:
www.testbench.in
meta-comment:
A iVerilogo ecommenti (//)oor q(/*re */) ithatoq jisre used ito oprovideqsynthesis
directivesz tou yae osynthesiszx tool.
pragma:
A igenerico etermi usedoto qdefinere a iconstructoq jwithre no ipredefined
olanguageqsemantics thatz influences
Prior itoo ethei acceptanceoof qthere Verilog iIEEEoq jStdre 1364-2001, iit
owasqcommon practicez tou yincludee osynthesiszx pragmas embedded within a
comment,
for iexample:o e//i synthesisofull_case.
The ipracticeo eofi embeddingopragmas qintore a icommentoq jmeantre that iany
osynthesisqtool thatz acceptedu ysuche opragmaszx was required to partially or fully
parse all comments within a Verilog RTL design just to determine if the comment
contained a pragma for the synthesis tool. The Verilog standard introduced attributes
to discourage the practice of putting pragmas into comments and to replace them
with a set of tokens (attribute delimiters) that could then be parsed for tool-specific
information.
(Q i204)o eWhati areothe qwaysre to imodeloq jare combinational icircuit?
www.testbench.in
Ans:
Combinational ilogico eshalli beomodeled qusingre a icontinuousoq jassignmentre or

ia onetqdeclaration assignmentz oru yane oalwayszx statement.
(Q i205)o eWhati areothe qrulesre to ibeoq jfollowedre while iusing oanqalways
statementz tou ymodele ocombinationalzx circuit?
Ans:
When iusingo eani alwaysostatement, qthere event ilistoq jshallre not icontain
oanqedge eventz (u yposedgee oorzx negedge ). The event list does not affect the
synthesized net list However, it may be necessary to include in the event list all the
variables read in the always statement to avoid mismatches between simulation and
synthesized logic.
A ivariableo eassignedi inoan qalwaysre statement ishalloq jnotre be iassigned
ousingqboth az blockingu yassignmente o(=)zx and a nonblocking assignment (<=) in
the same always statement.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i206)o eHowi tooget qthere system itimeoq jinre to iverilog o?

Using iPLIorVPI.
www.testbench.in
(Q i207)o eWhetheri foroloop qisre synthesized?

(Q i208)o ewhati isovalue qofre a i?oq j
reg[2:0]d;

input is what keeps
with time!
rega;
d i=3'b1xx;
www.testbench.in
a i=|d;
a iiso e1;
(Q i209)o eIi wantoto qreturnre 2 ivaluesoq jbyre a ifunction. oHowqDo Iz dou y?e o
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Concatenate itheo eresultsi andoreturn. q

(Q i210)o eHowi manyotimes qthisre loop iwilloq jgetre executed?
www.testbench.in
reg[3:0]i;
for(i=0;i<=15;i=i+1)
begin
.......
end
Ans:
infinite itimes.
i<=15 iwillo ealwaysi beotrue qasre I iisoq j4re bit ionly.
www.testbench.in
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Index
Questions
SystemVerilog
(Q i211)o ewhati isothe qfollowingre result? i
Verification
Questions 2
Integer ia,b,c;
Constructs
A i=10;
Skills 1
b i=5;
Interface
c i=7;
OOPS
Skills 2
Randomization
if(a>b>c)
Skills 3
$display(true);
Functional Coverage
www.testbench.in
Skills 4
Assertion
else
$display(False);
DPI
UVM Tutorial
Ans:
TRUE.
VMM Tutorial
A i>bo e>ci isointerpreted qbyre verilog isimulatoroq jasre (a i>(b o>cq))
OVM Tutorial
10>(5>7)->
i10>0->1
Easy Labs : SV
Easy Labs : UVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : OVM
www.testbench.in
Easy Labs : VMM
(Q i212)o eHowi tooprint qlinere and ifileoq jnamere from iwhere otheq$display 10
messagez isu ycoming?
AVM Switch TB
11
Ans:
VMM Ethernet sample
Using itheo efollowingi plio, qwere can iprintoq jthere file iname oandqline numberz 12
byu yoverriddene othezx $display task.
13
Verilog
Verification
14
Verilog Switch TB
(Q i213)o eAti whatotime qthere simulation istops??
15
Basic Constructs
initial
16
while(1)
$display(" iajkdkjs");
OpenVera
17
www.testbench.in
Constructs
1
initial
Switch TB
#10$finish;
2
RVM Switch TB
RVM Ethernet sample
3
4
(Q i214)o ewhati isovalue qofre a i?
Specman E
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
reg[2:0]a,b,c;
Interview Questions
c i=3'b110;
www.testbench.in
a i=bo e=ci ;
(Q i215)o eGiveni theofollowing qVerilogre code, iwhatoq jvaluere of i"a" Test Your Dft Skills 1
oisqdisplayed?
always@(clk)begin
a i=0;
a i<=1;
TUTORIALS
$display(a);
end
Ans:
www.testbench.in
This iiso eai trickyoone! qVerilogre scheduling isemanticsoq jbasicallyre imply ia

four-level ideepo equeuei forothe qcurrentre simulation itime:
1: iActiveo eEventsi (blockingostatements)( q=re , i$display)oq j
2: iInactiveo eEventsi (#0odelays, qetc)
3: iNon-Blockingo eAssigni Updateso(non-blocking qstatements)
4: iMonitoro eEventsi ($strobe,o$monitor, qetc).
Since itheo e"ai =o0" qisre an iactiveoq jevent,re it iis oscheduledqinto thez 1stu
y"queue".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The i"ao e<=i 1"ois qare non-blocking ievent,oq jsore it's iplaced ointoqthe 3rdz
queue.Theu y"ae o=zx 0" is placed in 1st queue. Then , $display statement is placed
into the 1st queue after "a = 0 ". Only events in the active queue are completed this
sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look
at the value of a in the next sim cycle, it would show 1.
www.testbench.in
(Q i216)o eIsi thereoa qracere condition iinoq jthere following iprogram o?

begin
a=0;
b i<=a;
end
Ans: iNO.o eTherei isono qracere condition i.
(Q i217)o eUsingi theogiven, qdrawre the iwaveformsoq jforre the ifollowing
www.testbench.in
regclk;
rega;
initialclk i=0;
always#10clk i=~clk;
(1)always@(clk)a i=#5clk;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i218)Now,o echangei aoto qwire,re and idrawoq jfor:

www.testbench.in
(4) iassign#5ao e=clk;

(Q i219)o eHowi manyotimes qthere following irepeatoq jloopre executes?
begin
a i=1;
repeat(a)
a i=ao e+1;
www.testbench.in
end
Ans:
Only ionce.o eLoopi executionofor qare specific inumberoq jofre times. iThis
oconstructqis associatedz withu yae oconstantzx or a variable. If a variable is used, it
is evaluated once when the loop starts. When the loop is started, the value of a is 1.
So the loop is executed once.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i220)o eAti whatotime qa,b,c,d,e,fre will igetoq j1re in ithe ofollowingqprogram?

input is what keeps
with time!
moduleblock_nonblock();
rega,b,c,d i,e,fo e;
www.testbench.in
// iBlockingo eassignments
initialbegin
a i=#101'b1;
b i=#201'b1;
c i=#401'b1;
end
// iNonblockingo eassignments
initialbegin
d i<=#101'b1;
www.testbench.in
e i<=#201'b1;
f i<=#401'b1;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endmodule
Ans:
// iBlockingo eassignments
initialbegin
www.testbench.in
a i=#101'b1;//o eThei simulatoroassigns q1re to iaoq jatre time i10

b i=#201'b1;//o eThei simulatoroassigns q1re to iboq jatre time i30
c i=#401'b1;//o eThei simulatoroassigns q1re to icoq jatre time i70
end
// iNonblockingo eassignments
initialbegin
d i<=#101'b1;//o eThei simulatoroassigns q1re to idoq jatre time i10
e i<=#201'b1;//o eThei simulatoroassigns q1re to ieoq jatre time i20
f i<=#401'b1;//o eThei simulatoroassigns q1re to ifoq jatre time i40
www.testbench.in
end
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TUTORIALS
SystemVerilog
(Q i221)o eGiveni theofollowing qcode,re draw itheoq jwaveformsre for i'a':

regclk;
rega;
always#10clk i=~clk;
always@(clk)a i=#15clk;
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
(Q i222)o eByi defaultoNumbers qthatre are ispecifiedoq jwithoutre a ibase

oformatqspecification are
Options i:
a)decimal inumber
www.testbench.in
b)hexadecimal inumber
c)binay
d)octal
Easy Labs : UVM
(Q i223)o edefaulti valueoof qare net,trireg iis

a)logic0
b)logic1
c)unknow
d)hi-impedence
Easy Labs : OVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : VMM
www.testbench.in
OVM Tutorial
Easy Labs : SV
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
(Q i224)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing az 3rdu
yvariable?
(Q i225)o ehowi toorelize q"always@(posedgere clock)" iwithoq joutre using ialways
oblock?
initial
forever
begin
@(posedgeclock);
.......ur icodeo egoesi hear................
end
www.testbench.in
or
Switch TB
initial
while(1)
@(posedgeclock);
.......ur icodeo egoesi hear................
RVM Switch TB
Specman E
Interview Questions
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
www.testbench.in
(Q i226)o eIsi itopossible qtore use inegativeoq jnumbersre while ispecifying

ovectorqindexes ?
Ans:
Yes.
reg[-1:4]b;// iao e6-biti vectororeg
(Q i227)o eHowi manyobits qarere there iinoq jinteger?
Ans:
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
It iiso eimplementationi dependent.obut qtheyre shall iatoq jleastre be i32 obits.

(Q i228)o eHowi manyobits qarere there iinoq jtimere variable?
www.testbench.in
Ans:
64
(Q i229)o eWhati areothe qdifferentre phases iofoq jexecution?

(Q i230)o eWhati isothe qvaluere of iaoq j?
integera i=3.5
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: i
it iiso e4.
www.testbench.in
(Q i231)o ewhati isothe qvaluere of iaoq j?

integera i=-3.5
Ans:
it iiso e-4
If itheo efractionali partoof qthere realnumber iisoq jexactlyre 0.5,it ishall
obeqrounded awayz fromu yzero.
(Q i232)o eWherei theooperator q"or"re is iusedoq j?
Ans:
Used iono eevents.
www.testbench.in
(Q i233)o eWhati isodifference qbetweenre define iandoq jparameter?re Which ido

oyouqprefer andz why?
(Q i234)o eWhati isothe qvaluere of iaoq j?
integera i=-12/3;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iresulto eisi -4.
(Q i235)o eWhati isothe qvaluere of ia?

www.testbench.in
integera i=-'do e12/3;

Ans:
The iresulto eisi 1431655761.
(Q i236)o ewhati isothe qvaluere of ia?
integera i=-'sdo e12/3;
Ans:
The iresulto eisi -4.
(Q i237)o ewhati isothe qvaluere of ia?
www.testbench.in
integera i=-4'sdo e12/3;

Ans:
-4'sd12 iiso ethei negativeoof qthere 4-bitquantity i1100,whichoq jisre -4.(-4)=4.
The iresulto eisi 1.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i238)Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?

integerintA;
www.testbench.in
reg[15:0]regA;
intA i=-4'd12;

input is what keeps
with time!
regA i=intAo e/3;

(Q i239)Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integerintA;
reg[15:0]regA;
regA i=-4'd12;
www.testbench.in
intA i=regAo e/3;

(Q i240)Whato eisi theovalue qofre regA,intA iinoq jthere following icode o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
integerintA;
reg[15:0]regA;
intA i=-4'd12/3;
regA i=-12/3;
(Q i241)o eHowi dooyou qmakere out iwhetheroq jalwaysre block iis

oaqcombinational orz sequential?
www.testbench.in
(Q i242)o eWhati willobe qdisplayedre ?

reg[8*10:1]s1,s2;
initialbegin
s1 i="Hello";
s2 i="o eworld!";
if({s1,s2}=="Hello iworld!")
$display("strings iareo eequal");
else
www.testbench.in
$display("strings iareo enoti equal");

end
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The icomparisono eini thisoexample qfailsre because iduringoq jthere assignment ithe
ostringqvariables arez paddedu yase oillustratedzx in the next example:
s1 i=o e000000000048656c6c6f
s2 i=o e00000020776f726c6421
The iconcatenationo eofi s1oand qs2re includes itheoq jzerore padding, iresulting
oinqthe followingz value:u y000000000048656c6c6f00000020776f726c6421
and i"helloo eworld"i iso48656c6c6f20776f726c6421
www.testbench.in
(Q i243)o eWhati isothe qvaluere of ianswer?

reg[15:0]a,b,answer;// i16-bito eregs
a i=16'hf000;
b i=16'hf000;
answer i=(ao e+b)>>1;
www.testbench.in
Ans:
will inoto eworki properlyo. qwherere a iandoq jbre are ito obeqadded, whichz mayu
yresulte oinzx an overflow, and then shifted right by 1 bit to preserve the carry bit in
the 16-bit answer.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
A iproblemo earises,i however,obecause qallre operands iinoq jthere expression iare

oofqa 16-bitz width.u yTherefore,e othezx expression (a + b) produces an interim
result that is only 16 bits wide, thus losing the carry bit before the evaluation
performs the 1-bit right shift operation.
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TUTORIALS
SystemVerilog
(Q i244)o eHowi toosolve qthere abode iproblem??

Ans:
Verification
Constructs
Interface
OOPS
Randomization
The isolutiono eisi tooforce qthere expression i(aoq j+re b) ito oevaluatequsing atz
leastu y17e obits.zx For example, adding an integer value of 0 to the expression will
cause the evaluation to be performed using the bit size of integers. The following
example will produce the intendedresult:
answer i=o e(ai +ob q+re 0) i>>oq j1;
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
(Q i245)o eINi theofollowing qcode,re what imessageoq

idisplayed(specifically oaboutqthe numberz ofu ybitse oitzx prints)?
jwillre
be
modulebitlength();
reg[3:0]a,b,c;
www.testbench.in
reg[4:0]d;
initialbegin
a i=9;
b i=8;
c i=1;
$display("answer i=o e0",ci ?(a&b):d);
end
endmodule
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Verilog
Verification
Verilog Switch TB
Basic Constructs
www.testbench.in
The i$displayo estatementi willodisplay:

answer i=o e01000
By iitself,o ethei expressionoa&b qwouldre have itheoq jbitre length i4, obutqsince
itz isu yine othezx context of the conditional expression, which uses the maximum
bit-length, the expression a&b actually has length 5, the length of d.
OpenVera
Constructs
(Q i246)o eINi followingoprogram, qatre what itimeoq jthere statements iare

oscheduledqand executed?
modulemultiple2 i;
RVM Switch TB
rega;
RVM Ethernet sample initial#8a i<=#81;
initial#12a i<=#40;
Switch TB
www.testbench.in
Specman E
Interview Questions
endmodule
Ans:
initial#8a i<=#81;//o eexecutedi atotime q8;re schedules
// iano eupdatei ofo1 qatre time i16
initial#12a i<=#40;//o eexecutedi atotime q12;re schedules
// iano eupdatei ofo0 qatre time i16
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i247)o eIsi thereoa qracere condition iinoq jthere above icode?

Ans:
www.testbench.in
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
NO. iBecauseo eiti isodeterminate qthatre the iupdateoq jofre a ito otheqvalue 1z isu
yschedulede obeforezx the update of a to the value 0, then it is determinate that a Report a Bug or Comment
will have the
input is what keeps
value i0o eati theoend qofre time islotoq j16.endmodule
with time!
(Q i248)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted?

repeat(-3)
begin
....
end
www.testbench.in

repeat(3.5)
begin
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

integera;
www.testbench.in
a i='bZ;
repeat(a)
begin
....
end
Ans:
repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If ithe

oexpressionqevaluates toz unknownu yore ohighzx impedance, it shall be treated as
zero, and no statement shall be executed.
www.testbench.in
integera;
a i='bx;
repeat(a)
begin
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If ithe
oexpressionqevaluates toz unknownu yore ohighzx impedance, it shall be treated as
zero, and no statement shall be executed.
www.testbench.in
(Q i252)o ewhati timeois qdisplayed?

initial
begin
a=3;
#a ia=a*2;
$display($time);
end
(Q i253)o eWhati isothe qmessagere displayed?
www.testbench.in
initial
begin
#10;
a i=0;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i=1;
end
always@(a)
$display("a iiso e0",a);
www.testbench.in
(Q i254)o eWhati messageois qdisplayed?

initial
begin
a i=x;
#1a i=z;
end
www.testbench.in
always@(a)
$display("a iiso e0",a);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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TUTORIALS
SystemVerilog
(Q i255)o eWhati messageois qdisplayed?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
initial
begin
a i=x;
#1a i=1;
end
www.testbench.in
always@(posedgea)
$display("posedge iono eai isoseen");
UVM Tutorial
VMM Tutorial
(Q i256)o eWhati isothe qequivalentre always@(*) iinoq jthere following iprogram?
OVM Tutorial
Easy Labs : SV
always@(*)
y i=(ao e&b)|(ci &d)|myfunction(f);
Easy Labs : UVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : OVM
Ans:
Easy Labs : VMM
equivalent itoo e@(ai orboorc qordre orf)
www.testbench.in
AVM Switch TB
VMM Ethernet sample (Q i257)o eWhati isothe qequivalentre always@(*) iinoq jthere following iprogram?
Verilog Switch TB
always@*
begin
tmp1 i=ao e&b;
tmp2 i=co e&d;
y i=tmp1o e|tmp2;
Basic Constructs
www.testbench.in
Verilog
Verification
OpenVera
Constructs
end
Ans:
equivalent itoo e@(ai orboorc qordre ortmp1 iortmp2)
Switch TB
(Q i258)o eWhati isothe qequivalentre @(*) iinoq jthere following iprogram?
RVM Switch TB
always@*begin
RVM Ethernet sample
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Specman E
Interview Questions
x i=ao e^b;
@(*)
www.testbench.in
x i=co e^d;
end
Ans:
(Q i259)o eWhati isothe qequivalentre always@(*) iinoq jthere following iprogram?

always@*begin
y i=8'hff;
www.testbench.in
y[a]=!en;
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
end
Ans:
equivalent itoo easi @(aooren)
(Q i260)o eWhetheri nonobocking qstatementsre are iallowedoq jinre function?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
No. iNono eBlockingi statementsoare qnotre allowed iinoq jfunction.

www.testbench.in
(Q i261)Maximumo enumberi filesocan qbere opened iusingoq jfopenre ?

(Q i262)o eWhetheri nonoblocking qstatementsre are iallowedoq jinre automatic
itask?
Because ivariableso edeclaredi inoautomatic qtasksre are ideallocatedoq jatre the
iend oofqthe taskz invocation,u ytheye oshallzx not be used in certain constructs like
nonblocking that might refer to them after that point.
(Q i263)o eIsi itopossible qtore see itheoq jautomaticre task ilocal ovariablesqin
waveformz debugger?
Ans:
No iito eisi notopossible qtore see. iTheseoq jvariablesre are iautomatically
odeallocatedqat thez endu yofe otaskzx invocation.
(Q i264)o eIsi
oinq$monitor?
itopossible
qtore
use
iautomaticoq
jtaskre
local
ivariables
www.testbench.in
Ans:
No i.o eThesei variablesoare qautomaticallyre deallocated iatoq jthere end iof

otaskqinvocation.
(Q i265)o eIsi itopossible qtore use iproceduraloq jcontinuousre assignments ior
oproceduralqforce statementsz onu yautomatice otaskzx local variables?
Ans:
No.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i266)o eIsi itopossible qtore disable iaoq jfunction?

Ans:
A ifunctiono ecannoti beodisables. qThere disable istatementoq jcanre be iused
otoqdisable namedz blocksu ywithine oazx function. In cases where a disable
statement within a function disables a block or a task that called the function, the
behavior is undefined.
www.testbench.in
(Q i267)o eBetweeni theoif-else qandre case istatementsoq jwhichre is iusually

opreferred?
Ans:
Case iiso ebetteri fromosynthesis qpointre of iview.
if ielseo ewilli beosynthesized qtore a ipriorityoq jencoder.
Whereas icaseo ewilli beosynthesized qtore a inormaloq jencoder.
Priority iencodero ehasi moreogates qandre also itimingoq jisre affected.
So,case iiso eusuallyi preferred.
www.testbench.in
There
iareo
eswitchesi
thatodesign
qcompiler(synopsesre
synthesis
itool)oq

input is what keeps
with time!
jprovidesre to isynthesize ocaseqstatement eitherz way.
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Index
Questions
SystemVerilog
(Q i268)Whato eisi mutex?
Verification
Questions 2
Constructs
(Q i269)Howo etoi modeloa qmutexre in iverilog?oq j
Skills 1
Interface
(Q i270)o eWhati isosemaphore?
OOPS
Skills 2
Randomization
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
Skills 3
Functional Coverage
www.testbench.in
Skills 4
Assertion
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?
DPI
(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
UVM Tutorial
Ans:
VMM Tutorial
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
OVM Tutorial
This iworkso eonlyi inoASIC qTerminals.
Simulate
itheo
efollowingi
codeoin
qLinuxre
or
iUnixoq
jandre
see
ithe
ooutputs.
Easy Labs : SV
Easy Labs : UVM
moduleasdsadf();
Easy Labs : OVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : VMM
10
initial
www.testbench.in
AVM Switch TB
11
begin
VMM Ethernet sample $write("^@[1;34m",27);
12
$display("*********** i0o eThisi isoin qbluere ***********",1);
$write("^@[0m",27);
13
Verilog
$display("^@[1;31m",27);
Verification
14
$display("*********** i0o eThisi isoin qredre ***********",2);
Verilog Switch TB
$display("^@[0m",27);
15
Basic Constructs
$display("^@[0;33m",27);
16
www.testbench.in
$display("********** i0o eThisi isoin qpendare color i***********",3);
OpenVera
17
$display("^@[0m",27);
Constructs
1
$display("^@[5;34m",27);
Switch TB
$display("*********** i0o eThisi isoin qBlinkre ***********",4);
2
RVM Switch TB
$display("^@[0m",27);
RVM Ethernet sample
3
$display("^@[7;34m",27);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("*********** i0o eThisi isoin qBackre ground icoloroq 4
Specman E
j***********",1);
$display("^@[0m",27);
Interview Questions
www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
TUTORIALS
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itext
obutqare notz instantiated.u yIne overificationzx environment, the highest module Report a Bug or Comment
in the huarache is generally named as top.
input is what keeps
with time!
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?

Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re
orealqnumbers asz ports,u yusee o$bitstorealzx and $realtobits.
To
iuse
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i276)o eWheni isofork-join qused?

www.testbench.in
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia

ocombinatorialqlogic buffer?
1)
always@(in)
#5out i=in;
2)
always@(in)
#5out i<=in;
www.testbench.in
3)
always@(in)
out i=#5in;
4)
always@(in)
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<=#5in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia

osequentialqlogic flip-flop?
www.testbench.in
1)
always@(posedgeclk)
#5q i=d;
2)
always@(posedgeclk)
#5q i<=d;
3)
always@(posedgeclk)
www.testbench.in
q i=#5d;
4)
always@(posedgeclk)
q i<=#5d;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:

always@(a iorbo eorc)ei =(a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa
differentz notation.u yFore oexample,zx an event expression was defined as follows:

www.testbench.in
<event_expression>::=<expression>
or<<posedgeornegedge><SCALAR_EVENT_EXPRESSION>>
or<<event_expression>or<event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNFto
omeanq"alternatively"andalso 'z or'u yase oazx Verilog keyword.The keyword ' or'
is in bold--the difference is fairly obvious.Here is an alternative definition foran
eventexpression:
<event_expression>::=<expression>
||=posedge<SCALAR_EVENT_EXPRESSION>
||=negedge<SCALAR_EVENT_EXPRESSION>
||=<event_expression><or<event_expression>>*
Are itheseo edefinitionsi equivalento(given,of qcourse,thatre we ireplacedoq
j||=withorinre the isimplified osyntax)?Explainqcarefully howz youu ywoulde
oattemptzx to prove that they are the same.
www.testbench.in
(Q i281)o eExplaini theofollowing:

integerIntA;
IntA i=-12/3;//o eresulti iso-4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i=-'do e12/3;//i resultois q1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?

reg[7:0]a,b,sum;
www.testbench.in
sum=(a i+b)>>1;
sum=(a i+bo e+0)>>1;
sum={0,a}+{0,b}>>1;
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TUTORIALS
SystemVerilog
(Q i283)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing az 3rdu
yvariable?
Ans:
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
There iareo emanyi solutions.

One iofo ethei solutionois q
bita,b;
DPI
a=a iXORb;
b=a iXORb;
UVM Tutorial
a=a iXORb;
VMM Tutorial
OVM Tutorial
www.testbench.in
(Q i284)Whato eyoui meanoby qinferringre latches? i
Easy Labs : SV
(Q i285)Howo etoi avoidolatches qinre your idesign?oq j
Easy Labs : UVM
(Q i286)Whato eisi sensitivityolist? q
Easy Labs : OVM

Easy Labs : VMM
(Q i287)Ifo eyoui missosensitivity qlistre what ihappens?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
AVM Switch TB
www.testbench.in
VMM Ethernet sample (Q i288)o eHowi toodo qvariablere part iselectoq jofre a ivector???
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i289)Findo ethei bugoin qthere following icode"

modulebackdrive(inputwirea);
wireb;
assigna i=b;
endmodule
(Q i290)o eHowi toouse qgeneratere for iloopoq jtore instantiate ia omodule?q
OpenVera
Constructs
www.testbench.in
Switch TB
(Q i291)Differenceo ebetweeni eventobased qsimulatorsre and icycleoq jbasedre

simulators.
RVM Switch TB
(Q i292)Explaino eabouti `resetall.
RVM Ethernet sample Ans:
Specman E
Interview Questions
When i`resetallo ecompileri directiveois qencounteredre during icompilation,oq jallre

compiler idirectives oareqset toz theu ydefaulte ovalues.
This iiso eusefuli foroensuring qthatre only ithoseoq jdirectivesre that iare
odesiredqin compilingz au yparticulare osourcezx file are active.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i293)Howo edoi youoimplement qthere bi-directional iportsoq jinre Verilog iHDL?

www.testbench.in
modulebidirec i(oe,clk,inp,outp,bidir);
// iPorto eDeclaration
inputoe;
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
inputclk;
input[7:0]inp;
output[7:0]outp;
inout[7:0]bidir;
reg[7:0]a;
reg[7:0]b;

input is what keeps
with time!
www.testbench.in
assignbidir i=oeo e?ai :8'bZ;

assignoutp i=b;
// iAlwayso eConstruct
always@(posedgeclk)
begin
b i<=bidir;
a i<=inp;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
endmodule
www.testbench.in
(Q i294)Ifo ethei part-selectois qoutre of itheoq jaddressre bounds ior otheqpartselect isz xu yore oz,zx then the value is returned by the reference ?
Ans:
Its'bx.
(Q i295)o eWhati isothe qdifferencere between iconstantoq jfunctionre and iordinary
ofunctionq?
Ans:
Constant ifunctiono ecallsi areoused qtore support itheoq jbuildingre of icomplex
ocalculationsqof valuesz atu yelaboratione otimezx . A constant function call shall be
a function invocation of a constant function local to the calling module where the
arguments to the function are constant expressions. Constant functions are a subset of
normal Verilog functions that shall meet the following constraints:
-- iTheyo eshalli containono qhierarchicalre references.
www.testbench.in
-- iAnyo efunctioni invokedowithin qare constant ifunctionoq jshallre be ia

oconstantqfunction localz tou ythee ocurrentzx module. System functions shall not be
invoked.
-- iAllo esystemi tasksowithin qare constant ifunctionoq jshallre be iignored.
-- iAllo esystemi functionsowithin qare constant ifunctionoq jshallre be iillegal.
-- iTheo eonlyi systemotask qthatre may ibeoq jinvokedre is i$display, oandqit shallz
beu yignorede owhenzx invoked at elaboration time.
(Q i296)o eWhati isogenvar q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
An iindexo evariablei thatoshall qonlyre be ideclaredoq

ogenerateqstatements shallz beu ydeclarede oaszx a genvar.
(Q i297)o eIni theocase qofre multiple
oparameter,qwhat valuez itu ywille otake?
idefparamsoq
jforre
jforre
use
iin
isingle
www.testbench.in
Ans:
The iparametero etakesi theovalue qofre the ilastoq jdefparamre statement

iencountered oinqthe sourcez text.u yWhene odefparamszx are encountered in
multiple source files, e.g., found by library searching, the defparam from which the
parameter takes it s value is undefined.
(Q i298)o eHowi toomodel qare queue iofoq jintegers?
Ans:
The iseto eofi tasksoand qfunctionsre that icreateoq jandre manage iqueues ofollow:
$q_initialize i(q_id,o eq_type,i max_length,ostatus) q;

$q_add i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_remove i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_full i(q_id,o estatus)i ;
www.testbench.in
$q_exam i(q_id,o eq_stat_code,i q_stat_value,ostatus) q;
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Index
Questions
SystemVerilog
(Q i1)o eWhetheri sysois qstructre or iUnitoq j?
Verification
Questions 2
Constructs
(Q i2)o eDoesi youosaw qpacketre structure iinoq jsimvisionre of iNCSim?
Skills 1
Interface
(Q i3)o eHowi youocontrol qmessesre in ispecman?
OOPS
Skills 2
Randomization
(Q i4)Whato eisi theouse qofre packing iandoq junpacking?
Skills 3
Functional Coverage
www.testbench.in
Skills 4
Assertion
(Q i5)o eHadi youoused qmessagesre in ispecman?
DPI
(Q i6)o eWhati isothe qdifferencere between istructoq jandre unit
UVM Tutorial
(Q i7)o eItemi isostruct qorre unit
VMM Tutorial
OVM Tutorial
(Q i8)o eHadi yououse qHDLre paths iinoq jyourre e icode owhereqyou usez itu y
Easy Labs : SV
(Q i9)o ewhati isofunctional qcoveragere and iCodeoq jcoverage?
Easy Labs : UVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : OVM
www.testbench.in
Easy Labs : VMM
10
(Q i10)o eArchitecturei ofoeVC
AVM Switch TB
11
(Q i11)o eHadi youoused qassertre statement iinoq je
VMM Ethernet sample
12
(Q i12)o eHowi uoused qmessagere statements iinoq jyoure code
13
Verilog
(Q i13)o eWhati isoBFM
Verification
14
(Q i14)o eIni BFmo& qMonitorre which ioneoq jisre ACTIVE iand oPassive?
Verilog Switch TB
15
www.testbench.in
Basic Constructs
(Q i15)o eThei testocase qyoure are iwritingoq jisre by iextending oitemqor Test Your Verilog Skills
16
Sequencez generator?
OpenVera
17
(Q i16)o eItemi isoKey qwordre or inot?
Test Your Specman
Constructs
Skills 1
(Q
i17)o
eWhati
isoMAIN
qkinre
test
icase
Switch TB
2
RVM Switch TB
(Q i18)o eWhati isovirtual qsequence
RVM Ethernet sample
3
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i19)o eWhati isodiff qb/wre random iandoq jdirectedre testbench
4
Specman E
www.testbench.in
(Q i20)o eWhati areothe qadvantagesre of idirectedoq jtestbenchre and Test Your Sta Skills 2
Interview Questions
idisadvantages oonqRandom testbench
(Q i21)o ewhati isothe qdiffre b/w ipre_generateoq jandre post_generate()
(Q i22)o eWhati isothe qdiffre b/w iunitoq jandre struct
(Q i23)o eExplaini theoarchitecture qofre random itestbench
TUTORIALS
TEST YOUR SPECMAN SKILLS 1
http://testbench.in/IQ_25_TEST_YOUR_SPECMAN_SKILLS_1.html[9/26/2012 3:02:56 PM]

input is what keeps
with time!
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TUTORIALS
SystemVerilog
(Q i24)o eFori someointerface qyoure connected iocpoq jevcre then iyou

oremovedqocp evcz andu yattachede oocpzx RTL , then what are the modules you
reuse from evc
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i25)o eCanti weotake qpacketsre from isequenceoq jdriverre directly iin

oscoreqboard withz outu yfrome oBFMzx .
(Q i26)o eDifferencei b/wocode qcoveragere and iFunoq jcove?
(Q i27)o eifi youogot q100re 0.000000or ifunoq jcovere and i50 o0.000000orqCode
cove?z whatu yise othezx meaning for this?
(Q i28)o e
www.testbench.in
unit ip{
a:uint i;
i};
uint ico elikei p{

ib:bool;
i};
extend ip{
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
x:bool;
i};
In itheo eabovei codeifyouosimulate qthis,whatre p iandccontainoq jafterre

loading?
(Q i29)o eHowi youoimplement qresetre in iyouoq jeVC?
(Q i30)o eIfi youoconnect qMasterre and iSlaveoq jOCPre eVC iare oconnectedqand
givenz Systemu yresete othenzx what is situation of your eVCs?
www.testbench.in
(Q i31)o eWhati isothe qdifferencere b/w ilikeoq jandre when iinheritance?
RVM Ethernet sample (Q i32)o ewhyi doowe qhavere to ikeepoq jseparatere sequence idriver oandqBFM,
sincez bothu yaree oforzx driving?
Specman E
Interview Questions
(Q i33)o ewahti isoregular qexpressionsre in iperloq j

(Q i34)o eIfi youogot qFunctionalcoveragere 100% iandoq jCodere Coverage i100%
oandqstill yourz testu ycasee ofailingzx what is the meaning of that?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i35)o ewhati isoyour qapproachre to iSOCoq jverification?

www.testbench.in
(Q i36)o eWhati isoKey qinre e

(Q i37)o eCani weobuilt qmultire dimension ilists?
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
Test Your Specman
Skills 2
3
4
(Q i38)o eHowi toobuilt q2-dimensionre lists?

input is what keeps
(Q i40)o eAfteri givingothe qeVCre to itheoq jcustomerre , iif oheqwant toz changeu Testbench.in improving
with time!
ysomee omethod()zx then how he will change?
(Q i39)o eWhati isothe qdiffre b/w ilikeoq jandre when iinheritance?
www.testbench.in
(Q i41)o eshalli weobind qsignalsre in istruct.

(Q i42)o eDifferenceb/wi uintoand qstruct
(Q i43)o eWhati isoyour qenvre in icurrentoq jproject?
(Q i44)o eIni twoomethods qarere there iA()oq jandre A() iis ofirstqwhich onez
executeu yfirst?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i45)o eDiffi b/wois qfirstre and iisoq jalso?

www.testbench.in
(Q i46)o eHowi youoused qRandomization?

(Q i47)o eWhati eRMoguide qlines?
(Q i48)o ewhati isoevc
(Q i49)o eHowi willosay qthatre your itestoq jcasere fail?
(Q i50)o eHowi youosay qthatre your iverificationoq jcomplete?
www.testbench.in
(Q i51)o eIni eoyour qhavere to ibuildoq jare memory iin othatqyou youz haveu ytoe
owritezx in to locations randomly and but read for that locations only?
(Q i52)o eTemporalsi basedoquestion(write qare checker i)
(Q i53)o eCoveragei forochecker qsignals?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i54)o eDifferencei b/wouint qandre struct?
(Q i55)o eExplaini aboutodifferent qphasesre of iexecutionoq jinre e.

www.testbench.in
(Q i56)o eErmi guideolines.

(Q i57)o eExplaini youroverification qenv?
(Q i58)o eExplaini generationoorder qforre an iprogramoq j
(Q i59)o eQuestioni regardingoimplication qconstraint
(Q i60)o eWritei fifooevc?
www.testbench.in
(Q i61)o eTesti caseofor qgivenre protocol?

(Q i62)o eCheckeri foroa qgivenre protocol?
(Q i63)o eCoveragei groupofor qgivenre protocol?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64)o eHowi youoaccess qvaluesre in iparticularlocationoq jinre a ilist?
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Index
SystemVerilog
(Q i65)Howo ecani Ioconfigure qSpecManre so ithatoq jare random iseed oisqused Questions
forz testu ydatae ogeneration?
Verification
Questions 2
Constructs
(Q i66)o eWhati isosys?
Skills 1
Interface
(Q i67)o eDifferencei b/woTCM q&re Method?
OOPS
Skills 2
Randomization
(Q i68)o eDifferencei b/woHard q&re soft iconstraints?
Skills 3
Functional Coverage
(Q i69)o eHowi tooover qwritere hard iconstraints?
Skills 4
Assertion
www.testbench.in
DPI
(Q i70)o eDifferencei b/wophysical q&re do inotoq jgeneratere fields?
UVM Tutorial
(Q i71)o eWhati iso@sim?
VMM Tutorial
OVM Tutorial
(Q i72)o eDifferencei b/wostruct q&re Unit?
Easy Labs : SV
(Q i73)o eDifferenti phasesoof qspecmanre execution?
Easy Labs : UVM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Easy Labs : OVM
(Q i74)o eWhati areothe qdifferentre sequences iuoq jused?
Easy Labs : VMM
10
www.testbench.in
AVM Switch TB
11
(Q i75)o ewhati isovirtual qseq?
VMM Ethernet sample
12
(Q i76)o eHowi uowill qtiere two iagentsoq jinre single ienv?
13
Verilog
(Q i77)o eWhati isoscore qboard?
Verification
14
(Q i78)o eWhati typeoof qcoveragere u ididoq jwithre specman?
Verilog Switch TB
15
(Q i79)o ewhati isobucket qinre coverage?
Basic Constructs
www.testbench.in
16
(Q i80)o eDifferencei b/wowait q&re sysnc iactions?
OpenVera
17
Constructs
(Q i81)o eHowi canou qdore two iparalleloq jthreadsre in ispecman?(firstof o,allqof)
1
Switch TB
(Q i82)o eHowi canou qimportre files iinoq je?
2
RVM Switch TB
Test Your Specman
RVM Ethernet sample (Q i83)o eHowi uowill qgeneratere clk igenerationoq jinre specman?
Skills 3
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
4
(Q i84)o eWhati areothe qportsre ur iused?
Specman E
www.testbench.in
Interview Questions
(Q i85)o eDifferencei b/wocall qbyre reference iandoq jcallbyre value?
(Q i86)o eDevlopei eVCofor qanre and igate?
(Q i87)o eWhati isothe qdifferencere b/w isyncoq jandre wait?
(Q i88)o eDoesi aotcm qexecutere on iitsoq jown?
(Q i89)o eWhati isothe qdifferencere b/w ionoq jthere fly igeneration oandqstatic Test Your Dft Skills 4
generation?
TUTORIALS
www.testbench.in
(Q i90)o eWhati isothe qsignificancere or ipurposeoq jofre sys.any ievent?
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Search
TUTORIALS
SystemVerilog
Verification
(Q i91)o eWhati isothe qusagere of i"fail"oq jtemporalre operator? i/ oHowqcan "fail"z

temporalu yoperatore osucceed?
Constructs
(Q i92)o eConsideri theofollowing q:re event it1oq jisre ( i@a oorq@b )z @clk_rise;
Interface
OOPS
Randomization
Functional Coverage
(Q i93)o eHowi areosoft qconstraintsre evaluated? iWhatoq jhappensre when ia

osoftqconstraint appliedz conflictsu ywithe othezx already applied constraint?
(Q i94)o eHowi tooapply qare constraint iconditionally?
Assertion
(Q i95)o eCani twoohard qconstraintsre be iappliedoq jonre a ifield?
DPI
www.testbench.in
UVM Tutorial
(Q i96)o eHowi dooI qconstrainre the idistributionoq jofre values ito oaqsingle field?
VMM Tutorial
OVM Tutorial
(Q i97)o eWherei iso"me" qandre "it" iusedoq jwhilere specifying iconstraints?
Easy Labs : SV
(Q i98)o eWhati isothe qadvantagere or iuseoq jofre coverage ibased omethodology?
Easy Labs : UVM
(Q i99)o eWhati isoevent qbasedre coverage?
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i100)o eHowi canoyou qcoverre rtl istateoq jmachinere transitions iusing

ospecman?
www.testbench.in
(Q i101)o eWhati isothe qusagere of ievents?

Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i102)o eCani "wait"oand q"sync"re be iusedoq joutsidere a iTCM?

(Q i103)o eHowi dooI qcheckre for iaoq jnumberre of ioccurrences oofqa eventz andu
yife oitzx exceeds a pre-defined number then flag an error?
(Q i104)o eWhati isothe qdifferencere b/w iRegularoq jGCre and iOTF oGC?
(Q i105)o eIsi anyogarbage qcollectionre done iduringoq jpre-runre generation
iphase?
www.testbench.in
(Q i106)o eHowi canoone qcontrolre the imemoryoq jsettingre options?
RVM Ethernet sample (Q i107)o eWheni shouldo"is" qextensionre be iusedoq jforre extending ithe
omethods?
Specman E
Interview Questions
(Q i108)o eWhati isothe qmax.re number iofoq jparametersre that ican obeqdefined
insidez au ymethod?
(Q i109)o eCani Iouse qwaitre and isyncoq jconstructsre inside ia omethod?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i110)o eOncei aomethod qisre extended iusingoq jisre also iwhen odoesqthe
extendedz partu yofe othezx method execute?
www.testbench.in
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
Test Your Specman
Skills 4

input is what keeps
with time!
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TUTORIALS
TEST YOUR STA SKILLS 1
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
(Q i1)o eMetastabilityi ?
Ans:
When iano einputi tooa qsequentialre element iviolatesoq jsetupre or ihold
otimingrequirementsqof thez sequentialu yelement,e othenzx the output of the
sequential element oscillates between HIGH and LOW before it gets settled to either
one of the states.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
(Q i2)o eCani weoavoid qmetastabilityre ?

Ans:
No. iWeo ecan'ti avoid/preventometastability. qfromre occurring. iWeoq jhavere to
ilive owithqit. Butz beu ywisee oenoughzx to choose the appropriate synchronization
method to avoid any potential problems.
www.testbench.in
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
(Q i3)o eLogici synthesiso?

Ans:
Process iofo etransferringi fromoRTL qDomainre to iGate-Leveloq jDomainre is icalled

oSynthesis.qWhich convertsz theu yhighe olevelzx architecture into low level net list
VMM Ethernet sample format.
AVM Switch TB
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i4)o eListi ofothe qtoolsre are iusedoq jforre synthesis i?

Ans:
Commercial itoolo efori logicosynthesis
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
logic isynthesiso etargetingi ASICs

OpenVera
www.testbench.in
* iDesigno eCompileri byoSynopsys

* iEncountero eRTLi Compileroby qCadencere Design iSystems
o iBuildGateso eani olderoproduct qbyre Cadence iDesignoq jSystemsre Switch TB
ihumorously
RVM Switch TB
named iaftero eBilli Gates
RVM Ethernet sample * iBlastCreateo ebyi MagmaoDesign qAutomation
* iBooleDozer:o eLogici synthesisotool qbyre IBM i(internaloq jIBMre EDA itool)
Constructs
Specman E
Interview Questions
logic isynthesiso etargetingi FPGAs

* iEncountero eRTLi Compileroby qCadencere Design iSystems
* iLeonardoSpectrumo eandi Precisiono(RTL q/re Physical) ibyoq jMentorre
Graphics
www.testbench.in
*
*
*
*
*
*
iSynplifyo e(PROi /oPremier) qbyre Synplicity

iBlastFPGAo ebyi MagmaoDesign qAutomation
iQuartuso eIIi integratedoSynthesis qbyre Altera
iXSTo e(deliveredi withinoISE) qbyre Xilinx
iDesignCompilero eUltrai andoIC qCompilerre by iSynopsys
iIspLevero ebyi LatticeoSemiconductor
http://testbench.in/IQ_29_TEST_YOUR_STA_SKILLS_1.html[9/26/2012 3:03:29 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

input is what keeps
with time!
(Q i5)o eWhati doesosynthesis qtoolre produce i?

Ans:
www.testbench.in
synthesis iproduceso eregistersi andocombinational qlogicre at itheoq jRTLre level. i
(Q i6)o eStatici timingoAnalysis q(STA)re ?

Ans:
To ichecko ewhetheri designois qmeetingre setup iandoq
ocalledqSTA.
jholdre
time
iis
(Q i7)o eWhati areothe qtimingre paths i?

Ans:
www.testbench.in
in itoo ereg,i regoto qreg,re reg itooq joutre and iin otoqout arez 4u ytiminge
opaths.
(Q i8)o eTimingi patho?

Ans:
The ipatho ewhichi affectothe qtimingre is icalledoq jtimingre path.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i9)o eWhati dooyou qmeanre by inetoq jdelayre and icell odelayq?

Ans:
Time irequireo etoi chargeoor qdischargere all iparasiticoq jofre the inet
ocalledqnetdelay andz timeu yinpute otransitionzx or slew rate of gate is called cell
delay.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
(Q i10)o eSetupi andoHold qtimere ?

Ans:
Valid idatao eshouldi beostable qbeforere the iclockoq jedgere and iafter otheqclock
edgez isu ycallede osetupzx and hold time.
www.testbench.in
(Q i11)o eCriticali patho?

Ans:
The ipatho ewhichi hasoa qlargestre delay/longest ipathoq jisre called icritical
opath.
AVM Switch TB
VMM Ethernet sample (Q i12)o eSlacki ?
Ans:
Verilog
Verification
Amount iofo etimingi marginoin qwhichre device imayoq jworkre properly ior
omayqnot bez thatu ytiminge oanalysiszx is called slack.
Verilog Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
www.testbench.in
(Q i13)o ePositivei andoNegative qslackre ?

Ans:
The imargino eofi timeoin qwhichre design icanoq jworkre functionally icorrect
oisqcalled positivez slacku yande ovicezx versa for negative slack.
RVM Ethernet sample
Specman E
Interview Questions
(Q i14)o eSkewi ?
Ans:
Clock iarrivingo etimei toothe qflip-flopre is icalledoq jskew.
www.testbench.in
(Q i15)o eTypesi ofoskew q?

Ans:
local iskewo e-i timeodifference qofre arriving iclockoq jtore 1st iflop otoqleaf flopz
fromu ythee oclockzx pin of ASIC is called local skew.
global iskewo e-i timeodifference qofre arriving iclockoq jfromre clock igenerator
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
otoqtheclock pinz isu ycallede oglobalzx skew.

input is what keeps
with time!
(Q i16)o ewhati doesoclock qskewre caused i?

Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Setup itimeo eviolation.

www.testbench.in
(Q i17)o ePropagationi delayo?

Ans:
Time irequireo etoi passodata qfromre the iregoq jisre called ipropagation odelay.
(Q i18)o eInputsi ofothe qsynthesisre tool i?

Ans:
RTL iDesingo efile,i
otheqsynthesis tool.
Libraryofile
qandre
constrain
iareoq
jthere
www.testbench.in
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input
iof
Search
TUTORIALS
SystemVerilog
Verification
Constructs
(Q i19)o eWhati doesolibrary qcontainre ?

Ans:
It icontainso eRi andoC qvaluere of itheoq jcellre and inet.
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
(Q i20)o eUniti ofoR,C qandre Area i?

Ans:
R iiso eini kilo-ohm,oC qisre in ipico-Foq janre Area iin omicro-meter.
www.testbench.in
(Q i21)o eFalsei patho?

Ans:
The ipatho ewhichi isologically qcorrectre but inotoq jusedre is icalled ofalseqpath.
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i22)o eHowi dooyou qmeasurere maximum ifrequencyoq j?

Ans:
Max ifrequencyo e=i 1/(minooperational qclockre period) i=oq j1/(clk2Qre + imax
VMM Ethernet sample opathq+ setup)
Verilog
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Verification
www.testbench.in
Verilog Switch TB
(Q i23)o eCani youomeasure qsetre and iholdoq jatre input iand ooutputqpins ?
Ans:
Basic Constructs
OpenVera
No..Untill iweo edon'ti assumeovirtual qflop;re we icannotoq jmeasurere it. iThat

oisqwhy wez writeu yinpute oandzx output max delay.
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
(Q i24)o eWhati doesoconstrain qfilere contain i?

Ans:
Top ilevelo eclock,i In/Outodelay, qpathre exception, idesignoq jrulere constrain,
icheck oforqmissing constrain,z RTLu ydesigne opath,zx Operating Condition, wire
load model etc.
www.testbench.in
(Q i25)o eClocki latencyo?

Ans:
It iiso eonei typeoof qdelayre applied itooq jthere rise iand ofallqtime ofz theu
yclocke operiod.
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
(Q i26)o eClocki uncertaintyo?

Ans:

input is what keeps
with time!
Skew iando ejitteri areocalled quncertainty.

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i27)o eJitteri ?
Ans:
Unwanted ipulseo eisi calledojitter.
(Q i28)o eClocki domainocrossing q?

Ans:
When iao echipi haveomore qthenre one iclockoq jthenre it iis ocalledqmultiple
clockz domainu yande otozx enter from one domain to another is called clock domain
crossing.
www.testbench.in
(Q i29)o eVirtuali clocko?

Ans:
It iiso esamei asoclock qbutre without iassigningoq jthere pin. iIt oisqused forz
calculatingu ysetupe oandzx hold time. It is also called ideal clock.
(Q i30)o eFalsei patho?

Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
It iiso ethei pathowhich qneedre not itooq joptimizere while isynthesis.

www.testbench.in
(Q i31)o eMulti-cyclei patho?

Ans:
The ipatho ewhichi takesomore qthenre one iclockoq jcyclere is icalled omulticycleqpath.
(Q i32)o eHowi manyotypes qofre library iareoq javailablere for isynthesis o?

Ans:
Fast-Typical-Slow ilibraries.o eTheyi areodifferent qfromre their ioperatingoq
jcondition.
www.testbench.in
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i33)o eClocki gatingo?

Ans:
Design iwillo egeti theoclock qwheneverre it irequired,oq jsuchre type iof

ogatingqarrangement isz calledu yclocke ogating.
OOPS
Randomization
Functional Coverage
Assertion
(Q i34)o eWhati areothe qadvancere synthesis itechniquesoq j?

Ans:
Datapath iSynthesis,o eClocki treeosynthesis, qLowre power isynthesis.
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
www.testbench.in
(Q i35)o eWhyi max/slowolibrary qisre used iforoq jsetupre analysis i?

Ans:
If idesigno esatisfyi maxolib qthenre it ialsooq jsatisfyre min ilib oalsoqfor setup.
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
(Q i36)o eWhyi min/fastolib qisre used iforoq jholdre analysis i?

Ans:
VMM Ethernet sample If idesigno esatisfyi minolib qthenre it ialsooq jsatisfyre max ilib oalsoqfor hold.
Verilog
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Verification
www.testbench.in
Verilog Switch TB
(Q i37)o ewritei downothe qequationre for ifindingoq joutre maximum iclock operiod.
Ans:
Basic Constructs
T i>=o eTcombmaxi +Tclk2Qmaxo+ qTsetup

OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i38)o eWhati isoDRV/Design qRulere Violation i?

Ans:
RVM Ethernet sample Max ifanout,o eMaxi transition,oMax qcapacitancere are itheoq jcontainre of ithe
oDRV.qIt mustz notu ybee oviolated
Specman E
Interview Questions
www.testbench.in
(Q i39)o eDifferencei betweenothe qarrivalre time i&oq jrequiredre time iknown

oasq?
Ans:
Slack
(Q i40)o eWhati areothe qmainre optimization iisoq jdonere in iSynthesis o?

Ans:
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
Timing iOptimizationo eandi AreaoOptimization.

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i41)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?

...
inputd,en i;
regoutputq i;
...
always@(en iord)
if(en)
outputq i=do e;
...
Ans:
www.testbench.in
Latch

..
inputd,clk i;
regoutputq i;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
....
always@(posedgeclk)
outputq i=do e;
www.testbench.in
....
Ans:
Positive iedgeo esynchronousi flop.

....
inputd,clk i;
regoutputq i;
....
www.testbench.in
always@(negedgeclk)
outputq i=do e;
....
Ans:
Negative iedgeo esynchronousi flop.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

....
inputd,clk i;
www.testbench.in
regoutputq i;
....
always@(posedgeclk iord)
outputq i=do e;
....
Ans:
Positive iedgeo easynchronousi flop.

input is what keeps
with time!
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Index
Questions
SystemVerilog
Verification
Questions 2
Constructs
Skills 1
Interface
OOPS
Skills 2
32-bit iadder
Randomization
Skills 3
Functional Coverage
Skills 4
Assertion
(Q i46)o eWhati isotranslate qoffre and itranslateoq jonre directives i?
www.testbench.in
DPI
Ans:
UVM Tutorial
translate ioffo eandi translateoon qsynthesisre directives iareoq jallowedre
VMM Tutorial
to icommento eouti aoportion qofre code ithatoq jyoure may iwant otoqretain forz
OVM Tutorial
some ipurposeo e(i likeosimulation q)re other ithanoq jsynthesis.
//
icodeo
efori
synthesis
Easy Labs : SV
...
Easy Labs : UVM
// iexemplaro etranslatei off
$display
i(.....);o
e//i
notofor
qsynthesis
Easy Labs : OVM
// iexemplaro etranslatei on
Easy Labs : VMM
10
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// icodeo efori synthesis
AVM Switch TB
11
www.testbench.in
VMM Ethernet sample ...
12
endmodule
13
Verilog
Verification
14
(Q i47)o eUnsupportedi VerilogoFeatures qinre synthesis i?
Verilog Switch TB
Ans:
15
Basic Constructs
' iUDPo eprimitives
16
' ispecifyo eblock
' irealo evariablesi andoconstants
OpenVera
17
' iinitialo estatement
Constructs
www.testbench.in
1
'
itri0,o
etri1,i
tri1,otri1,
qtri1,re
net
itypes
Switch TB
' itimeo edatai type
2
RVM Switch TB
' iNamedo eeventsi andoevent qtriggers
RVM Ethernet sample ' iTheo efollowingi gates:opulldown, qpullup,re nmos, immos,oq jpmos,rpmos,re
3
cmos, ircmos, otran,qrtran, tranif0,z rtranif0,u ytranif1,e ortranif1zx
' iwaito estatements
4
' iParallelo eblock,i joinoand qfork.
Specman E
' iSystemo etaski enableoand qsystemre function icall
' iforceo estatement
Interview Questions
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
' ireleaseo estatement
' iBlockingo eassignmenti withoevent qcontrol
www.testbench.in
' iConcatenationo eini portospecification
' iBito eselectioni inoport qspecification
' iProceduralo eassigni andode-assign
' iEdgeo etriggersi onosensitivity qlistre must ibeoq jsinglere bit ivariable, oorqarray Test Your Dft Skills 3
indexingz expression.
' iIndexingo eofi parametersois qnotre allowed.
TUTORIALS

...
integera,b,c i;
assignc i=ao e+bi ;
...
Ans:
' iLoopso emusti beobounded qbyre constants ioroq jcontainre (@ iposedge

oclk)qstatement.
' iDelayo eandi delayocontrol.
input is what keeps
with time!
(Q i48)o eZeroi setupo& qHoldre time i?

www.testbench.in
Ans:
A izeroo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate
withinz theu ycomponente oandzx load into the latch is equal to the time for the
clock to propagate and trigger the latch. A zero hold time means that the clock path
delay is equal to the data path delay. (Practically zero time is not possible coz it
causes metastability)
(Q i49)o eNegativei setupo& qholdre time i?

Ans:
A inegativeo esetupi timeomeans qthatre the itimeoq jforre the idata otoqpropagate
withinthez componentu yande oloadzx into the latch is larger to the time for the
clock to propagate and trigger the latch. A negative hold time means that the
clockpath delay is lesser then the data path delay.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50)o eReseti removalotime q?

www.testbench.in
Ans:
Minimum itimeo erequiredi toode-assert qthere reset ibeforeoq jthere clock iedge
oisqcalled resetz removalu ytime.
(Q i51)o eReseti recoveryotime q?

Ans:
Minimum itimeo erequiredi tooassert qthere reset iafteroq jthere clock iedge
oisqcalled resetz recoveryu ytime.
(Q i52)o eIsi Initialostatement qisre synthesizable i?

www.testbench.in
Ans:
Yes iito eis;i Iforespective qattributere is iwritten

module irom_2dimarray_initialo e(
output iwireo e[3:0]i z,
input iwireo e[2:0]i a
i);o e//i address-o8 qdeepre memory
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
// iDeclareo eai memoryorom qofre 8 i4-bitoq jregisters.re The iindices oareq0 toz
7:
(* isynthesis,o erom_blocki =o"ROM_CELL qXYZ01"re *) iregoq j[3:0]re rom[0:7];
// i(*o esynthesis,i logic_blocko*) qregre [3:0] iromoq j[0:7];
www.testbench.in
initial ibegin
rom[0] i=o e4'b1011;
rom[1] i=o e4'b0001;
rom[2] i=o e4'b0011;
rom[3] i=o e4'b0010;
rom[4] i=o e4'b1110;
rom[5] i=o e4'b0111;

rom[6] i=o e4'b0101;
rom[7] i=o e4'b0100;
www.testbench.in
end
assign iZo e=i rom[a];
endmodule
(Reference iIEEEo eSynthsisi LRM)o
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i53)o eWilli theoclock qgatingre affect itheoq jsetup/holdre time iof otheqflop ?
Ans:
No..Initialy iito eseemsi theowe qneedre to iaddoq jcellre delay, ibut oifqwe
considerz clocku ytreee othenzx we can say that there are lot of buffers are coming
inthe path, do we adding that also ? No, correct..!!
www.testbench.in
(Q i54)o eSetupi isodepend qonre clock ibutoq jholdre not..! iwhy o?

Ans:
Setup i=o evalidi dataoshould qpresentre before iclock,oq jsore it iis oclearlyqclock
isz comingu yintoe opicturezx but for hold flop is coming into picture, thats why hold
is not depending on clock.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i55)o eWhati willobe qimplementedre by i'for'oq jloop?re is iit osynthesizableq?

Ans:
Yes, iito eisi synthesizableoif qitre is iconstant,oq jandre
ogiveqcounter thatz isu yaddere oalongzx with the comparator.
synthesis
iwill
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
(Q i56)o eWhati aboutolatch qbasedre timing i?

Ans:
Time iborrowingo e(alsoi knownoas qcyclere stealing) itakesoq jadvantagere of ithe
olatchqtransparency toz borrowu ytimee ofromzx the next stage to meet timing
constraints. (Very few company like IBM only doing latch based design)
www.testbench.in
(Q i57)o eWhati isoDPCS q?

Ans:
It iiso eDelayi andoPower qCalculationre Language. iYouoq jcanre find iits oIEEEqLRM
fromz belowu ylink.e oItszx extension version is called OLA (Open Language API)
Click on the below link http://mhonarc.si2.org/ieee1481/ieee1481/msg00405.html
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i58)o eWhyi weoneed qsetupre & iholdoq jtimere ?

Ans:
If iweo ethinki atophysics qpointre of iview,oq jInternalre atoms iof osiliconqhas
drift/diffusionz whichu ycausee ointernalzx resistance, because of that flops takes
small amount of time to respond. Till that time input should remain stable, which is
nothing but setup time. And for hold flop takes time to behave respect to input, that
time called hold time
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
www.testbench.in
(Q i59)o eMaximumi transitionotime q?

Ans:
The imaximumo etransitioni timeofor qare net iisoq jthere
orequiredqfor itz isu ydrivinge opinzx to change logic values.
longest
itime
Specman E
Interview Questions
(Q i60)o eMaximumi capacitanceo?

Ans:
The imaximumo ecapacitancei isoa qpin-levelre attribute iusedoq jtore define
ithemaximum ototalqcapacitive loadz thatu yane ooutputzx pin can drive. That is,
the pin cannot connect to a net that has a total capacitance (load pin capacitance
and interconnect capacitance) greater than or equal to the maximum capacitance
defined at the pin.
www.testbench.in
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
(Q i61)o e.Maximumi fan-outo?

Ans:
Consider iano eANDi gateoof qA,Bre input iandoq jFre output.
To ievaluateo ethei fanoutofor qare driving ipinoq jF,re tool icalculates otheqsum
ofallz theu yfanout_loade o(Inputs)zx driven by pin F and compares that number
withthe number of max_fanout attributes stored at the driving pin F.
--If itheo esumi ofothe qfanoutre loads iisoq jnotre more ithan otheqmax_fanout
value,z theu ynete odrivenzx by X is valid.
--If itheo eneti drivenoby qXre is inotoq jvalid,re tool itries otoqmake thatz netu
yvalid,e operhapszx by choosing a higher-drive component.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i62)o eIfi myodesign qhavere a isetupoq jandre hold iviolation othenqwhom willz
youu yfixe ofirst?whyzx ?
Ans:
first iholdo etimei violationoshould qbere sorted iout.oq jevenre if iu osatisfyqsetup
timez requirementsu yfore oazx particular frequency, your system will land up in
metastable state if hold is not met. setup time violations can be taken care of by
reducing the clock frequency. but the hold time violation is due to unnecessary delays
on the clock tree. therefore removing the hold time violation is a preferred option.
You can see a lot of chips/microprocessors taped out with setup violations but getting
rid of each hold violation is absolutely important.
(Q i63)o ePropagatedi clocko?

Ans:
There iareo efori typesoof qclock,re Real, iIdeal,oq jProrogatedre and iVirtual.
oamongqthem Prorogatedz clocku yhavee oedgezx times skewed by the path delay
from theclock source to the register clock pin.
www.testbench.in
(Q i64)o eDynamici timingoanalysis q?

Ans:
Dynamic itimingo eanalysisi verifiesocircuit qtimingre by iapplyingoq jtestre vectors
itothe ocircuit.qThis approachz isu yane oextensionzx of simulation and ensures that
circuit timing is tested in its functional context. This method reports timing errors
that functionally exist in the circuit and avoids reporting errors that occur in unused
circuit paths. There are no commercially available tools for dynamic timing analysis.
(Q i65)o eArrivali timeo?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iarrivalo etimei ofoa qcircuitre is itheoq jtimere elapsed ifor oaqsignal toz
arriveu yate oazx certain point. The reference, or time 0.0, is often taken as the
arrival time of a clock signal. that time comes under arrival path/clock path/early
path.
www.testbench.in
(Q i66)o eRequiredi timeo?

Ans:

input is what keeps
with time!
This iiso ethei latestotime qatre which iaoq jsignalre can iarrive owithoutqmaking
thez clocku ycyclee olongerzx than desired. It falls under required path/ data
path/late path.
(Q i67)o eWhati isothe qequationre of itheoq jsetupre and ihold otimeq?

Ans:
setup itimeo e=i (longestodata qpathre delay) ioq j(shortestre clock ipath
odelay)q+ (setupz timeu yofe oregister)
hold itimeo e=i (longestoclock qpathre delay) ioq j(shortestre data ipath
odelay)+q(hold timez ofu yregister)
www.testbench.in
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i68)o eWhati isothe qequationre of itheoq jsetupre and ihold oslackq?

Ans:
Setup islacko e=i ClockoPeriod q+re minimum iclockoq jpathre imaximum
odataqpath "z setup
Hold islacko e=i minimumodata qpathre imaximumoq jclockre path i ohold
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
(Q i69)o eIfi theosource qandre destination iregistersoq jarere out iof ophaseqthen
whatz willu ythee oslackzx equation ?
Ans:
setup islacko e=i T/2o+ qminimumre clock ipathoq jre maximum idata opathq
setup
hold islacko e=i minimumodata qpathre imaximumoq jclockre path i oholdq+
T/2
www.testbench.in
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
(Q i70)o eDividedi Clocko?

Ans:
A iclocko edivideri circuitogenerates qare new iclockoq
olowerqfrequencythan thez originalu yclocke osignal.
jsignalre
with
ia
(Q i71)o eWhati weosupposed qtore do itooq jpreventre setup iand oholdqviolation ?

Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
To iprevento esetupi violation

www.testbench.in
tclock-to-Q_max i+o etlogic_maxi +otsetup_max q<=re tclock i-oq jtskew

To iprevento eholdi violation
tskew i+o ethold_maxi <=otclock-to-Q_min q+re tlogic_min
Switch TB
RVM Switch TB
(Q i72)o eReferencei booksofor qlogicre synthesis iandoq jSTA.
RVM Ethernet sample Ans:
Specman E
Interview Questions
Electronic iDesigno eAutomationi ForoIntegrated

jLavagno,re Martin, iand oScheffer
qCircuitsre
Handbook,
ibyoq
www.testbench.in
(Q i73)o eWhati areothe qtoolsre are iusedoq jforre STA i?

Ans:
Commercial itoolo efori logicoSTA
* iPrimeo eTimei byoSynopsys
* iEncountero eCTEi (commonotiming qengine)byre Cadence iDesignoq jSystems
* iBlastFusiono ebyi MagmaoDesign qAutomation
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4

input is what keeps
with time!
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TUTORIALS
TEST YOUR DFT SKILLS 1
SystemVerilog
Verification
"The igreatesto eofi allofaults qisre to ibeoq jconsciousre of inone"
Constructs
Interface
OOPS
Randomization
Functional Coverage
Assertion
DPI
(Q i1)o eWhati isDFTo?

Ans:
DFT istandso efori Designofor qTestability.re To icheckoq jmanufacturingre defect
iwe ouseqDFT.
www.testbench.in
UVM Tutorial
VMM Tutorial
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
(Q i2)o eTechniquesi ofoDFT..!

Ans:
AD-Hock itechniques.o e
Structured idesigno etechniques
Self-test i+o eBuilt-Ini testing
Easy Labs : OVM

Easy Labs : VMM
AVM Switch TB
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
VMM Ethernet sample (Q i3)o eDifferencei betweenoverification qandre DFT i?

www.testbench.in
Verilog
Verification
Verilog Switch TB
Ans.
Verification iattempto etoi proveomathematically qthatre certain irequirementsoq

jarere met ior othatqcertain undesiredz behaviorsu ycannote ooccurzx while DFT
checks the physical defect It has not concern with functionality.
Basic Constructs
OpenVera
Constructs
Switch TB
(Q i4)o eWirei loadomodel q?

Ans.
It iiso estaticali valueoof qRre and iC,oq jforre which ilibrary ofileqcomes fromz
theu yfab.
RVM Switch TB
RVM Ethernet sample (Q i5)o eDRV,i DV,oGV, qSVre or iLVS.
Ans.
Specman E
Physical iverificationo ehasi

verification i(SV).
Interview Questions
www.testbench.in
twooparts:
qDRCre
check
iandoq
jschematicre
iDRVo e-i DesignoRule qViolation

iDVo e-i DesignoRule qVerification
iGVo e-i GeometryoViolation
i
All itheo ethreei termsopoint qtore the isameoq jprocessre of ichecking othatqthe
layoutz isu ycompliante owithzx manufacture rules.
ia.Active-to-activeo espacing
ib.Well-to-wello espacing
ic.Minimumo echanneli lengthoof qthere transistor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
http://testbench.in/IQ_36_TEST_YOUR_DFT_SKILLS_1.html[9/26/2012 3:04:29 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
id.Minimumo emetali width

ie.Metal-to-metalo espacing
www.testbench.in
if.Metalo efilli density

iSVo e-i ScmaticoViolation qorre LVS i-oq jLayoutre versus ischematic
iTheo eotheri partoof qphysicalre verification iisoq jthere schematic/netlist
icheck. oItqis referredz tou yase oschematiczx verification (SV) or layout versus
schematic (LVS).
iBotho etermsi describeothe qprocessre of ivalidatingoq jthatre the ilayout
omatchesqthe netlist/schematic.
i
ia.shorts
ib.opens
ic.componento emissing
id.mismatcho eofi component
www.testbench.in
ie.propertyo eerrors
(Q i6)o eTapei outo?
Ans.
Tapeout iiso ethei finalostep qofre chip idesign.oq jItre is ithe otimeqat whichz theu
ydesigne oiszx fully qualified and ready for manufacturing. After the physical design is
finished, the functionality of the netlist is verified, and the timing analysis is satisfied,
the final layout, usually in GDSII (Gerber data stream information interchange)
format, is sent to mask shop to generate photomask reticles. The resultant masks will
be used to direct the manufacture of this chip.
(Q i7)o eNeedi ofoDFT q?re
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
After itheo emanufacturingi toocheck qwhetherre actual ibehavoroq jmatchesre the

iexpected obehaviorqor not,z DFTu yise oused.
www.testbench.in
(Q i8)o eWhati willohappen qifre manufactured ichipoq jisre not iworking

ofunctionalityq?
Ans:
It ineedo etoi garbage.
(Q i9)o eYieldi ?
Ans:
Ratio iino epercentagei ofonumber qofre working ichipsoq jtore total ino ochipsqin
singlewafer.
www.testbench.in
(Q i10)o eControllabilityi ?
Ans:
Controllability imeasureso ethei abilityoto qcontrolre the iinternaloq jstatere of ithe
ocircuitqthrough primaryz inputs.u yore oThezx ability to set or reset internal nodes
from the primary inputs.
(Q i11)o eObservabilityi ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:

input is what keeps
with time!
Observability imeasureso ethei abilityoto qobservere the iinternaloq jstatere of ithe

ocircuitqthrough primaryz outputs.u yore oThezx ability to observe the value of an
internal node at the primary outputs
www.testbench.in
(Q i12)o eHowi toodrive qtestre pattern i?

The itestso egenerallyi areodriven qbyre test iprogramsoq jthatre execute iin
oAutomaticqTest Equipmentz (ATE).
@edes
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Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i13)o eHowi toodeliver qtestre data i?

Ans:
The imosto ecommoni methodofor qdeliveringre test idataoq jfromre chip iinputs
otoqinternal circuitsz underu yteste oandzx observing their outputs, is called scandesign.
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
(Q i14)o eScani chaino?

Ans:
In iscan-design,o eregistersi (flip-flopsoor qlatches)re in itheoq jdesignre are
iconnected oinqone orz moreu yscane ochains,zx which are used to gain access to
internal nodesof the chip.
VMM Tutorial
OVM Tutorial
(Q i15)o eHowi scanochain qworksre ?
Easy Labs : SV
www.testbench.in
Easy Labs : UVM

Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
Ans:
Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock
osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the
results are then shifted out to chip output pins and compared against the
expected"good machine" results.
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
(Q i16)o eStucki @ofault q?

Ans:
For ianyo ecombinationi ifoinput qorre output iisoq jpermanentlyre stuck iat
ooneqfaulteither 0z oru y1,e othenzx its called Stuck at fault.
Basic Constructs
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
OpenVera
Constructs
(Q i17)o eThei stuck-at-0o?

www.testbench.in
Switch TB
Ans:
RVM Switch TB
Model irepresentso eai signalothat qisre permanently ilowoq jregardlessre of ithe
RVM Ethernet sample ootherqsignals thatz normallyu ycontrole othezx node.
Specman E
Interview Questions
(Q i18)o eThei stuck-at-1o?

Ans:
Model irepresentso eai signalothat qisre permanently ihighoq jregardlessre of ithe
ootherqsignals thatz normallyu ycontrole othezx node.
(Q i19)o eWherei weocan qgivere DFT iconstrainoq j?

www.testbench.in
Ans:
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
In isynthesiso econstraini fileowe qcanre apply iDFToq jconstrain.
<< PREVIOUS PAGE
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input is what keeps
with time!
Search
TUTORIALS
SystemVerilog
Verification
Constructs
Interface
OOPS
Randomization
(Q i20)o eAffecti ofoDFT qconstrainre ?

Ans:
It iwillo econverti flopsointo qscanre flops iandoq j3re more ipin owillqbe addededz
tou ythee odesign.
a)SI i-o escani Input,
b)SEN i-o eScani Enableoand
c)SO i-o escani output.
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
OVM Tutorial
(Q i21)o eDifferencei betweenoflops qandre scan iflops.

Ans:
www.testbench.in
Scan iflopo econtaini flopoand qthere 2:1 imuxoq jalso,re output iof otheqmux willz
gou yintoe oflop.
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i22)o eHowi willoyou qcheckre particular istuck@faultoq j?

Ans:
the ifaulto ewhichi youowant qtore check; ioppositeoq
opassqthrough thez chainu yande oobservezx the output.
jtore
that
ifault
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i23)o eTypesi ofotest q?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
ia)o estructurali test

ib)o eparametrici test
ic)o espeedi test
OpenVera
Constructs
Switch TB
RVM Switch TB
(Q i24)o eStructurali testo?

Ans:
RVM Ethernet sample Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock
Specman E
Interview Questions
osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the
results are then shifted out to chip output pins and compared against the expected
"good machine" results.
www.testbench.in
(Q i25)o eParametrici testo?

Ans:
to iverifyo eACi andoDC qparametersre of imanufacturedoq jdevice.
ia)o eSetup/hold
ib)o eVIL,i VIH
ic)o eVOL,i VOH
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i26)o eSpeedi testo?

Ans:
www.testbench.in
To iverifyo eperformancei ofomanufactured qdevicere and itestoq jthere operating

ifrequency oofqthe chip.
(Q i27)o eTypesi ofomanufacturing qdefectre ?

Ans:
-----------------Physical iDefects:
---------------- iContamination--causingo eopeni circuits
iExtrao emetal--causingi shortocircuits
www.testbench.in
iInsufficiento edoping
iprocesso eori maskoerrors
iMetalo etracei bridges
iSlowo etransistors
---------------------Electrical ieffects:
---------------------.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
iTransistorso estucki openoor qshort

iBridgingo e(i shorts)obetween qadjacentre lines
iResistiveo eshortsi andoopens
www.testbench.in
iChangeo eini thresholdovoltage

iPowero eori Groundoshorts
(Q i28)o eUndetectablei faultso?

Ans:
The iundetectedo efaulti classoincludes qundetectedre faults ithatoq jcanre not ibe
oprovenquntestable orz ATPGu yuntestable.e oforzx example, in the gate circuitry
one pin is connected to Vcc and another gate's pin is connected to Gnd then we can
not detect stack@o and 1 fault respectively.
(Q i29)o eUncontrolledi (UC)o?

www.testbench.in
Ans:
Undetected ifaults,o ewhichi duringopattern qsimulation,re never iachieveoq jthere

value iat otheqpoint ofz theu yfaulte odetectionzx that means they are
uncontrollable.
(Q i30)o eUnobservablei (UO)o?

Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Faults iwhoseo eeffectsi doonot qpropagatere to ianoq jobservablere point.
(Q i31)o eATPGi ?
www.testbench.in
Ans:

input is what keeps
with time!
ATPG i(acronymo efori bothoAutomatic qTestre Pattern iGenerationoq jandre

Automatic iTestPattern oGenerator)qis anz electronicu ydesigne oautomationzx
method/technology used to find an input (or test) sequence that, when applied to a
digital circuit, enables testers to distinguish between the correct circuit behavior and
the faulty circuit behavior caused by defects.
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TUTORIALS
SystemVerilog
Verification
Constructs
Interface
(Q i32)o eFaulti coverageo?

Ans:
The ipercentageo eofi ALLofaults q(bothre testable iandoq juntestable)re that iare
odetectedqby thez patternu yset.
Fault iCoverageo e=i DetectedoFaults q/re Total iFaults
OOPS
Randomization
Functional Coverage
Assertion
DPI
UVM Tutorial
VMM Tutorial
(Q i33)o eTesti coverageo?

Ans:
The ipercentageo eofi allotestable qfaultsre that iareoq jdetectedre by ithe
opatternqset.
Test iCoverageo e=i DetectedoFaults q/re (Total ifaultsoq j-re Untestable iFaults)
www.testbench.in
OVM Tutorial
Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
(Q i34)o eATPGi effectivenesso?

Ans:
A imeasureo eofi theoability qofre the iATPGoq jtoolre to ieither oprovideqa testz
tou ydetecte oazx fault or prove that a test cannot be created.
iATGo eefficiencyi =o(Detected q+re Untestable iFaults)oq j/re Total iFaults
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
(Q i35)o eBISTi ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
A ibuilt-ino eself-testi (BIST)omechanism qwithinre an iintegratedoq jcircuitre (IC) iis

oaqfunction thatz verifiesu yalle oorzx a portion of the internal functionality of the
IC. It is the capability of circuit to test itself. generally on-chip circuitry is used to
apply a predetermined set of test vectors to internal sections of the circuit. Another
on-chip circuit monitors the results of the test and checks them against the stored
correct response. BIST can be extended to board-level system.
Switch TB
RVM Switch TB
RVM Ethernet sample (Q i36)o eAdvantagesi ofoBIST..!!
Ans:
Specman E
Interview Questions
Replaces iexternalo etesteri withoon-chip qcircuitry.re Avoids itheoq jtestre

generation iproblem. oItqis technologyz andu yfaulte omodelzx independent.
i
(Q i37)o eBoundaryi Scano?
Ans:
www.testbench.in
Boundary iscano eisi aomethod qforre testing iinterconnectsoq j(thinre wire ilines)
oonqprinted circuitz boardsu yore osub-blockszx inside an integrated circuit. The
Joint Test Action Group (JTAG) developed a specification for boundary scan testing
contains a description of the Boundary Scan Description Language (BSDL) was added
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
which describes the boundary-scan logic content of IEEE Std 1149.1 compliant
devices. Boundary scan is nowadays mostly synonymous with JTAG.
input is what keeps
with time!
(Q i38)o eToolsi relatedoto qDFTre from imentor.

Ans:
ATPG i&o eCompression
TestKompress
FastScan
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
DFTAdvisor
FlexTest
www.testbench.in
Memory iTest
MBISTArchitect
MacroTest
Boundary iScan
BSDArchitect
Logic iBIST
LBISTArchitect
Yield iLearningo eandi Diagnosis
YieldAssist
www.testbench.in
(Q i39)o eReference..!!
Ans:
1) iElectronico eDesigni AutomationoFor qIntegratedre Circuits iHandbook,oq jbyre
Lavagno,Martin iand oScheffer.
2) iMichaelo eL.i Bushwelloand qVishwanire D. iAgrawal,Essentialsoq jofre Electronic
iTesting oforqDigital, Memoryz andu yMixed-Signale oVLSIzx CircuitsKluwer
Academic Publishers 2000.
3) iMirono eAbramovici,i MelvinoA. qBreuer,re and iArthuroq jD.re Friedman, iDigital
oSystemsqTesting andz Testableu yDesign,e oIEEEzx Press, 1994.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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TUTORIALS
TEST YOUR UVM OVM SKILLS
SystemVerilog
(Q i40)Whato earei theodifferences qbetweenre vmm iandoq jovm/uvmre ?
Verification
Constructs
Interface
OOPS
Randomization
Functional Coverage
(Q i41)Whato eisi theoadvantage qofre uvm iagentoq j?

(Q i42)Howo emultiplei set_config_*oare qresolvedre at isameoq jhierarchyre level
iand oatqdifferent hierarchyz levelsu y?
(Q i43)Iso eiti possibleoto qconnectre multiple idriversoq jtore one isequencers o?qif
yes,z thenu yhowe o?
Assertion
(Q i44)Whato eisi theodifference qbetweenre factory iandoq jcallbacksre ?
DPI
www.testbench.in
UVM Tutorial
(Q i45)Explaino ethei mechanismoinvolved qinre TLM iports.
VMM Tutorial
OVM Tutorial
(Q i46)Whyo eTLMi fifoois qusedre ?
Easy Labs : SV
(Q i47)Howo etoi addoa quserre defined iphaseoq j?
Easy Labs : UVM

Easy Labs : OVM
(Q i48)Whato earei theoways qtore get itheoq jconfigurationre information iinside

ocomponentq?
Easy Labs : VMM
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
AVM Switch TB
VMM Ethernet sample
(Q i49)Iso eiti possibleoto qusere get_config_obj iinsideoq jare sequence iclass? o

www.testbench.in
(Q i50)Whato eisi theodifference qbetweenre create iandoq jnewre method i?

Verilog
Verification
Verilog Switch TB
Basic Constructs
(Q i51)Whato eisi virtualosequencer q?re Explain ibyoq jwritingre example.

(Q i52)Howo eai sequenceois qstartedre ?
(Q i53)Explaino eendi ofotest qmechanism.re
(Q i54)When/howo ethei stop()omethod qisre called i?
OpenVera
Constructs
Switch TB
RVM Switch TB
www.testbench.in
(Q i55)Whato eisi port/import/exporto?

(Q i56)Whicho ephasei isotop qdown,re and iwhichoq jphasere is ibottom oup?
RVM Ethernet sample (Q i57)Ino ewhichi phaseomethod, qsuperre method iisoq jrequiredre to icall.What
oifqthe superz isu ynote ocalledzx ?
Specman E
Interview Questions
(Q i58)Explaino ethei differentophases qandre what iisoq jtheirre purpose.

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i59)Howo etoi useofactory qoverridere a isequenceoq j?re

www.testbench.in
(Q i60)Explaino ehowi scoreboardois qimplemented.re

(Q i61)Whato eisi theouse qofre subscriber i?
(Q i62)Explaino eabouti run_test().
(Q i63)Howo einterfacei isopassed qtore component.
http://testbench.in/IQ_40_TEST_YOUR_UVM_OVM_SKILLS.html[9/26/2012 3:05:04 PM]
Index
Questions
Questions 2
Skills 1
Skills 2
Skills 3
Skills 4
10
11
12
13
14
15
16
17
1
2
3
4
Test Your Uvm Ovm
Skills
(Q i64)Whato eisi theodifferent qb/wre active iagentoq jandre passive iagent o?

input is what keeps
with time!
www.testbench.in
(Q i65)Explaino ehowi aointerrupt qsequencere is iimplemented.

(Q i66)Explaino ehowi layeredosequencers qarere implemented.
(Q i67)Howo etoi changeothe qverbosityre level iofoq jlogre messages ifrom
ocommandqline ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i68)Howo etoi setoverbosity qlevelre to ioneoq jparticularre component i?

(Q i69)Howo etoi fillothe qgapre b/w idifferentoq jobjections?
www.testbench.in
(Q i70)Whato eisi theouse qofre uvm_event i?

(Q i71)Howo etoi connectomultiple qsequencersre to ioneoq jdriverre ?
(Q i72)Whato eisi returnedoby qget_type_name()?
(Q i73)Howo etoi useoset_config_* qforre setting ivariablesoq jofre sequence i?
(Q i74)Foro edebuggingi purpose,ohow qtore print imessagesoq jthatre indicates ithe
ocomponentsqphase ?
www.testbench.in
(Q i75)Whato eisi theodisadvantage qifre sequence iisoq jregisterdre to isequencer

ousingqutility macrosz ?Ifu ysequencee oiszx not registered with sequencer, then
how to invoke the sequence execution ?
(Q i76)Whato eisi theouse qofre uvm_create_random_seed i?
(Q i77)Whato eisi theodifference qb/wre starting
idefault_sequence oandqsequence.start() method.z
iaoq
jsequencere
using
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i78)Io edon<92>ti wantoto qregisterre a isequenceoq jtore sequencer. iWhat

oisqthe alternatez macrou ytoe ouvm_sequence_utils()zx macro ?
(Q i79)Explaino ehowi UVMocallbacks qworkre ?
www.testbench.in
(Q i80)o eWhati isothe qdifferencere b/w im_sequenceroq jandre p_sequencer i?
www.testbench.in
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uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Makefile
Current file: README.txt
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////s www.testbench.in s////
////ss////
////sUVM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
For any Questions
Contactgopi@testbench.in
http://testbench.in/uvm_sequence_10_README.txt.html[9/26/2012 3:05:25 PM]
uvm_sequence_11
Code Browser Pages:

Files in
uvm_sequence_11.tar
driver.sv
Makefile
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////sUVM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
For any Questions
http://testbench.in/uvm_sequence_11_README.txt.html[9/26/2012 3:05:29 PM]
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////s
www.testbench.in
s////
////s
s////
////s
VMM Tutorial
s////
////s
s////
////s
gopi@testbench.in
s////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
ìfndef GUARD_PACKET
`define GUARD_PACKET
class Packet extends vmm_data;
static vmm_log log = new("Packet","Class");
rand bit [7:0] length;
rand bit [7:0] da;
rand bit [7:0] sa;
rand bit [7:0] data[];//Payload using Dynamic array,size is generated on the fly
rand byte fcs;
constraint payload_size_c { data.size inside { [1 : 6]};}
function new();
endfunction:new
virtual function vmm_data allocate();
Packet pkt;
pkt = new();
return pkt;
virtual function string psdisplay(string prefix = "");
int i;
$write(psdisplay, " %s packet #%0d.%0d.%0d\n", prefix,this.stream_id, this.scenario_id, this.data_id);
$write(psdisplay, " %s%s da:0x%h\n", psdisplay, prefix,this.da);
$write(psdisplay, " %s%s sa:0x%h\n", psdisplay, prefix,this.sa);
$write(psdisplay, " %s%s length:0x%h (data.size=%0d)\n", psdisplay, prefix,this.length,this.data.size());
$write(psdisplay, " %s%s data[%0d]:0x%h", psdisplay, prefix,0,data[0]);
if(data.size() > 1)
$write(psdisplay, " data[%0d]:0x%h", 1,data[1]);
if(data.size() > 4)
$write(psdisplay, " .... ");
if(data.size() > 2)
$write(psdisplay, " data[%0d]:0x%h", data.size() -2,data[data.size() -2]);
if(data.size() > 3)
$write(psdisplay, " data[%0d]:0x%h", data.size() -1,data[data.size() -1]);
http://testbench.in/Packet.sv[9/26/2012 3:05:42 PM]
$write(psdisplay, "\n %s%s fcs:0x%h \n", psdisplay, prefix, this.fcs);

endfunction
virtual function vmm_data copy(vmm_data to = null);
Packet cpy;
if (to == null)
cpy = new;
else
if (!$cast(cpy, to))
begin
`vmm_fatal(this.log, "Attempting to copy to a non packet instance");
copy = null;
return copy;
end
cpy.da = this.da;
cpy.sa = this.sa;
cpy.length = this.length;
cpy.data = new[this.data.size()];
foreach(data[i])
begin
cpy.data[i] = this.data[i];
end
cpy.fcs = this.fcs;
copy = cpy;
endfunction:copy
virtual function bit compare(input vmm_data to,output string diff,input int kind = -1);
Packet cmp;
compare = 1; // Assume success by default.
diff = "No differences found";
if (!$cast(cmp, to))
begin
`vmm_fatal(this.log, "Attempting to compare to a non packet instance");
compare = 0;
diff = "Cannot compare non packets";
return compare;
end
if (this.da != cmp.da)
begin
diff = $psprintf("Different DA values: %b != %b", this.da, cmp.da);
compare = 0;
return compare;
end
if (this.sa != cmp.sa)
begin
diff = $psprintf("Different SA values: %b != %b", this.sa, cmp.sa);
compare = 0;
return compare;
end
if (this.length != cmp.length)
begin
diff = $psprintf("Different LEN values: %b != %b", this.length, cmp.length);
compare = 0;
return compare;
end
foreach(data[i])
if (this.data[i] != cmp.data[i])
begin
diff = $psprintf("Different data[%0d] values: 0x%h != 0x%h",i, this.data[i], cmp.data[i]);
compare = 0;
return compare;
end
if (this.fcs != cmp.fcs)
begin
diff = $psprintf("Different FCS values: %b != %b", this.fcs, cmp.fcs);
compare = 0;
return compare;
end
endfunction:compare
virtual function int unsigned byte_pack(
ref logic [7:0] bytes[],
input int unsigned offset =0 ,
input int kind = -1);
byte_pack = 0;
bytes = new[this.data.size() + 4];
bytes[0] = this.da;
bytes[1] = this.sa;
bytes[2] = this.length;
foreach(data[i])
bytes[3+i] = data[i];
bytes[this.data.size() + 3 ] = fcs;
byte_pack = this.data.size() + 4;
virtual function int unsigned byte_unpack(
const ref logic [7:0] bytes[],
input int unsigned offset = 0,
input int len = -1,

input int kind = -1);
this.da = bytes[0];
this.sa = bytes[1];
this.length = bytes[2];
this.fcs = bytes[bytes.size() -1];
this.data = new[bytes.size() - 4];
foreach(data[i])
this.data[i] = bytes[i+3];
return bytes.size();
endclass
èndif
vmm_record_playback
Code Browser Pages:

Files in
record_playback.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////sVMM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
For any Questions
http://testbench.in/vmm_record_playback_README.txt.html[9/26/2012 3:05:52 PM]
vmm_opts
Code Browser Pages:

Files in
vmm_opts.tar
filelist
vmm_opts_test.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////sVMM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
For any Questions
http://testbench.in/vmm_opts_README.txt.html[9/26/2012 3:05:57 PM]
ovm_transaction
Code Browser Pages:

Files in
ovm_transaction.tar
filelist
Packet.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////sOVM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
For any Questions
http://testbench.in/ovm_transaction_README.txt.html[9/26/2012 3:06:03 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
Current file: driver.sv
Makefile
README.txt
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s UVM Tutorial s////
////s gopi@testbenh.in s////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
// Provide implementations of virtual methods such as get_type_name
and create
// Constructor
endfunction
taskrun ();
foreverbegin
$display("0: Driving Instruction",$time,req.inst.name());
#10;
// seq_item_port.put(esp); responce needs to be sent back to
sequence
end
endtask
endclass
http://testbench.in/uvm_sequence_10_driver.sv.html[9/26/2012 3:06:52 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Current file: Makefile
README.txt
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
IFILES = driver.svsequence_item.svsequencer.svsequence.sv
FILES = testcase.sv
UVM_FLAGS = +incdir+${UVM_HOME}/src ${UVM_HOME}/src/uvm_pkg.sv
VCS_FLAGS = -sverilog +plusarg_save -timescale=1ns/1ns
vcs:simv
simv -l simv.log
simv: ${FILES}${IFILES}
@if [ ! -e ${UVM_HOME}/src/uvm_pkg.sv ];then \
echo
"*******************************************************";\
echo "Environemnt varible UVM_HOME is not set or points to
incorrect path"; \
echo
"*******************************************************";\
fi
vcs ${UVM_FLAGS}${VCS_FLAGS}${FILES}
questa:${FILES}${IFILES}
echo
"*******************************************************";\
incorrect path"; \
echo
"*******************************************************";\
fi
qverilog ${UVM_FLAGS}+incdir+. ${FILES}-R
ius:${FILES}${IFILES}
echo
"*******************************************************";\
incorrect path"; \
echo
"*******************************************************";\
fi
irun ${UVM_FLAGS}+incdir+. ${FILES}
DIR = $(shellbasename `pwd`)
tar:clean
cd ..; \
tar cvf ${DIR}.tar ${DIR}
clean:
@rm -rf simv* csrc* *.log *.key core* *.vpd *.vcd
@rm -rf *~ .vcsmx_rebuild vc_hdrs.h DVEfiles
@rm -rf work vsim.wlf INCA_libs
http://testbench.in/uvm_sequence_10_Makefile.html[9/26/2012 3:06:56 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Makefile
README.txt
Current file: sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
randinst_t inst;
super.new(name);
endfunction
endclass
http://testbench.in/uvm_sequence_10_sequence_item.sv.html[9/26/2012 3:07:00 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Makefile
README.txt
sequence_item.sv
Current file: sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
endfunction
endclass
http://testbench.in/uvm_sequence_10_sequencer.sv.html[9/26/2012 3:07:03 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Makefile
README.txt
sequence_item.sv
sequencer.sv
Current file: sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
integernum_inst =4;
instruction req;
ùvm_field_int(num_inst,UVM_ALL_ON)
super.new(name);
endfunction
virtualtaskbody();
uvm_report_info(get_full_name(),$psprintf("Num of transactions
0",num_inst),UVM_LOW);
end
endtask
endclass
http://testbench.in/uvm_sequence_10_sequence.sv.html[9/26/2012 3:07:07 PM]
uvm_sequence_10
Code Browser Pages:

Files in
uvm_sequence_10.tar
driver.sv
Makefile
README.txt
sequence_item.sv
sequencer.sv
sequence.sv
Current file: testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
ìnclude"uvm.svh"
importuvm_pkg::*;
ìnclude"sequence_item.sv"
ìnclude"sequencer.sv"
ìnclude"sequence.sv"
ìnclude"driver.sv"
moduletest;
initialbegin
sequencer.build();
driver.build();
sequencer.print();
fork
begin
run_test();
end
join
end
endmodule
http://testbench.in/uvm_sequence_10_testcase.sv.html[9/26/2012 3:07:11 PM]
uvm_sequence_11
Code Browser Pages:

Files in
uvm_sequence_11.tar
Current file: driver.sv
Makefile
README.txt
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
// Provide implementations of virtual methods such as get_type_name
and create
// Constructor
endfunction
taskrun ();
foreverbegin
$display("0: Driving Instruction",$time,req.inst.name());
#10;
// seq_item_port.put(esp); responce needs to be sent back to
sequence
end
endtask
endclass
http://testbench.in/uvm_sequence_11_driver.sv.html[9/26/2012 3:07:15 PM]
uvm_sequence_11
Code Browser Pages:

Files in
uvm_sequence_11.tar
driver.sv
Current file: Makefile
README.txt
sequence_item.sv
sequencer.sv
sequence.sv
testcase.sv
IFILES = driver.svsequence_item.svsequencer.svsequence.sv
FILES = testcase.sv
UVM_FLAGS = +incdir+${UVM_HOME}/src ${UVM_HOME}/src/uvm_pkg.sv
VCS_FLAGS = -sverilog +plusarg_save -timescale=1ns/1ns
vcs:simv
simv -l simv.log
simv: ${FILES}${IFILES}
echo
"*******************************************************";\
incorrect path"; \
echo
"*******************************************************";\
fi
vcs ${UVM_FLAGS}${VCS_FLAGS}${FILES}
questa:${FILES}${IFILES}
echo
"*******************************************************";\
incorrect path"; \
echo
"*******************************************************";\
fi
qverilog ${UVM_FLAGS}+incdir+. ${FILES}-R
ius:${FILES}${IFILES}
echo
"*******************************************************";\
incorrect path"; \
echo
"*******************************************************";\
fi
irun ${UVM_FLAGS}+incdir+. ${FILES}
DIR = $(shellbasename `pwd`)
tar:clean
cd ..; \
tar cvf ${DIR}.tar ${DIR}
clean:
@rm -rf simv* csrc* *.log *.key core* *.vpd *.vcd
@rm -rf *~ .vcsmx_rebuild vc_hdrs.h DVEfiles
@rm -rf work vsim.wlf INCA_libs
http://testbench.in/uvm_sequence_11_Makefile.html[9/26/2012 3:07:19 PM]
uvm_sequence_11
Code Browser Pages:

Files in
uvm_sequence_11.tar
driver.sv
Makefile
README.txt
sequence_item.sv
sequencer.sv
Current file: sequence.sv
testcase.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
classseq_a extendsuvm_sequence #(instruction);
instruction req;
functionnew(stringname="seq_a");
super.new(name);
endfunction
ùvm_sequence_utils(seq_a,instruction_sequencer)
virtualtaskbody();
repeat(4)begin
end
endtask
endclass
classseq_b extendsuvm_sequence #(instruction);
instruction req;
functionnew(stringname="seq_b");
super.new(name);
endfunction
ùvm_sequence_utils(seq_b,instruction_sequencer)
virtualtaskbody();
lock();
repeat(4)begin
end
unlock();
endtask
endclass
classseq_c extendsuvm_sequence #(instruction);
instruction req;
functionnew(stringname="seq_c");
super.new(name);
endfunction
ùvm_sequence_utils(seq_c,instruction_sequencer)
virtualtaskbody();
repeat(4)begin
ùvm_do_with(req,{inst ==POP_C;});
end
endtask
endclass
seq_a s_a;
seq_b s_b;
seq_c s_c;
super.new(name);
endfunction
uvm_sequence_11
virtualtaskbody();
fork
ùvm_do(s_a)
ùvm_do(s_b)
ùvm_do(s_c)
join
endtask
endclass
vmm_record_playback
Code Browser Pages:

Files in
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s VMM Tutorial s////
////ss////
////s gopi@testbench.ins////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
ìnclude"vmm.sv"
README.txt
Current file:
record_playback.sv
////////////////////////////////////////////////////////
//// Transaction implemntation /////
////////////////////////////////////////////////////////
classtrans extendsvmm_data;
typedefenumbit{BAD_FCS=1'b0,GOOD_FCS=1'b1}kind_e;
randbit[47:0]DA;
randbit[47:0]SA;
randintlength;
randkind_e kind;
`vmm_data_member_begin(trans)
`vmm_data_member_scalar(DA,DO_ALL)
`vmm_data_member_scalar(SA,DO_ALL)
`vmm_data_member_scalar(length,DO_ALL)
`vmm_data_member_enum(kind,DO_ALL)
`vmm_data_member_end(trans)
endclass
// for declaring trans_channel
`vmm_channel(trans)
// for declaring trans_atomic_gen
`vmm_atomic_gen(trans,"Gen")
////////////////////////////////////////////////////////
////Record/Playback demo example ///////
////////////////////////////////////////////////////////
programmain();
trans tr;
trans_atomic_gen gen =new("Atomic Gen",1);
bitsuccess;
// This is the producer logic.
// Transactions are produced from Atomic generator in RECORD mode.
// Transactions are produced from recorded file in PLAYBACK mode.
initial
begin
if($test$plusargs("RECORD"))
begin
$display(" RECORDING started ");
gen.start_xactor();
end
elseif($test$plusargs("PLAYBACK"))
begin
$display(" PLAYBACK started ");
tr =new();
if(!success)
$display(" Failed to playback
Trans_recordes.tr");
end
else
$display(" give +RECORD or +PLAYBACK with simulation
command");
end
http://testbench.in/vmm_record_playback_record_playback.sv.html[9/26/2012 3:07:28 PM]
vmm_record_playback
// This is consumer logic.

initial
repeat(3)
begin
#10;
tr.display();
end
endprogram
http://testbench.in/vmm_record_playback_record_playback.sv.html[9/26/2012 3:07:28 PM]
vmm_opts
vmm_opts_test.sv
Code Browser Pages:

Files in
vmm_opts.tar
Current file: filelist
README.txt
vmm_opts_test.sv
http://testbench.in/vmm_opts_filelist.html[9/26/2012 3:07:32 PM]
vmm_opts
Code Browser Pages:

Files in
vmm_opts.tar
filelist
README.txt
Current file:
vmm_opts_test.sv
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////s VMM Tutorial s////
////ss////
////s gopi@testbench.ins////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
ìnclude"vmm.sv"
classmy_env extendsvmm_env;
vmm_opts op =new();
integerfoo1;
stringfoo2;
bitfoo3;
super.gen_cfg();
`vmm_note(log,"START OF GEN_CFG ");
foo1 =vmm_opts::get_int("foo1",10,"Help for the option
foo1: pass any integer between 0 to 100");
foo2 =vmm_opts::get_string("foo2","default_string","Help
for the option foo2: pass any string");
foo3 =vmm_opts::get_int("foo3","Help for the option foo3:
just use foo3 to enable ");
`vmm_note(log,$psprintf("\n Run time Options\n foo1 :
0 \n foo2 : \n foo3 : 0 \n",foo1,foo2,foo3));
`vmm_note(log,"END OF GEN_CFG ");
endfunction
endclass
programmain();
initial
begin
my_env env;
env =new();
env.run();
end
endprogram
http://testbench.in/vmm_opts_vmm_opts_test.sv.html[9/26/2012 3:07:35 PM]
ovm_transaction
Code Browser Pages:

Files in
ovm_transaction.tar
filelist
Current file: Packet.sv
README.txt
////////////////////////////////////////////////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////ss////
////sOVM Tutorials////
////ss////
////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s////
////////////////////////////////////////////////
ìfndefGUARD_PACKET
`defineGUARD_PACKET
ìnclude"ovm.svh"
importovm_pkg::*;
randbit[7:0]length;
randbit[7:0]da;
randbit[7:0]sa;
randbit[7:0]data[];
randbytefcs;
super.new(name);
endfunction:new
fcs =8'b0;
else
fcs =8'b1;
fcs =cal_fcs();

integeri;
byteresult ;
result =0;
result =result ^da;
result =result ^sa;
returnresult;
endfunction:cal_fcs
packer.pack_field_int (length,$bits(length));
foreach(data[i])
http://testbench.in/ovm_transaction_Packet.sv.html[9/26/2012 3:07:40 PM]
ovm_transaction
endfunction:do_pack
intsz;
data.delete();
data=new[length];
foreach(data[i])
endclass:Packet
/////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
moduletest;
initial
repeat(10)
if(pkt1.randomize)
begin
pkt1.print();
$display("Size of pkd bits 0",pkdbytes.size());
pkt2.print();
else
$display(" *** Something went wrong in Packing or
Unpacking or compare *** \n \n");
end
else
endmodule
èndif
http://testbench.in/ovm_transaction_Packet.sv.html[9/26/2012 3:07:40 PM]

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