BULETINUL INSTITUTULUI POLITEHNIC DIN IAI

Publicat de
Universitatea Tehnic Gheorghe Asachi din Iai
Tomul LXI (LXV), Fasc. 1, 2015
Secia
AUTOMATIC i CALCULATOARE

STUDY OF METASTABILITY IN DIGITAL SYSTEMS

BY

CLIN MIRCEA MONOR, MIHAI TIMI*

and ALEXANDRU VALACHI
Gheorghe Asachi Technical University of Iai, Romnia,
Faculty of Automatic Control and Computer Engineering

Received: January 25, 2015

Accepted for publication: February 15, 2015

Abstract. In this paper, the authors propose a study of the metastability in

digital systems. We develop a comprehensive study for the metastability and
propose a new algorithm in order to reduce it in the digital systems. Our proposed
idea is to add a regular two-flop synchronizer. Also an experimental system and
method for measuring synchronizers and metastable flip-flops are described. The
regular synchronizer is useful for communications between asynchronous clock
domains, while the other synchronizers can provide higher bandwidth
communications between synchronous systems.
Key words: metastability, digital systems, finite state machine, asynchronous
inputs synchronization, hazard in digital systems.
2010 Mathematics Subject Classification: 06E30, 49M27, 94C05.

1. Introduction
Fault-free digital circuits may work incorrectly when asynchronous
inputs have critical timing combinations that generate metastability operation.
This mode of failure is often not noticed in the analysis of the digital system
design. In this paper, the authors propose a study in the domain of metastable
*

Corresponding author; e-mail: mtimis@tuiasi.ro

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Clin Mircea Monor et al.

timing behavior and identify their relevance to digital system design and
reliability. Also the authors describe and evaluate a number of techniques for
reducing the probability of metastability appearance.
Two separate settling time constants are shown for a metastable flipflop, confirming earlier results of (Kleeman, 2007; Yarbrough, 1997).
The errors are caused by the undefined response time of a flip-flop as it
recovers from its metastable state. To obtain their frequency, the timing diagram
of the flip-flops has been analyzed and the probability distribution of the
anomalous response times has been measured. The measurement technique
presented may be used for any type of input synchronizer. One well-known
method of reducing failure probability is presented by (Pechoucek, 2009a).
2. Synchronization of the Asynchronous Inputs
2.1. FSM Input Synchronization Using DFF

First, we consider the design from Fig. 1:

x

x
D

asynchronous

synchronous
DFF

OUT
FSM

Ck

Fig. 1 General view synchronization inputs design.

The timing analysis diagram is shown in Fig. 2:

T

T/2
Ck
signal
X

b
FSM Ck

Fig. 2 General view Timing diagram signals.

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From the timing signals diagram it can be observed that a set-up time
(ts-u) is provided and it is greater than the half of the period T: (T/2).
Analyzing the previous research papers (Pechoucek, 2009b; Kleeman et
al., 1987; Willie& Jerome, 2008), we can say that there is possible to lose some
X input signals.
Beside of this, we propose a new design collection and
synchronization inputs, presented in Figs. 3a and 3b.
X

D
RS latch

OUT
CBB D

FSM

Ck

Fig. 3a Stretcher synchronization inputs.

TCK

Ck

(1)

(2)

(3)

X
X = R
Fig. 3b Timing diagram with stretcher signals (1), (3) also with lost signal cases.

Lets consider the input signal X in the (2) state, as we can observe that
impulse signal appears before the latch stretch device, this signal will not be
taken into consideration.
As it can be observed in the timing diagram from Fig. 2b, if the (2) state
neighbor signal has the negative edge delayed with less than 2 TCk , we can
affirm that signal cannot be stretched.

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Clin Mircea Monor et al.

We made the assumption that set-up time - t s _ u is equal with hold time
- th based on the clock period T.
2.2. Metastable Timing and Synchronization Methods

One of the important functions for synchronization is to protect the

FSM from the mestastability effects caused by the changes of the input signals
during the clocking activation (command edge).
In general, the metastability in digital systems with feedbacks
represents an event with very low probability to be produced, but when it
appears, the system can have a strange behaviour for a short time.
There are no methods to reduce to zero the possibility of occurrence for
the metastability in digital systems.
Fig. 4 represents the time when the metastability can occur.

Fig. 4a Mechanical metastability.

metastable
state
H
(X)
L
stable state

tm
Fig. 4b FSM metastability with no importance for X state.

Bul. Inst. Polit. Iai, t. LXI (LXV), f. 1, 2015

55

metastable
state
H
(X)
L
stable state

tm
Fig. 4c FSM metastability with oscilation state.

tm represents the get out timing from the metastable state.

Before the system enters into the metastable state, the changing variable
is on a stable one, means 1 logic or 0 logic.
After the system gets out from the metastable state, we can consider the
output of the DFF, it has an unknown value for example, the SETx command
does not cause the change of X in 1 logic, etc.
We can say that the digital schematic proposed in Fig. 1 can pass
through a metastable state.

Ck

Fig. 5 Metastability on synchronization.

In Fig. 6, we proposed a new method of reducing the probability of

metastable states with two synchronization blocks.

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Clin Mircea Monor et al.

block 1
X

block 2

DFF
Ck

Q1

OUT

DFF

FSM

Fig. 6 New method for reducing metastability.

The eq. (1) represents the MTBF(Mean Time Between Failure) formula
(Tinder, 2000):
(T

MTBF =

) /

e CK s _ u
sec
T0 f CK f D

(1)

where: TCK the clock period is nsec; f CK the clock frequency in MHz; t s _ u
the set-up time in nsec; f D the average change number for the input variable
per second, Hz; (n sec) and T0 (sec) are provided by the DFF manufacturers.
We can consider the following inequality:

f CK >> f D

(2)

In order to have reasonable values for the DFF MTBF, it is necessary to use
high speed circuits like 74HCxx, 74Fxxx or 74Asxx, (Tinder, 2000; Coner, 1995).

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Bul. Inst. Polit. Iai, t. LXI (LXV), f. 1, 2015

For these kind of DFF circuits, 0.3n sec , T0 1 sec .

When we use low frequencies, we obtained the following relations:

MTBF 1010 sec 317 years

(3)

The relation (3) is available in case of using a smaller value for the
set_up time ( t s _ u ).
The modern technologies use high frequency rates, so it can be
observed that only one synchronization DFF is not enough.
A study about the anomalous research behavior of input synchronizers
can be found in (Pechoucek, 2009b; Roth, 1999; De Micheli, 1994). The errors
are caused by the undefined response time of a flip-flop as it recovers from its
metastable state. To obtain their frequency, the timing diagram of the flip-flops
has been analysed and the probability distribution of the anomalous response
times has been measured. As an example, maximum response time of SN74S74
is estimated on the basis of a set of statistical measurements.
The measurement technique presented may be used for any type of
input synchronizer. In this case, we propose to use one two level synchronizer
like in Fig. 8.

Ck

t m
Q1

X""

(1)

(2)

Fig. 7 Synchronization without divider.

From the Fig. 7, we can affirm that metastability disappears after

tm time.

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Clin Mircea Monor et al.

Analysing the diagram from Fig. 7, we can conclude that the system
with two synchronization levels significantly reduces the probability of
metastability. Fig. 7 uses the proposed schematic design with only two
synchronization levels.
Fig. 7 uses the proposed schematic design with timing diagram which
shows the metastability produced in the state (1) level (without division).
The changes for the X input variable are well done in (2nd) level (in
(1st) level we are not so sure that it was produced).
From our simulations, we observed that the probability of metastability
appearance decreases with the increase of the CK period clock system. Thats
why we proposed to use a divider by 2, like in Fig. 5.
We observed also if tm < TCK the 2nd level cannot present
metastability.
The MTBF formula from (1) was deducted from our simulation
environment experiments and test cases.
We can also affirm that if the proposed method doesnt satisfy the
conditions, there can be use other methods as:
changes the divider by 2 with one of divider by 4;
usage of a synchronizer with many levels with or without clock divider.
The performance study of two synchronization schemes was done also
by (Willie & Jerome, 2008; Roth, 1999). One scheme uses a fixed-period clock
with the allowable resolution time of the synchronizing flip-flop being one
clock period, the other scheme uses a clock with extensible clock-pulse
recurrence time and a special flip-flop with an additional output, M, which is
asserted whenever the flip-flop is in the metastable state. By asserting the pause
input to the clock, clock-pulse generation is inhibited. The M outputs of the
rank of flip-flops are collectively ORed to drive the pause input of the clock,
thus pausing clock-pulse generation when one or more of them is in the
metastable state. A system using the first scheme fails when conflicting actions
are taken by its components, owing to inconsistent interpretation of the outputs of
the flip-flops that are in the metastable state. In the second scheme, a system fails
when the execution time exceeds a specified upper bound, owing to extension in
clock pulse recurrence times. If the path delays from the M outputs to the pause
input of the disabled clock are small, the second scheme performs better.
As a general conclusion, the system performance degrades
exponentially as the delays increase.
3. Conclusions
Based on previously researches (Pechoucek, 2009a; Pechoucek, 2009b;
Yarbrough, 1997; Willie & Jerome, 2008) the paper presents the available
methods in order to reduce the mestability effect in digital circuits.

Bul. Inst. Polit. Iai, t. LXI (LXV), f. 1, 2015

59

After a brief exposure of the mestastability reducing methods, the

authors, through the proposed example, show the reduction of the
implementation cost using standard logical circuits DFF.
The authors show that when if the presented method is not enough in
order to reduce the metastability effect, there are another methods, like:
changes the divider by 2 with one of 4;
use of a synchronizer with many levels with or without clock divisor.
Balanced, the proposed algorithms proved to be very useful in reducing
the metastability in digital systems. However, the results presented in this paper
show that methods used to reduce the effect of the functional metastability in
digital systems can be efficiently and effectively applied also to implement
digital systems in metastable-robust self-timed circuit synthesis from live safe
simple signal transition graphs (Chung & Kleeman, 2014).

REFERENCES
Chung E.G.Y., Kleeman L., Metastable-Robust Self-Timed Circuit Synthesis from Live
Safe Simple Signal Transition Graphs. IEEE Advanced Research in
Asynchronous Circuits and Systems, Proceedings of the International
Symposium, Salt Lake City, UT, 2014.
Coner D.J., Digital Logic and State Machine Design. 3rd rd. Sounders College
Publishing, Forth Worth, TX, 1995.
De Micheli G., Synthesis and Optimisation of Digital Circuits. Ed. Mc. Graw-Hill,
NewYork, 1994.
Kleeman L., Cantoni A., On the Unavoidability of Metastable Behaviour in Digital
Systems. IEEE Trans on Computing, C-36, 1, 109112, 1987.
Kleeman L., Design & Test of Computers. IEEE, 4, 6, 2007.
Pechoucek M., Decomposition of Boolean Functions Specified by Cubes. Computers,
IEEE Transactions on, C-25, 2, 2009a.
Pechoucek M., Anomalous Response Times of Input Synchronizers Computers. IEEE
Transactions on, C-25, 2, 2009b.
Roth C.H., Fundamentals of Logic Design. West Publishing Company, 148172, 1999.
Tinder F.R, Engineering Digital Design. Academic Press www.academicspress.com,
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Willie Y.-P. Lim, Jerome R. Cox, Clocks and the Performance of Synchronisersx; MIT.
Laboratory for Computer Science, Cambridge, USA; Cox, Jerome R.MIT,
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Yarbrough J.M., Digital Logic Applications and Design. West Minneapolis/St. Paul,
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STUDIU PRIVIND REDUCEREA EFECTELOR

METASTABILITII
N SISTEMELE DIGITALE
(Rezumat)
n lucrarea prezent, autorii prezint o metod nou de reducere a efectelor
metastabilitii n sistemele logice digitale. O important funcie a sincronizrii este de a
proteja sistemul de metastabiliti cauzate de modificarea variabilei de intrare pe timpul
activitii clock-ului (frontul de comand). Metastabilitatea este un eveniment cu
probabilitatea foarte mic, dar care se poate produce, fiind o ,,problem n sistemele cu
reacie. Consultnd literatura de specialitate se poate trage concluzia c nu exist
metode de a reduce la zero probabilitatea - de micorare a acesteia.
Pentru exemplul ales, se realizeaz o descriere detailat a sintezei i
implementrii.