An FPGA Prototype for a Multiplierless FIR Filter

Built Using the Logarithmic Number System

Peter Lee,
University of Kent at Canterbury,
Canterbury, Kent,
CT2 7NT

Abstract
This paper describes the development of a prototype 64-tap
multiplierless FIR filter based on the Logarithmic Number System
(LNS). The circuit has been implemented and tested using a single
Xilinx X64C64 device with external coefficient memory, data memory,
ADC and DAC. The filter samples at 14KHz and runs at a rate of
895KHz (64 x 14KHz). This architecture is suitable for implementation
using custom VLSI and can provide a compact, low-power solution to a
number of simple filtering problems. It can also be expanded or cascaded
to produce higher orderfilters.

1. Introduction
There are a number of applications, such as digital hearing aids, where the
requirement for low power digital signal processing precludes the use of standard DSP
chips and techniques. For such applications a number of alternative solutions have
been considered. One such approach is to use the Logarithmic number system (LNS)
which makes it possible to develop multiplierless filter structures [1,2,3]. This paper
presents a novel architecture for a generic multiplierless FIR filter which uses both
linear and logarithmic arithmetic and describes the implementation of a prototype
Log-filter using a Xilinx FPGA. It begins with a brief overview of the LNS and
includes an analysis of the performance of the Log-filter compared with equivalent
linear and floating point solutions.

2. The Logarithmic Number System

In the logarithmic number system a binary number x is used to represent the
exponential function
y = 2 x.
Or

x = Log2y.

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For signal processing applications the major advantages of using the LNS are:

(i)

Multiplication of two linear numbers is achieved by addition of their

exponents; division is achieved by subtraction. For example the product P of
two binary numbers A and B can simply be calculated by summing the
exponents of the two numbers.
if

A = 2 xx

B = 2x2

then

P = A 9 B = (2x0 ~ (2x2) = 2 (x~+x2)

This property can be used to develop multiplierless filter architectures.

(ii)

If signals have a large dynamic range but the overall system can tolerate a lower
relative accuracy (or signal to noiSe ratio) they can be represented in the LNS
using fewer bits. Bit reduction is usually achieved by using a piecewise linear
approximation to the exponential function [4,5].

For some applications (i) and (ii) can result in a significant reduction in overall power
consumption. Unfortunately a major disadvantage in using the LNS is that the
process of linear addition (and subtraction) is both difficult and approximate. Addition
in the LNS is generally achieved by using the following approximation [5,6]:
S=A+B
is replaced by

S = A(1 + B/A)

where S = Sum and A and B are two numbers in the LNS. The factors (1 + B/A) are
usually stored in some form of look-up table or PLA. Although a considerable
amount of work has been done to minimise the hardware overhead required to
implement this function [4,5] this drawback has limited the use of the LNS in many
practical systems. However for the special case of a generic FIR filter it is possible to
develop an efficient solution based on the LNS..

3. A Generic FIR Filter Architecture

The basic architecture of a linear phase FIR filter is shown in Figure 1. It evaluates
the following expression:
i=In

Dout(n) = aid[n-i]
i=0
By simply placing Log-to-Linear and Linear-to-Log converters before the input and
output of the filter it is possible build such filter where all the arithmetic functions
are performed using the LNS.

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Ain ~

Din~I

||

DataRegister

~out

= Multiplier
= Accumulator

Aout
Fig 1. Generic FIR Filter

nin_~~

DataRegister
dO

=Accumulator

[dl

:3

~i ~
out
Fig 2. EnhancedLog-FIRstructure

]dn

306
However, for such Log-filters another "mixed" approach which uses both the LNS
and linear-binary arithmetic is more efficient. Consider the filter shown in Figure 2.
The products aix i are still calculated using the LNS, But now the sum of products is
calculated by first translating each product aixi back into the linear-binary domain and
then using a simple accumulator to calculate the sum of products. This removes the
requirement for a look-up table which would be needed to perform addition in the
LNS. Furthermore the final output of the FIR is already in a linear-binary format
which can be sent directly to a standard DAC.
By using this new mixed architecture, it is possible to build a multiplierless FIR
filter where multiplication is performed in the logarithmic domain and addition is
performed in the linear domain. This mixed approach may also be used in applications
other than in the design of FIR filters.

4. Filter

Design

A prototype 64-tap FIR filter was used to investigate the properties and
performance of the Log-filter. This architecture was chosen because of its simplicty
and linear phase characteristic. Before building the prototype a number of software
simulations were performed using MATLAB to make a comparison between the Logfilter and equivalent binary fixed-point and floating point filters. A number of different
compression ratios were tried to observe the effect on the Log-filter characteristics. A
compression from 12 to 10 bits was finally chosen because this most closely matched
CompositeLPF Response

-50

-100

Log-FIR

--- = Binary-FIR
.... Real-FIR

-150

~ i il i ~ i! !i il

"

-200

i.i_

-250

-300

::~ 'I;

50

100

150

200

250

300

350

400

norm~ised~equency
Fig 3. Log-Filter response Impulse Function = 1024

450

500

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CompositeLPF Response

-50

-100

__ = Log-FIR

.... Binary-FIR

' , I

.... Re~-~

',i

i~ 7
,

"

"

~i

.----.
',i

" /

"~

i:

, :

,:

2 -150

~ ~ . - .
-200

?!

....

-250

-300
0

50

100

150

200

250

300

350

400

450

500

normalisedfrequency
Fig 4. Log-Filter response Impulse Function = 32

the performance of the equivalent fixed-point binary filter9 The 10 bits comprised 1
sign bit, 1 zero bit 3 segment bits and 5 fractional bits. A similar performance can
also be achieved with a greater compression ratio by increasing the order of the filter.
As expected, the log-FIR filter had a far superior dynamic range than the equivalent
fixed-point FIR filter9 This is mainly due to the effects of truncation of the multiplier
output in the fixed-point implementation of the filter for low input values. The
performance of the filter for impulse functions of different magnitudes is shown in
Figures 3 and 4.

5. C i r c u i t D e s i g n
A prototype circuit has been built using a Xilinx FPGA to implement the FIR
filter. External EPROM and RAM were used to store filter coefficients and data. The
Xilinx device also interfaced to serial 12-bit ADC (LTC1291) and DAC (MAX539)
devices9 For this solution a standard linear ADC was used, although it would also be
possible to use an equivalent logarithmic ADC. This would remove the necessity for
a Linear to Log converter. The whole system was built to run off a single 5V supply9
A block diagram and photograph of the test board are shown in Figures 5 and 6.

308
A Xilinx 30C64 was used a total of 175 out of a possible 224 configurable logic
blocks (CLBs) was required. For the Linear to Log (Lin2Log) and Log to Linear
(Log2Lin) functions simple and efficient circuits which form piecewise linear
approximations to this function have been used [6]. Because of the mismatch in data
throughput rates of the Lin2Log converter (14KHz) and the Log2Lin converter
(895KHz) a serial implementation of the Lin2Log converter and a parallel
implementation of the Log2Lin converter was used. The Lin2Log converter is shown
in Figure 7. It is similar to the circuit described in [6] except that this circuit can
convert 2's complement binary values into logarithmic values. A zero detect circuit
has also been added to remove the problem of calculating the logarithm of zero. The
Log2Lin circuit is shown in Figure 8. In [6] it has been shown that parallel
implementation of such circuits are both regular and efficient and require far fewer
transistors than a multiplier This makes them suitable for implementation using
VLSI. Similar circuit can also be implemented on FPGAs using multiplexors instead
of transistors as switches.

Acknowledgements
This work was supported through the Nuffield Award to Newly Appointed
Lecturers number SCI/180/91/430/G.

References
[1].

Integrated Circuit Logarithmic Units

Jeffrey et al IEEE Trans on Computers Vol C-34 No 5 May 1985

[2].

Digital Filtering using Logarithmic Arithmetic

N.G Kingsbury P.J.W Rayner
IEE Electronics Letters 28th Jan 1971 Vol.7 NO.2 pp 56-58

[31.

Error Analysis of Recursive Digital Filters Implemented with Logarithmic

Number Systems. T. Kurokawa, J. A. Payne, S.C. Lee
IEEE Transactions ASSP Vol. ASSP-28 No. 6 December 1980.

[4].

Computation of the Base Two Logarithm of Binary Numbers.- M. Combet,

H.Van Zonneveld, L Verbeek
IEEE Transactions on Electronic Computers Vol EC-14 No. 6 Dec 1963
pp 863-867

[5].

New Algorithms for the Approximate Evaluation in Hardware of Binary

Logarithms and Elementary Functions. - D. Marino
IEEE Transactions on Computers December 1972 pp1416-1421

[6].

Efficient VLSI Digital Logarithmic Codecs - B. Hoefflinger

lEE Electronics Letters 20th June 1991 Vol 27 N013 pp1132-1134

309

I
Coefficient
memory
64x 10

'

Data
memory
64x10

i
-- Analog

Linear

Log

t
I
I
I

1
Fig 5. Log-Filter Block Diagram

Fig 6. Log-Filter Prototype Board

Linear

Analog

I
t

310

Succesive
Approximation
Register

Linear in ~1

msb~'

Down
Counter

P
Zero

Log Register

[
.4 Count

t3t3msb
msb
[SignI-

I~ Load

Log out
Fig 6. Serial Linear to Log Converter

Log
Fraction

Integer

Decoder

x32

~1

x16

?_1

,~
x4
x2
xl

21
21
21
21
-I

Si~

Z~ro

Shift Logic

~r

Set to Zero
~12
Linear
Fig 7. Log to Linear Converter

inv ~ _