Optimal Design of a Half-Wave Cockroft-Walton

Voltage Multiplier with Minimum

Total Capacitance
I.C. Kobougias and E.C. Tatakis
University of Patras / Department of Electrical and Computer Engineering
Laboratory of Electromechanical Energy Conversion, Rion Patras, Greece
AbstractThe Half-Wave Cockroft-Walton Voltage
Multiplier (H-W C-W VM) is one of the most common ACDC step-up topologies, known for its large voltage gain and
its high efficiency. However, over the worldwide
bibliography, the most of H-W C-W VM designers persist in
using equal capacitances in every stage without considering
an optimal design. The aim of this paper is to introduce a
new designing method of H-W C-W VM that lays both on
the choice of the adequate capacitance values to minimize
the output voltage drop and ripple (so the voltage gain is
maximized) as well as the calculation of the optimal number
of stages that is necessary to produce the desired output
voltage with the minimum total capacitance. The theoretical
analysis is validated by PSPICE simulations and
experimental results, accomplished on laboratory
prototypes.

I.
INTRODUCTION
High voltage conversion ratio becomes more and more
essential in a multitude of industrial and laboratory
research applications [1-4], such as front-end stages for
battery or photovoltaic sources, DC back up systems, UPS
devices, step down inverters and many more. Among
these applications the Voltage Multipliers (VM) and
especially the Half Wave CockroftWalton Voltage
Multiplier (H-W C-W VM), shown in Fig. 1, stand in the
foremost rank [5-8].
However, due to the AC impedance of the capacitors,
there is a voltage drop Vo and a peak to peak voltage
ripple Vo when the circuit is loaded [8-10]. According to
the studied worldwide bibliography, almost all C-W VM
are designed with equal capacitances. In addition, only
one paper refers to an optimal design [11], without,
however, taking into account the voltage ripple Vo and
considering that all capacitors have the same value.
This paper is focused on two critical subjects for an
optimal designed H-W C-W VM, namely the best choice
of the capacitance values that offers the maximum voltage
ratio (minimization of the output voltage drop and ripple)
as well as the optimal number of stages Nopt that are
necessary to achieve a given output voltage gain with the
minimum total capacitance Ctot,min.
The theoretical analysis is validated by PSPICE
simulations and experimental results, accomplished on
laboratory prototypes.

This work was funded by the European Social Fund (75%), the Greek
Secretariat Research and Technology (25%) as well as ANCO S.A. and
ENERGY SOLUTIONS S.A., within the framework of Measure 8.3 of
the Operational Programme Competitiveness and the 3rd Community
Support Programme (PENED 2003, 03400).

978-1-4244-1668-4/08/$25.00 2008 IEEE

Figure 1. Half-Wave Cockroft-Walton Voltage Multiplier with n

stages and resistive load as a function of applied field

II.

CHOICE OF THE CAPACITANCE VALUES FOR AN

H-W C-W TOPOLOGY
Based on the theoretical analysis and the assumptions
presented in [9, 12, 13] for the H-W C-W topology, the
ratio X of the output voltage Vo over Epk - the peak value
of the sinusoidal input supply voltage - is given by the
equations:

X nl 

X nl
'Vo
E pk

1
E pk

Vo  Vo
2

Vo,nl
E pk

2n

(1)

(2)

2
n 1 n  1  i n  1

   (3)
g n n 1 i

f i 1 C 2i1
C2i
i 1

GVo
E pk

g n n 1 i

f i1
C2i

(4)

where Xnl is the no-load voltage ratio, n the number of

stages, f the frequency of the voltage supply, IL the
average value of the load current and g=IL/pk.
Looking over (4) we can notice that the output voltage
ripple Vo is affected by the smoothing capacitors
(capacitors with even index) values, whereas the voltage
drop Vo - according to (3) - is affected from both
smoothing and transition capacitors (capacitors with odd
index) values. The latter ones have greater influence on
Vo due to their larger coefficient, as shown in (3). So,
choosing the capacitance values of a loaded H-W C-W
VM judiciously, it is possible to minimize Vo and Vo
leading to maximized output voltage Vo. According to

1104

these remarks four different choices (cases) of the

capacitance values of a H-W C-W VM can be advised:
Case 1: C2i C 2i 1 C (the classical case, analyzed by
many authors)
Case 2: C1 2 C and C2i C2i 1 C for i1 (case
often found in the bibliography)
Case 3: C2i C 2i 1 ( n  1  i) C
Case 4: C2i

(n  1  i) C and C2i 1

(n  1  i) 2 C

where i the number of every stage and C the capacitance

of the last stage (base capacitance).
Considering that the total capacitance Ctot is the sum of
Figure 3. Vo/Epk as a function of n, for the different cases

all the capacitances of each topology C tot

, new

i 1

formulas can be extracted to calculate the voltage gain X

for every case as a function of Ctot:
Case 1: X 2 n 
and C tot
Case 2: X 2 n 
and C tot
Case 3: X 2 n 
and C tot
Case 4: X

g
n 8 n3  9 n 2  n

f C tot
6

(5)

2n C

2 n  1 8 n 3  3 n 2  n
g

f C tot
12

2 n  1 C
g
n 2 n  1 2 n  1

f C tot
2

(7)

Figure 4. X=Vo/Epk as a function of n, for the different cases

n n  1 C

g
n 2 n  1 n  2 2

2n 
f C tot
6

and C tot

(6)

(8)

n n  1 n  2 
C
3

Fig. 2, Fig. 3 and Fig. 4 show, respectively, the

normalized (by Epk) values of the ripple Vo, the voltage
drop Vo, and the output voltage Vo, for a given value of
the term g/fCtot, as a function of the number of stages n.
From these figures it is obvious that for the same number
of stages Cases 3 and 4 offer lower Vo and Vo as well
as higher Vo in regard to the common used cases 1 and 2.

III. OPTIMUM DETERMINATION OF THE NUMBER OF

STAGES TO ACHIEVE MINIMUM TOTAL CAPACITANCE
For the aforementioned analysis it is worth mentioning
that the optimum design of a H-W C-W VM implies the
minimization of the number of stages n, for a specific
voltage gain. In addition the cost and the lifetime of a HW C-W VM are inversely proportional to Ctot. So, the
problem is stated as follows: Determination of the
minimum total capacitance Ctot,min, leading to an optimal
number of stages Nopt, when the output voltage has a
specific value Vo and taking into account that Epk and IL
are given quantities. Note that as f and Ctot appear as a
product in the equations (5)-(8) they are initially
considered as a single variable FCtot and the solution for
the above problem accrues from the equation:

wFC tot  n,g, X 

wn

(9)

where g=IL/Epk and X=Vo/Epk are considered as constants.

Considering the relation:

wX
wn

wX wFC tot

wFC tot
wn

(10)

and substituting (9), we conclude that:

Figure 2. Vo/Epk as a function of n, for the different cases

wX
wn

(11)

meaning that the smallest product fCtot,min also implies an

optimum value for the number of stages Nopt to obtain the
desired output voltage Vo.

1105

Applying (11) to the equation that corresponds to each

case we obtain:
Case 1:

g
 32 n 3  27 n 2  2 n  12
FC tot

Case 2:
For this case (16) has four roots. Only the one that is a
real number equals to Nopt. These roots are:
1
1
1
 a1  R4  D4
4
2
2
1
1
1
 a1  R4  D4
4
2
2
1
1
1
 a1  R4  E4
4
2
2
1
1
1
 a1  R4  E4
4
2
2

N r1

(12)

Nr 2

Case 2:

g
 64 n 3  42 n 2  10 n  1 24
FC tot

Nr3

(13)

Nr 4

Case 3:

g
8 n 3  9 n 2  2 n  4
FC tot

(14)

g
n  n  2   5 n 2  10 n  4  12
FC tot

(15)

R4
y1

Case 2

Case 3

Case 4

a2
a1
a0

8X  7
12

8X  9

12
27 X  2

48

21 X  5

48

X

24

X

96

5X
48

2X 3

3

5 X  14

8

9X  2
12

X

6

E4

5X  2
4

(18f)

, R4

3
1

3 2
1 4 a1 a2  8 a3  a
a1  R4 2  2 a2 
4
4
R4

, R4 z 0

3 2
a1  R4 2  2 a2  2 y12  4 a4
4

, R4

Case 3:
N opt

T
16 X 2  33 X  18 cos  2 X  3 (19)
9
3

where:
cos T 

(17a)

R
Q 3

(19a)

16 X 2  33 X  18
182

(19b)

64 X 3  198 X 2  81 X  54
2 542

(19c)

Case 4:

64 X  99 X  63
362

(17b)

1024 X 3  2376 X 2  1161 X  972

2 363

(17c)

(18d)

3 2
a1  R4 2  2 a2  2 y12  4 a4
4

where:
Q 3

Q R

(18c)

R D

3 2
1 4 a1 a2  8 a3  a13
a1  R4 2  2 a2 
, R4 z 0
4
4
R4

1
T 8 X  9
(17)
64 X 2  99 X  63 cos 
18
3
3
R

39 X 2  78 X  25
1442

Case 1:

cos T 

and T

(18h)

X

2

Using well known formulas [14] an analytical solution

can be obtained. Thus, for each case the optimum number
of stages Nopt is given by the following equations:

N opt

(18b)

(18g)

1
S  T  a1
3

(18e)

D4

Case 1

(18a)

1053 X  63 X  603 X  125

1443

(16)

TABLE I.
COEFFICIENTS OF THE (12), FOR EACH CASE.

a3

R D

1 2
a1  a2  y1
4

is obtained. The coefficients for every single case are

given in the Table 1.

a4

Combining for each case the corresponding equations

(5) and (12), (6) and (13), (7) and (14), (8) and (15) an
algebraic equation having the following general form:
0

(18)

where:

Case 4:

a 4 n 4  a 3 n 3  a 2 n 2  a1 n  a 0

N opt

5 X

T 1
T
2 cos  1  10 cos  7 (20)
24
3 12
3

where:
cos T 

1106

R
Q 3

(20a)

5  X  2


24

(20a)

125 X 3  750 X 2  636 X  728

242

In any case the value of Nopt depends only on the

voltage gain X and not on the output current IL.
According to Fig. 5, for a certain value X of the gain,
Case 4 requires the fewer number of stages (Nopt),
having a slight difference from the other cases.
On the other hand, from Figure 6 it is obvious that
Case 3 leads to a minimum value of the quantity

(20b)

Moreover, it can be proven that the Nopt solution for

each case can be approximated by a linear equation. In
fact, for all cases, when X tends to infinity tends to zero,
so cos(/3) tends to unity. So, the optimal number of
stages can be approximated by the following equations:
Case 1:
N opt |

2
10
X 
3
108

(21)

N opt |

2
3
X 
3
41

(22)

Case 2:

f C tot,min

for a certain value of X, that means a

minimum total capacitance for given values of g (p.u.

output current) and f.
Finally, Fig. 7 depicts the quantity fCtot/g as a function
of the number of stages n - for each case - and for a given
value of the voltage conversion ratio X (in this example
X=23.8). Moreover, the result obtained applying the
method proposed in [11] is also reported (by a square) in
this figure.
Nopt Comparison

Case 3:

40

N opt |

2
1
X 
3
8

35

(23)

Case 1
Case 2

30

Case 4:

Case 3

Case 4

25

5
1
N opt | X 
8
4

Nopt

According [11]

(24)

15

The mathematical and graphical analyses reveal that the

precision of this linear approximation is remarkable and it
gives an easy tool to estimate the necessary optimal
number of stages to obtain a desired voltage gain X, for
given values of f and IL.
Finally, the equations which give the minimum total
capacitance Ctot,min, from which the base capacitance C as
well as the capacitance values of each stage can be
calculated, are the following:
Case 1:
3
2
g  8 N opt  9 N opt  N opt  N opt

f
6  2 N opt  X 

(25)

10

0
0

10

15

20

25

30
X=Vo/Epk

35

40

45

50

55

60

55

60

Figure 5. Nopt as function of X, for the different cases

FCtot,min/g Comparison (g=IL/Epk)
2,50E+05
2,25E+05

Case 1
2,00E+05

Case 2
Case 3

1,75E+05
FCtot,min/g

Ctot ,min

20

Case 4

1,50E+05

According [11]
1,25E+05
1,00E+05
7,50E+04

Case 2:
Ctot ,min

3
2
g  8 N opt  3 N opt  N opt   2 N opt  1

f
12  2 N opt  X 

5,00E+04

(26)

2,50E+04
0,00E+00
0

Case 3:

10

15

20

25
30
X=Vo/Epk

35

40

45

50

Figure 6. fCtot,min/g as a function of X, for the different cases

Ctot ,min

2
g N opt  N opt  1  2 N opt  1

f
2  2 N opt  X 

(27)

Case 4:
Ctot ,min

2
g N opt  N opt  1  N opt  2 

f
6  2 N opt  X 

(28)

Fig. 5 gives the value of Nopt (rounded to the closer

upper integer) whereas Fig. 6 gives the quantity

f C tot,min
g

as a function of the voltage gain X. Taking a

closer look to the previously mentioned equations and

figures, the following conclusions come up:

1107

Figure 7. fCtot,min/g as a function of n, for the different cases

(X=23.8)

From the previous remarks we can conclude that case 3

can be characterized as the best choice among the four
cases for an optimized design of a Half-Wave CocroftWalton VM, because it gives the desired output voltage
with a nearly optimum number of stages and the minimum
total capacitance. Furthermore the proposed design
method leads to a better result than the method proposed
in [11].
IV. SIMULATION VERIFICATION
To verify the theoretical analysis a large number of
simulations is carried out using the circuit simulation
software PSPICE. Four different circuits per case are
simulated, consisting of 3, 5, 7 and 14 stages respectively.
In these simulations the following values are adopted:
C=5F, f=100kHz, Epk=20V and IL0.1A
The voltage gain X and the ripple Vo, that are
extracted by the aforementioned simulations, are depicted
respectively at Fig. 8 and Fig. 9, as functions of n. Causes
for this small divergence between theoretical and
simulation results are both the voltage drop across the
diodes, that was ignored during the theoretical analysis
and the small variations of IL during the simulation
process. Despite that, the simulation results still keep up
remarkably with the theoretical ones.

V. EXPERIMENTAL VERIFICATION
For the experimental verification three Case 3 H-W CW laboratory prototypes are used that consist of 3, 5 and 7
stages, respectively. Every stage includes two MKP
capacitors and two STP40NF10 diodes. The capacitors of
the last stage are both equal to 0.8 F.
The 100 kHz AC input voltage is supplied by another
laboratory prototype, a 100W Full Bridge Parallel Loaded
Resonant Inverter, shown in Fig. 10. The resonant
inductance is chosen to 3.7H while the resonant
capacitance equals to 0.25F. The inverter is driven by the
dsPIC4011F Microchip microcontroller, which generates
100kHz pulses with 50% duty cycle. This helps the
resonant converter produce an almost sinusoidal output
voltage. Because of the higher frequency harmonics, the
peak value of the first harmonic was adjusted to 30V
during the experimental procedure. Fig.10 represents a
typical waveform of the aforementioned voltage.
In order to test the operation of the H-W C-W VM for
different IL, six resistive loads - 1460, 2140, 2700,
3660, 5860 and 13660 - were used. The extracted
measurements are represented at Fig. 11, Fig. 12 and Fig.
13.
The expected divergence between the experimental and
the theoretical results rely on three main reasons:
x The higher frequency harmonics of the H-W C-W
V-Ms input voltage make difficult to choose the
right Epk for the theoretical analysis.
x The voltage drop across the used diodes.
x The accuracy of the measurement instruments,
especially those which measure the small amplitude
of IL.
Nonetheless the experimental results fit with such a
good accuracy those obtained by the theoretical analysis,
confirming the aforementioned conclusions.
Finally, Fig.14 represents an aspect of the experimental
prototypes.

Figure 8. X as a function of n, for the different cases (simulation

results)

Figure 10. Typical output voltage of the Resonant Inverter

Figure 9. Vo/Epk as a function of n, for the different cases

(simulation results)

1108

Figure 11. X as a function of g, for Case 3 and n=7

VI. CONCLUSIONS
In this paper is presented a novel method of designing a
H-W C-W VM based on using different capacitances per
stage. For that reason four different choices (cases) of the
capacitance values of an H-W C-W VM (conventional and
new) are compared. A theoretical analysis is held that
produced new and improved equations about C-Ws
voltage gain. Furthermore new formulas are introduced
that give the minimum number of stages that not only
provide the proper voltage gain but also minimize the total
capacitance, a fact that minimizes the cost and increases
the lifetime of the VM. The analysis reveals the case
which is the best choice among the four ones. These
conclusions are validated by PSPICE simulations and
experimental results, accomplished on laboratory
prototypes
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[1]

[2]

[3]

[4]
Figure 12. X as a function of g, for Case 3 and n=5

[5]

[6]

[7]

[8]
Figure 13. X as a function of g, for Case 3 and n=3

[9]

[10]

[11]

[12]

[13]
[14]
Figure 14. Resonant Inverter, Case 3 H-W C-W VM with n=7 and
resistive load

1109

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