A First Course in Digital Communications (Ch12-Synchronization)

Chapter 12: Synchronization
A First Course in Digital Communications

Ha H. Nguyen and E. Shwedyk
February 2009
1/40
Introduction
Any successful communication system must establish
synchronization.
At the physical-layer level the receiver needs to estimate three
parameters:
(i) The incoming carrier frequency, fc (Hz);
(ii) Any phase shift or phase drift, (t) (radians), introduced
during transmission (for coherent demodulation);
(iii) The bit (symbol) timing, i.e., where on the time axis do the
kTb (or kTs ) (seconds) ticks occur.
The concepts involved are illustrated by the discussion of the

analysis and design of two basic circuits: the phase-locked
loop (PLL) for fc and (t) estimation and the early-late gate
synchronizer for symbol timing.
2/40
Effect of Phase Error on BPSK and QPSK

Q (t )
Q (t )
!

1R

Eb
0T
Eb
I (t )
I (t )
1

T
2 Eb
0R
"
$
2 Eb sin & +
rQ
#
%
'
rQ
1(DQ )
0D
1D
Eb cos
Eb cos
rI
rI
(
*
2 Eb cos , +
0(DI )
0(DQ )

)
+
-
1(DI )

3/40
BPSK: P [bit error] = Q

10
P[bit error]
10
10
q
2Eb
N0
cos
(a) BPSK
=0, 10, 15, 20, 25, 30 degrees

10
10
10
6
8
E /N (dB)
b
10
12
14
4/40
1
2Q
q
2Eb
N0

q

2Eb
1
(cos sin ) + 2 Q
N0 (cos + sin )
10
P[bit error]
10
10
(b) QPSK
=0, 5, 10, 15, 20, 25, 30 degrees

10
10
10
6
8
E /N (dB)
b
10
12
14
5/40
Effect of Symbol Timing Error on NRZ-L Modulation

Eb
Tb
0
E
b
Tb
2Tb
Tb
t = ( + 1)Tb
( +.1)Tb
w (t )
( ) dt
Tb
1
Tb
<
0D
0 1/ 2
0 Tb
( + 1)Tb
r = Eb + w when two consecutive bits agree and

r = Eb (1 2) + w if they disagree.
1D
6/40
P [bit error] =
10
P[bit error]
10
10
1
2Q
q
2Eb
N0
1
2Q
q
2Eb
N0 (1
2)
=0, 0.05, 0.1, 0.2, 0.3

10
10
10
6
8
E /N (dB)
b
10
12
14
7/40
Phase-Locked Loop (PLL)

PLL is a circuit that locks onto the frequency c (rad/sec) of
a received sinusoid, V cos(c t + ) and estimates the phase
offset, (radians).
Loop implies a feedback circuit and this is precisely what a
PLL is: It is a feedback control system whose function is to
track the frequency and phase of an input sinusoid.
89:;6
V cos(ct + )
vin (t )
<656=507
/001
234567
Vc cos(i t + (t ))
>045:?6 @0A57044 6B
vout (t )
C;=344 :507
8/40
A Sinusoid Phase Detector

E
NOPQK RKJ KSJ
t =0
V cos(c t + )
vin (t )
"double" frequency
term (c + i )
Vc cos(i t + (t ))
Estimate of
(c , )
D EE
Lowpass Filter for
F
GHIJKL
out (t )
K VCO
VDC
vout (t )
vout (t )
VDC
sets the bias or operating point of the VCO, which determines
A First Course
DC in Digital Communications
9/40
Four Possible Loop Filters

R1
R
vout (t ) vin (t )
vin (t )
vout (t )
C
T V WXXY
X^_
U
ZU[[ \]
`
abc de ghi
ime
f
fj kl
n
R1
R1
vin (t )
opq rs
tuvwxx yz{|}~
vout (t ) vin (t )
vout (t )
10/40
Analysis of the First-Order PLL Circuit

Consider the simplest case where the loop filter is an allpass filter.
A of the loop is
The signal at point
Km V Vc
{cos [(c + i ) + + (t)] + cos [(c i )t + (t)]} ,
2
where Km is a constant, i is the nominal frequency of the VCO
(reasonably close to c ), and (t) is a slow phase variation in the
output of the VCO.
Km V Vc
Km V Vc
cos [(c i ) t + (t)] =
cos (t) ,
2
2
where (t) (c i )t + (t) = (c t + ) (i t + (t)) is
the instantaneous phase error.
vin (t) =
out (t)
= i + Kvco vout (t) = i + Kvco vin (t)

Kvco Km V Vc
= i +
cos (t) = i + Kloop cos (t),
2
where Kloop
Kvco Km V Vc
2
is called the loop gain.

11/40
As out (t) is the instantaneous frequency of the VCO output, one

has
out (t) =
d
d(t)
[i t + (t)] = i +
= i + Kloop cos (t)
dt
dt
d(t)
= Kloop cos (t).
dt
Let (c i ). Then (t) = t + (t) and

d
d
d(t)
[((t) t) + t] =
[(t) + t] =
+.
dt
dt
dt
The differential equation governing the phase error, (t), is:
d(t)
+ Kloop cos (t) = ,
dt
t 0.
12/40
Phase Plane of the First-Order PLL Circuit

d(t)
+ Kloop cos (t) = ,
dt
t 0.
d (t )
dt
d (t )
= K loop cos (t )
dt
+ K loop
(t )
K loop
13/40
Observations about the Phase Plane Plot

1) The phase error, (t), at all times, has to be a point on the
trajectory. Where one starts depends on (0), the initial
condition.
2) The intersection points represent equilibrium or solution
points in the steady state, i.e., as t and the transient
response has died out. However, some are stable and others
are unstable. Note that d(t)
dt > 0 implies that (t) increases
d(t)
with time while dt < 0 means (t) decreases.
3) The stable operating points are given by:

1
(t)
+ 2k, k = 0, 1, 2, . . .
= cos
Kloop
t
14/40

4) Consider the stable operating point of cos1 K
. Since
loop
(t) = (c i )t + (t) approaches a constant as
t , we conclude that the angular frequency i approaches
frequency.
c as t , i.e., the loop locks onto
h the incoming

i
The phase (t), however, tends to + cos1 K
.
loop

Therefore there is a phase error of magnitude, cos1 K
.
loop
5) The stable operating point and achievement of lock occurs
only if Kloop < < Kloop , i.e., the trajectory must
intersect the axis. Otherwise the phase error either keeps
increasing if > Kloop , or keeps decreasing if
< Kloop , with time.
6) Observe that if = 0 at t = 0, i.e., initially the incoming

frequency and VCO frequency are the same, the steady-state
phase error is 2 , i.e., the VCO signal is in quadrature with
the incoming signal.
15/40
To understand the PLLs transient performance (how does the phase

error behaves over time), need to solve the differential equation:
(t)
Z
(t=0)
d
=
Kloop cos
Zt
dt = t.
t=0
q
=(t)
2
Kloop
()2 tan 2 + Kloop
q
= t,
ln q
2
2
Kloop
()2 Kloop
()2 tan 2 + Kloop
=(0)
where || < Kloop (the lock-in region). Define d
Kloop ,
we get
(p
)
1 d2 tan (t)
2 (1 d )
ln p
=
1 d2 tan (t)
2 + (1 d )
)
(p
q

1 d2 tan (0)
2 (1 d )
2
Kloop
1 d t + ln p
.
1 d2 tan (0)
2 + (1 d )
16/40
Without loss of generality we let 0 < < Kloop , which means

0 < d < 1. Therefore the numerator of the LHS is less than
denominator of the LHS. Multiply both sides of the above equation
by 1 and then take the exponential of both sides, one has
"
#
a tan (0)
a tan (t)
2 +b
2 +b
=
ea Kloop t , t 0.
(0)
a tan (t)
b
a
tan
b
2
2
where a
p
1 d2 ; b (1 d ).
From the above equation we would infer that (t) approximately

decays exponentially to its steady-state value with a time constant
of a K1loop .

a tan (0)
2 +b
Letting A
, the explicit expression for (t) is
(0)
a tan
(t) = 2 tan
)
b 1 + Aea Kloop t
.
a (1 Aea Kloop t )
17/40
(t) = 2 tan1
1
b(1+Aea Kloop t )
a(1Aea Kloop t )

d=0.1
(0)=/4
=0.5
d
0.5
0
(t)
(0)=/10
0.5
1
cos1(d)
1.5
0
The steady-state is reached within

4
5
Kloopt (sec)
3
aKloop
seconds.
to
5
aKloop
18/40
Equivalent Model of a Sinusoidal PLL

Practical loop filter is chosen so that the PLL become a
second-order PLL, meaning that the differential equation for the
phase error is a second-order, nonlinear differential equation.
The loop filter in this case is chosen from one of those shown in
Figures (b), (c) or (d) of page 10.
A second-order PLL extends its lock range, has better performance
in noise and can achieve a steady-state phase error of zero, i.e., not
only is frequency lock achieved but also phase lock as well.
We now develop a somewhat more general model for the sinusoidal
PLL. It could be termed the equivalent baseband model or the
incremental model because the frequency c is suppressed.
The VCO output is assumed to have an angular frequency of c ,
any deviation from this, say t, is subsumed in the instantaneous
phase, (t), i.e., (t) = t + (t).
19/40
Sinusoidal PLL

K mVVc
sin( (t ) (t )) = vin (t )
2
V sin(ct + (t ))
Loop Filter
2 f c Filter
h(t )
vout (t ) = h(t ) vin (t )
Vc cos(c t + (t ))
out (t )
K VCO
VDC
vout (t )
VDC
d(t)
= Kloop h(t) sin((t) (t)),
dt
where (t) (t) (t) is the phase error. It follows that
R
R
(t) = Kloop h(t) sin((t) (t))dt = Kloop vout (t)dt. This leads to
an equivalent model of the PLL.
20/40
Equivalent Model of the Sinusoidal PLL

(t ) = (t ) (t )
vin (t ) = sin( (t ))
sin
(t )
h(t )
(t )
vout (t )
K loop
K loop vout (t ) = K loop h(t ) sin (t )
( ) dt
Other nonlinearities for the phase detector are shown below.

Output (volt)
Output (volt)
Phase error
(rad)
Phase error
(rad)
2
V

21/40
Linear Model of the Sinusoidal PLL

If the phase error is small enough (a situation that occurs once the
PLL has locked onto the frequency of the incoming signal and now
is tracking slow phase changes in it) then sin ( 1) and
the PLL can be represented by a linear model:
(t ) ( s )
vin (t ) Vin ( s )
1
(t ) ( s )
h(t ) H ( s )
vout (t ) Vout ( s )
K loop

(t ) ( s ) =
Vout ( s )
s
1
s
vout (t ) K loop H ( s )Vin ( s )
22/40
Second-Order Phase-Locked Loop Dynamics

Consider the filter of Figure (d) on page 10 with H(s) = 1 + as .
Vout (s) =
Since
d(t)
dt
s+a
dvout (t)
dvin (t)
Vin (s)
= avin (t) +
s
dt
dt
= Kloop vout (t) and vin (t) = sin (t), one has
dvout (t)
d(t)
d (t)
= Kloop
= aKloop sin (t) + Kloop cos (t)
.
dt2
dt
dt
2
d (t)
d
Because d dt(t)
= dt
+
2
2 [(t) (t) + (t)] = dt2
differential equation for the phase error is:
d2 (t)
dt2 ,
the
d2 (t)
d(t)
d2 (t)
+
K
cos
(t)
+
aK
sin
(t)
=
.
loop
loop
dt2
dt
dt2
Consider a constant frequency input, (t) = t. Then
d2 (t)
d(t)
+ Kloop cos (t)
+ aKloop sin (t) = 0.
dt2
dt
Unfortunately, no solution is available for the above equation.
23/40
Phase Plane Plot for Second-Order Phase-Locked Loop

Normalize the time axis by letting Kloop t, then

2
d ( )
d( )
a
2
+ cos ( )
+
sin ( ) = 0.
Kloop
d 2
d
Kloop
d2 ( )
d( )
a
+ a sin ( ) = 0where a
+ cos ( )
.
2
d
d
Kloop
h
i
2 ( )
d d( )
Now d d
=
. Divide the previous equation by
2
d
d
d( )
d
and realize that
d
d
d( )
d
d( )
d
h
i
)
d d(
d
d( )
, we have
d
sin
d( )
= cos a
, where =
.
d
d
The phase plane is a plot of versus and the above

equation gives the slope of the trajectories at each point
) in the phase plane.
(,
24/40
(b) a=1/8
5
4
Derivative of the phase error, d()/d
(a) a=1/2
5
3
2
1
0
1
2
3
4
5
3
2
1
0
1
2
3
4
/2
/2
0
Phase error, ()
/2
/2
0
Phase error, ()
25/40
Some Observations of the Phase Plane

) plane where the phase error
There is a region in the (,
converges to 0 without the phase exceeding the [, ] range.
Outside this region the PLL still converges to a stable point, but one
that is a multiple of 2. This phenomena is known as cycle skipping.
The phase plane plot is shown only in the range [, ] since the
plot is periodic with period 2.
There are singular points at ( = 0, = k2) which are stable
operating points. There are also singular points at
( = 0, = (2k + 1)), which are unstable and called saddle points.
0.05
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
0.05
3.06
3.08
3.1
3.12
3.16
Phase error, ()
3.18
3.2
3.22
3.24
26/40
Lock-in Range of Second-Order PLL

Multiply the previous equation by and integrate over [, ]:
Z
Z
i
1 h 2
2
() () = cos d a
sin d.
2
The second term is zero. Integrating the first term gives:

i Z
1 h 2
2
() () =
sin d.
2
Substituting d = cos a sin d yields
Z
Z
Z
i
1 h 2
sin2
1 cos(2)
2
() () = sin cos d a
d = a
d.
)
If = d(
> 0, the RHS < 0 and if < 0 the RHS > 0 For any
d
must decrease regardless of the initial value of
cycle of width 2, ||
the lock range is infinite.
27/40
State-Space Approach to The Phase Plane Method

A high-order differential equation is changed into a set of first-order
differential equations which can then be solved numerically.
Define two states y =
d( )
d
and x = ( ). Then
dy
= y cos x a sin x,
d
dx
= y.
d
(a) a=1/2
Phase error, ()
20
15
.
(0)=2.5
10
5
0
5
0
.
(0)=0.5
10
20
30
Time,
40
50
60
(b) a=1/8
Phase error, ()
80
.
(0)=2.5
60
(0)=0.5
40
20
0
20
0
.
(0)=0.5
10
20
30
Time,
40
50
60
28/40
Phase and Carrier Frequency Acquisition

PLL needs a spectral component at the carrier frequency, fc .
Suppressed carrier modulations such as BPSK, QPSK, and
M -QAM do not have the spectral component at fc .
How to obtain a spectral component for these modulations?
For BPSK, the received signal can be written as
(
)
r
X
p
2
bk [u(kTb ) u((k + 1)Tb )]
Eb
cos(2fc t + ) + w(t),
r(t) =
Tb
k=
r (t) = I (t)Eb
=
2
Tb
cos2 (2fc t + ) + noise terms
Eb
+ cos(2(2fc )t + 2) + noise terms.
Tb
r2 (t) has a spectral component at 2fc for the PLL to lock on!
29/40
2nd-Power Synchronizer for Carrier Recovery for BPSK

r (t )
()
r 2 (t ) V cos(4 f ct + 2 )
4 f c Filter

Vc sin(4 f ct + )
= 2
A sin(2 f ct + )
900 Phase
Shifter at fc
30/40
Carrier Recovery for QPSK

p
r(t) = I(t) Eb
I(t)
k=
p
2
cos(2fc t+)+Q(t) Eb
Ts
(I)
bk [u(kTs ) u((k + 1)Ts )] , Q(t)
r2 (t) =
+
=
r4 (t) =
+
2
sin(2fc t+)+w(t),
Ts
k=
(Q)
bk [u(kTs ) u((k + 1)Ts )],

2
cos2 (2fc t + ) + Q2 (t)Eb
sin2 (2fc t + )
Ts

2
2I(t)Q(t)Eb
cos(2fc t + ) sin(2fc t + ) + noise terms
Ts
2Eb
2Eb
+
I(t)Q(t) sin(2(2fc )t + 2) + noise terms.
Ts
Ts
I 2 (t)Eb
2
Ts
4Eb2
8Eb2
+
I(t)Q(t) sin(2(2fc )t + 2)
Ts2
Ts
4Eb2 2
I (t)Q2 (t) sin2 (2(2fc )t + 2) + even more noise terms.
Ts2
31/40
4th-Power Synchronizer for Carrier Recovery for QPSK

r 4 (t ) Vc cos(8 f ct + 4 )
r (t )
()
8 f c Filter

Vc sin(8 f ct + )
= 4
A sin(2 f ct + )
/2 Phase
Shifter at f c
32/40
Carrier Recovery for M-PSK and M-QAM

M -PSK needs an M th-power block to produce a spectral
component at M fc for the PLL circuit.
Consider QAM with signals on a rectangular grid:
(
)r
X
2
s(t) =
Ii,k [u(kTs ) u ((k + 1)Ts )]
cos(2fc t + )
Ts
k=
|
{z
}
I(t)
k=
Qj,k [u(kTs ) u ((k + 1)Ts )]

{z
Q(t)
)r
2
sin(2fc t + ),
Ts
where Ii,k is one of the amplitudes (, 3, . . .) on the

inphase axis, Qj,k is one of the amplitudes (, 3, . . .) on
the quadrature axis, i = 1, 2, . . . , 2I , j = 1, 2, . . . , 2Q .
33/40
Treat I(t), Q(t) as two random processes and note that

E{I(t)} = E{Q(t)} = 0;
E{I(t)Q(t)} = E{I(t)}E{Q(t)} = 0; E{I2 (t)} = I2 ;
2.
E{Q2 (t)} = Q
2 ) it can be
For nonsymmetrical QAM constellations (I2 6= Q
2
shown that E r (t) has a spectral component at 2fc and
one can use the same synchronizer circuit as for BPSK.
2 = 2 ),
For symmetrical QAM constellations (I2 = Q
4
E r (t) has a spectral component at 4fc . Therefore the
QPSK synchronizer block diagram can be used for
symmetrical QAM.
34/40
Costas Loop for Carrier Recovery for BPSK

Costas loop avoids the squaring or fourth-power block, which is difficult
to implement at high frequencies.
I (t ) cos
2 f c Filter
( = )
2 cos(2 f ct + )
K sin(2 )
r (t )
/2 Phase
Shifter at f c
2sin(2 f ct + )
I 2 (t )
sin(2 )
2
I (t ) sin
2 f c Filter
35/40
Costas Loop for Carrier Recovery for QPSK

I (t ) cos(2 f c t + ) +
Q(t ) sin(2 fc t + )
I (t ) cos + Q(t ) sin
2 f c Filter

2 cos(2 f ct + )
r (t )

I (t )

I (t )Q(t ) cos sin

2sin
/2 Phase
I (t )Q(t ) cos + sin
Shifter at f c
2sin(2 f ct + )
2 f c Filter

I (t ) sin + Q (t ) cos
Q(t )

36/40
Estimation of Symbol Timing

Symbol timing recovery circuits can be broadly classified into
open-loop and closed-loop.
They may be further classified into non-data-aided (NDA) and
data-aided (DA) synchronizers
Shall consider NDA symbol synchronizers and restrict to binary
baseband signals.
The following circuit works if a baseband modulation m(t) has a
spectral component at f = T1b :
r (t ) = m(t ) cos(2 f ct + ) + w (t )
m(t ) + w 0 (t )
2 f c Filter

!
#
BPF
1 "
$ Hz
Tb
1
1
2 cos(2 f ct + )
clock signal
from carrier /phase

recovery circuit
37/40
Most popular baseband modulations (NRZ-L, Miller, bi-phase, etc.)

do not have a spectral component at T1b : it needs to be created.
In the first circuit, m1 (t) is always positive in the second half of
every bit period, Tb . It will be negative in the first half if two
successive bits disagree. This produces a spectral component at the
data rate rb = T1b as well as at the harmonics.
m(t )
m1 (t )
Delay
Tb
2
%
'
)
BPF
clock signal
&
1 (
* Hz
Tb
m(t Tb / 2)
The second circuit is an edge detector where the differentiator

produces positive or negative spikes at symbol transitions.
m(t )
123
d
dt
0
+
/
BPF
,
1 .
0 Hz
Tb
clock signal
1
1
38/40
Early-Late Gate Clock Synchronizer

Open-loop synchronizer has an unavoidable nonzero average
tracking error (though small for large SNR, it cannot be made zero).
A closed-loop symbol synchronizer circumvents this problem.
Early-late gate synchronizer is the most popular.
Late-gate integrator
T:b
( ) dt
V1
m(t )
V1
0
789
456
Tb; d
( ) dt
V2
V2
Early-gate integrator
39/40
When the VCOs square-wave clock and the incoming data, m(t),
are in perfect synchronization, both integrators accumulate the same
amount of signal energy over (Tb d) the error signal is zero.
If m(t) is delayed by < d, the early-gate integrator accumulates
over (Tb d), while the late-gate integrator still accumulates
over (Tb d) seconds the error signal is proportional to
which would delay VCOs timing. The opposite happens when the
data timing is in advance of the VCO timing.
m(t )
+V
FGHIJKLGMN
<=>?@AB=CD
OGMNKLGMN
E=CDAB=CD
d
d
t =0
t = Tb
t =0
Synchronized
t = Tb
m(t ) is delayed by
with respect to VCO timing
40/40

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Chapter 12: Synchronization