ELX304 Topic5 Lesson 1 Pr2

ElectricalSystemsDesign(ELX304)
Part5VLSIimplementationplatforms
PART5
VLSIIMPLEMENTATION
PLATFORMS
UniversityofSunderland
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ElectricalSystemsDesign(ELX304)
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Part5VLSIimplementationplatforms
ElectronicSystemsDesign(ELX304)
Lesson1Regulararraystructures
LESSON1
REGULARARRAYSTRUCTURES
INTRODUCTION
Thismoduleintroducestheconceptofregulararraystructuresthat
providethebasicmethodologyforoptimumuseofVLSIdesign.
Itproceedstolookatthemostcommonapplications,namely
memorydevices,andintroducesprogrammabledevicesfor
efficientlogicimplementation.
YOURAIMS
Attheendofthislesson,youshouldbeableto
understandthereasonsbehindtheuseofregulararray
structures
investigatebasicstructuresthatareimplementedinVLSI
technology.
STUDYADVICE
Thisparticularlessonisdesignedtobeselfcontained.However,
thefollowingreferenceswillprovideadditionalsupportmaterial.
SUPPORTMATERIAL
Uyemura,J.P. (2001) IntroductiontoVLSICircuits&SystemsJ.
Wiley&Sons.(Chapters13)
Geiger,R.L.,Allen,P.E.&Strader,N.R. (1990) VLSI,Design
techniquesforAnaloganddigitalcircuits.McGrawHill.(Chapter
9)
Martin,K.(1999)DigitalIntegratedCircuitDesign.Oxford
UniversityPress.(Chapter10)
Fabricus,E.D.(1990) IntroductiontoVLSIDesign.McGraw
Hill.(Chapters9&10)
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1.1 REGULARARRAYSTRUCTURES
InVLSIdesignthecontinuousdrivetowardssmallertechnologies
isnotonlycompoundedbythemanufacturingcapabilitiesbutalso
thetechniquesutilisedtooptimiseanydesignslayoutfor
performance.Oneofthemainproblemsencounteredistherouting
oftheinterconnectionsbetweengatesandconsequentlytheuseof
structuredarchitecturesbecomesincreasinglymoreimportant.
Therepetitivestructuresthatresultallowthedesignertospend
considerablymoreeffort,thanwouldnormallybethecase,onthe
optimisationofthesmallersubcircuitsthattheoveralldesign
breaksdownto.
Aswewillinvestigatelater,andhasbeenpreviouslyidentified
underintegrationlevels(seetopic4lesson1),typicalexamples
thatfitwithinthisphilosophyarememorydevicesandgatearrays
butletusfirstofallinvestigatethesimplecaseofdatatransfer
usingtherepetitiveshiftregistersblocks.Thesedevicesrequire
twobasicbuildingblocks:
i)
ii)
ShiftRegister(S/R)storageelements,and
CombinationalLogic(C/L)controlelements.
1.1.1
DATATRANSMISSION
Adatatransmissionpathcanbeconstructedusingthefollowing
cascadearrangement:
S/R
C/L
S/R
C/L
Inordertocontrolsuchdevicesandpreventdatasimplycascading
freelydownthenetworkthenclockcontrolisnecessary.An
operationwhichisrelativelysimplewithedgetriggeredbipolar
devicesasthefinitedurationoftheclocksedgeensuresthat
insufficienttimeexistsforthecombinationallogicblocksto
propagatethedatafromthepreviousregisterstageonthroughthe
subsequentstage.Hencesingleclockcontrolispossible.
However,thisisnotthecasewithleveltriggeredCMOSdevices
asthelengthoftimethattheclockisheldattheappropriatelevel
canbegreaterthanthepropagationdelaythroughthelogicblocks
allowingdatatofreerundownthestructureuntiltheclock
changeslevel.Forthisreasonitiscommontoseemultiphase
clockoperationwhichisdesignedtoensureonlyoneclocklevel
existsatanysinglepointintime,therefore:
f1 f 2 L f n = 0
Page5
andthereforethedatapathbecomes
f1
f2
S/R
C/L
f1
S/R
C/L
S/R
AsolutionofthetypefirstencounteredwithmasterslaveJKflip
flopsinordertopreventcontinuousfeedbackaffectingoperation.
1.1.2
LOGICIMPLEMENTATION
Similarly,themultiphaseclockisrequiredfortheconstructionof
synchronousmachines(seepart1lesson1)forthesamereason:
f1
f2
S/R
C/L
S/R
Inordertokeepthestructuresregularthenthecombinational
logicblocksarethemselvesoftenrealisedinPLAorROM
structures.
WORKEDEXAMPLE1
Thefollowingsimplecircuitillustratesastructurewhichis
capableofperformingdatatransmissioninbothshiftrightand
shiftleftmodes:
SHL
DATA
SHR
TRR
TRL
SHL
DATA
Derivethenecessarycontrollogictoallow,inconjunctionwitha
twophaseclock,shiftrightoperationwhenasinglecontrolsignal
(CTRL)ishighandshiftleftoperation whenitislow.
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SOLUTION
ConsiderdatamovingbetweenAandBthenthefollowing
transistorsrequireswitching:
ShiftRight: SHR,TRR,SHR,TRR,etc..
ShiftLeft:
TRL,SHL,TRL,SHL,etc..
Thereforethefollowingtableillustratesonesolutiontothe
problemwhichusestheabovesequencesforsequential
applicationsofthetwophasedclock(i.e. f1, f2, f1, f2,etc..):
ShiftRight
ShiftLeft
Thus
CTRL
CTRL
f1
f2
SHR
TRL
TRR
SHL
SHR= f1 .CTRL
TRR= f2 .CTRL
TRL= f1 .CTRL
SHL= f2 .CTRL
f1
f2
CTRL
SHL
DATA
SHR
TRR
TRL
DATA
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1.2 MEMORYSTRUCTURES
Therepetitivearraystructureofmemorydevicesmakethemideal
forimplementationinVLSI.ThebasicmemorytypesbeingRAM
(RandomAccessMemory)andROM (ReadOnlyMemory)both
ofwhichwillbebrieflydiscussedbelow:
1.2.1
RANDOMACCESSMEMORY
Asthenamesuggeststhistypeofmemorycanbereadorwrite
accessedatanytimeandcomesinbothstaticanddynamicforms:
1.2.1.1
STATICRAM(SRAM)
SRAMsarebaseduponflipflopswherethememorycontents
willremainoncesetuntileitherthememoryisdeliberatelyover
writtenorthepowersupplyisturnedoff.Thebasicbuildingblock
forasinglememorycellisapairofcrosscoupledinverters.The
followingdiagramillustratingaCMOScell:
Vdd
Q3
BIT
Q4
Q5
Q6
Q1
WORD
BIT
Q2
WORD
Gnd
TowritetothememorycelltheBITandBIT lineshavetobeset
totherequiredvaluesandtheWORDlineactivated.TheNMOS
deviceswilllatchthecellandtheWORDlinecannowbede
activated.ThePMOSgatesactasloaddevicestoensurethatthe
latchiscompletedandalsocounteracttheaffectsofcharge
leakageviathepasstransistors.
ReadingisperformedbyprechargingtheBIT andBIT linesand
activatingtheWORDline.Theappropriatebitlinewilldischarge
viathecurrentlyactiveNMOSpulldowntransistortoleavethe
memorycontentsontheBITlines.
ThefollowingdiagramillustratesaSRAMcelllayout.Notethe
useofatwometalprocessinordertoachieveaccesstothebit
linesandpowersupplies.Acommonprobleminarraystructures.
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VDD
GND
Bit
Word
Word
Metal
Poly
PMoat
NMoat
Bit
NWell
ACMOSSRAMCell
Page9
1.2.1.2
DYNAMICRAM(DRAM)
AsinSRAMacrosscoupledinverterstructureisusedbutthe
storageisperformedintheparasiticgate/sourcecapacitanceofthe
NMOSpulldowntransistors.Themajorbenefitisthatthe
controllingdevicesworkonanentirecolumnandhencethe
overalltransistorcountisreducedandlargermemoriescanbe
constructed.AnNMOSsolutionisshownbelow:
BIT
BIT
Sharedbyentirecolumn
Vdd
Q
v
x
Row
Line
Q3
Q4
Q1
Q2
Gnd
ToR/W
Amplifiers
ToR/W
Amplifiers
However,leakagecurrentscausethestoredvoltagetodecay
towardsgroundlevelsandDRAMsmustbecontinuously
refreshedtooperate correctly.Thisisachievedinarowbyrow
fashionbyselectingtheappropriaterowline(x)andpulsingthe
columnrefreshsignal(v)forapproximately1mSwhichconnects
thestoragedevicestoVddforrefreshasQ/Q1andQ/Q2actas
NMOSactiveenhancementloadinverters.Thisproceduremustbe
repeatedevery2mStosecurestoragelevels.
FromtheDRAMstructureabove,thegate/sourcecapacitorwill
discharge,fromVdd,ataratedependinguponthesizeofthe
capacitanceandtheeffectiveleakageresistanceofthepulldown
FET.Duringrefresh,thelogiclevelswillberesettosupplyrail
levelsbyreconnectingthebitlinestotheFETS.Thus,duringa
typicalrefreshcycle,thefollowingvoltagecharacteristicswillbe
seen:
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VS
Vdd
Vmin
time
0
tp tr
tp
Refresh
Hold
Therefore,duringtheholdtime,(0t tp - tr ):
-
VS =Vdde
t
CGSReff
and,refresh(t p -tr t tp ):
-
VS =Vdd - (Vdd - Vmin)e
t
CGSRon
Ideally,inpracticethetimeconstantsaresuchthat(notingthat
CGSistypicallyaround50fF):
11
th = CGSReff >> (tp - tr ) asReff isintheregionof10 W,and
tr = CGSRon << tr
asRon isintheregionof104W
(seePart4lesson6).
Ensuringthatthedecayisalmostlinearandtherefreshisalmost
instantaneousincomparison,guaranteeingreestablishmentof
Vdd.
INTEXTQUESTION
InaDRAMcellthepropagationdelayalongtherowselectlinewasfoundtobelarge.Would
thewideningofthepolysiliconlineimprovethings?
ANSWER
WideningthelinewillreducetheresistanceasRpoly =(L/W)Rs.However,thiswillalso
increasethecapacitanceassociatedwiththelineby Cpoly =(L*W)Cs andthereforetheoverall
propagationdelay, tpoly=CpolyRpoly willremainthesameatL2CsRs.
Page11
WORKEDEXAMPLE2
ADRAMcellisconstructedusingapulldownFETof
gate/sourcecapacitance50fF.Ifavoltageof3.8Vistheminimum
thatcanberecognizedandaperiodof2mSandrefreshtimeof
1mSistobeused,whatwouldbetheminimumpermissible
leakageresistanceoftheFET?
SOLUTION
Actual:
Basedupontheaboverelationshipforthedecayof
thegate/sourcecapacitorthenrearrangingprovides:
Reff =
Linear:
(t - t )
p
V
- CGS loge min
Vdd
(2 10
- 1 10- 6)
= 1.46 1011W
-15
- 50 10 loge(3.8/5)
-3
Assumingthatalineardecayrateexiststhenthe
changeinchargeexperiencedbythecapacitoris
DQ = CGSDVS = 50 10-15(5- 3.8)= 60 10-15C
Hencetheeffectiveresistanceitexperiences,linearlyfromVdd is:
Reff =
V VDt 5(2 10-3 - 1 10-6)

=
=
= 1.66 1011W
-15
I DQ
60 10
Note:
Evaluatingtherelationshipsforthelinearapproachprovides
Reff =
Vdd(tp - tr)
CGS(Vdd - Vmin)
(t - t )
p
V - V
CGS dd min
Vdd
(t - t )
p
V
CGS1- min
Vdd
However,since loge (1+x) x as x0 thentheabove

equationscanbeshowntobeidenticalwhen
V - Vdd Vmin
x= min
=
- 1 0,
Vdd
Vdd
Hencethetworelationshipsbecomeequivalentas Vmin Vdd .

Thedesiredresult!
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ForhighcapacityDRAMdevicesthenasingleNMOSdeviceis
usedtocontrolmemorystorageinacapacitor.Refreshisstill
requiredasleakageproblemsstillexist:
BIT
Row
Line
CC
VC
CR
VR
y
ToR/W
Amplifiers
Themajorproblemwiththisstructureisthatthereadingoperation
destroysthecellsmemorycontentsasthechargeeachcell
containsdissipatesintotheread/writedatalinescapacitance,CR.
Aproblemthatisfurthercompoundedbythefactthatthereare
manycellsconnectedtotheBIT datalineandhenceCR >>CC ,
thusVR<<VC.
WORKEDEXAMPLE3
ForasingleMOSDRAMcellwhichstoresachargethatproduces
VC voltsacrossCC.Whatisthevoltageseenbytheread
amplifiersifthebitlinecapacitanceisCR? Assumingthattheread
lineisinitiallyuncharged.
SOLUTION
Priortoactivatingtherowlinesignal,X,andreadsignal,Y,all
thechargeisstoredinthecellitself (VR* =0),thus
QT =CCVC
However,afterthesignalshavebeenactivatedthischargeis
sharedbetweenthecellandtheBITlinecapacitances.Asthese
arenowinparallelthechargeisredistributedsothatthefinal
voltageVR is:
QT =CCVR+CRVR =(CC+CR)VR
Thus,assumingnochargeislost,then
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CC
VC
V R =
CC + CR
1.2.1.3
PHOTOSENSITIVERAM
CMOSCamerasareconstructedusingsingleMOSRAM
structuresbutwithareversebiasedphotodiode,formedby
extendingandexposingthesourceregionofastandardMOS,
whichisconnectedtothecellcontrollingMOSdevicestransistors
source.Thusdischargingitsgatecapacitanceataratewhichis
proportionaltotheincidentlightandhencetheresultingstored
potentialformsagreyscaleimageoftheincidentlightatthat
particularcellslocation.Eachcellthereforerepresentingasingle
pixeloftheoverallimageandtheentirearraysurfacetheimage
itself.Theimageisreadinthenormalmannerviaeachcolumns
ownchargesenseamplifier.
Column
Line
Row
Line
ToR/W
Amplifiers
INTEXTQUESTION
Howcouldtheabovetechnologybeconvertedtoprovidecolourimages?
ANSWER
Acolourimageismadepossibleusingsuitablefilterstoisolatered,greenandbluelight
individuallystoreeachindividuallevelonacellasabove.Thereforerequiringthreecellsfor
everypixelintheimage.
Page14
1.2.2
READONLYMEMORY
Asthenamesuggeststhistypeofmemorycanonlybereadandis
normallyusedincomputerstostoretheoperatingsystemsdueto
itslongtermstability (barringcircuitfailure).ROMdevicesare
programmedatmanufacturebythecreation/noncreationofMOS
devicesintheappropriatecelllocationsmakingtheminflexible
andhenceunsuitablefordevelopment.Toovercomethisproblem
programmabledevicesarealsoavailable(PROMs)andcomein
variousstructures,someofthemostcommonbeing:
1.2.2.1
ERASABLEPROM(EPROM)
ThistechnologyusesadoublegateNMOStransistorstructure
oftencalledafloatinggateavalancheinjectionMOS(FAMOS)
gate:
Vdd
ToR/W
Amplifiers
Gate2
Drain
Word
Line
x
Source
Gate1
n+
n+
psubs
psub
BIT
Gate1isleftfloating(electricallyisolated)andisusedtocontrol
theoperationoftheNMOSchannel.Toprogrammethecellthena
largepositivevoltage,typically25V,isappliedbetweenGate2
andthedrainoftheFAMOSdeviceandtheresultinghigh
electricalfieldinthedepletionregionaboutthedraincauses
avalanchebreakdownofthePNjunction.Thisallowselectrons,
whichareacceleratedbythelargeelectricalfield,topenetratethe
insulatinglayerandaccumulateonGate1.Thenownegatively
chargedgatewillpreventformulationofachannelinthe
depletionregion andthecellsFAMOSdeviceisnowincapableof
pullingtheappropriatedatalinelow.Hencealogichighoutputis
programmingonthecell.
Becauseoftheinsulatingpropertiesofthesilicondioxidethis
chargecanremainformanyyears.However,assilicondioxide
becomesmoreconductivewhenexposedtoUVlightthenthis
canbeusedtoresetthedevice,byallowingthestoredelectronsto
migratefromtheisolatedgate.
Page15
1.2.2.2
ELECTRICALLYERASABLEPROMS
(EEPROMS)
ThemajorproblemwithEPROMisthewindowcreatedinthe
package,thefactthatplasticpackagingisnegatedbytheneedto
exposeittoUVlightandthesubsequentexposuretimetakento
erasememory.EEPROMisbasicallythesamestructureas
EPROMexceptthattheGate1insulatinglayersareconsiderably
thinner,typicallyintheregionof100A.Thisallowspenetrationof
electronstotheisolatedgateviaquantummechanicaltunneling
affectsfortheapplicationofapproximately10V.Usingsuchlow
voltagelevelsthenthememorycellscanbeerasedbyapplying
theprogrammingvoltageinreversewithoutdamagingthe
structure,amuchmoreefficientprocedurethanforEPROM.
1.2.3
CHARGECOUPLEDDEVICES
(CCDS)
BasicallyMOStransistorsdesignedwithalongchannelwith
thousandsoftinycloselyspacedgatesbetweenthesourceandthe
drain.Eachgateeffectivelyformingacapacitorbetweenitselfand
thesubstratewhosechargecanbetransferredalongthestructure.
Thisisachievedbyapplyingapositivevoltage(withrespectto
thegroundedsubstrate)profiletoeachgateinturn,seebelow:
Therebycreatingdepletionregionsinthechannel,andunderthe
gateconcerned,andformingpotentialenergywellswithinwhich
mobileminoritycarriersfromthesubstratecanbeattracted.
f1
f2
f3
123456n
psubs
T1Period
T2Period
T3Period
Page16
T4Period
Inordertocontrolthepassageofthechargepacketsalongthe
structure,startingwithachargepacketinlocation1,thenthe
aboveillustratesthelocationsoftheelectronholdingenergywells
toallowthedataheldinposition 1tobepassedontolocation2.
Thereforethreephasesarerequiredtoallowforthenecessary
phaseoverlap,whilstavoidingfreerundownthestructure,
althoughitispossibletoconstructtwophasedevicesusing
overlappinggates.Toworkeffectively thenthesedevicesmustbe
operatedathighfrequencies,upto30MHz,andtheirminimum
operatingfrequency,typically10kHz,isrestrictedbecause
thermallygeneratedcarriersbecometrappedinemptywellsandin
timecanleadtoachangeinlogicstatefromlowtohigh.
Theserialnatureofthesedevicesgenerallymakethemunsuitable
formemorystoragedevicesbuttheyarecommonlyusedfor
imageanddigitalsignalprocessingduetotheirveryhighdensity.
Page17
Page18
SUMMARY
Theimportanceofregulararray structurestoachievetheVLSI
benefitswithminimdesignefforthasbeenintroduced.Asthe
mostefficientprocessesforthisarememorydevicesthenthis
lessonhasconcentrateduponthem.
Followingonwiththeregulararraystructurephilosophythengate
arraysprovidestructuresforprogrammablelogicarchitecture.
Eachofthearchitecturesoffervariouslevelsofimplementation
andvendorspecificsubvariantswithinthem.Typicalsub
categoriesinclude:
SimpleProgrammableLogicDevices(SPLDs),
ComplexProgrammableLogicDevices(CPLDs),and
FieldProgrammableGateArrays(FPGAs)
FieldProgrammableInterConnect(FPICs)
Thefollowinglessonwilllookattheselogicimplementation
structures.
Page19
Page20
SELFASSESSMENTQUESTIONS
QUESTION1
Usingthesolutiontoworkedexample1,whatlogiccontrolisrequiredtoholdthedatainits
currentlocation?
QUESTION2
If theSRAMcellofsection 1.2.1.1hadbothBITlinesgroundedandtheWORDlinesseparated
forcontrolpurposeswhatlogicfunctionwouldresultattheinverteroutputs?
QUESTION3
A256kSRAMdevice,offeaturesize2mm,isconstructedusingminimumwidthdesignforthe
polysiliconwordselectlinesandassociatedtransistorchannels.Iftheselectlinesare4mmlong
onthechipsurfacethen,assumingasquarearchitecture,estimatetheirpropagationdelay(seethe
MOSISvaluesinPart4Lesson5).
QUESTION4
ADRAMcellisconstructedusingapulldownFETofgate/sourcecapacitance40fFandleakage
current1nA.Whatwouldbetheminimumtimebetweenrefreshesiftheminimumvoltagethat
canbereadis3.8Vfromasupplyof5V.
QUESTION5
ForthesingletransistorDRAMdeviceshowninsection 1.2.1.2:
(a) DevelopanalternativeexpressionfortheBITreadvoltageiftheBITlinehastheinitial
voltage,VR*,andnotzeroasassumedinworkedexample3.
(b)Rearrangetheaboveequationintermsofthechangeinreadvoltage.
(c) WhatwouldbethemaximumallowablecapacitanceoftheBITlineifthecellscapacitance
was40fFandtheminimumtriggervalueforthesenseamplifierswas80mV.Youmay
assumethatthesmallestchangeincellvoltagethatwillallowasuccessfulreadisVdd/2
(whereVdd =5V).
Page21
Page22
ANSWERSTOSELFASSESSMENTQUESTIONS
ANSWER1
Inordertoholddatathenitmustberecirculatedaroundthetransmissioncells.Thiscanbe
achievedintwoways:
CircleCW: SHR,SHL,SHR,SHL,etc.
CircleACW: TRL,TRR,TRL,TRR,etc.
Withthepreviouscontrolsignalsfortheaboveoperations,i.e.
ShiftRight
ShiftLeft
CTRL
CTRL
f1
SHR
TRL
f2
TRR
SHL
Thenthesolutionistotogglethestatusofthecontrolsignal,CTRL,witheachclockphase.
ANSWER2
Hence,thecircuitbecomes
Vdd
f2
f1
Gnd
Thus
A
0
0
1
1
B
0
1
0
1
f1
f2
NoChange
1
0
0
1
Race
AnRSFlipFlop(f1 =Q,f2 =Q,withA=Reset,B=Set).
Page23
ANSWER3
Forasquare256kmemory (218 gates) thenitwillhave512*512gates.Henceeachselectlinewill
drive512devicesandasminimumMOSISdimensionsare2lwideforthepolysiliconand2l*2l
areaforthegatesthen:
Totalselectlinearea=4mm*2l = 4mm*2(2mm) = 16000mm2
GateArea=512*(2l*2l)=512*2(2mm)*2(2mm)=8192mm2
Henceeffectivepolysiliconarea(nongate)is160008192=7808mm2
Nowfrom Table2inPart4Lesson5,thentheinputcapacitanceassociatedwiththeselectline
(l=2mm) is:
Cin =Cg +Cpoly =8192(0.8)+7808(0.06)=6553.6fF+468.48fF=7.022pF
FromTable1inPart4Lesson5,thentheresistanceofthepolysilicon(assuminganaverage
value)is22.5W/o,asthepolysiliconis4mmlongand(2(2mm))widethen
Rpoly =(4mm/(2(2mm))*22.5=1000*22.5=22.5kW
Thusthepropagationdelaytimeconstantis:
tselect =Rpoly*Cin =22.5e+3*7.022e12=158ns=0.158ms
ANSWER4
Assumingconstantleakagecurrentthen
IL =-
dQ d(CGSVS )
d(VS )
=
= -CGS
dt
dt
dt
Therefore,asallchangesareassumedlinear,then
IL =-
DQ
D (VS )
= -CGS
Dt
Dt
andtherefore
Dt = -CGS
Page24
D(VS )
(3.8- 5)
= -40 10-15
= 48ms
- 9
IL
1 10
ANSWER5
(a) Thetotalchargeinthesystemmustbethesamebeforeandaftertheread,
hence
QT =CCVC+CRVR* =CCVR+CRVR
*
C V + CRVR
VR = C C
CC + CR
Therefore
(b)SubtractingVR* frombothsidesthen
*
C V + CRVR
CC
*
*
*
VR -VR = C C
- VR = VC - VR
CC + CR
CC + CR
(c) From (b)above,rearranging(intermsofCR)

V - V *
2.5
CR = C R* - 1CC =
- 140fF = 1210fF
0
.
08
V
V
R R
(
(
)
)
Page25
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ELX304 Topic5 Lesson 1 Pr2

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VS =Vdd - (Vdd - Vmin)e

DQ = CGSDVS = 50 10-15(5- 3.8)= 60 10-15C

V VDt 5(2 10-3 - 1 10-6)

However,since loge (1+x) x as x0 thentheabove

Hencethetworelationshipsbecomeequivalentas Vmin Vdd .

AnRSFlipFlop(f1 =Q,f2 =Q,withA=Reset,B=Set).

(c) From (b)above,rearranging(intermsofCR)

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