A MID SEM REPORT

ON
DESIGN AND ANALYSIS OF VESA DISPLAY STREAM COMPRESSION

BY

NAJMUS SAHAR

2013A3PS046U

AT

BITS, Pilani Dubai Campus

Dubai International Academic City (DIAC)
Dubai, U.A.E

First Semester, 2016-2017

EEE

A MID SEM REPORT

ON

DESIGN AND ANALYSIS OF VESA DISPLAY STREAM COMPRESSION

BY

NAJMUS SAHAR

2013A3PS046U

Prepared in Partial Fulfillment of the

Project Course: EEE F367

AT

BITS, Pilani Dubai Campus

Dubai International Academic City (DIAC)
Dubai, UAE

First Semester, 2016-17

EEE

ABSTRACT
BITS, Pilani Dubai Campus
Dubai International Academic City (DIAC)
Dubai, UAE
Course Name: Design Project
Course No: EEE F367
Duration: 4 months
Date of Start: August 17, 2016
Date of Submission: October 19, 2016
Title of Report: Design and Analysis of VESA Display Stream Compression
Name: NAJMUS SAHAR
ID Number: 2013A3PS046U
Discipline: EEE
Name of Project Supervisor: Dr. Anand Kumar
Keywords: VESA, Display Stream Compression,
Project Area: Control Systems and Analog Electronics
Abstract: With advancements in the pixel technology for displays, televisions and
monitors with high definition and ultra-high definition resolutions are being
manufactured. But the display links connecting computers to monitors or set-top boxes
to televisions are not capable of handling such high bandwidths of information. This
results in loss of pixel data even if the display is capable of handling higher resolutions.
Display compression schemes are hence employed to address this issue. This project
deals with the study and analysis of one scheme in particular, the VESA Display
Compression Scheme. The objective is to implement all of part of the DSC using better
technologies or schemes.

Signature of the Student

Signature of Faculty
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Date: 19.10.16

Date:
Acknowledgements

Firstly, I would like to express my heartfelt gratitude to the Director of BITS Pilani, Dubai
Campus, Prof. R.N. Saha, who has ushered a new light on our college.
Next, I would like to thank Dr. Anand Kumar, my Project Supervisor, for his faith in me
and for his motivation, support, guidance and encouragement throughout the course of
this project. He has been a great influence, urging me to learn and to be innovative,
pushing me to excel.
Lastly, I would like to thank Dr. Abdul Rajak, Instructor-in-Charge of Design Projects, for
taking his time to look into my work and for his support regarding my project.

Najmus Sahar
2013A3PS046U

Contents
ABSTRACT........................................................................................................................II
ACKNOWLEDGEMENTS.................................................................................................III
LIST OF FIGURES............................................................................................................V
LIST OF TABLES.............................................................................................................VI
OVERVIEW OF DISPLAY STREAM COMPRESSION.....................................................1
1.1 INTRODUCTION...............................................................................................................1
1.2 REQUIREMENTS FOR INDUSTRY STANDARD DISPLAY COMPRESSION................................1
1.3 EXISTING COMPRESSION TECHNIQUES...........................................................................2
DSC ALGORITHM.............................................................................................................3
2.1 OVERVIEW OF HARDWARE.............................................................................................3
2.2 ALGORITHM...................................................................................................................3
2.3 COMPONENTS OF THE ENCODER....................................................................................5
2.4 ADVANTAGES OF THE ALGORITHM...................................................................................6
2.5 PHYSICAL IMPLEMENTATION OF DSC ALGORITHM...........................................................7
FIELD PROGRAMMABLE GATE ARRAYS.......................................................................8
3.1 WHAT IS FPGA?...........................................................................................................8
3.2 HDL VERILOG............................................................................................................8
3.3 SOME BASIC VERILOG MODULES...................................................................................8
3.3.1 IMPLEMENTATION OF AND GATE............................................................8
3.3.2 IMPLEMENTATION OF FULL ADDER.......................................................10
3.3.3 IMPLEMENTATION OF 2 BIT COMPARATOR.............................................11
CONCLUSION.................................................................................................................13
REFERENCES................................................................................................................14

LIST OF FIGURE
FIGURE 1 HARDWARE IMPLEMENTATION OF DSC.....................................................3
FIGURE 2 DSC ALGORITHM OVERVIEW.......................................................................4
FIGURE 3 AND GATE SYMBOL AND TRUTH TABLE.....................................................9
FIGURE 4 AND GATE OUTPUT WAVEFORM...............................................................10
FIGURE 5 FULL ADDER LOGIC GATES AND TRUTH TABLE......................................10
FIGURE 6 FULL ADDER OUTPUT WAVEFORM...........................................................11
FIGURE 7 OUTPUT WAVEFORM FOR 2 BIT COMPARATOR......................................13

List of Tables
Table 1.Truth table for 2 bit comparator..12

CHAPTER 1
OVERVIEW OF DISPLAY STREAM COMPRESSION
1.1 Introduction
The advancement in pixel technology for displays has brought about a revolutionary
change in the standards of image quality in televisions and monitors. Ultra-high
definition and high definition resolution displays are common place. But such increased
quality of display also means that there is more bandwidth of pixel data to be
transmitted over display links. Most display links connecting monitors to computers and
set-top boxes to televisions are not able to handle such increased amount of
bandwidths.
This is where different display compression schemes come into picture. Compression
reduces the amount of pixel data sent over display links enabling higher resolutions to
be displayed in the available bandwidth But many of these techniques are either too
difficult to implement, expensive or visually lossy. It is also possible that the
compression schemes may not work on every device thus not being interoperable.
The Video Electronics Standards Association (VESA) addressed these issues by
implementing an industry standard for video compression called the Display Stream
Compression (DSC).
1.2 Requirements for Industry Standard Display Compression
When VESA decided to formulate an industry standard for compression which display
link standards could directly use, the following requirements were expected to be met by
the newly designed compression scheme:
1. The compression should be visually lossless, i.e., the user should not be able to
perceive any difference in the image quality before and after compression.
2. The compressed data rate should be constant as this ensures that the display
link does not run out of bandwidth while transmitting the image.
3. The specification should enable small regions or slices of the image to be altered
or updated.
4. A wide range of video formats should be supported for instance, RGB, YCbCr of
different ratios, (4:2:2, 4:4:4), etc.
5. Lastly, the scheme must be easy to implement, inexpensive and interoperable. It
should be developed using pre-existing technologies and conventional hardware.

1.3 Existing Compression Techniques

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Most of the existing compression techniques have many shortcomings. They are
visually lossless, too expensive and complex to implement or not operable on any given
display link or display device. As a result they fail to meet the requirements that VESA
charted out for a good compression specification standard.
MPEG-2 and H.264 are two compression schemes which are built on transform based
algorithm. Such schemes encode only the differences between successive frames.
JPEG-2000 and VC-2 uses a wavelet based algorithm. Wavelet based algorithm is
advantageous over transform based algorithm in the fact that encoding and decoding
can stop at a predetermined bit rate. The major disadvantage of all the above
mentioned schemes is that they require the storage of too many lines of pixel data. The
image quality is also compromised after compression.

CHAPTER 2
2

DSC ALGORITHM
2.1 Overview of Hardware

Figure 1 Hardware implementation of DSC

The DSC hardware is composed of and encoder and a decoder. The encoder is present
in the graphic source such as set top box or application processors. The decoder is
present in the display module such as television or monitor. The uncompressed pixel
data is sent to the DSC encoder which compresses it and sends it through the
transmission port, over the display link cable to the receiver port on the display module.
This compressed pixel data is then sent through the DSC decoder, which decoded the
data resulting in uncompressed pixel data. This visually lossless, uncompressed pixel
data is then finally displayed on the screen for the user.
This compression enables the display link to handle the lower bandwidth data and
prevents loss of image quality.

2.2 Algorithm
The DSC encoding scheme has been designed based on pulse code modulation
(PCM). This enables the analog signals to be converted to binary data thus reducing the
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number of lines of storage for pixel data. DSC requires only a single line of pixel storage
as compared to MPEG-2 and other compression schemes that we saw earlier on.

Figure 2 DSC Algorithm Overview

Display stream compression is able handle streams of data, i.e., they can continuously
compress new data using older one kept in a memory buffer, hence the name stream
compression. This is different from block compression where they absolutely need to
work with blocks of data specific size.
The input image pixel data goes to the color space converter, where the image is
converted from RGB format to YCoCg if it is not already in that format. This pixel data is
then stored in a buffer from where it is sent to the predictor, quantization, reconstruction
block, the flatness determination block and also the Indexed Color History (ICH) block.
The outputs of all the above mentioned blocks are then sent to a Variable Length
Coding (VLC) entropy encoder from where the streams are multiplexed, put through a
rate buffer and the final compressed image is sent over the display link.

2.3 Components of the Encoder

The main components of the encoder are the following:
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1. Color space converter: RGB image input data contains very high amount of
pixel data so it is converted to YCoCg-R format. This format contains Y
component which is the luminance component. Our eyes are more sensitive
to this data and hence it is retained. Co and Cg are the chrominance orange
and green components, to which our eyes are less sensitive. As a result these
components can be discarded. This conversion is a reversible transform that
is performed by some addition and shifts.
2. Buffer: It temporarily stores data when it is being moved from one place to
another. The buffer holds data right before it is used, making it more efficient.
This is especially done when there is a difference between the rate at which
data is received and the rate at which it is processed.
3. Predictor: The predictor scans bits of pixel data that it received from the
buffer, predicts a value based on different modes and gets approximate value.
This enables us to predict pixel values instead of actually scanning the entire
image and increasing bandwidth occupancy. There are three modes of
prediction, median adaptive prediction, block prediction and midpoint
prediction.
4. Quantization: This performs rounding or truncation of pixel values. Here, we
used power-of-2 quantizer.
5. Reconstruction: The inverse of the quantized value from the quantizer is
added to the predicted value to obtain the compressed pixel value. It is
ensured that the reconstructed value does not exceed the valid range of the
samples considered.
6. Flatness detection: It detects changes from complex (non-flat) to flat regions.
The rate controller selects a quantization parameter (QP) value for a current
block based on the bit rate of a previous block. Flat region basically means a
region of low frequency of pixel data and vice versa.
When the bit rate of the previous block is higher than the average bitrate of
the previously encoded blocks (due to high activity), the QP value of the
current block increases in order to maintain the bit-rate constraint and also to
prevent rate buffer overflow.
When a flat region follows right after a complex region, visual artifacts may be
noticeable if the flat region is encoded with a high QP. Therefore, it is useful
to identify this transition from a complex region to a flat region of video data
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so that the encoding of the flat region can be performed using a low QP
value, thereby reducing quantization artifacts.

7. Rate controller: Determines the quantization parameter QP and adjusts it

based on buffer fullness. It minimizes distortion of the reconstructed images.
8. Line Buffer: This holds output from predictor, quantizer and reconstructor so
that these components can use the buffered video data.
9. Indexed Color History: Color information is stored in a separate piece of data
called a palette which is an array of color elements.
10. VLC Entropy encoder: Variable length coding is used to encode the
prediction residual which comes from the prediction, quantization and
reconstruction block, based on ICH and flatness transition. It can encode
three samples per clock.
11. Sub stream Multiplexing: The bit streams that come out of the encoder is
multiplexed and then sent to three entropy decoders running in parallel which
facilitates decoding three pixels per clock.

2.4 Advantages of the Algorithm

DSC will help lower the data rate. This helps mobile device developers to lower the
RAM requirement, reduce power consumption, EMI emissions and save on costs.

2.5 Physical Implementation of DSC Algorithm

These are the ways in which DSC has been physically implemented:
1. MIPI DSI (Mobile Industry Processor Interface Display Serial Interface) 1.2
interface for within-device communication. This is in case of compression in
mobile devices which does not involve use of display links.
2. DisplayPort for a wired connection between devices (like mobile phone and TV or
monitor).
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CHAPTER 3
FIELD PROGRAMMABLE GATE ARRAYS
3.1 What is FPGA?
FPGA stands for field programmable gate array. It is a semiconductor device on which
we can define different functions using Hardware Description Language (HDL) even
after it is manufactured.
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It is called field programmable because it enables us to change the functions and

features in the hardware of the device even after it has been installed in the field. Gate
arrays are two dimensional arrays of gates which can be put together to perform various
simple calculations which in turn can perform bigger functions like controlling the rearview camera of a car.
Xilink FPGA has been used to implement the display stream compression standards
successfully. FPGAs can be programmed using HDLs like VHDL, Verilog and the likes.
3.2 HDL Verilog
Hardware description language is programming language used to model and describe
the structure of electronic circuits. Verilog is a common design language used for
describing FPGAs. Verilog modules describe the hardware, i.e., the various
interconnected logic gates, wires and registers, which the programmer wants to design.
This is particularly useful in programming the display stream compression standard on
an FPGA.
3.3 Some Basic Verilog Modules
The following Verilog modules were written as a starting point of understanding the
HDL:

3.3.1 Implementation of AND Gate

Figure 3 AND Gate symbol and Truth Table

Program:
module andgate
(
output out,
input in1,in2
);
assign out=in1&in2;
endmodule

Ouput Waveform:

Figure 4 AND gate output waveform

3.3.2 Implementation of Full Adder

Figure 5 Full Adder Logic Gates and Truth Table

Program:
module fulladder
(output sum,
output carry,
wire out1,
wire out2,
wire out3,
input a,b,c);
assign sum=a^b^c;
assign out1=a&b;
assign out2=b&c;
assign out3=a&c;
assign carry=out1|out2|out3;
endmodule
Output Waveform:

10

Figure 6 Full Adder output waveform

3.3.3 Implementation of 2 bit comparator

11

Table 1 Truth table for 2 bit comparator

Program:
module twobitcomp
(output alb,agb,aeb,
input [1:0]a,b);
assign alb=(~a)&b;
assign aeb=~(a^b);
assign agb=a&(~b);
endmodule
Output Waveform:

12

Figure 7 Output Waveform for 2 bit comparator

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CHAPTER 4
CONCLUSION
The report started off with a detailed analysis of the VESA Display stream compression
scheme and its various advantages as compared to other existing video compression
schemes. We saw the algorithm for the encoder of DSC. The various blocks of the DSC
encoder and their functions were explored.
This gave an idea of what the methodology of the DSC is and how it can be
implemented using similar pre-existing techniques but with improved efficiency. It is
understood that FPGAs would serve the purpose of hardware implementation of the
DSC. For this, Verilog would be an ideal HDL to be used.
Hereafter, more complex Verilog programs involving control signals and pipelining must
be studied and designed. This is help in the achievement of partial implementation of
the display stream compression standard.

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REFERENCES

[1] http://www.hardent.com/electronic-FPGA-design-consulting-services/a-quick-guideto-vesa-display-stream-compression/
[2] Malvar, H.G. Sullivan, and S Srinivasan. Liftingbased reversible color
transformations for image compression Proc.SPIE,Vol.7073.2008.
[3] VESA Display Stream Compression Written by Frederick Walls, Associate Technical
Director, and Sandy MacInnis, Senior Technical Director, Broadcom Corporation (VESA
member)
[4] DISPLAY STREAM COMPRESSION, United States
US 20140362098A1 Patent Application Publication
Pub. No.: US 2014/0362098 A1 Kerofsky Pub. Date: Dec. 11, 2014

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